From 212396335481fed59e124f04c72a66a4e78856d5 Mon Sep 17 00:00:00 2001 From: 93Urbano Date: Thu, 13 Oct 2022 21:23:39 +0200 Subject: [PATCH] Apps2 deshabilitado --- ETC.X/ETC.c | 3 +- ETC.X/PARAMETERS.h | 6 +- ETC.X/build/default/debug/ANALOG.i | 37875 ++++++++++++ ETC.X/build/default/debug/ANALOG.p1 | 3821 ++ ETC.X/build/default/debug/ANALOG.p1.d | 5 + ETC.X/build/default/debug/CLUTCH.i | 38615 ++++++++++++ ETC.X/build/default/debug/CLUTCH.p1 | 4026 ++ ETC.X/build/default/debug/CLUTCH.p1.d | 21 + ETC.X/build/default/debug/ETC.i | 39055 ++++++++++++ ETC.X/build/default/debug/ETC.p1 | 5309 ++ ETC.X/build/default/debug/ETC.p1.d | 22 + ETC.X/build/default/debug/GPIO.i | 37712 ++++++++++++ ETC.X/build/default/debug/GPIO.p1 | 3786 ++ ETC.X/build/default/debug/GPIO.p1.d | 8 + ETC.X/build/default/debug/MESSAGES.i | 38653 ++++++++++++ ETC.X/build/default/debug/MESSAGES.p1 | 4160 ++ ETC.X/build/default/debug/MESSAGES.p1.d | 20 + ETC.X/build/default/debug/TEMPORIZATIONS.i | 38548 ++++++++++++ ETC.X/build/default/debug/TEMPORIZATIONS.p1 | 3768 ++ ETC.X/build/default/debug/TEMPORIZATIONS.p1.d | 22 + ETC.X/build/default/debug/main.i | 38523 ++++++++++++ ETC.X/build/default/debug/main.p1 | 3751 ++ ETC.X/build/default/debug/main.p1.d | 22 + .../default/debug/mcc_generated_files/DAC3.i | 386 + .../default/debug/mcc_generated_files/DAC3.p1 | 100 + .../debug/mcc_generated_files/DAC3.p1.d | 5 + .../debug/mcc_generated_files/DAC3_example.i | 38300 ++++++++++++ .../debug/mcc_generated_files/DAC3_example.p1 | 3604 ++ .../mcc_generated_files/DAC3_example.p1.d | 17 + .../default/debug/mcc_generated_files/adc.i | 38391 ++++++++++++ .../default/debug/mcc_generated_files/adc.p1 | 5393 ++ .../debug/mcc_generated_files/adc.p1.d | 3 + .../default/debug/mcc_generated_files/can1.i | 39038 ++++++++++++ .../debug/mcc_generated_files/can1.i-8e07095c | 39038 ++++++++++++ .../default/debug/mcc_generated_files/can1.p1 | 5761 ++ .../debug/mcc_generated_files/can1.p1.d | 17 + .../debug/mcc_generated_files/device_config.i | 125 + .../mcc_generated_files/device_config.p1 | 124 + .../mcc_generated_files/device_config.p1.d | 2 + .../drivers/i2c_simple_master.i | 472 + .../drivers/i2c_simple_master.p1 | 539 + .../drivers/i2c_simple_master.p1.d | 4 + .../examples/i2c1_master_example.i | 473 + .../examples/i2c1_master_example.p1 | 527 + .../examples/i2c1_master_example.p1.d | 4 + .../debug/mcc_generated_files/i2c1_master.i | 38490 ++++++++++++ .../debug/mcc_generated_files/i2c1_master.p1 | 6028 ++ .../mcc_generated_files/i2c1_master.p1.d | 3 + .../mcc_generated_files/interrupt_manager.i | 38288 ++++++++++++ .../mcc_generated_files/interrupt_manager.p1 | 3701 ++ .../interrupt_manager.p1.d | 16 + .../default/debug/mcc_generated_files/mcc.i | 38308 ++++++++++++ .../default/debug/mcc_generated_files/mcc.p1 | 3702 ++ .../debug/mcc_generated_files/mcc.p1.d | 16 + .../debug/mcc_generated_files/pin_manager.i | 37565 ++++++++++++ .../debug/mcc_generated_files/pin_manager.p1 | 3733 ++ .../mcc_generated_files/pin_manager.p1.d | 3 + .../debug/mcc_generated_files/pwm1_16bit.i | 37708 ++++++++++++ .../debug/mcc_generated_files/pwm1_16bit.p1 | 4031 ++ .../debug/mcc_generated_files/pwm1_16bit.p1.d | 3 + .../debug/mcc_generated_files/pwm2_16bit.i | 37708 ++++++++++++ .../debug/mcc_generated_files/pwm2_16bit.p1 | 4030 ++ .../debug/mcc_generated_files/pwm2_16bit.p1.d | 3 + .../default/debug/mcc_generated_files/tmr0.i | 37639 ++++++++++++ .../default/debug/mcc_generated_files/tmr0.p1 | 3804 ++ .../debug/mcc_generated_files/tmr0.p1.d | 4 + .../default/debug/mcc_generated_files/tmr1.i | 37714 ++++++++++++ .../default/debug/mcc_generated_files/tmr1.p1 | 4038 ++ .../debug/mcc_generated_files/tmr1.p1.d | 4 + ETC.X/build/default/production/ETC.i | 17 +- ETC.X/build/default/production/ETC.p1 | 600 +- ETC.X/dist/default/debug/ETC.X.debug.cmf | 4308 ++ ETC.X/dist/default/debug/ETC.X.debug.elf | Bin 0 -> 139086 bytes ETC.X/dist/default/debug/ETC.X.debug.hxl | 396 + ETC.X/dist/default/debug/ETC.X.debug.lst | 30885 ++++++++++ ETC.X/dist/default/debug/ETC.X.debug.map | 8072 +++ ETC.X/dist/default/debug/ETC.X.debug.mum | 8 + ETC.X/dist/default/debug/ETC.X.debug.o | Bin 0 -> 346180 bytes ETC.X/dist/default/debug/ETC.X.debug.rlf | Bin 0 -> 2454933 bytes ETC.X/dist/default/debug/ETC.X.debug.sdb | 3457 ++ ETC.X/dist/default/debug/ETC.X.debug.sym | 4163 ++ ETC.X/dist/default/debug/memoryfile.xml | 17 + .../default/production/ETC.X.production.cmf | 3622 +- .../default/production/ETC.X.production.elf | Bin 139086 -> 138542 bytes .../default/production/ETC.X.production.hex | 1282 +- .../default/production/ETC.X.production.hxl | 23 +- .../default/production/ETC.X.production.lst | 49776 ++++++++-------- .../default/production/ETC.X.production.map | 1998 +- .../default/production/ETC.X.production.mum | 2 +- .../default/production/ETC.X.production.o | Bin 346200 -> 337289 bytes .../default/production/ETC.X.production.rlf | Bin 2454933 -> 2402676 bytes .../default/production/ETC.X.production.sdb | 48 +- .../default/production/ETC.X.production.sym | 3278 +- ETC.X/dist/default/production/memoryfile.xml | 4 +- ETC.X/nbproject/private/private.xml | 12 +- 95 files changed, 887887 insertions(+), 30674 deletions(-) create mode 100644 ETC.X/build/default/debug/ANALOG.i create mode 100644 ETC.X/build/default/debug/ANALOG.p1 create mode 100644 ETC.X/build/default/debug/ANALOG.p1.d create mode 100644 ETC.X/build/default/debug/CLUTCH.i create mode 100644 ETC.X/build/default/debug/CLUTCH.p1 create mode 100644 ETC.X/build/default/debug/CLUTCH.p1.d create mode 100644 ETC.X/build/default/debug/ETC.i create mode 100644 ETC.X/build/default/debug/ETC.p1 create mode 100644 ETC.X/build/default/debug/ETC.p1.d create mode 100644 ETC.X/build/default/debug/GPIO.i create mode 100644 ETC.X/build/default/debug/GPIO.p1 create mode 100644 ETC.X/build/default/debug/GPIO.p1.d create mode 100644 ETC.X/build/default/debug/MESSAGES.i create mode 100644 ETC.X/build/default/debug/MESSAGES.p1 create mode 100644 ETC.X/build/default/debug/MESSAGES.p1.d create mode 100644 ETC.X/build/default/debug/TEMPORIZATIONS.i create mode 100644 ETC.X/build/default/debug/TEMPORIZATIONS.p1 create mode 100644 ETC.X/build/default/debug/TEMPORIZATIONS.p1.d create mode 100644 ETC.X/build/default/debug/main.i create mode 100644 ETC.X/build/default/debug/main.p1 create mode 100644 ETC.X/build/default/debug/main.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/DAC3.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/DAC3.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/DAC3.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/DAC3_example.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/DAC3_example.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/DAC3_example.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/adc.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/adc.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/adc.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/can1.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/can1.i-8e07095c create mode 100644 ETC.X/build/default/debug/mcc_generated_files/can1.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/can1.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/device_config.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/device_config.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/device_config.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/i2c1_master.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/i2c1_master.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/i2c1_master.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/mcc.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/mcc.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/mcc.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/pin_manager.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/pin_manager.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/pin_manager.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/tmr0.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/tmr0.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/tmr0.p1.d create mode 100644 ETC.X/build/default/debug/mcc_generated_files/tmr1.i create mode 100644 ETC.X/build/default/debug/mcc_generated_files/tmr1.p1 create mode 100644 ETC.X/build/default/debug/mcc_generated_files/tmr1.p1.d create mode 100644 ETC.X/dist/default/debug/ETC.X.debug.cmf create mode 100644 ETC.X/dist/default/debug/ETC.X.debug.elf create mode 100644 ETC.X/dist/default/debug/ETC.X.debug.hxl create mode 100644 ETC.X/dist/default/debug/ETC.X.debug.lst create mode 100644 ETC.X/dist/default/debug/ETC.X.debug.map create mode 100644 ETC.X/dist/default/debug/ETC.X.debug.mum create mode 100644 ETC.X/dist/default/debug/ETC.X.debug.o create mode 100644 ETC.X/dist/default/debug/ETC.X.debug.rlf create mode 100644 ETC.X/dist/default/debug/ETC.X.debug.sdb create mode 100644 ETC.X/dist/default/debug/ETC.X.debug.sym create mode 100644 ETC.X/dist/default/debug/memoryfile.xml diff --git a/ETC.X/ETC.c b/ETC.X/ETC.c index 184f50f..8d82c0f 100644 --- a/ETC.X/ETC.c +++ b/ETC.X/ETC.c @@ -411,7 +411,8 @@ void APPSAnalysis (void) ucAPPS1Perc = ETCPercentCalc(uiAPPS1, uiAPPS1min, uiAPPS1max); ucAPPS2Perc = ETCPercentCalc(uiAPPS2, uiAPPS2min, uiAPPS2max); - ucAPPS = ( ( ucAPPS1Perc + ucAPPS2Perc ) / 2 ); + //ucAPPS = ( ( ucAPPS1Perc + ucAPPS2Perc ) / 2 ); + ucAPPS = ucAPPS1Perc; Nop(); } diff --git a/ETC.X/PARAMETERS.h b/ETC.X/PARAMETERS.h index bda489c..bc839ee 100644 --- a/ETC.X/PARAMETERS.h +++ b/ETC.X/PARAMETERS.h @@ -21,11 +21,11 @@ extern "C" { //PARAMETROS CONSTANTES #define TPSMARGEN 50 #define APPSMARGEN 100 -#define APPS1max 1990 //0.001v -#define APPS2max 160 //0.001v +#define APPS1max 2670 //0.001v +#define APPS2max 4600 //0.001v #define TPSRulesPercent 30 #define APPSRulesPercent 30 -#define ActiveRules 1 +#define ActiveRules 0 #define DesembragueTime_ms 500 extern signed long sl_K; diff --git a/ETC.X/build/default/debug/ANALOG.i b/ETC.X/build/default/debug/ANALOG.i new file mode 100644 index 0000000..bd69fd4 --- /dev/null +++ b/ETC.X/build/default/debug/ANALOG.i @@ -0,0 +1,37875 @@ +# 1 "ANALOG.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "ANALOG.c" 2 + + + + + + + +# 1 "./ANALOG.h" 1 +# 22 "./ANALOG.h" +unsigned int ANALOG_GetVoltage (unsigned char ucEntradaAnalogica); +void ANALOGRead (void); +# 8 "ANALOG.c" 2 + +# 1 "./ETC.h" 1 +# 65 "./ETC.h" +unsigned int uiTPS1TableIn [21]; +unsigned char ucTPS1TableOut [21]; +unsigned int uiTPS2TableIn [21]; +unsigned char ucTPS2TableOut [21]; + +typedef struct { + + + float Kp; + float Ki; + float Kd; + + + float tau; + + + float limMin; + float limMax; + + + float limMinInt; + float limMaxInt; + + + float T; + + + float integrator; + float prevError; + float differentiator; + float prevMeasurement; + + + float out; + +} PIDController; + +PIDController pid = { 2.4f, 1.4f, 0.0f, + 0.02f, + 0.0f, 100.0f, + -10.0f, 10.0f, + 0.01f }; + + + +extern unsigned int uiAPPS1min; +extern unsigned int uiAPPS1max; +extern unsigned int uiAPPS2min; +extern unsigned int uiAPPS2max; +extern unsigned int uiTPS1min; +extern unsigned int uiTPS1max; +extern unsigned int uiTPS2min; +extern unsigned int uiTPS2max; +extern unsigned int uiAPPS1; +extern unsigned int uiAPPS2; +extern unsigned char ucAPPS_STATE; +extern unsigned long ulAPPS1calc; +extern unsigned long ulAPPS2calc; +extern unsigned int ucAPPS1Perc; +extern unsigned int ucAPPS2Perc; +extern unsigned int ucAPPS; +extern unsigned int uiTPS1; +extern unsigned int uiTPS2; +extern signed long ulTPS1calc; +extern signed long ulTPS2calc; +extern unsigned int ucTPS1Perc; +extern unsigned int ucTPS2Perc; +extern unsigned int ucTPS; +extern unsigned char ucTPS_STATE; +extern unsigned char ucTPS1_STATE; +extern unsigned char ucTPS2_STATE; +extern unsigned char ucTPS_Volts_STATE; +extern unsigned int uiETCDuty; +extern unsigned char ucETB_STATE; +extern unsigned char ucETCBeatSupervisor; +extern unsigned char ucETCFlagSupervisor; +extern unsigned char ucAPPSManual; +extern unsigned char ucETCTimerRuleTPS; +extern unsigned char ucETCTimerRuleAPPS; +extern unsigned char ucCount100msTPSError; +extern unsigned char ucCount100msAPPSError; +extern unsigned char ucETCRuleSupervisor; +extern unsigned char ucETCTargetTPSDiff; +extern unsigned char ucCount500msTPSDiff; +extern unsigned char ucETCMotorNotClose; +extern unsigned char ucETCResolveNotCloseError; +extern unsigned char ucCount500msResolveNotCloseError; + +extern unsigned int ucAPPSTargetPruebas; + +void ETCInit(void); +void APPSSend (unsigned char ucPercent); +void APPSReadmin (void); +void APPSReadmax (void); +void ETCModeSelect (unsigned char ucModeSelect); +void ETCRulesSupervision(void); +void ETCMove(unsigned char ucTargetMove, unsigned char ucMode); +void ETC_PID(signed long slTargetMove, unsigned char ucMode); +void ETCCalibrate(void); +void TPSAnalysis (void); +void APPSAnalysis (void); +void ETCXavierSupervisor (void); +void ETCManual (unsigned char ucTargetManual); +unsigned int ETCPercentCalc(signed long val, signed long min, signed long max); +void ETCRulesSensorsSupervision(void); +void ETC100msSupervisor (void); +void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactual); +void ETC500msSupervisor (void); +void PIDController_Init(PIDController *pid); +float PIDController_Update(PIDController *pid, float setpoint, float measurement); +unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +# 9 "ANALOG.c" 2 + +# 1 "./mcc_generated_files/adc.h" 1 +# 56 "./mcc_generated_files/adc.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 56 "./mcc_generated_files/adc.h" 2 + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 58 "./mcc_generated_files/adc.h" 2 + + + + + + + +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "./mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "./mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "./mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "./mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "./mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "./mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "./mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "./mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "./mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "./mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "./mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "./mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "./mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "./mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "./mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "./mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "./mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "./mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "./mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "./mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "./mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "./mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "./mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "./mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "./mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "./mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "./mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 10 "ANALOG.c" 2 + + + + + +unsigned int ANALOG_GetVoltage (unsigned char ucEntradaAnalogica) +{ + uint16_t uiValorAnalog; + uint16_t uiValorVoltage; + unsigned char ucFlag; + + switch (ucEntradaAnalogica) + { + case 3: + ADC_DisableChannelSequencer(); + ADC_SelectContext(CONTEXT_TPS1); + uiValorAnalog = ADC_GetSingleConversion(TPS1); + ucFlag = 1; + break; + case 4: + ADC_DisableChannelSequencer(); + ADC_SelectContext(CONTEXT_TPS2); + uiValorAnalog = ADC_GetSingleConversion(TPS2); + ucFlag = 1; + break; + case 1: + ADC_DisableChannelSequencer(); + ADC_SelectContext(CONTEXT_APPS1); + uiValorAnalog = ADC_GetSingleConversion(APPS1); + ucFlag = 1; + break; + case 2: + ADC_DisableChannelSequencer(); + ADC_SelectContext(CONTEXT_APPS2); + uiValorAnalog = ADC_GetSingleConversion(APPS2); + ucFlag = 1; + break; + default: + ucFlag = 2; + break; + } + + if ( ucFlag == 1 ) + { + if ( uiValorAnalog <= 6 ) + { + uiValorVoltage = 0; + } + else + { + + + uiValorVoltage = (1*uiValorAnalog); + uiValorVoltage = uiValorVoltage - 5; + } + + if ( uiValorVoltage > 5000 ) + { + + + } + else + { + return (uiValorVoltage); + } + } + else if ( ucFlag == 2 ) + { + + + } + else + { + + } + +} + + +void ANALOGRead (void) +{ + uiAPPS1 = ANALOG_GetVoltage(1); + uiAPPS2 = ANALOG_GetVoltage(2); + uiTPS1 = ANALOG_GetVoltage(3); + uiTPS2 = ANALOG_GetVoltage(4); + __nop(); +} diff --git a/ETC.X/build/default/debug/ANALOG.p1 b/ETC.X/build/default/debug/ANALOG.p1 new file mode 100644 index 0000000..e8ca7f4 --- /dev/null +++ b/ETC.X/build/default/debug/ANALOG.p1 @@ -0,0 +1,3821 @@ +Version 4.0 HI-TECH Software Intermediate Code +"70 ./ETC.h +[; ;./ETC.h: 70: typedef struct { +[s S1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 ] +[n S1 . Kp Ki Kd tau limMin limMax limMinInt limMaxInt T integrator prevError differentiator prevMeasurement out ] +[v F22277 `(v ~T0 @X0 1 tf ] +"172 ./mcc_generated_files/adc.h +[; ;./mcc_generated_files/adc.h: 172: __attribute__((inline)) void ADC_DisableChannelSequencer(void); +[v _ADC_DisableChannelSequencer `TF22277 ~T0 @X0 0 e ] +"25 ANALOG.c +[; ;ANALOG.c: 25: ADC_SelectContext(CONTEXT_TPS1); +[c E22267 0 1 2 3 .. ] +[n E22267 . CONTEXT_TPS1 CONTEXT_TPS2 CONTEXT_APPS1 CONTEXT_APPS2 ] +[v F22281 `(v ~T0 @X0 1 tf1`E22267 ] +"227 ./mcc_generated_files/adc.h +[; ;./mcc_generated_files/adc.h: 227: __attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +[v _ADC_SelectContext `TF22281 ~T0 @X0 0 e ] +"26 ANALOG.c +[; ;ANALOG.c: 26: uiValorAnalog = ADC_GetSingleConversion(TPS1); +[c E22256 4 16 17 18 59 60 61 62 63 .. ] +[n E22256 . TPS2 TPS1 APPS2 APPS1 channel_VSS channel_Temp channel_DAC1 channel_FVR_Buffer1 channel_FVR_Buffer2 ] +"378 ./mcc_generated_files/adc.h +[; ;./mcc_generated_files/adc.h: 378: adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +[v _ADC_GetSingleConversion `(us ~T0 @X0 0 ef1`E22256 ] +"118 ./ETC.h +[; ;./ETC.h: 118: extern unsigned int uiAPPS1; +[v _uiAPPS1 `ui ~T0 @X0 0 e ] +"119 +[; ;./ETC.h: 119: extern unsigned int uiAPPS2; +[v _uiAPPS2 `ui ~T0 @X0 0 e ] +"126 +[; ;./ETC.h: 126: extern unsigned int uiTPS1; +[v _uiTPS1 `ui ~T0 @X0 0 e ] +"127 +[; ;./ETC.h: 127: extern unsigned int uiTPS2; +[v _uiTPS2 `ui ~T0 @X0 0 e ] +"8 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\builtins.h +[v ___nop `(v ~T0 @X0 0 ef ] +[p i ___nop ] +"65 ./ETC.h +[; ;./ETC.h: 65: unsigned int uiTPS1TableIn [21]; +[v _uiTPS1TableIn `ui ~T0 @X0 -> 21 `i e ] +"66 +[; ;./ETC.h: 66: unsigned char ucTPS1TableOut [21]; +[v _ucTPS1TableOut `uc ~T0 @X0 -> 21 `i e ] +"67 +[; ;./ETC.h: 67: unsigned int uiTPS2TableIn [21]; +[v _uiTPS2TableIn `ui ~T0 @X0 -> 21 `i e ] +"68 +[; ;./ETC.h: 68: unsigned char ucTPS2TableOut [21]; +[v _ucTPS2TableOut `uc ~T0 @X0 -> 21 `i e ] +"102 +[; ;./ETC.h: 102: PIDController pid = { 2.4f, 1.4f, 0.0f, +[v _pid `S1 ~T0 @X0 1 e ] +[i _pid +:U .. +:U .. +-> .2.4 `f +-> .1.4 `f +-> .0.0 `f +-> .0.02 `f +-> .0.0 `f +-> .100.0 `f +-U -> .10.0 `f +-> .10.0 `f +-> .0.01 `f +.. +.. +] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"15 ANALOG.c +[; ;ANALOG.c: 15: unsigned int ANALOG_GetVoltage (unsigned char ucEntradaAnalogica) +[v _ANALOG_GetVoltage `(ui ~T0 @X0 1 ef1`uc ] +"16 +[; ;ANALOG.c: 16: { +{ +[e :U _ANALOG_GetVoltage ] +"15 +[; ;ANALOG.c: 15: unsigned int ANALOG_GetVoltage (unsigned char ucEntradaAnalogica) +[v _ucEntradaAnalogica `uc ~T0 @X0 1 r1 ] +"16 +[; ;ANALOG.c: 16: { +[f ] +"17 +[; ;ANALOG.c: 17: uint16_t uiValorAnalog; +[v _uiValorAnalog `us ~T0 @X0 1 a ] +"18 +[; ;ANALOG.c: 18: uint16_t uiValorVoltage; +[v _uiValorVoltage `us ~T0 @X0 1 a ] +"19 +[; ;ANALOG.c: 19: unsigned char ucFlag; +[v _ucFlag `uc ~T0 @X0 1 a ] +"21 +[; ;ANALOG.c: 21: switch (ucEntradaAnalogica) +[e $U 3179 ] +"22 +[; ;ANALOG.c: 22: { +{ +"23 +[; ;ANALOG.c: 23: case 3: +[e :U 3180 ] +"24 +[; ;ANALOG.c: 24: ADC_DisableChannelSequencer(); +[e ( _ADC_DisableChannelSequencer .. ] +"25 +[; ;ANALOG.c: 25: ADC_SelectContext(CONTEXT_TPS1); +[e ( _ADC_SelectContext (1 . `E22267 0 ] +"26 +[; ;ANALOG.c: 26: uiValorAnalog = ADC_GetSingleConversion(TPS1); +[e = _uiValorAnalog ( _ADC_GetSingleConversion (1 . `E22256 1 ] +"27 +[; ;ANALOG.c: 27: ucFlag = 1; +[e = _ucFlag -> -> 1 `i `uc ] +"28 +[; ;ANALOG.c: 28: break; +[e $U 3178 ] +"29 +[; ;ANALOG.c: 29: case 4: +[e :U 3181 ] +"30 +[; ;ANALOG.c: 30: ADC_DisableChannelSequencer(); +[e ( _ADC_DisableChannelSequencer .. ] +"31 +[; ;ANALOG.c: 31: ADC_SelectContext(CONTEXT_TPS2); +[e ( _ADC_SelectContext (1 . `E22267 1 ] +"32 +[; ;ANALOG.c: 32: uiValorAnalog = ADC_GetSingleConversion(TPS2); +[e = _uiValorAnalog ( _ADC_GetSingleConversion (1 . `E22256 0 ] +"33 +[; ;ANALOG.c: 33: ucFlag = 1; +[e = _ucFlag -> -> 1 `i `uc ] +"34 +[; ;ANALOG.c: 34: break; +[e $U 3178 ] +"35 +[; ;ANALOG.c: 35: case 1: +[e :U 3182 ] +"36 +[; ;ANALOG.c: 36: ADC_DisableChannelSequencer(); +[e ( _ADC_DisableChannelSequencer .. ] +"37 +[; ;ANALOG.c: 37: ADC_SelectContext(CONTEXT_APPS1); +[e ( _ADC_SelectContext (1 . `E22267 2 ] +"38 +[; ;ANALOG.c: 38: uiValorAnalog = ADC_GetSingleConversion(APPS1); +[e = _uiValorAnalog ( _ADC_GetSingleConversion (1 . `E22256 3 ] +"39 +[; ;ANALOG.c: 39: ucFlag = 1; +[e = _ucFlag -> -> 1 `i `uc ] +"40 +[; ;ANALOG.c: 40: break; +[e $U 3178 ] +"41 +[; ;ANALOG.c: 41: case 2: +[e :U 3183 ] +"42 +[; ;ANALOG.c: 42: ADC_DisableChannelSequencer(); +[e ( _ADC_DisableChannelSequencer .. ] +"43 +[; ;ANALOG.c: 43: ADC_SelectContext(CONTEXT_APPS2); +[e ( _ADC_SelectContext (1 . `E22267 3 ] +"44 +[; ;ANALOG.c: 44: uiValorAnalog = ADC_GetSingleConversion(APPS2); +[e = _uiValorAnalog ( _ADC_GetSingleConversion (1 . `E22256 2 ] +"45 +[; ;ANALOG.c: 45: ucFlag = 1; +[e = _ucFlag -> -> 1 `i `uc ] +"46 +[; ;ANALOG.c: 46: break; +[e $U 3178 ] +"47 +[; ;ANALOG.c: 47: default: +[e :U 3184 ] +"48 +[; ;ANALOG.c: 48: ucFlag = 2; +[e = _ucFlag -> -> 2 `i `uc ] +"49 +[; ;ANALOG.c: 49: break; +[e $U 3178 ] +"50 +[; ;ANALOG.c: 50: } +} +[e $U 3178 ] +[e :U 3179 ] +[e [\ -> _ucEntradaAnalogica `i , $ -> 3 `i 3180 + , $ -> 4 `i 3181 + , $ -> 1 `i 3182 + , $ -> 2 `i 3183 + 3184 ] +[e :U 3178 ] +"52 +[; ;ANALOG.c: 52: if ( ucFlag == 1 ) +[e $ ! == -> _ucFlag `i -> 1 `i 3185 ] +"53 +[; ;ANALOG.c: 53: { +{ +"54 +[; ;ANALOG.c: 54: if ( uiValorAnalog <= 6 ) +[e $ ! <= -> _uiValorAnalog `ui -> -> 6 `i `ui 3186 ] +"55 +[; ;ANALOG.c: 55: { +{ +"56 +[; ;ANALOG.c: 56: uiValorVoltage = 0; +[e = _uiValorVoltage -> -> 0 `i `us ] +"57 +[; ;ANALOG.c: 57: } +} +[e $U 3187 ] +"58 +[; ;ANALOG.c: 58: else +[e :U 3186 ] +"59 +[; ;ANALOG.c: 59: { +{ +"62 +[; ;ANALOG.c: 62: uiValorVoltage = (1*uiValorAnalog); +[e = _uiValorVoltage -> * -> -> 1 `i `ui -> _uiValorAnalog `ui `us ] +"63 +[; ;ANALOG.c: 63: uiValorVoltage = uiValorVoltage - 5; +[e = _uiValorVoltage -> - -> _uiValorVoltage `ui -> -> 5 `i `ui `us ] +"64 +[; ;ANALOG.c: 64: } +} +[e :U 3187 ] +"66 +[; ;ANALOG.c: 66: if ( uiValorVoltage > 5000 ) +[e $ ! > -> _uiValorVoltage `ui -> -> 5000 `i `ui 3188 ] +"67 +[; ;ANALOG.c: 67: { +{ +"70 +[; ;ANALOG.c: 70: } +} +[e $U 3189 ] +"71 +[; ;ANALOG.c: 71: else +[e :U 3188 ] +"72 +[; ;ANALOG.c: 72: { +{ +"73 +[; ;ANALOG.c: 73: return (uiValorVoltage); +[e ) -> _uiValorVoltage `ui ] +[e $UE 3177 ] +"74 +[; ;ANALOG.c: 74: } +} +[e :U 3189 ] +"75 +[; ;ANALOG.c: 75: } +} +[e $U 3190 ] +"76 +[; ;ANALOG.c: 76: else if ( ucFlag == 2 ) +[e :U 3185 ] +[e $ ! == -> _ucFlag `i -> 2 `i 3191 ] +"77 +[; ;ANALOG.c: 77: { +{ +"80 +[; ;ANALOG.c: 80: } +} +[e $U 3192 ] +"81 +[; ;ANALOG.c: 81: else +[e :U 3191 ] +"82 +[; ;ANALOG.c: 82: { +{ +"84 +[; ;ANALOG.c: 84: } +} +[e :U 3192 ] +[e :U 3190 ] +"86 +[; ;ANALOG.c: 86: } +[e :UE 3177 ] +} +"89 +[; ;ANALOG.c: 89: void ANALOGRead (void) +[v _ANALOGRead `(v ~T0 @X0 1 ef ] +"90 +[; ;ANALOG.c: 90: { +{ +[e :U _ANALOGRead ] +[f ] +"91 +[; ;ANALOG.c: 91: uiAPPS1 = ANALOG_GetVoltage(1); +[e = _uiAPPS1 ( _ANALOG_GetVoltage (1 -> -> 1 `i `uc ] +"92 +[; ;ANALOG.c: 92: uiAPPS2 = ANALOG_GetVoltage(2); +[e = _uiAPPS2 ( _ANALOG_GetVoltage (1 -> -> 2 `i `uc ] +"93 +[; ;ANALOG.c: 93: uiTPS1 = ANALOG_GetVoltage(3); +[e = _uiTPS1 ( _ANALOG_GetVoltage (1 -> -> 3 `i `uc ] +"94 +[; ;ANALOG.c: 94: uiTPS2 = ANALOG_GetVoltage(4); +[e = _uiTPS2 ( _ANALOG_GetVoltage (1 -> -> 4 `i `uc ] +"95 +[; ;ANALOG.c: 95: __nop(); +[e ( ___nop .. ] +"96 +[; ;ANALOG.c: 96: } +[e :UE 3193 ] +} diff --git a/ETC.X/build/default/debug/ANALOG.p1.d b/ETC.X/build/default/debug/ANALOG.p1.d new file mode 100644 index 0000000..689994f --- /dev/null +++ b/ETC.X/build/default/debug/ANALOG.p1.d @@ -0,0 +1,5 @@ +build/default/debug/ANALOG.p1: \ +ANALOG.c \ +ANALOG.h \ +ETC.h \ +mcc_generated_files/adc.h diff --git a/ETC.X/build/default/debug/CLUTCH.i b/ETC.X/build/default/debug/CLUTCH.i new file mode 100644 index 0000000..a355f05 --- /dev/null +++ b/ETC.X/build/default/debug/CLUTCH.i @@ -0,0 +1,38615 @@ +# 1 "CLUTCH.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "CLUTCH.c" 2 + + + + + + + + +# 1 "./CLUTCH.h" 1 +# 31 "./CLUTCH.h" +extern unsigned char ucCLUTCHlmin; +extern unsigned char ucCLUTCHlmax; +extern unsigned char ucCLUTCHDuty; +extern unsigned char ucCLUTCHState; + + + +void CLUTCH_Init (void); +void CLUTCH_Move (unsigned char ucTargetMove, unsigned char ucMode); +void CLUTCH_AnalyseState (void); +void CLUTCHInitMove(void); +void CLUTCH_HighLevelMovements (unsigned char ucClutchAction); +# 9 "CLUTCH.c" 2 + +# 1 "./mcc_generated_files/pin_manager.h" 1 +# 54 "./mcc_generated_files/pin_manager.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 54 "./mcc_generated_files/pin_manager.h" 2 +# 402 "./mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "./mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 10 "CLUTCH.c" 2 + +# 1 "./PARAMETERS.h" 1 +# 31 "./PARAMETERS.h" +extern signed long sl_K; +extern signed long sl_K_P; +extern signed long sl_K_I; +extern signed long sl_K_D; +# 11 "CLUTCH.c" 2 + +# 1 "./GPIO.h" 1 +# 16 "./GPIO.h" +void GPIOInit (void); +void GPIO_PWM1_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +void GPIO_PWM2_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +void GPIO_INT2_desembragar (void); +# 12 "CLUTCH.c" 2 + +# 1 "./MESSAGES.h" 1 +# 16 "./MESSAGES.h" +# 1 "./mcc_generated_files/mcc.h" 1 +# 50 "./mcc_generated_files/mcc.h" +# 1 "./mcc_generated_files/device_config.h" 1 +# 50 "./mcc_generated_files/mcc.h" 2 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 53 "./mcc_generated_files/mcc.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 1 3 + + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 1 3 +# 12 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 3 +extern int errno; +# 8 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__null.h" 1 3 +# 9 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + + + +extern void init_uart(void); + +extern char getch(void); +extern char getche(void); +extern void putch(char); +extern void ungetch(char); + +extern __bit kbhit(void); + + + +extern char * cgets(char *); +extern void cputs(const char *); +# 54 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/interrupt_manager.h" 1 +# 87 "./mcc_generated_files/interrupt_manager.h" +void INTERRUPT_Initialize (void); +# 55 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/i2c1_master.h" 1 +# 54 "./mcc_generated_files/i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "./mcc_generated_files/i2c1_master.h" 2 + + + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "./mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "./mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "./mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 56 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/adc.h" 1 +# 65 "./mcc_generated_files/adc.h" +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "./mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "./mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "./mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "./mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "./mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "./mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "./mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "./mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "./mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "./mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "./mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "./mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "./mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "./mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "./mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "./mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "./mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "./mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "./mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "./mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "./mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "./mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "./mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "./mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "./mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "./mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "./mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 57 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/tmr1.h" 1 +# 101 "./mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "./mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "./mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "./mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "./mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "./mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "./mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "./mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "./mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "./mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "./mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "./mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "./mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 58 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/tmr0.h" 1 +# 106 "./mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "./mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "./mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "./mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "./mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "./mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "./mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "./mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "./mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "./mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "./mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 59 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/can1.h" 1 +# 56 "./mcc_generated_files/can1.h" +# 1 "./mcc_generated_files/can_types.h" 1 +# 65 "./mcc_generated_files/can_types.h" +typedef union +{ + uint8_t msgfields; + struct + { + uint8_t idType:1; + uint8_t frameType:1; + uint8_t dlc:4; + uint8_t formatType:1; + uint8_t brs:1; + }; +} CAN_MSG_FIELD; + +typedef struct +{ + uint32_t msgId; + CAN_MSG_FIELD field; + uint8_t *data; +} CAN_MSG_OBJ; +# 94 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NON_BRS_MODE = 0, + CAN_BRS_MODE = 1 +} CAN_MSG_OBJ_BRS_MODE; +# 109 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_STD = 0, + CAN_FRAME_EXT = 1, +} CAN_MSG_OBJ_ID_TYPE; +# 124 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_DATA = 0, + CAN_FRAME_RTR = 1, +} CAN_MSG_OBJ_FRAME_TYPE; +# 139 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_2_0_FORMAT = 0, + CAN_FD_FORMAT = 1 +} CAN_MSG_OBJ_TYPE; +# 154 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_MSG_REQUEST_SUCCESS = 0, + CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR = 1, + CAN_TX_MSG_REQUEST_BRS_ERROR = 2, + CAN_TX_MSG_REQUEST_FIFO_FULL = 3, +} CAN_TX_MSG_REQUEST_STATUS; +# 171 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NORMAL_FD_MODE = 0, + CAN_DISABLE_MODE = 1, + CAN_INTERNAL_LOOPBACK_MODE = 2, + CAN_LISTEN_ONLY_MODE = 3, + CAN_CONFIGURATION_MODE = 4, + CAN_EXTERNAL_LOOPBACK_MODE = 5, + CAN_NORMAL_2_0_MODE = 6, + CAN_RESTRICTED_OPERATION_MODE =7, +} CAN_OP_MODES; +# 192 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_OP_MODE_REQUEST_SUCCESS, + CAN_OP_MODE_REQUEST_FAIL, + CAN_OP_MODE_SYS_ERROR_OCCURED +} CAN_OP_MODE_STATUS; +# 208 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_FIFO_FULL, + CAN_TX_FIFO_AVAILABLE, +} CAN_TX_FIFO_STATUS; +# 223 "./mcc_generated_files/can_types.h" +typedef enum +{ + + DLC_0, + DLC_1, + DLC_2, + DLC_3, + DLC_4, + DLC_5, + DLC_6, + DLC_7, + DLC_8, + + + + DLC_12, + DLC_16, + DLC_20, + DLC_24, + DLC_32, + DLC_48, + DLC_64, +} CAN_DLC; +# 56 "./mcc_generated_files/can1.h" 2 + + + + + +typedef enum +{ + TXQ = 0 +} CAN1_TX_FIFO_CHANNELS; + +typedef enum +{ + FIFO1 = 1 +} CAN1_RX_FIFO_CHANNELS; +# 106 "./mcc_generated_files/can1.h" +void CAN1_Initialize(void); +# 147 "./mcc_generated_files/can1.h" +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +# 185 "./mcc_generated_files/can1.h" +CAN_OP_MODES CAN1_OperationModeGet(void); +# 235 "./mcc_generated_files/can1.h" +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +# 275 "./mcc_generated_files/can1.h" +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *rxCanMsg); +# 334 "./mcc_generated_files/can1.h" +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +# 390 "./mcc_generated_files/can1.h" +_Bool CAN1_IsBusOff(void); +# 448 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorPassive(void); +# 507 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorWarning(void); +# 566 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorActive(void); +# 614 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorPassive(void); +# 662 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorWarning(void); +# 710 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorActive(void); +# 761 "./mcc_generated_files/can1.h" +void CAN1_Sleep(void); +# 815 "./mcc_generated_files/can1.h" +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +# 857 "./mcc_generated_files/can1.h" +uint8_t CAN1_ReceivedMessageCountGet(void); +# 924 "./mcc_generated_files/can1.h" +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +# 981 "./mcc_generated_files/can1.h" +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +# 1049 "./mcc_generated_files/can1.h" +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +# 1100 "./mcc_generated_files/can1.h" +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +# 1169 "./mcc_generated_files/can1.h" +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +# 1237 "./mcc_generated_files/can1.h" +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +# 1289 "./mcc_generated_files/can1.h" +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +# 1324 "./mcc_generated_files/can1.h" +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +# 1368 "./mcc_generated_files/can1.h" +void CAN1_SetTXQnullHandler(void (*handler)(void)); + + +void CAN1_ISR(void); +void CAN1_RXI_ISR(void); +# 60 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 37 "./mcc_generated_files/drivers/i2c_simple_master.h" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 61 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/pwm2_16bit.h" 1 +# 63 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 62 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/DAC3.h" 1 +# 29 "./mcc_generated_files/DAC3.h" +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 63 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/pwm1_16bit.h" 1 +# 63 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 64 "./mcc_generated_files/mcc.h" 2 +# 79 "./mcc_generated_files/mcc.h" +void SYSTEM_Initialize(void); +# 92 "./mcc_generated_files/mcc.h" +void OSCILLATOR_Initialize(void); +# 105 "./mcc_generated_files/mcc.h" +void PMD_Initialize(void); +# 16 "./MESSAGES.h" 2 + + + + + + +CAN_MSG_OBJ msgTransmit; +CAN_MSG_OBJ msgReceipt; +uint8_t CANDATAdata[8]; + + +extern unsigned char CANDATAdata[8]; + +extern unsigned char ucTargetAccelerator; +extern unsigned char ucTargetClutch; +extern unsigned char ucTargetClutch_PREV; +extern unsigned char ucTargetBrake; +extern unsigned char ucTargetDirection; +extern unsigned char ucTargetGear; + +extern unsigned char ucAS_state; +extern unsigned char ucEBS_state; +extern unsigned char ucAMI_state; +extern unsigned char ucSteering_state; +extern unsigned char ucService_brake; +extern unsigned char ucLap_counter; +extern unsigned char ucCones_count_actual; +extern unsigned char ucCones_count_all; + +extern unsigned char ucSpeed_actual; +extern unsigned char ucSpeed_target; +extern unsigned char ucSteering_angle_actual; +extern unsigned char ucSteering_angle_target; +extern unsigned char ucBrake_hydr_actual; +extern unsigned char ucBrake_hydr_target; +extern unsigned char ucMotor_moment_actual; +extern unsigned char ucMotor_moment_target; + +extern unsigned int uiAcc_longitudinal; +extern unsigned int uiAcc_lateral; +extern unsigned int uiYaw_rate; + +extern unsigned char ucASBState; +extern unsigned char ucASRequesState; + +extern unsigned char ucASMode; + +extern unsigned char ucSTEER_WH_Clutch; +# 98 "./MESSAGES.h" +void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8); +void CANReadMessage (void); +void CANDisableErrorInterrupt (unsigned char ucInterruptSet); +# 13 "CLUTCH.c" 2 + +# 1 "./ETC.h" 1 +# 65 "./ETC.h" +unsigned int uiTPS1TableIn [21]; +unsigned char ucTPS1TableOut [21]; +unsigned int uiTPS2TableIn [21]; +unsigned char ucTPS2TableOut [21]; + +typedef struct { + + + float Kp; + float Ki; + float Kd; + + + float tau; + + + float limMin; + float limMax; + + + float limMinInt; + float limMaxInt; + + + float T; + + + float integrator; + float prevError; + float differentiator; + float prevMeasurement; + + + float out; + +} PIDController; + +PIDController pid = { 2.4f, 1.4f, 0.0f, + 0.02f, + 0.0f, 100.0f, + -10.0f, 10.0f, + 0.01f }; + + + +extern unsigned int uiAPPS1min; +extern unsigned int uiAPPS1max; +extern unsigned int uiAPPS2min; +extern unsigned int uiAPPS2max; +extern unsigned int uiTPS1min; +extern unsigned int uiTPS1max; +extern unsigned int uiTPS2min; +extern unsigned int uiTPS2max; +extern unsigned int uiAPPS1; +extern unsigned int uiAPPS2; +extern unsigned char ucAPPS_STATE; +extern unsigned long ulAPPS1calc; +extern unsigned long ulAPPS2calc; +extern unsigned int ucAPPS1Perc; +extern unsigned int ucAPPS2Perc; +extern unsigned int ucAPPS; +extern unsigned int uiTPS1; +extern unsigned int uiTPS2; +extern signed long ulTPS1calc; +extern signed long ulTPS2calc; +extern unsigned int ucTPS1Perc; +extern unsigned int ucTPS2Perc; +extern unsigned int ucTPS; +extern unsigned char ucTPS_STATE; +extern unsigned char ucTPS1_STATE; +extern unsigned char ucTPS2_STATE; +extern unsigned char ucTPS_Volts_STATE; +extern unsigned int uiETCDuty; +extern unsigned char ucETB_STATE; +extern unsigned char ucETCBeatSupervisor; +extern unsigned char ucETCFlagSupervisor; +extern unsigned char ucAPPSManual; +extern unsigned char ucETCTimerRuleTPS; +extern unsigned char ucETCTimerRuleAPPS; +extern unsigned char ucCount100msTPSError; +extern unsigned char ucCount100msAPPSError; +extern unsigned char ucETCRuleSupervisor; +extern unsigned char ucETCTargetTPSDiff; +extern unsigned char ucCount500msTPSDiff; +extern unsigned char ucETCMotorNotClose; +extern unsigned char ucETCResolveNotCloseError; +extern unsigned char ucCount500msResolveNotCloseError; + +extern unsigned int ucAPPSTargetPruebas; + +void ETCInit(void); +void APPSSend (unsigned char ucPercent); +void APPSReadmin (void); +void APPSReadmax (void); +void ETCModeSelect (unsigned char ucModeSelect); +void ETCRulesSupervision(void); +void ETCMove(unsigned char ucTargetMove, unsigned char ucMode); +void ETC_PID(signed long slTargetMove, unsigned char ucMode); +void ETCCalibrate(void); +void TPSAnalysis (void); +void APPSAnalysis (void); +void ETCXavierSupervisor (void); +void ETCManual (unsigned char ucTargetManual); +unsigned int ETCPercentCalc(signed long val, signed long min, signed long max); +void ETCRulesSensorsSupervision(void); +void ETC100msSupervisor (void); +void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactual); +void ETC500msSupervisor (void); +void PIDController_Init(PIDController *pid); +float PIDController_Update(PIDController *pid, float setpoint, float measurement); +unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +# 14 "CLUTCH.c" 2 + + + +unsigned char ucCLUTCHlmin; +unsigned char ucCLUTCHlmax; +unsigned int uiCLUTCHDuty; +unsigned char ucCLUTCHState; + + +void CLUTCH_Init (void) +{ + GPIO_PWM1_Control( 0, 50 ); + ucCLUTCHState = 0; +} + +void CLUTCH_HighLevelMovements (unsigned char ucClutchAction) +{ + unsigned char ucIndex; + + if (ucTargetClutch_PREV != ucTargetClutch) + { + switch (ucClutchAction) + { + case 3: + CLUTCH_Move(0, 1); + break; + case 1: + for (ucIndex = 60; ucIndex > 0 ; ucIndex--) + { + CLUTCH_Move(ucIndex, 1); + _delay((unsigned long)((500/60)*(10000000/4000.0))); + } + break; + case 2: + CLUTCH_Move(60, 1); + break; + case 0: + default: + + break; + } + ucTargetClutch_PREV = ucTargetClutch; + } +} + + +void CLUTCH_Move (unsigned char ucTargetMove, unsigned char ucMode) +{ + + if ( ucETCFlagSupervisor == 0x01 ) + { + + + + + + uiCLUTCHDuty = ucTargetMove * 60; + uiCLUTCHDuty = uiCLUTCHDuty / 100; + uiCLUTCHDuty = (uiCLUTCHDuty & 0xFF); + + + + + + + if ( ucMode == ucASMode ) + { +# 94 "CLUTCH.c" + if ( ucCLUTCHState < 4 ) + { + GPIO_PWM1_Control(uiCLUTCHDuty, 300); + } + } + else + { + + } + } + else + { + GPIO_PWM1_Control(0, 300); + } + +} + + +void CLUTCH_AnalyseState (void) +{ + unsigned char ucFDC1; + unsigned char ucFDC2; + + ucFDC1 = PORTBbits.RB2; + ucFDC2 = PORTAbits.RA1; + + __nop(); + + if ( ( ucFDC1 == 0x01 ) && ( ucFDC2 == 0x00 ) ) + { + ucCLUTCHState = 1; + ucCLUTCHlmin = ucCLUTCHDuty; + } + else if ( ( ucFDC1 == 0x00 ) && ( ucFDC2 == 0x01 ) ) + { + ucCLUTCHState = 2; + ucCLUTCHlmax = ucCLUTCHDuty; + } + else if ( ( ucFDC1 == 0x00 ) && ( ucFDC2 == 0x00 ) ) + { + ucCLUTCHState = 3; + } + else if ( ( ucFDC1 == 0x01 ) && ( ucFDC2 == 0x01 ) ) + { + ucCLUTCHState = 4; + } + else + { + ucCLUTCHState = 5; + } + +} + + +void CLUTCHInitMove(void) +{ + CLUTCH_Move(0, 1); + CLUTCH_AnalyseState(); + if ( ucCLUTCHState == 1 ) + { + CLUTCH_Move(30, 1); + _delay((unsigned long)((200)*(10000000/4000.0))); + CLUTCH_Move(50, 1); + _delay((unsigned long)((200)*(10000000/4000.0))); + } + CLUTCH_AnalyseState(); + if ( ucCLUTCHState == 3 ) + { + + CLUTCH_Move(70, 1); + _delay((unsigned long)((200)*(10000000/4000.0))); + CLUTCH_Move(100, 1); + _delay((unsigned long)((150)*(10000000/4000.0))); + } + CLUTCH_AnalyseState(); + if ( ucCLUTCHState == 2 ) + { + + CLUTCH_Move(0, 1); + } +} diff --git a/ETC.X/build/default/debug/CLUTCH.p1 b/ETC.X/build/default/debug/CLUTCH.p1 new file mode 100644 index 0000000..59afebf --- /dev/null +++ b/ETC.X/build/default/debug/CLUTCH.p1 @@ -0,0 +1,4026 @@ +Version 4.0 HI-TECH Software Intermediate Code +"69 ./mcc_generated_files/can_types.h +[; ;./mcc_generated_files/can_types.h: 69: { +[s S3179 :1 `uc 1 :1 `uc 1 :4 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3179 . idType frameType dlc formatType brs ] +"66 +[; ;./mcc_generated_files/can_types.h: 66: { +[u S3178 `uc 1 `S3179 1 ] +[n S3178 . msgfields . ] +"79 +[; ;./mcc_generated_files/can_types.h: 79: { +[s S3180 `ul 1 `S3178 1 `*uc 1 ] +[n S3180 . msgId field data ] +"70 ./ETC.h +[; ;./ETC.h: 70: typedef struct { +[s S3181 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 ] +[n S3181 . Kp Ki Kd tau limMin limMax limMinInt limMaxInt T integrator prevError differentiator prevMeasurement out ] +"17 ./GPIO.h +[; ;./GPIO.h: 17: void GPIO_PWM1_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +[v _GPIO_PWM1_Control `(v ~T0 @X0 0 ef2`ui`ui ] +"31 ./MESSAGES.h +[; ;./MESSAGES.h: 31: extern unsigned char ucTargetClutch_PREV; +[v _ucTargetClutch_PREV `uc ~T0 @X0 0 e ] +"30 +[; ;./MESSAGES.h: 30: extern unsigned char ucTargetClutch; +[v _ucTargetClutch `uc ~T0 @X0 0 e ] +"39 ./CLUTCH.h +[; ;./CLUTCH.h: 39: void CLUTCH_Move (unsigned char ucTargetMove, unsigned char ucMode); +[v _CLUTCH_Move `(v ~T0 @X0 0 ef2`uc`uc ] +[v F195 `(v ~T0 @X0 1 tf1`ul ] +"12 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\builtins.h +[v __delay `JF195 ~T0 @X0 0 e ] +[p i __delay ] +"140 ./ETC.h +[; ;./ETC.h: 140: extern unsigned char ucETCFlagSupervisor; +[v _ucETCFlagSupervisor `uc ~T0 @X0 0 e ] +"61 ./MESSAGES.h +[; ;./MESSAGES.h: 61: extern unsigned char ucASMode; +[v _ucASMode `uc ~T0 @X0 0 e ] +"1935 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1935: +[s S3077 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3077 . RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 ] +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[u S3076 `S3077 1 ] +[n S3076 . . ] +"1946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1946: unsigned MD1CLSYNC :1; +[v _PORTBbits `VS3076 ~T0 @X0 0 e@1231 ] +"1873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1873: unsigned OPOL :1; +[s S3075 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3075 . RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 ] +"1872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1872: unsigned :3; +[u S3074 `S3075 1 ] +[n S3074 . . ] +"1884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1884: unsigned MD1EN :1; +[v _PORTAbits `VS3074 ~T0 @X0 0 e@1230 ] +"8 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\builtins.h +[v ___nop `(v ~T0 @X0 0 ef ] +[p i ___nop ] +"33 ./CLUTCH.h +[; ;./CLUTCH.h: 33: extern unsigned char ucCLUTCHDuty; +[v _ucCLUTCHDuty `uc ~T0 @X0 0 e ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"22 ./MESSAGES.h +[; ;./MESSAGES.h: 22: CAN_MSG_OBJ msgTransmit; +[v _msgTransmit `S3180 ~T0 @X0 1 e ] +"23 +[; ;./MESSAGES.h: 23: CAN_MSG_OBJ msgReceipt; +[v _msgReceipt `S3180 ~T0 @X0 1 e ] +"24 +[; ;./MESSAGES.h: 24: uint8_t CANDATAdata[8]; +[v _CANDATAdata `uc ~T0 @X0 -> 8 `i e ] +"65 ./ETC.h +[; ;./ETC.h: 65: unsigned int uiTPS1TableIn [21]; +[v _uiTPS1TableIn `ui ~T0 @X0 -> 21 `i e ] +"66 +[; ;./ETC.h: 66: unsigned char ucTPS1TableOut [21]; +[v _ucTPS1TableOut `uc ~T0 @X0 -> 21 `i e ] +"67 +[; ;./ETC.h: 67: unsigned int uiTPS2TableIn [21]; +[v _uiTPS2TableIn `ui ~T0 @X0 -> 21 `i e ] +"68 +[; ;./ETC.h: 68: unsigned char ucTPS2TableOut [21]; +[v _ucTPS2TableOut `uc ~T0 @X0 -> 21 `i e ] +"102 +[; ;./ETC.h: 102: PIDController pid = { 2.4f, 1.4f, 0.0f, +[v _pid `S3181 ~T0 @X0 1 e ] +[i _pid +:U .. +:U .. +-> .2.4 `f +-> .1.4 `f +-> .0.0 `f +-> .0.02 `f +-> .0.0 `f +-> .100.0 `f +-U -> .10.0 `f +-> .10.0 `f +-> .0.01 `f +.. +.. +] +"17 CLUTCH.c +[; ;CLUTCH.c: 17: unsigned char ucCLUTCHlmin; +[v _ucCLUTCHlmin `uc ~T0 @X0 1 e ] +"18 +[; ;CLUTCH.c: 18: unsigned char ucCLUTCHlmax; +[v _ucCLUTCHlmax `uc ~T0 @X0 1 e ] +"19 +[; ;CLUTCH.c: 19: unsigned int uiCLUTCHDuty; +[v _uiCLUTCHDuty `ui ~T0 @X0 1 e ] +"20 +[; ;CLUTCH.c: 20: unsigned char ucCLUTCHState; +[v _ucCLUTCHState `uc ~T0 @X0 1 e ] +"23 +[; ;CLUTCH.c: 23: void CLUTCH_Init (void) +[v _CLUTCH_Init `(v ~T0 @X0 1 ef ] +"24 +[; ;CLUTCH.c: 24: { +{ +[e :U _CLUTCH_Init ] +[f ] +"25 +[; ;CLUTCH.c: 25: GPIO_PWM1_Control( 0, 50 ); +[e ( _GPIO_PWM1_Control (2 , -> -> 0 `i `ui -> -> 50 `i `ui ] +"26 +[; ;CLUTCH.c: 26: ucCLUTCHState = 0; +[e = _ucCLUTCHState -> -> 0 `i `uc ] +"27 +[; ;CLUTCH.c: 27: } +[e :UE 3182 ] +} +"29 +[; ;CLUTCH.c: 29: void CLUTCH_HighLevelMovements (unsigned char ucClutchAction) +[v _CLUTCH_HighLevelMovements `(v ~T0 @X0 1 ef1`uc ] +"30 +[; ;CLUTCH.c: 30: { +{ +[e :U _CLUTCH_HighLevelMovements ] +"29 +[; ;CLUTCH.c: 29: void CLUTCH_HighLevelMovements (unsigned char ucClutchAction) +[v _ucClutchAction `uc ~T0 @X0 1 r1 ] +"30 +[; ;CLUTCH.c: 30: { +[f ] +"31 +[; ;CLUTCH.c: 31: unsigned char ucIndex; +[v _ucIndex `uc ~T0 @X0 1 a ] +"33 +[; ;CLUTCH.c: 33: if (ucTargetClutch_PREV != ucTargetClutch) +[e $ ! != -> _ucTargetClutch_PREV `i -> _ucTargetClutch `i 3184 ] +"34 +[; ;CLUTCH.c: 34: { +{ +"35 +[; ;CLUTCH.c: 35: switch (ucClutchAction) +[e $U 3186 ] +"36 +[; ;CLUTCH.c: 36: { +{ +"37 +[; ;CLUTCH.c: 37: case 3: +[e :U 3187 ] +"38 +[; ;CLUTCH.c: 38: CLUTCH_Move(0, 1); +[e ( _CLUTCH_Move (2 , -> -> 0 `i `uc -> -> 1 `i `uc ] +"39 +[; ;CLUTCH.c: 39: break; +[e $U 3185 ] +"40 +[; ;CLUTCH.c: 40: case 1: +[e :U 3188 ] +"41 +[; ;CLUTCH.c: 41: for (ucIndex = 60; ucIndex > 0 ; ucIndex--) +{ +[e = _ucIndex -> -> 60 `i `uc ] +[e $ > -> _ucIndex `i -> 0 `i 3189 ] +[e $U 3190 ] +[e :U 3189 ] +"42 +[; ;CLUTCH.c: 42: { +{ +"43 +[; ;CLUTCH.c: 43: CLUTCH_Move(ucIndex, 1); +[e ( _CLUTCH_Move (2 , _ucIndex -> -> 1 `i `uc ] +"44 +[; ;CLUTCH.c: 44: _delay((unsigned long)((500/60)*(10000000/4000.0))); +[e ( __delay (1 -> * -> / -> 500 `i -> 60 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"45 +[; ;CLUTCH.c: 45: } +} +[e -- _ucIndex -> -> 1 `i `uc ] +[e $ > -> _ucIndex `i -> 0 `i 3189 ] +[e :U 3190 ] +} +"46 +[; ;CLUTCH.c: 46: break; +[e $U 3185 ] +"47 +[; ;CLUTCH.c: 47: case 2: +[e :U 3192 ] +"48 +[; ;CLUTCH.c: 48: CLUTCH_Move(60, 1); +[e ( _CLUTCH_Move (2 , -> -> 60 `i `uc -> -> 1 `i `uc ] +"49 +[; ;CLUTCH.c: 49: break; +[e $U 3185 ] +"50 +[; ;CLUTCH.c: 50: case 0: +[e :U 3193 ] +"51 +[; ;CLUTCH.c: 51: default: +[e :U 3194 ] +"53 +[; ;CLUTCH.c: 53: break; +[e $U 3185 ] +"54 +[; ;CLUTCH.c: 54: } +} +[e $U 3185 ] +[e :U 3186 ] +[e [\ -> _ucClutchAction `i , $ -> 3 `i 3187 + , $ -> 1 `i 3188 + , $ -> 2 `i 3192 + , $ -> 0 `i 3193 + 3194 ] +[e :U 3185 ] +"55 +[; ;CLUTCH.c: 55: ucTargetClutch_PREV = ucTargetClutch; +[e = _ucTargetClutch_PREV _ucTargetClutch ] +"56 +[; ;CLUTCH.c: 56: } +} +[e :U 3184 ] +"57 +[; ;CLUTCH.c: 57: } +[e :UE 3183 ] +} +"60 +[; ;CLUTCH.c: 60: void CLUTCH_Move (unsigned char ucTargetMove, unsigned char ucMode) +[v _CLUTCH_Move `(v ~T0 @X0 1 ef2`uc`uc ] +"61 +[; ;CLUTCH.c: 61: { +{ +[e :U _CLUTCH_Move ] +"60 +[; ;CLUTCH.c: 60: void CLUTCH_Move (unsigned char ucTargetMove, unsigned char ucMode) +[v _ucTargetMove `uc ~T0 @X0 1 r1 ] +[v _ucMode `uc ~T0 @X0 1 r2 ] +"61 +[; ;CLUTCH.c: 61: { +[f ] +"63 +[; ;CLUTCH.c: 63: if ( ucETCFlagSupervisor == 0x01 ) +[e $ ! == -> _ucETCFlagSupervisor `i -> 1 `i 3196 ] +"64 +[; ;CLUTCH.c: 64: { +{ +"70 +[; ;CLUTCH.c: 70: uiCLUTCHDuty = ucTargetMove * 60; +[e = _uiCLUTCHDuty -> * -> _ucTargetMove `i -> 60 `i `ui ] +"71 +[; ;CLUTCH.c: 71: uiCLUTCHDuty = uiCLUTCHDuty / 100; +[e = _uiCLUTCHDuty / _uiCLUTCHDuty -> -> 100 `i `ui ] +"72 +[; ;CLUTCH.c: 72: uiCLUTCHDuty = (uiCLUTCHDuty & 0xFF); +[e = _uiCLUTCHDuty & _uiCLUTCHDuty -> -> 255 `i `ui ] +"79 +[; ;CLUTCH.c: 79: if ( ucMode == ucASMode ) +[e $ ! == -> _ucMode `i -> _ucASMode `i 3197 ] +"80 +[; ;CLUTCH.c: 80: { +{ +"94 +[; ;CLUTCH.c: 94: if ( ucCLUTCHState < 4 ) +[e $ ! < -> _ucCLUTCHState `i -> 4 `i 3198 ] +"95 +[; ;CLUTCH.c: 95: { +{ +"96 +[; ;CLUTCH.c: 96: GPIO_PWM1_Control(uiCLUTCHDuty, 300); +[e ( _GPIO_PWM1_Control (2 , _uiCLUTCHDuty -> -> 300 `i `ui ] +"97 +[; ;CLUTCH.c: 97: } +} +[e :U 3198 ] +"98 +[; ;CLUTCH.c: 98: } +} +[e $U 3199 ] +"99 +[; ;CLUTCH.c: 99: else +[e :U 3197 ] +"100 +[; ;CLUTCH.c: 100: { +{ +"102 +[; ;CLUTCH.c: 102: } +} +[e :U 3199 ] +"103 +[; ;CLUTCH.c: 103: } +} +[e $U 3200 ] +"104 +[; ;CLUTCH.c: 104: else +[e :U 3196 ] +"105 +[; ;CLUTCH.c: 105: { +{ +"106 +[; ;CLUTCH.c: 106: GPIO_PWM1_Control(0, 300); +[e ( _GPIO_PWM1_Control (2 , -> -> 0 `i `ui -> -> 300 `i `ui ] +"107 +[; ;CLUTCH.c: 107: } +} +[e :U 3200 ] +"109 +[; ;CLUTCH.c: 109: } +[e :UE 3195 ] +} +"112 +[; ;CLUTCH.c: 112: void CLUTCH_AnalyseState (void) +[v _CLUTCH_AnalyseState `(v ~T0 @X0 1 ef ] +"113 +[; ;CLUTCH.c: 113: { +{ +[e :U _CLUTCH_AnalyseState ] +[f ] +"114 +[; ;CLUTCH.c: 114: unsigned char ucFDC1; +[v _ucFDC1 `uc ~T0 @X0 1 a ] +"115 +[; ;CLUTCH.c: 115: unsigned char ucFDC2; +[v _ucFDC2 `uc ~T0 @X0 1 a ] +"117 +[; ;CLUTCH.c: 117: ucFDC1 = PORTBbits.RB2; +[e = _ucFDC1 . . _PORTBbits 0 2 ] +"118 +[; ;CLUTCH.c: 118: ucFDC2 = PORTAbits.RA1; +[e = _ucFDC2 . . _PORTAbits 0 1 ] +"120 +[; ;CLUTCH.c: 120: __nop(); +[e ( ___nop .. ] +"122 +[; ;CLUTCH.c: 122: if ( ( ucFDC1 == 0x01 ) && ( ucFDC2 == 0x00 ) ) +[e $ ! && == -> _ucFDC1 `i -> 1 `i == -> _ucFDC2 `i -> 0 `i 3202 ] +"123 +[; ;CLUTCH.c: 123: { +{ +"124 +[; ;CLUTCH.c: 124: ucCLUTCHState = 1; +[e = _ucCLUTCHState -> -> 1 `i `uc ] +"125 +[; ;CLUTCH.c: 125: ucCLUTCHlmin = ucCLUTCHDuty; +[e = _ucCLUTCHlmin _ucCLUTCHDuty ] +"126 +[; ;CLUTCH.c: 126: } +} +[e $U 3203 ] +"127 +[; ;CLUTCH.c: 127: else if ( ( ucFDC1 == 0x00 ) && ( ucFDC2 == 0x01 ) ) +[e :U 3202 ] +[e $ ! && == -> _ucFDC1 `i -> 0 `i == -> _ucFDC2 `i -> 1 `i 3204 ] +"128 +[; ;CLUTCH.c: 128: { +{ +"129 +[; ;CLUTCH.c: 129: ucCLUTCHState = 2; +[e = _ucCLUTCHState -> -> 2 `i `uc ] +"130 +[; ;CLUTCH.c: 130: ucCLUTCHlmax = ucCLUTCHDuty; +[e = _ucCLUTCHlmax _ucCLUTCHDuty ] +"131 +[; ;CLUTCH.c: 131: } +} +[e $U 3205 ] +"132 +[; ;CLUTCH.c: 132: else if ( ( ucFDC1 == 0x00 ) && ( ucFDC2 == 0x00 ) ) +[e :U 3204 ] +[e $ ! && == -> _ucFDC1 `i -> 0 `i == -> _ucFDC2 `i -> 0 `i 3206 ] +"133 +[; ;CLUTCH.c: 133: { +{ +"134 +[; ;CLUTCH.c: 134: ucCLUTCHState = 3; +[e = _ucCLUTCHState -> -> 3 `i `uc ] +"135 +[; ;CLUTCH.c: 135: } +} +[e $U 3207 ] +"136 +[; ;CLUTCH.c: 136: else if ( ( ucFDC1 == 0x01 ) && ( ucFDC2 == 0x01 ) ) +[e :U 3206 ] +[e $ ! && == -> _ucFDC1 `i -> 1 `i == -> _ucFDC2 `i -> 1 `i 3208 ] +"137 +[; ;CLUTCH.c: 137: { +{ +"138 +[; ;CLUTCH.c: 138: ucCLUTCHState = 4; +[e = _ucCLUTCHState -> -> 4 `i `uc ] +"139 +[; ;CLUTCH.c: 139: } +} +[e $U 3209 ] +"140 +[; ;CLUTCH.c: 140: else +[e :U 3208 ] +"141 +[; ;CLUTCH.c: 141: { +{ +"142 +[; ;CLUTCH.c: 142: ucCLUTCHState = 5; +[e = _ucCLUTCHState -> -> 5 `i `uc ] +"143 +[; ;CLUTCH.c: 143: } +} +[e :U 3209 ] +[e :U 3207 ] +[e :U 3205 ] +[e :U 3203 ] +"145 +[; ;CLUTCH.c: 145: } +[e :UE 3201 ] +} +"148 +[; ;CLUTCH.c: 148: void CLUTCHInitMove(void) +[v _CLUTCHInitMove `(v ~T0 @X0 1 ef ] +"149 +[; ;CLUTCH.c: 149: { +{ +[e :U _CLUTCHInitMove ] +[f ] +"150 +[; ;CLUTCH.c: 150: CLUTCH_Move(0, 1); +[e ( _CLUTCH_Move (2 , -> -> 0 `i `uc -> -> 1 `i `uc ] +"151 +[; ;CLUTCH.c: 151: CLUTCH_AnalyseState(); +[e ( _CLUTCH_AnalyseState .. ] +"152 +[; ;CLUTCH.c: 152: if ( ucCLUTCHState == 1 ) +[e $ ! == -> _ucCLUTCHState `i -> 1 `i 3211 ] +"153 +[; ;CLUTCH.c: 153: { +{ +"154 +[; ;CLUTCH.c: 154: CLUTCH_Move(30, 1); +[e ( _CLUTCH_Move (2 , -> -> 30 `i `uc -> -> 1 `i `uc ] +"155 +[; ;CLUTCH.c: 155: _delay((unsigned long)((200)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 200 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"156 +[; ;CLUTCH.c: 156: CLUTCH_Move(50, 1); +[e ( _CLUTCH_Move (2 , -> -> 50 `i `uc -> -> 1 `i `uc ] +"157 +[; ;CLUTCH.c: 157: _delay((unsigned long)((200)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 200 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"158 +[; ;CLUTCH.c: 158: } +} +[e :U 3211 ] +"159 +[; ;CLUTCH.c: 159: CLUTCH_AnalyseState(); +[e ( _CLUTCH_AnalyseState .. ] +"160 +[; ;CLUTCH.c: 160: if ( ucCLUTCHState == 3 ) +[e $ ! == -> _ucCLUTCHState `i -> 3 `i 3212 ] +"161 +[; ;CLUTCH.c: 161: { +{ +"163 +[; ;CLUTCH.c: 163: CLUTCH_Move(70, 1); +[e ( _CLUTCH_Move (2 , -> -> 70 `i `uc -> -> 1 `i `uc ] +"164 +[; ;CLUTCH.c: 164: _delay((unsigned long)((200)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 200 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"165 +[; ;CLUTCH.c: 165: CLUTCH_Move(100, 1); +[e ( _CLUTCH_Move (2 , -> -> 100 `i `uc -> -> 1 `i `uc ] +"166 +[; ;CLUTCH.c: 166: _delay((unsigned long)((150)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 150 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"167 +[; ;CLUTCH.c: 167: } +} +[e :U 3212 ] +"168 +[; ;CLUTCH.c: 168: CLUTCH_AnalyseState(); +[e ( _CLUTCH_AnalyseState .. ] +"169 +[; ;CLUTCH.c: 169: if ( ucCLUTCHState == 2 ) +[e $ ! == -> _ucCLUTCHState `i -> 2 `i 3213 ] +"170 +[; ;CLUTCH.c: 170: { +{ +"172 +[; ;CLUTCH.c: 172: CLUTCH_Move(0, 1); +[e ( _CLUTCH_Move (2 , -> -> 0 `i `uc -> -> 1 `i `uc ] +"173 +[; ;CLUTCH.c: 173: } +} +[e :U 3213 ] +"174 +[; ;CLUTCH.c: 174: } +[e :UE 3210 ] +} diff --git a/ETC.X/build/default/debug/CLUTCH.p1.d b/ETC.X/build/default/debug/CLUTCH.p1.d new file mode 100644 index 0000000..8a78e91 --- /dev/null +++ b/ETC.X/build/default/debug/CLUTCH.p1.d @@ -0,0 +1,21 @@ +build/default/debug/CLUTCH.p1: \ +CLUTCH.c \ +CLUTCH.h \ +mcc_generated_files/pin_manager.h \ +PARAMETERS.h \ +GPIO.h \ +MESSAGES.h \ +mcc_generated_files/mcc.h \ +mcc_generated_files/device_config.h \ +mcc_generated_files/interrupt_manager.h \ +mcc_generated_files/i2c1_master.h \ +mcc_generated_files/adc.h \ +mcc_generated_files/tmr1.h \ +mcc_generated_files/tmr0.h \ +mcc_generated_files/can1.h \ +mcc_generated_files/can_types.h \ +mcc_generated_files/drivers/i2c_simple_master.h \ +mcc_generated_files/pwm2_16bit.h \ +mcc_generated_files/DAC3.h \ +mcc_generated_files/pwm1_16bit.h \ +ETC.h diff --git a/ETC.X/build/default/debug/ETC.i b/ETC.X/build/default/debug/ETC.i new file mode 100644 index 0000000..964f962 --- /dev/null +++ b/ETC.X/build/default/debug/ETC.i @@ -0,0 +1,39055 @@ +# 1 "ETC.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "ETC.c" 2 + + + + + + + +# 1 "./mcc_generated_files/DAC3.h" 1 +# 26 "./mcc_generated_files/DAC3.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; + + + + +typedef __int24 int24_t; + + + + +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; + + + + +typedef __uint24 uint24_t; + + + + +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 26 "./mcc_generated_files/DAC3.h" 2 + + + +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 8 "ETC.c" 2 + +# 1 "./mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 34 "./mcc_generated_files/drivers/i2c_simple_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 34 "./mcc_generated_files/drivers/i2c_simple_master.h" 2 + +# 1 "./mcc_generated_files/drivers/.././i2c1_master.h" 1 +# 56 "./mcc_generated_files/drivers/.././i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 56 "./mcc_generated_files/drivers/.././i2c1_master.h" 2 + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "./mcc_generated_files/drivers/.././i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "./mcc_generated_files/drivers/.././i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "./mcc_generated_files/drivers/.././i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "./mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "./mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "./mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "./mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "./mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "./mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "./mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 35 "./mcc_generated_files/drivers/i2c_simple_master.h" 2 + + +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 9 "ETC.c" 2 + +# 1 "./MESSAGES.h" 1 +# 16 "./MESSAGES.h" +# 1 "./mcc_generated_files/mcc.h" 1 +# 49 "./mcc_generated_files/mcc.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + + + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 49 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/device_config.h" 1 +# 50 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/pin_manager.h" 1 +# 402 "./mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "./mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 51 "./mcc_generated_files/mcc.h" 2 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 1 3 + + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 1 3 +# 12 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 3 +extern int errno; +# 8 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__null.h" 1 3 +# 9 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + + + +extern void init_uart(void); + +extern char getch(void); +extern char getche(void); +extern void putch(char); +extern void ungetch(char); + +extern __bit kbhit(void); + + + +extern char * cgets(char *); +extern void cputs(const char *); +# 54 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/interrupt_manager.h" 1 +# 87 "./mcc_generated_files/interrupt_manager.h" +void INTERRUPT_Initialize (void); +# 55 "./mcc_generated_files/mcc.h" 2 + + +# 1 "./mcc_generated_files/adc.h" 1 +# 65 "./mcc_generated_files/adc.h" +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "./mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "./mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "./mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "./mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "./mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "./mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "./mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "./mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "./mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "./mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "./mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "./mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "./mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "./mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "./mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "./mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "./mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "./mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "./mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "./mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "./mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "./mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "./mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "./mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "./mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "./mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "./mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 57 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/tmr1.h" 1 +# 101 "./mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "./mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "./mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "./mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "./mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "./mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "./mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "./mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "./mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "./mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "./mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "./mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "./mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 58 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/tmr0.h" 1 +# 106 "./mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "./mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "./mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "./mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "./mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "./mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "./mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "./mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "./mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "./mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "./mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 59 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/can1.h" 1 +# 56 "./mcc_generated_files/can1.h" +# 1 "./mcc_generated_files/can_types.h" 1 +# 65 "./mcc_generated_files/can_types.h" +typedef union +{ + uint8_t msgfields; + struct + { + uint8_t idType:1; + uint8_t frameType:1; + uint8_t dlc:4; + uint8_t formatType:1; + uint8_t brs:1; + }; +} CAN_MSG_FIELD; + +typedef struct +{ + uint32_t msgId; + CAN_MSG_FIELD field; + uint8_t *data; +} CAN_MSG_OBJ; +# 94 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NON_BRS_MODE = 0, + CAN_BRS_MODE = 1 +} CAN_MSG_OBJ_BRS_MODE; +# 109 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_STD = 0, + CAN_FRAME_EXT = 1, +} CAN_MSG_OBJ_ID_TYPE; +# 124 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_DATA = 0, + CAN_FRAME_RTR = 1, +} CAN_MSG_OBJ_FRAME_TYPE; +# 139 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_2_0_FORMAT = 0, + CAN_FD_FORMAT = 1 +} CAN_MSG_OBJ_TYPE; +# 154 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_MSG_REQUEST_SUCCESS = 0, + CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR = 1, + CAN_TX_MSG_REQUEST_BRS_ERROR = 2, + CAN_TX_MSG_REQUEST_FIFO_FULL = 3, +} CAN_TX_MSG_REQUEST_STATUS; +# 171 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NORMAL_FD_MODE = 0, + CAN_DISABLE_MODE = 1, + CAN_INTERNAL_LOOPBACK_MODE = 2, + CAN_LISTEN_ONLY_MODE = 3, + CAN_CONFIGURATION_MODE = 4, + CAN_EXTERNAL_LOOPBACK_MODE = 5, + CAN_NORMAL_2_0_MODE = 6, + CAN_RESTRICTED_OPERATION_MODE =7, +} CAN_OP_MODES; +# 192 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_OP_MODE_REQUEST_SUCCESS, + CAN_OP_MODE_REQUEST_FAIL, + CAN_OP_MODE_SYS_ERROR_OCCURED +} CAN_OP_MODE_STATUS; +# 208 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_FIFO_FULL, + CAN_TX_FIFO_AVAILABLE, +} CAN_TX_FIFO_STATUS; +# 223 "./mcc_generated_files/can_types.h" +typedef enum +{ + + DLC_0, + DLC_1, + DLC_2, + DLC_3, + DLC_4, + DLC_5, + DLC_6, + DLC_7, + DLC_8, + + + + DLC_12, + DLC_16, + DLC_20, + DLC_24, + DLC_32, + DLC_48, + DLC_64, +} CAN_DLC; +# 56 "./mcc_generated_files/can1.h" 2 + + + + + +typedef enum +{ + TXQ = 0 +} CAN1_TX_FIFO_CHANNELS; + +typedef enum +{ + FIFO1 = 1 +} CAN1_RX_FIFO_CHANNELS; +# 106 "./mcc_generated_files/can1.h" +void CAN1_Initialize(void); +# 147 "./mcc_generated_files/can1.h" +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +# 185 "./mcc_generated_files/can1.h" +CAN_OP_MODES CAN1_OperationModeGet(void); +# 235 "./mcc_generated_files/can1.h" +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +# 275 "./mcc_generated_files/can1.h" +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *rxCanMsg); +# 334 "./mcc_generated_files/can1.h" +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +# 390 "./mcc_generated_files/can1.h" +_Bool CAN1_IsBusOff(void); +# 448 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorPassive(void); +# 507 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorWarning(void); +# 566 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorActive(void); +# 614 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorPassive(void); +# 662 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorWarning(void); +# 710 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorActive(void); +# 761 "./mcc_generated_files/can1.h" +void CAN1_Sleep(void); +# 815 "./mcc_generated_files/can1.h" +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +# 857 "./mcc_generated_files/can1.h" +uint8_t CAN1_ReceivedMessageCountGet(void); +# 924 "./mcc_generated_files/can1.h" +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +# 981 "./mcc_generated_files/can1.h" +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +# 1049 "./mcc_generated_files/can1.h" +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +# 1100 "./mcc_generated_files/can1.h" +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +# 1169 "./mcc_generated_files/can1.h" +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +# 1237 "./mcc_generated_files/can1.h" +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +# 1289 "./mcc_generated_files/can1.h" +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +# 1324 "./mcc_generated_files/can1.h" +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +# 1368 "./mcc_generated_files/can1.h" +void CAN1_SetTXQnullHandler(void (*handler)(void)); + + +void CAN1_ISR(void); +void CAN1_RXI_ISR(void); +# 60 "./mcc_generated_files/mcc.h" 2 + + +# 1 "./mcc_generated_files/pwm2_16bit.h" 1 +# 63 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 62 "./mcc_generated_files/mcc.h" 2 + + +# 1 "./mcc_generated_files/pwm1_16bit.h" 1 +# 63 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 64 "./mcc_generated_files/mcc.h" 2 +# 79 "./mcc_generated_files/mcc.h" +void SYSTEM_Initialize(void); +# 92 "./mcc_generated_files/mcc.h" +void OSCILLATOR_Initialize(void); +# 105 "./mcc_generated_files/mcc.h" +void PMD_Initialize(void); +# 16 "./MESSAGES.h" 2 + + + + + + +CAN_MSG_OBJ msgTransmit; +CAN_MSG_OBJ msgReceipt; +uint8_t CANDATAdata[8]; + + +extern unsigned char CANDATAdata[8]; + +extern unsigned char ucTargetAccelerator; +extern unsigned char ucTargetClutch; +extern unsigned char ucTargetClutch_PREV; +extern unsigned char ucTargetBrake; +extern unsigned char ucTargetDirection; +extern unsigned char ucTargetGear; + +extern unsigned char ucAS_state; +extern unsigned char ucEBS_state; +extern unsigned char ucAMI_state; +extern unsigned char ucSteering_state; +extern unsigned char ucService_brake; +extern unsigned char ucLap_counter; +extern unsigned char ucCones_count_actual; +extern unsigned char ucCones_count_all; + +extern unsigned char ucSpeed_actual; +extern unsigned char ucSpeed_target; +extern unsigned char ucSteering_angle_actual; +extern unsigned char ucSteering_angle_target; +extern unsigned char ucBrake_hydr_actual; +extern unsigned char ucBrake_hydr_target; +extern unsigned char ucMotor_moment_actual; +extern unsigned char ucMotor_moment_target; + +extern unsigned int uiAcc_longitudinal; +extern unsigned int uiAcc_lateral; +extern unsigned int uiYaw_rate; + +extern unsigned char ucASBState; +extern unsigned char ucASRequesState; + +extern unsigned char ucASMode; + +extern unsigned char ucSTEER_WH_Clutch; +# 98 "./MESSAGES.h" +void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8); +void CANReadMessage (void); +void CANDisableErrorInterrupt (unsigned char ucInterruptSet); +# 10 "ETC.c" 2 + +# 1 "./mcc_generated_files/DAC3_example.h" 1 +# 27 "./mcc_generated_files/DAC3_example.h" +void DAC3_example(void); +# 11 "ETC.c" 2 + +# 1 "./ETC.h" 1 +# 65 "./ETC.h" +unsigned int uiTPS1TableIn [21]; +unsigned char ucTPS1TableOut [21]; +unsigned int uiTPS2TableIn [21]; +unsigned char ucTPS2TableOut [21]; + +typedef struct { + + + float Kp; + float Ki; + float Kd; + + + float tau; + + + float limMin; + float limMax; + + + float limMinInt; + float limMaxInt; + + + float T; + + + float integrator; + float prevError; + float differentiator; + float prevMeasurement; + + + float out; + +} PIDController; + +PIDController pid = { 2.4f, 1.4f, 0.0f, + 0.02f, + 0.0f, 100.0f, + -10.0f, 10.0f, + 0.01f }; + + + +extern unsigned int uiAPPS1min; +extern unsigned int uiAPPS1max; +extern unsigned int uiAPPS2min; +extern unsigned int uiAPPS2max; +extern unsigned int uiTPS1min; +extern unsigned int uiTPS1max; +extern unsigned int uiTPS2min; +extern unsigned int uiTPS2max; +extern unsigned int uiAPPS1; +extern unsigned int uiAPPS2; +extern unsigned char ucAPPS_STATE; +extern unsigned long ulAPPS1calc; +extern unsigned long ulAPPS2calc; +extern unsigned int ucAPPS1Perc; +extern unsigned int ucAPPS2Perc; +extern unsigned int ucAPPS; +extern unsigned int uiTPS1; +extern unsigned int uiTPS2; +extern signed long ulTPS1calc; +extern signed long ulTPS2calc; +extern unsigned int ucTPS1Perc; +extern unsigned int ucTPS2Perc; +extern unsigned int ucTPS; +extern unsigned char ucTPS_STATE; +extern unsigned char ucTPS1_STATE; +extern unsigned char ucTPS2_STATE; +extern unsigned char ucTPS_Volts_STATE; +extern unsigned int uiETCDuty; +extern unsigned char ucETB_STATE; +extern unsigned char ucETCBeatSupervisor; +extern unsigned char ucETCFlagSupervisor; +extern unsigned char ucAPPSManual; +extern unsigned char ucETCTimerRuleTPS; +extern unsigned char ucETCTimerRuleAPPS; +extern unsigned char ucCount100msTPSError; +extern unsigned char ucCount100msAPPSError; +extern unsigned char ucETCRuleSupervisor; +extern unsigned char ucETCTargetTPSDiff; +extern unsigned char ucCount500msTPSDiff; +extern unsigned char ucETCMotorNotClose; +extern unsigned char ucETCResolveNotCloseError; +extern unsigned char ucCount500msResolveNotCloseError; + +extern unsigned int ucAPPSTargetPruebas; + +void ETCInit(void); +void APPSSend (unsigned char ucPercent); +void APPSReadmin (void); +void APPSReadmax (void); +void ETCModeSelect (unsigned char ucModeSelect); +void ETCRulesSupervision(void); +void ETCMove(unsigned char ucTargetMove, unsigned char ucMode); +void ETC_PID(signed long slTargetMove, unsigned char ucMode); +void ETCCalibrate(void); +void TPSAnalysis (void); +void APPSAnalysis (void); +void ETCXavierSupervisor (void); +void ETCManual (unsigned char ucTargetManual); +unsigned int ETCPercentCalc(signed long val, signed long min, signed long max); +void ETCRulesSensorsSupervision(void); +void ETC100msSupervisor (void); +void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactual); +void ETC500msSupervisor (void); +void PIDController_Init(PIDController *pid); +float PIDController_Update(PIDController *pid, float setpoint, float measurement); +unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +# 12 "ETC.c" 2 + +# 1 "./GPIO.h" 1 +# 16 "./GPIO.h" +void GPIOInit (void); +void GPIO_PWM1_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +void GPIO_PWM2_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +void GPIO_INT2_desembragar (void); +# 13 "ETC.c" 2 + +# 1 "./PARAMETERS.h" 1 +# 31 "./PARAMETERS.h" +extern signed long sl_K; +extern signed long sl_K_P; +extern signed long sl_K_I; +extern signed long sl_K_D; +# 14 "ETC.c" 2 + +# 1 "./ANALOG.h" 1 +# 22 "./ANALOG.h" +unsigned int ANALOG_GetVoltage (unsigned char ucEntradaAnalogica); +void ANALOGRead (void); +# 15 "ETC.c" 2 + + + +unsigned int uiAPPS1min; +unsigned int uiAPPS1max; +unsigned int uiAPPS2min; +unsigned int uiAPPS2max; +unsigned int uiTPS1min; +unsigned int uiTPS1max; +unsigned int uiTPS2min; +unsigned int uiTPS2max; +unsigned int uiAPPS1; +unsigned int uiAPPS2; +unsigned char ucAPPS_STATE; +unsigned long ulAPPS1calc; +unsigned long ulAPPS2calc; +unsigned int ucAPPS1Perc; +unsigned int ucAPPS2Perc; +unsigned int ucAPPS; +unsigned int uiTPS1; +unsigned int uiTPS2; +signed long ulTPS1calc; +signed long ulTPS2calc; +unsigned int ucTPS1Perc; +unsigned int ucTPS2Perc; +unsigned int ucTPS; +unsigned char ucTPS_STATE; +unsigned char ucTPS1_STATE; +unsigned char ucTPS2_STATE; +unsigned char ucTPS_Volts_STATE; +unsigned int uiETCDuty; +unsigned char ucETB_STATE; +unsigned char ucETCBeatSupervisor = 0x00; +unsigned char ucETCFlagSupervisor = 0x00; +unsigned char ucAPPSManual; +unsigned char ucETCTimerRuleTPS = 0x00; +unsigned char ucETCTimerRuleAPPS = 0x00; +unsigned char ucCount100msTPSError = 0; +unsigned char ucCount100msAPPSError = 0; +unsigned char ucETCRuleSupervisor = 0x01; +unsigned char ucETCTargetTPSDiff = 0; +unsigned char ucCount500msTPSDiff = 0; +unsigned char ucETCMotorNotClose = 0x01; +unsigned char ucETCResolveNotCloseError = 0x00; +unsigned char ucCount500msResolveNotCloseError = 0; + + +unsigned int uiTPS1TableIn[] = {1147,1167,1169,1202,1376,1349,1385,1572,1729,1780,1900,1951,2033,2145,2251,2318,2402,2493,2774,2778,2962}; +unsigned char ucTPS1TableOut[] = { 0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100}; + +unsigned int uiTPS2TableIn[] = {2618,2603,2594,2490,2365,2273,2215,1960,1761,1708,1604,1546,1485,1393,1329,1291,1238,1178,1070,1060,999}; +unsigned char ucTPS2TableOut[] = { 0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100}; + + +unsigned int ucAPPSTargetPruebas; + + +void ETCInit(void) +{ + do { LATCbits.LATC6 = 1; } while(0); + do { LATCbits.LATC7 = 1; } while(0); + ETCCalibrate(); + PIDController_Init(&pid); +} +void APPSSend (unsigned char ucPercent) +{ + float voltage; + uint16_t dacAPPS1, dacAPPS2; + + + dacAPPS1 = (4096*ucPercent)/5; + dacAPPS2 = (4096*ucPercent)/5; + + i2c_write2ByteRegister(0x60,(dacAPPS1>>8),dacAPPS1); + + i2c_write2ByteRegister(0x61,(dacAPPS2>>8),dacAPPS2); + DAC3_example(); +} + + + + +void APPSReadmin (void) +{ + + uiAPPS1min = uiAPPS1 + 100; + uiAPPS2min = uiAPPS2 - 100; +} + +void APPSReadmax (void) +{ + + uiAPPS1max = 1990 - 100; + uiAPPS2max = 160 + 100; +} + + +void ETCModeSelect (unsigned char ucModeSelect) +{ + switch (ucModeSelect) + { + case 1: + + + do { LATAbits.LATA5 = 1; } while(0); + break; + case 0: + do { LATAbits.LATA5 = 0; } while(0); + break; + default: + do { LATAbits.LATA5 = 0; } while(0); + break; + } +} + + +void ETCRulesSensorsSupervision(void) +{ + if ( 1 == 1 ) + { + + if (ucTPS1Perc>ucTPS2Perc+30) + { + ucETCTimerRuleTPS = 0x00; + } + else if (ucTPS2Perc>ucTPS1Perc+30) + { + ucETCTimerRuleTPS = 0x00; + } + else + { + ucETCTimerRuleTPS = 0x01; + ucCount100msTPSError = 0; + } + + + if (ucAPPS1Perc>ucAPPS2Perc+30) + { + ucETCTimerRuleAPPS = 0x00; + } + else if (ucAPPS2Perc>ucAPPS1Perc+30) + { + ucETCTimerRuleAPPS = 0x00; + } + else + { + ucETCTimerRuleAPPS = 0x01; + ucCount100msAPPSError = 0; + } + } +} + +void ETC100msSupervisor (void) +{ + if ( 1 == 1 ) + { + if ( ucETCTimerRuleTPS == 0x00 ) + { + if ( ucCount100msTPSError < 255 ) + { + ucCount100msTPSError++; + } + } + if ( ucETCTimerRuleAPPS == 0x00 ) + { + if ( ucCount100msTPSError < 255 ) + { + ucCount100msAPPSError++; + } + } + if ( ucCount100msTPSError >= 2 ) + { + ucTPS_STATE |= 0x08; + ucETCRuleSupervisor = 0x00; + } + if ( ucCount100msAPPSError >= 2 ) + { + ucTPS_STATE |= 0x08; + ucETCRuleSupervisor = 0x00; + } + } +} + +void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactual) +{ + CANWriteMessage(0x500, 6, ucTPStarget, ucTPSactual, ucTPS, ucAPPS, ucTPS_STATE, 0, 0, 0); + if ( 1 == 1 ) + { + if (ucTPStarget>ucTPSactual+30) + { + ucETCTargetTPSDiff = 0x00; + } + else if (ucTPSactual>ucTPStarget+30) + { + ucETCTargetTPSDiff = 0x00; + } + else + { + ucETCTargetTPSDiff = 0x01; + ucCount500msTPSDiff = 0; + if (( ucTPSactual <= 5 ) && ( (ucTPS_STATE & 0x20) == 0x20 )) + { + ucETCResolveNotCloseError = 0x01; + } + else + { + ucETCResolveNotCloseError = 0x00; + ucCount500msResolveNotCloseError = 0; + } + } + } +} +void ETC500msSupervisor (void) +{ + if ( 1 == 1 ) + { + if ( ucETCTargetTPSDiff == 0x00 ) + { + if ( ucCount500msTPSDiff < 255 ) + { + ucCount500msTPSDiff++; + } + } + if (ucCount500msTPSDiff == 2) + { + ucTPS_STATE |= 0x10; + ucETCRuleSupervisor = 0x00; + } + else if (ucCount500msTPSDiff >= 3) + { + ucTPS_STATE |= 0x20; + ucETCMotorNotClose = 0x00; + + do { LATCbits.LATC6 = 0; } while(0); + } + if ( ucETCResolveNotCloseError == 0x01 ) + { + if ( ucCount500msResolveNotCloseError < 255 ) + { + ucCount500msResolveNotCloseError++; + } + if ( ucCount500msResolveNotCloseError >= 3 ) + { + ucETCMotorNotClose = 0x01; + ucETCResolveNotCloseError = 0x00; + ucTPS_STATE &= 0xDF; + } + } + } +} + +void ETCCalibrate(void) { + + + + + + + + GPIO_PWM2_Control(0, 600); + + _delay((unsigned long)((200)*(10000000/4000.0))); + + ANALOGRead(); + + _delay((unsigned long)((200)*(10000000/4000.0))); + uiTPS1min = uiTPS1 - 50; + uiTPS2min = uiTPS2 + 50; + uiTPS1TableIn[0]= uiTPS1 - 50; + uiTPS2TableIn[0]= uiTPS2 + 50; + __nop(); + + + GPIO_PWM2_Control(100, 600); + + _delay((unsigned long)((700)*(10000000/4000.0))); + + ANALOGRead(); + + _delay((unsigned long)((200)*(10000000/4000.0))); + uiTPS1max = uiTPS1 - 50; + uiTPS2max = uiTPS2 + 50; + uiTPS1TableIn[21 -1]= uiTPS1 - 50; + uiTPS2TableIn[21 -1]= uiTPS2 + 50; + __nop(); + + + GPIO_PWM2_Control(0, 300); +} + +void TPSAnalysis(void) +{ +# 331 "ETC.c" + ucTPS1Perc = ETCPercentCalc (uiTPS1, uiTPS1min, uiTPS1max); + ucTPS2Perc = ETCPercentCalc (uiTPS2, uiTPS2min, uiTPS2max); + + + ucTPS = ( ( ucTPS1Perc + ucTPS2Perc ) / 2 ); + __nop(); + + + + if ( ( ulTPS1calc > uiTPS1 + 50 ) || ( ulTPS1calc < uiTPS1 - 50 ) ) + { + + ucTPS_STATE |= 0x01; + } + else + { + + ucTPS_STATE |= 0xFE; + } + + if ( ( ulTPS2calc > uiTPS2 + 50 ) || ( ulTPS2calc < uiTPS2 - 50 ) ) + { + + ucTPS_STATE |= 0x02; + } + else + { + + ucTPS_STATE |= 0xFD; + } + + + if ( ucTPS_Volts_STATE == 5 ) + { + ucTPS_STATE |= 0x04; + } + else if ( ucTPS_Volts_STATE == 9 ) + { + + ucTPS_STATE &= 0xFB; + } + else if ( ucTPS_Volts_STATE == 6 ) + { + + ucTPS_STATE &= 0xFB; + } + else if ( ucTPS_Volts_STATE == 10 ) + { + ucTPS_STATE |= 0x04; + } + else + { + ucTPS_STATE |= 0x04; + } + + + + +} + +void APPSAnalysis (void) +{ +# 412 "ETC.c" + ucAPPS1Perc = ETCPercentCalc(uiAPPS1, uiAPPS1min, uiAPPS1max); + ucAPPS2Perc = ETCPercentCalc(uiAPPS2, uiAPPS2min, uiAPPS2max); + ucAPPS = ( ( ucAPPS1Perc + ucAPPS2Perc ) / 2 ); + __nop(); +} + + +void ETCMove(unsigned char ucTargetMove, unsigned char ucMode) +{ + ETCRulesMotorSupervisor (ucTargetMove, ucTPS); + + if ( ( ucETCFlagSupervisor == 0x01 ) && ( ucETCRuleSupervisor == 0x01 ) ) + { + + uiETCDuty = ucTargetMove; + + if ( ucMode == ucASMode ) + { + if ( ucASMode == 1 ) + { + + + GPIO_PWM2_Control(PIDController_Update(&pid, (float)(ucTargetMove), (float)(ucTPS)), 600); + } + else if ( ucASMode == 0 ) + { + + + GPIO_PWM2_Control(PIDController_Update(&pid, (float)(ucTargetMove), (float)(ucTPS)), 600); + } + else + { + + } + } + else + { + + } + do { LATAbits.LATA0 = 0; } while(0); + } + else + { + do { LATAbits.LATA0 = 1; } while(0); + GPIO_PWM2_Control(0, 600); + } +} + +void ETCXavierSupervisor (void) +{ + __nop(); + if ( ucASMode == 1 ) + { + if ( ucETCBeatSupervisor == 0x01 ) + { + ucETCFlagSupervisor = 0x01; + } + else + { + ucETCFlagSupervisor = 0x00; + + GPIO_PWM1_Control(0, 300); + GPIO_PWM2_Control(0, 600); + } + } + else if ( ucASMode == 0 ) + { + ucETCFlagSupervisor = 0x01; + } + +} + + +void ETCManual (unsigned char ucTargetManual) +{ + if ( ucASMode == 0 ) + { + ETCMove(ucTargetManual, 0); + + } +} + + +unsigned int ETCPercentCalc(signed long val, signed long min, signed long max) +{ + + + + + + + val = (100*(val - min))/(max - min); + if (val < 0) + { + val = 0; + } + else if (val > 100 ) + { + val = 100; + } + + return val; +} + +unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) +{ + unsigned char ucPos = 1; + signed long slResult; + unsigned int ucValCero= uiTab_in[0]; + unsigned int ucValMax= uiTab_in[ucSize-1]; + unsigned char ucValout=0; + + + if (value <= ucValCero) return ucTab_out[0]; + if (value >= ucValMax) return ucTab_out[ucSize-1]; + + + + while(value > uiTab_in[ucPos]) ucPos++; + ucValout = ucTab_out[ucPos]; + + if (value == uiTab_in[ucPos]) return ucTab_out[ucPos]; + + + slResult = ( (value - uiTab_in[ucPos-1]) * (ucTab_out[ucPos] - ucTab_out[ucPos-1]) / (uiTab_in[ucPos] - uiTab_in[ucPos-1]) + ucTab_out[ucPos-1] ); + + if ( slResult < 0 ) slResult = ucTab_out[0]; + if ( slResult > 100 ) slResult = ucTab_out[ucSize-1]; + + return slResult ; +} + +unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) +{ + unsigned char ucPos = 1; + signed long slResult; + unsigned int ucValCero= uiTab_in[0]; + unsigned int ucValMax= uiTab_in[ucSize-1]; + unsigned char ucValout=0; + + + if (value >= ucValCero) return ucTab_out[0]; + if (value <= ucValMax) return ucTab_out[ucSize-1]; + + + + while(value < uiTab_in[ucPos]) ucPos++; + ucValout = ucTab_out[ucPos]; + + if (value == uiTab_in[ucPos]) return ucTab_out[ucPos]; + + + slResult = ( ( (value - uiTab_in[ucPos-1]) * (ucTab_out[ucPos] - ucTab_out[ucPos-1]) / (uiTab_in[ucPos] - uiTab_in[ucPos-1]) ) + ucTab_out[ucPos-1] ); + + if ( slResult < 0 ) slResult = ucTab_out[0]; + if ( slResult > 100 ) slResult = ucTab_out[ucSize-1]; + + return slResult ; +} + + + +void PIDController_Init(PIDController *pid) { + + + pid->integrator = 0.0f; + pid->prevError = 0.0f; + + pid->differentiator = 0.0f; + pid->prevMeasurement = 0.0f; + + pid->out = 0.0f; + +} + +float PIDController_Update(PIDController *pid, float setpoint, float measurement) { + + + + + float error = setpoint - measurement; + + + + + + float proportional = pid->Kp * error; + + + + + + pid->integrator = pid->integrator + 0.5f * pid->Ki * pid->T * (error + pid->prevError); +# 624 "ETC.c" + pid->differentiator = -(2.0f * pid->Kd * (measurement - pid->prevMeasurement) + + (2.0f * pid->tau - pid->T) * pid->differentiator) + / (2.0f * pid->tau + pid->T); + + + + if ((pid->differentiator > 2.0f) || (pid->differentiator < -2.0f)){ + pid->integrator = 0; + } + + + + pid->out = proportional + pid->integrator + pid->differentiator; + + if (pid->out > pid->limMax) { + + pid->out = pid->limMax; + + } else if (pid->out < pid->limMin) { + + pid->out = pid->limMin; + + } + + + pid->prevError = error; + pid->prevMeasurement = measurement; + + + return pid->out; + +} diff --git a/ETC.X/build/default/debug/ETC.p1 b/ETC.X/build/default/debug/ETC.p1 new file mode 100644 index 0000000..764773b --- /dev/null +++ b/ETC.X/build/default/debug/ETC.p1 @@ -0,0 +1,5309 @@ +Version 4.0 HI-TECH Software Intermediate Code +"69 ./mcc_generated_files/can_types.h +[; ;./mcc_generated_files/can_types.h: 69: { +[s S3179 :1 `uc 1 :1 `uc 1 :4 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3179 . idType frameType dlc formatType brs ] +"66 +[; ;./mcc_generated_files/can_types.h: 66: { +[u S3178 `uc 1 `S3179 1 ] +[n S3178 . msgfields . ] +"79 +[; ;./mcc_generated_files/can_types.h: 79: { +[s S3180 `ul 1 `S3178 1 `*uc 1 ] +[n S3180 . msgId field data ] +"70 ./ETC.h +[; ;./ETC.h: 70: typedef struct { +[s S3181 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 ] +[n S3181 . Kp Ki Kd tau limMin limMax limMinInt limMaxInt T integrator prevError differentiator prevMeasurement out ] +"1604 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[s S3067 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3067 . LATC0 LATC1 LATC2 LATC3 LATC4 LATC5 LATC6 LATC7 ] +"1603 +[u S3066 `S3067 1 ] +[n S3066 . . ] +"1615 +[v _LATCbits `VS3066 ~T0 @X0 0 e@1216 ] +"163 ./ETC.h +[; ;./ETC.h: 163: void ETCCalibrate(void); +[v _ETCCalibrate `(v ~T0 @X0 0 ef ] +"173 +[; ;./ETC.h: 173: void PIDController_Init(PIDController *pid); +[v _PIDController_Init `(v ~T0 @X0 0 ef1`*S3181 ] +"40 ./mcc_generated_files/drivers/i2c_simple_master.h +[; ;./mcc_generated_files/drivers/i2c_simple_master.h: 40: void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); +[v _i2c_write2ByteRegister `(v ~T0 @X0 0 ef3`uc`uc`us ] +"27 ./mcc_generated_files/DAC3_example.h +[; ;./mcc_generated_files/DAC3_example.h: 27: void DAC3_example(void); +[v _DAC3_example `(v ~T0 @X0 0 ef ] +"1480 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1480: unsigned TU1MD :1; +[s S3063 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3063 . LATA0 LATA1 LATA2 LATA3 LATA4 LATA5 LATA6 LATA7 ] +"1479 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1479: struct { +[u S3062 `S3063 1 ] +[n S3062 . . ] +"1491 +[v _LATAbits `VS3062 ~T0 @X0 0 e@1214 ] +"98 ./MESSAGES.h +[; ;./MESSAGES.h: 98: void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8); +[v _CANWriteMessage `(v ~T0 @X0 0 ef10`ul`uc`uc`uc`uc`uc`uc`uc`uc`uc ] +"18 ./GPIO.h +[; ;./GPIO.h: 18: void GPIO_PWM2_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +[v _GPIO_PWM2_Control `(v ~T0 @X0 0 ef2`ui`ui ] +[v F606 `(v ~T0 @X0 1 tf1`ul ] +"12 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\builtins.h +[v __delay `JF606 ~T0 @X0 0 e ] +[p i __delay ] +"23 ./ANALOG.h +[; ;./ANALOG.h: 23: void ANALOGRead (void); +[v _ANALOGRead `(v ~T0 @X0 0 ef ] +"8 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\builtins.h +[v ___nop `(v ~T0 @X0 0 ef ] +[p i ___nop ] +"168 ./ETC.h +[; ;./ETC.h: 168: unsigned int ETCPercentCalc(signed long val, signed long min, signed long max); +[v _ETCPercentCalc `(ui ~T0 @X0 0 ef3`l`l`l ] +"61 ./MESSAGES.h +[; ;./MESSAGES.h: 61: extern unsigned char ucASMode; +[v _ucASMode `uc ~T0 @X0 0 e ] +"174 ./ETC.h +[; ;./ETC.h: 174: float PIDController_Update(PIDController *pid, float setpoint, float measurement); +[v _PIDController_Update `(f ~T0 @X0 0 ef3`*S3181`f`f ] +"17 ./GPIO.h +[; ;./GPIO.h: 17: void GPIO_PWM1_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +[v _GPIO_PWM1_Control `(v ~T0 @X0 0 ef2`ui`ui ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"22 ./MESSAGES.h +[; ;./MESSAGES.h: 22: CAN_MSG_OBJ msgTransmit; +[v _msgTransmit `S3180 ~T0 @X0 1 e ] +"23 +[; ;./MESSAGES.h: 23: CAN_MSG_OBJ msgReceipt; +[v _msgReceipt `S3180 ~T0 @X0 1 e ] +"24 +[; ;./MESSAGES.h: 24: uint8_t CANDATAdata[8]; +[v _CANDATAdata `uc ~T0 @X0 -> 8 `i e ] +"65 ./ETC.h +[; ;./ETC.h: 65: unsigned int uiTPS1TableIn [21]; +[v _uiTPS1TableIn `ui ~T0 @X0 -> 21 `i e ] +"66 +[; ;./ETC.h: 66: unsigned char ucTPS1TableOut [21]; +[v _ucTPS1TableOut `uc ~T0 @X0 -> 21 `i e ] +"67 +[; ;./ETC.h: 67: unsigned int uiTPS2TableIn [21]; +[v _uiTPS2TableIn `ui ~T0 @X0 -> 21 `i e ] +"68 +[; ;./ETC.h: 68: unsigned char ucTPS2TableOut [21]; +[v _ucTPS2TableOut `uc ~T0 @X0 -> 21 `i e ] +"102 +[; ;./ETC.h: 102: PIDController pid = { 2.4f, 1.4f, 0.0f, +[v _pid `S3181 ~T0 @X0 1 e ] +[i _pid +:U .. +:U .. +-> .2.4 `f +-> .1.4 `f +-> .0.0 `f +-> .0.02 `f +-> .0.0 `f +-> .100.0 `f +-U -> .10.0 `f +-> .10.0 `f +-> .0.01 `f +.. +.. +] +"18 ETC.c +[; ;ETC.c: 18: unsigned int uiAPPS1min; +[v _uiAPPS1min `ui ~T0 @X0 1 e ] +"19 +[; ;ETC.c: 19: unsigned int uiAPPS1max; +[v _uiAPPS1max `ui ~T0 @X0 1 e ] +"20 +[; ;ETC.c: 20: unsigned int uiAPPS2min; +[v _uiAPPS2min `ui ~T0 @X0 1 e ] +"21 +[; ;ETC.c: 21: unsigned int uiAPPS2max; +[v _uiAPPS2max `ui ~T0 @X0 1 e ] +"22 +[; ;ETC.c: 22: unsigned int uiTPS1min; +[v _uiTPS1min `ui ~T0 @X0 1 e ] +"23 +[; ;ETC.c: 23: unsigned int uiTPS1max; +[v _uiTPS1max `ui ~T0 @X0 1 e ] +"24 +[; ;ETC.c: 24: unsigned int uiTPS2min; +[v _uiTPS2min `ui ~T0 @X0 1 e ] +"25 +[; ;ETC.c: 25: unsigned int uiTPS2max; +[v _uiTPS2max `ui ~T0 @X0 1 e ] +"26 +[; ;ETC.c: 26: unsigned int uiAPPS1; +[v _uiAPPS1 `ui ~T0 @X0 1 e ] +"27 +[; ;ETC.c: 27: unsigned int uiAPPS2; +[v _uiAPPS2 `ui ~T0 @X0 1 e ] +"28 +[; ;ETC.c: 28: unsigned char ucAPPS_STATE; +[v _ucAPPS_STATE `uc ~T0 @X0 1 e ] +"29 +[; ;ETC.c: 29: unsigned long ulAPPS1calc; +[v _ulAPPS1calc `ul ~T0 @X0 1 e ] +"30 +[; ;ETC.c: 30: unsigned long ulAPPS2calc; +[v _ulAPPS2calc `ul ~T0 @X0 1 e ] +"31 +[; ;ETC.c: 31: unsigned int ucAPPS1Perc; +[v _ucAPPS1Perc `ui ~T0 @X0 1 e ] +"32 +[; ;ETC.c: 32: unsigned int ucAPPS2Perc; +[v _ucAPPS2Perc `ui ~T0 @X0 1 e ] +"33 +[; ;ETC.c: 33: unsigned int ucAPPS; +[v _ucAPPS `ui ~T0 @X0 1 e ] +"34 +[; ;ETC.c: 34: unsigned int uiTPS1; +[v _uiTPS1 `ui ~T0 @X0 1 e ] +"35 +[; ;ETC.c: 35: unsigned int uiTPS2; +[v _uiTPS2 `ui ~T0 @X0 1 e ] +"36 +[; ;ETC.c: 36: signed long ulTPS1calc; +[v _ulTPS1calc `l ~T0 @X0 1 e ] +"37 +[; ;ETC.c: 37: signed long ulTPS2calc; +[v _ulTPS2calc `l ~T0 @X0 1 e ] +"38 +[; ;ETC.c: 38: unsigned int ucTPS1Perc; +[v _ucTPS1Perc `ui ~T0 @X0 1 e ] +"39 +[; ;ETC.c: 39: unsigned int ucTPS2Perc; +[v _ucTPS2Perc `ui ~T0 @X0 1 e ] +"40 +[; ;ETC.c: 40: unsigned int ucTPS; +[v _ucTPS `ui ~T0 @X0 1 e ] +"41 +[; ;ETC.c: 41: unsigned char ucTPS_STATE; +[v _ucTPS_STATE `uc ~T0 @X0 1 e ] +"42 +[; ;ETC.c: 42: unsigned char ucTPS1_STATE; +[v _ucTPS1_STATE `uc ~T0 @X0 1 e ] +"43 +[; ;ETC.c: 43: unsigned char ucTPS2_STATE; +[v _ucTPS2_STATE `uc ~T0 @X0 1 e ] +"44 +[; ;ETC.c: 44: unsigned char ucTPS_Volts_STATE; +[v _ucTPS_Volts_STATE `uc ~T0 @X0 1 e ] +"45 +[; ;ETC.c: 45: unsigned int uiETCDuty; +[v _uiETCDuty `ui ~T0 @X0 1 e ] +"46 +[; ;ETC.c: 46: unsigned char ucETB_STATE; +[v _ucETB_STATE `uc ~T0 @X0 1 e ] +"47 +[; ;ETC.c: 47: unsigned char ucETCBeatSupervisor = 0x00; +[v _ucETCBeatSupervisor `uc ~T0 @X0 1 e ] +[i _ucETCBeatSupervisor +-> -> 0 `i `uc +] +"48 +[; ;ETC.c: 48: unsigned char ucETCFlagSupervisor = 0x00; +[v _ucETCFlagSupervisor `uc ~T0 @X0 1 e ] +[i _ucETCFlagSupervisor +-> -> 0 `i `uc +] +"49 +[; ;ETC.c: 49: unsigned char ucAPPSManual; +[v _ucAPPSManual `uc ~T0 @X0 1 e ] +"50 +[; ;ETC.c: 50: unsigned char ucETCTimerRuleTPS = 0x00; +[v _ucETCTimerRuleTPS `uc ~T0 @X0 1 e ] +[i _ucETCTimerRuleTPS +-> -> 0 `i `uc +] +"51 +[; ;ETC.c: 51: unsigned char ucETCTimerRuleAPPS = 0x00; +[v _ucETCTimerRuleAPPS `uc ~T0 @X0 1 e ] +[i _ucETCTimerRuleAPPS +-> -> 0 `i `uc +] +"52 +[; ;ETC.c: 52: unsigned char ucCount100msTPSError = 0; +[v _ucCount100msTPSError `uc ~T0 @X0 1 e ] +[i _ucCount100msTPSError +-> -> 0 `i `uc +] +"53 +[; ;ETC.c: 53: unsigned char ucCount100msAPPSError = 0; +[v _ucCount100msAPPSError `uc ~T0 @X0 1 e ] +[i _ucCount100msAPPSError +-> -> 0 `i `uc +] +"54 +[; ;ETC.c: 54: unsigned char ucETCRuleSupervisor = 0x01; +[v _ucETCRuleSupervisor `uc ~T0 @X0 1 e ] +[i _ucETCRuleSupervisor +-> -> 1 `i `uc +] +"55 +[; ;ETC.c: 55: unsigned char ucETCTargetTPSDiff = 0; +[v _ucETCTargetTPSDiff `uc ~T0 @X0 1 e ] +[i _ucETCTargetTPSDiff +-> -> 0 `i `uc +] +"56 +[; ;ETC.c: 56: unsigned char ucCount500msTPSDiff = 0; +[v _ucCount500msTPSDiff `uc ~T0 @X0 1 e ] +[i _ucCount500msTPSDiff +-> -> 0 `i `uc +] +"57 +[; ;ETC.c: 57: unsigned char ucETCMotorNotClose = 0x01; +[v _ucETCMotorNotClose `uc ~T0 @X0 1 e ] +[i _ucETCMotorNotClose +-> -> 1 `i `uc +] +"58 +[; ;ETC.c: 58: unsigned char ucETCResolveNotCloseError = 0x00; +[v _ucETCResolveNotCloseError `uc ~T0 @X0 1 e ] +[i _ucETCResolveNotCloseError +-> -> 0 `i `uc +] +"59 +[; ;ETC.c: 59: unsigned char ucCount500msResolveNotCloseError = 0; +[v _ucCount500msResolveNotCloseError `uc ~T0 @X0 1 e ] +[i _ucCount500msResolveNotCloseError +-> -> 0 `i `uc +] +"62 +[; ;ETC.c: 62: unsigned int uiTPS1TableIn[] = {1147,1167,1169,1202,1376,1349,1385,1572,1729,1780,1900,1951,2033,2145,2251,2318,2402,2493,2774,2778,2962}; +[v _uiTPS1TableIn `ui ~T0 @X0 -> 21 `i e ] +[i _uiTPS1TableIn +:U .. +-> -> 1147 `i `ui +-> -> 1167 `i `ui +-> -> 1169 `i `ui +-> -> 1202 `i `ui +-> -> 1376 `i `ui +-> -> 1349 `i `ui +-> -> 1385 `i `ui +-> -> 1572 `i `ui +-> -> 1729 `i `ui +-> -> 1780 `i `ui +-> -> 1900 `i `ui +-> -> 1951 `i `ui +-> -> 2033 `i `ui +-> -> 2145 `i `ui +-> -> 2251 `i `ui +-> -> 2318 `i `ui +-> -> 2402 `i `ui +-> -> 2493 `i `ui +-> -> 2774 `i `ui +-> -> 2778 `i `ui +-> -> 2962 `i `ui +.. +] +"63 +[; ;ETC.c: 63: unsigned char ucTPS1TableOut[] = { 0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100}; +[v _ucTPS1TableOut `uc ~T0 @X0 -> 21 `i e ] +[i _ucTPS1TableOut +:U .. +-> -> 0 `i `uc +-> -> 5 `i `uc +-> -> 10 `i `uc +-> -> 15 `i `uc +-> -> 20 `i `uc +-> -> 25 `i `uc +-> -> 30 `i `uc +-> -> 35 `i `uc +-> -> 40 `i `uc +-> -> 45 `i `uc +-> -> 50 `i `uc +-> -> 55 `i `uc +-> -> 60 `i `uc +-> -> 65 `i `uc +-> -> 70 `i `uc +-> -> 75 `i `uc +-> -> 80 `i `uc +-> -> 85 `i `uc +-> -> 90 `i `uc +-> -> 95 `i `uc +-> -> 100 `i `uc +.. +] +"65 +[; ;ETC.c: 65: unsigned int uiTPS2TableIn[] = {2618,2603,2594,2490,2365,2273,2215,1960,1761,1708,1604,1546,1485,1393,1329,1291,1238,1178,1070,1060,999}; +[v _uiTPS2TableIn `ui ~T0 @X0 -> 21 `i e ] +[i _uiTPS2TableIn +:U .. +-> -> 2618 `i `ui +-> -> 2603 `i `ui +-> -> 2594 `i `ui +-> -> 2490 `i `ui +-> -> 2365 `i `ui +-> -> 2273 `i `ui +-> -> 2215 `i `ui +-> -> 1960 `i `ui +-> -> 1761 `i `ui +-> -> 1708 `i `ui +-> -> 1604 `i `ui +-> -> 1546 `i `ui +-> -> 1485 `i `ui +-> -> 1393 `i `ui +-> -> 1329 `i `ui +-> -> 1291 `i `ui +-> -> 1238 `i `ui +-> -> 1178 `i `ui +-> -> 1070 `i `ui +-> -> 1060 `i `ui +-> -> 999 `i `ui +.. +] +"66 +[; ;ETC.c: 66: unsigned char ucTPS2TableOut[] = { 0, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, 100}; +[v _ucTPS2TableOut `uc ~T0 @X0 -> 21 `i e ] +[i _ucTPS2TableOut +:U .. +-> -> 0 `i `uc +-> -> 5 `i `uc +-> -> 10 `i `uc +-> -> 15 `i `uc +-> -> 20 `i `uc +-> -> 25 `i `uc +-> -> 30 `i `uc +-> -> 35 `i `uc +-> -> 40 `i `uc +-> -> 45 `i `uc +-> -> 50 `i `uc +-> -> 55 `i `uc +-> -> 60 `i `uc +-> -> 65 `i `uc +-> -> 70 `i `uc +-> -> 75 `i `uc +-> -> 80 `i `uc +-> -> 85 `i `uc +-> -> 90 `i `uc +-> -> 95 `i `uc +-> -> 100 `i `uc +.. +] +"69 +[; ;ETC.c: 69: unsigned int ucAPPSTargetPruebas; +[v _ucAPPSTargetPruebas `ui ~T0 @X0 1 e ] +"72 +[; ;ETC.c: 72: void ETCInit(void) +[v _ETCInit `(v ~T0 @X0 1 ef ] +"73 +[; ;ETC.c: 73: { +{ +[e :U _ETCInit ] +[f ] +"74 +[; ;ETC.c: 74: do { LATCbits.LATC6 = 1; } while(0); +[e :U 3185 ] +{ +[e = . . _LATCbits 0 6 -> -> 1 `i `uc ] +} +[e :U 3184 ] +"75 +[; ;ETC.c: 75: do { LATCbits.LATC7 = 1; } while(0); +[e :U 3188 ] +{ +[e = . . _LATCbits 0 7 -> -> 1 `i `uc ] +} +[e :U 3187 ] +"76 +[; ;ETC.c: 76: ETCCalibrate(); +[e ( _ETCCalibrate .. ] +"77 +[; ;ETC.c: 77: PIDController_Init(&pid); +[e ( _PIDController_Init (1 &U _pid ] +"78 +[; ;ETC.c: 78: } +[e :UE 3182 ] +} +"79 +[; ;ETC.c: 79: void APPSSend (unsigned char ucPercent) +[v _APPSSend `(v ~T0 @X0 1 ef1`uc ] +"80 +[; ;ETC.c: 80: { +{ +[e :U _APPSSend ] +"79 +[; ;ETC.c: 79: void APPSSend (unsigned char ucPercent) +[v _ucPercent `uc ~T0 @X0 1 r1 ] +"80 +[; ;ETC.c: 80: { +[f ] +"81 +[; ;ETC.c: 81: float voltage; +[v _voltage `f ~T0 @X0 1 a ] +"82 +[; ;ETC.c: 82: uint16_t dacAPPS1, dacAPPS2; +[v _dacAPPS1 `us ~T0 @X0 1 a ] +[v _dacAPPS2 `us ~T0 @X0 1 a ] +"85 +[; ;ETC.c: 85: dacAPPS1 = (4096*ucPercent)/5; +[e = _dacAPPS1 -> / * -> 4096 `i -> _ucPercent `i -> 5 `i `us ] +"86 +[; ;ETC.c: 86: dacAPPS2 = (4096*ucPercent)/5; +[e = _dacAPPS2 -> / * -> 4096 `i -> _ucPercent `i -> 5 `i `us ] +"88 +[; ;ETC.c: 88: i2c_write2ByteRegister(0x60,(dacAPPS1>>8),dacAPPS1); +[e ( _i2c_write2ByteRegister (3 , , -> -> 96 `i `uc -> >> -> _dacAPPS1 `ui -> 8 `i `uc _dacAPPS1 ] +"90 +[; ;ETC.c: 90: i2c_write2ByteRegister(0x61,(dacAPPS2>>8),dacAPPS2); +[e ( _i2c_write2ByteRegister (3 , , -> -> 97 `i `uc -> >> -> _dacAPPS2 `ui -> 8 `i `uc _dacAPPS2 ] +"91 +[; ;ETC.c: 91: DAC3_example(); +[e ( _DAC3_example .. ] +"92 +[; ;ETC.c: 92: } +[e :UE 3189 ] +} +"97 +[; ;ETC.c: 97: void APPSReadmin (void) +[v _APPSReadmin `(v ~T0 @X0 1 ef ] +"98 +[; ;ETC.c: 98: { +{ +[e :U _APPSReadmin ] +[f ] +"100 +[; ;ETC.c: 100: uiAPPS1min = uiAPPS1 + 100; +[e = _uiAPPS1min + _uiAPPS1 -> -> 100 `i `ui ] +"101 +[; ;ETC.c: 101: uiAPPS2min = uiAPPS2 - 100; +[e = _uiAPPS2min - _uiAPPS2 -> -> 100 `i `ui ] +"102 +[; ;ETC.c: 102: } +[e :UE 3190 ] +} +"104 +[; ;ETC.c: 104: void APPSReadmax (void) +[v _APPSReadmax `(v ~T0 @X0 1 ef ] +"105 +[; ;ETC.c: 105: { +{ +[e :U _APPSReadmax ] +[f ] +"107 +[; ;ETC.c: 107: uiAPPS1max = 1990 - 100; +[e = _uiAPPS1max -> - -> 1990 `i -> 100 `i `ui ] +"108 +[; ;ETC.c: 108: uiAPPS2max = 160 + 100; +[e = _uiAPPS2max -> + -> 160 `i -> 100 `i `ui ] +"109 +[; ;ETC.c: 109: } +[e :UE 3191 ] +} +"112 +[; ;ETC.c: 112: void ETCModeSelect (unsigned char ucModeSelect) +[v _ETCModeSelect `(v ~T0 @X0 1 ef1`uc ] +"113 +[; ;ETC.c: 113: { +{ +[e :U _ETCModeSelect ] +"112 +[; ;ETC.c: 112: void ETCModeSelect (unsigned char ucModeSelect) +[v _ucModeSelect `uc ~T0 @X0 1 r1 ] +"113 +[; ;ETC.c: 113: { +[f ] +"114 +[; ;ETC.c: 114: switch (ucModeSelect) +[e $U 3194 ] +"115 +[; ;ETC.c: 115: { +{ +"116 +[; ;ETC.c: 116: case 1: +[e :U 3195 ] +"119 +[; ;ETC.c: 119: do { LATAbits.LATA5 = 1; } while(0); +[e :U 3198 ] +{ +[e = . . _LATAbits 0 5 -> -> 1 `i `uc ] +} +[e :U 3197 ] +"120 +[; ;ETC.c: 120: break; +[e $U 3193 ] +"121 +[; ;ETC.c: 121: case 0: +[e :U 3199 ] +"122 +[; ;ETC.c: 122: do { LATAbits.LATA5 = 0; } while(0); +[e :U 3202 ] +{ +[e = . . _LATAbits 0 5 -> -> 0 `i `uc ] +} +[e :U 3201 ] +"123 +[; ;ETC.c: 123: break; +[e $U 3193 ] +"124 +[; ;ETC.c: 124: default: +[e :U 3203 ] +"125 +[; ;ETC.c: 125: do { LATAbits.LATA5 = 0; } while(0); +[e :U 3206 ] +{ +[e = . . _LATAbits 0 5 -> -> 0 `i `uc ] +} +[e :U 3205 ] +"126 +[; ;ETC.c: 126: break; +[e $U 3193 ] +"127 +[; ;ETC.c: 127: } +} +[e $U 3193 ] +[e :U 3194 ] +[e [\ -> _ucModeSelect `i , $ -> 1 `i 3195 + , $ -> 0 `i 3199 + 3203 ] +[e :U 3193 ] +"128 +[; ;ETC.c: 128: } +[e :UE 3192 ] +} +"131 +[; ;ETC.c: 131: void ETCRulesSensorsSupervision(void) +[v _ETCRulesSensorsSupervision `(v ~T0 @X0 1 ef ] +"132 +[; ;ETC.c: 132: { +{ +[e :U _ETCRulesSensorsSupervision ] +[f ] +"133 +[; ;ETC.c: 133: if ( 1 == 1 ) +[e $ ! == -> 1 `i -> 1 `i 3208 ] +"134 +[; ;ETC.c: 134: { +{ +"136 +[; ;ETC.c: 136: if (ucTPS1Perc>ucTPS2Perc+30) +[e $ ! > _ucTPS1Perc + _ucTPS2Perc -> -> 30 `i `ui 3209 ] +"137 +[; ;ETC.c: 137: { +{ +"138 +[; ;ETC.c: 138: ucETCTimerRuleTPS = 0x00; +[e = _ucETCTimerRuleTPS -> -> 0 `i `uc ] +"139 +[; ;ETC.c: 139: } +} +[e $U 3210 ] +"140 +[; ;ETC.c: 140: else if (ucTPS2Perc>ucTPS1Perc+30) +[e :U 3209 ] +[e $ ! > _ucTPS2Perc + _ucTPS1Perc -> -> 30 `i `ui 3211 ] +"141 +[; ;ETC.c: 141: { +{ +"142 +[; ;ETC.c: 142: ucETCTimerRuleTPS = 0x00; +[e = _ucETCTimerRuleTPS -> -> 0 `i `uc ] +"143 +[; ;ETC.c: 143: } +} +[e $U 3212 ] +"144 +[; ;ETC.c: 144: else +[e :U 3211 ] +"145 +[; ;ETC.c: 145: { +{ +"146 +[; ;ETC.c: 146: ucETCTimerRuleTPS = 0x01; +[e = _ucETCTimerRuleTPS -> -> 1 `i `uc ] +"147 +[; ;ETC.c: 147: ucCount100msTPSError = 0; +[e = _ucCount100msTPSError -> -> 0 `i `uc ] +"148 +[; ;ETC.c: 148: } +} +[e :U 3212 ] +[e :U 3210 ] +"151 +[; ;ETC.c: 151: if (ucAPPS1Perc>ucAPPS2Perc+30) +[e $ ! > _ucAPPS1Perc + _ucAPPS2Perc -> -> 30 `i `ui 3213 ] +"152 +[; ;ETC.c: 152: { +{ +"153 +[; ;ETC.c: 153: ucETCTimerRuleAPPS = 0x00; +[e = _ucETCTimerRuleAPPS -> -> 0 `i `uc ] +"154 +[; ;ETC.c: 154: } +} +[e $U 3214 ] +"155 +[; ;ETC.c: 155: else if (ucAPPS2Perc>ucAPPS1Perc+30) +[e :U 3213 ] +[e $ ! > _ucAPPS2Perc + _ucAPPS1Perc -> -> 30 `i `ui 3215 ] +"156 +[; ;ETC.c: 156: { +{ +"157 +[; ;ETC.c: 157: ucETCTimerRuleAPPS = 0x00; +[e = _ucETCTimerRuleAPPS -> -> 0 `i `uc ] +"158 +[; ;ETC.c: 158: } +} +[e $U 3216 ] +"159 +[; ;ETC.c: 159: else +[e :U 3215 ] +"160 +[; ;ETC.c: 160: { +{ +"161 +[; ;ETC.c: 161: ucETCTimerRuleAPPS = 0x01; +[e = _ucETCTimerRuleAPPS -> -> 1 `i `uc ] +"162 +[; ;ETC.c: 162: ucCount100msAPPSError = 0; +[e = _ucCount100msAPPSError -> -> 0 `i `uc ] +"163 +[; ;ETC.c: 163: } +} +[e :U 3216 ] +[e :U 3214 ] +"164 +[; ;ETC.c: 164: } +} +[e :U 3208 ] +"165 +[; ;ETC.c: 165: } +[e :UE 3207 ] +} +"167 +[; ;ETC.c: 167: void ETC100msSupervisor (void) +[v _ETC100msSupervisor `(v ~T0 @X0 1 ef ] +"168 +[; ;ETC.c: 168: { +{ +[e :U _ETC100msSupervisor ] +[f ] +"169 +[; ;ETC.c: 169: if ( 1 == 1 ) +[e $ ! == -> 1 `i -> 1 `i 3218 ] +"170 +[; ;ETC.c: 170: { +{ +"171 +[; ;ETC.c: 171: if ( ucETCTimerRuleTPS == 0x00 ) +[e $ ! == -> _ucETCTimerRuleTPS `i -> 0 `i 3219 ] +"172 +[; ;ETC.c: 172: { +{ +"173 +[; ;ETC.c: 173: if ( ucCount100msTPSError < 255 ) +[e $ ! < -> _ucCount100msTPSError `i -> 255 `i 3220 ] +"174 +[; ;ETC.c: 174: { +{ +"175 +[; ;ETC.c: 175: ucCount100msTPSError++; +[e ++ _ucCount100msTPSError -> -> 1 `i `uc ] +"176 +[; ;ETC.c: 176: } +} +[e :U 3220 ] +"177 +[; ;ETC.c: 177: } +} +[e :U 3219 ] +"178 +[; ;ETC.c: 178: if ( ucETCTimerRuleAPPS == 0x00 ) +[e $ ! == -> _ucETCTimerRuleAPPS `i -> 0 `i 3221 ] +"179 +[; ;ETC.c: 179: { +{ +"180 +[; ;ETC.c: 180: if ( ucCount100msTPSError < 255 ) +[e $ ! < -> _ucCount100msTPSError `i -> 255 `i 3222 ] +"181 +[; ;ETC.c: 181: { +{ +"182 +[; ;ETC.c: 182: ucCount100msAPPSError++; +[e ++ _ucCount100msAPPSError -> -> 1 `i `uc ] +"183 +[; ;ETC.c: 183: } +} +[e :U 3222 ] +"184 +[; ;ETC.c: 184: } +} +[e :U 3221 ] +"185 +[; ;ETC.c: 185: if ( ucCount100msTPSError >= 2 ) +[e $ ! >= -> _ucCount100msTPSError `i -> 2 `i 3223 ] +"186 +[; ;ETC.c: 186: { +{ +"187 +[; ;ETC.c: 187: ucTPS_STATE |= 0x08; +[e =| _ucTPS_STATE -> -> 8 `i `uc ] +"188 +[; ;ETC.c: 188: ucETCRuleSupervisor = 0x00; +[e = _ucETCRuleSupervisor -> -> 0 `i `uc ] +"189 +[; ;ETC.c: 189: } +} +[e :U 3223 ] +"190 +[; ;ETC.c: 190: if ( ucCount100msAPPSError >= 2 ) +[e $ ! >= -> _ucCount100msAPPSError `i -> 2 `i 3224 ] +"191 +[; ;ETC.c: 191: { +{ +"192 +[; ;ETC.c: 192: ucTPS_STATE |= 0x08; +[e =| _ucTPS_STATE -> -> 8 `i `uc ] +"193 +[; ;ETC.c: 193: ucETCRuleSupervisor = 0x00; +[e = _ucETCRuleSupervisor -> -> 0 `i `uc ] +"194 +[; ;ETC.c: 194: } +} +[e :U 3224 ] +"195 +[; ;ETC.c: 195: } +} +[e :U 3218 ] +"196 +[; ;ETC.c: 196: } +[e :UE 3217 ] +} +"198 +[; ;ETC.c: 198: void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactual) +[v _ETCRulesMotorSupervisor `(v ~T0 @X0 1 ef2`uc`uc ] +"199 +[; ;ETC.c: 199: { +{ +[e :U _ETCRulesMotorSupervisor ] +"198 +[; ;ETC.c: 198: void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactual) +[v _ucTPStarget `uc ~T0 @X0 1 r1 ] +[v _ucTPSactual `uc ~T0 @X0 1 r2 ] +"199 +[; ;ETC.c: 199: { +[f ] +"200 +[; ;ETC.c: 200: CANWriteMessage(0x500, 6, ucTPStarget, ucTPSactual, ucTPS, ucAPPS, ucTPS_STATE, 0, 0, 0); +[e ( _CANWriteMessage (4 , , , , , , , , , -> -> -> 1280 `i `l `ul -> -> 6 `i `uc _ucTPStarget _ucTPSactual -> _ucTPS `uc -> _ucAPPS `uc _ucTPS_STATE -> -> 0 `i `uc -> -> 0 `i `uc -> -> 0 `i `uc ] +"201 +[; ;ETC.c: 201: if ( 1 == 1 ) +[e $ ! == -> 1 `i -> 1 `i 3226 ] +"202 +[; ;ETC.c: 202: { +{ +"203 +[; ;ETC.c: 203: if (ucTPStarget>ucTPSactual+30) +[e $ ! > -> _ucTPStarget `i + -> _ucTPSactual `i -> 30 `i 3227 ] +"204 +[; ;ETC.c: 204: { +{ +"205 +[; ;ETC.c: 205: ucETCTargetTPSDiff = 0x00; +[e = _ucETCTargetTPSDiff -> -> 0 `i `uc ] +"206 +[; ;ETC.c: 206: } +} +[e $U 3228 ] +"207 +[; ;ETC.c: 207: else if (ucTPSactual>ucTPStarget+30) +[e :U 3227 ] +[e $ ! > -> _ucTPSactual `i + -> _ucTPStarget `i -> 30 `i 3229 ] +"208 +[; ;ETC.c: 208: { +{ +"209 +[; ;ETC.c: 209: ucETCTargetTPSDiff = 0x00; +[e = _ucETCTargetTPSDiff -> -> 0 `i `uc ] +"210 +[; ;ETC.c: 210: } +} +[e $U 3230 ] +"211 +[; ;ETC.c: 211: else +[e :U 3229 ] +"212 +[; ;ETC.c: 212: { +{ +"213 +[; ;ETC.c: 213: ucETCTargetTPSDiff = 0x01; +[e = _ucETCTargetTPSDiff -> -> 1 `i `uc ] +"214 +[; ;ETC.c: 214: ucCount500msTPSDiff = 0; +[e = _ucCount500msTPSDiff -> -> 0 `i `uc ] +"215 +[; ;ETC.c: 215: if (( ucTPSactual <= 5 ) && ( (ucTPS_STATE & 0x20) == 0x20 )) +[e $ ! && <= -> _ucTPSactual `i -> 5 `i == & -> _ucTPS_STATE `i -> 32 `i -> 32 `i 3231 ] +"216 +[; ;ETC.c: 216: { +{ +"217 +[; ;ETC.c: 217: ucETCResolveNotCloseError = 0x01; +[e = _ucETCResolveNotCloseError -> -> 1 `i `uc ] +"218 +[; ;ETC.c: 218: } +} +[e $U 3232 ] +"219 +[; ;ETC.c: 219: else +[e :U 3231 ] +"220 +[; ;ETC.c: 220: { +{ +"221 +[; ;ETC.c: 221: ucETCResolveNotCloseError = 0x00; +[e = _ucETCResolveNotCloseError -> -> 0 `i `uc ] +"222 +[; ;ETC.c: 222: ucCount500msResolveNotCloseError = 0; +[e = _ucCount500msResolveNotCloseError -> -> 0 `i `uc ] +"223 +[; ;ETC.c: 223: } +} +[e :U 3232 ] +"224 +[; ;ETC.c: 224: } +} +[e :U 3230 ] +[e :U 3228 ] +"225 +[; ;ETC.c: 225: } +} +[e :U 3226 ] +"226 +[; ;ETC.c: 226: } +[e :UE 3225 ] +} +"227 +[; ;ETC.c: 227: void ETC500msSupervisor (void) +[v _ETC500msSupervisor `(v ~T0 @X0 1 ef ] +"228 +[; ;ETC.c: 228: { +{ +[e :U _ETC500msSupervisor ] +[f ] +"229 +[; ;ETC.c: 229: if ( 1 == 1 ) +[e $ ! == -> 1 `i -> 1 `i 3234 ] +"230 +[; ;ETC.c: 230: { +{ +"231 +[; ;ETC.c: 231: if ( ucETCTargetTPSDiff == 0x00 ) +[e $ ! == -> _ucETCTargetTPSDiff `i -> 0 `i 3235 ] +"232 +[; ;ETC.c: 232: { +{ +"233 +[; ;ETC.c: 233: if ( ucCount500msTPSDiff < 255 ) +[e $ ! < -> _ucCount500msTPSDiff `i -> 255 `i 3236 ] +"234 +[; ;ETC.c: 234: { +{ +"235 +[; ;ETC.c: 235: ucCount500msTPSDiff++; +[e ++ _ucCount500msTPSDiff -> -> 1 `i `uc ] +"236 +[; ;ETC.c: 236: } +} +[e :U 3236 ] +"237 +[; ;ETC.c: 237: } +} +[e :U 3235 ] +"238 +[; ;ETC.c: 238: if (ucCount500msTPSDiff == 2) +[e $ ! == -> _ucCount500msTPSDiff `i -> 2 `i 3237 ] +"239 +[; ;ETC.c: 239: { +{ +"240 +[; ;ETC.c: 240: ucTPS_STATE |= 0x10; +[e =| _ucTPS_STATE -> -> 16 `i `uc ] +"241 +[; ;ETC.c: 241: ucETCRuleSupervisor = 0x00; +[e = _ucETCRuleSupervisor -> -> 0 `i `uc ] +"242 +[; ;ETC.c: 242: } +} +[e $U 3238 ] +"243 +[; ;ETC.c: 243: else if (ucCount500msTPSDiff >= 3) +[e :U 3237 ] +[e $ ! >= -> _ucCount500msTPSDiff `i -> 3 `i 3239 ] +"244 +[; ;ETC.c: 244: { +{ +"245 +[; ;ETC.c: 245: ucTPS_STATE |= 0x20; +[e =| _ucTPS_STATE -> -> 32 `i `uc ] +"246 +[; ;ETC.c: 246: ucETCMotorNotClose = 0x00; +[e = _ucETCMotorNotClose -> -> 0 `i `uc ] +"248 +[; ;ETC.c: 248: do { LATCbits.LATC6 = 0; } while(0); +[e :U 3242 ] +{ +[e = . . _LATCbits 0 6 -> -> 0 `i `uc ] +} +[e :U 3241 ] +"249 +[; ;ETC.c: 249: } +} +[e :U 3239 ] +[e :U 3238 ] +"250 +[; ;ETC.c: 250: if ( ucETCResolveNotCloseError == 0x01 ) +[e $ ! == -> _ucETCResolveNotCloseError `i -> 1 `i 3243 ] +"251 +[; ;ETC.c: 251: { +{ +"252 +[; ;ETC.c: 252: if ( ucCount500msResolveNotCloseError < 255 ) +[e $ ! < -> _ucCount500msResolveNotCloseError `i -> 255 `i 3244 ] +"253 +[; ;ETC.c: 253: { +{ +"254 +[; ;ETC.c: 254: ucCount500msResolveNotCloseError++; +[e ++ _ucCount500msResolveNotCloseError -> -> 1 `i `uc ] +"255 +[; ;ETC.c: 255: } +} +[e :U 3244 ] +"256 +[; ;ETC.c: 256: if ( ucCount500msResolveNotCloseError >= 3 ) +[e $ ! >= -> _ucCount500msResolveNotCloseError `i -> 3 `i 3245 ] +"257 +[; ;ETC.c: 257: { +{ +"258 +[; ;ETC.c: 258: ucETCMotorNotClose = 0x01; +[e = _ucETCMotorNotClose -> -> 1 `i `uc ] +"259 +[; ;ETC.c: 259: ucETCResolveNotCloseError = 0x00; +[e = _ucETCResolveNotCloseError -> -> 0 `i `uc ] +"260 +[; ;ETC.c: 260: ucTPS_STATE &= 0xDF; +[e =& _ucTPS_STATE -> -> 223 `i `uc ] +"261 +[; ;ETC.c: 261: } +} +[e :U 3245 ] +"262 +[; ;ETC.c: 262: } +} +[e :U 3243 ] +"263 +[; ;ETC.c: 263: } +} +[e :U 3234 ] +"264 +[; ;ETC.c: 264: } +[e :UE 3233 ] +} +"266 +[; ;ETC.c: 266: void ETCCalibrate(void) { +[v _ETCCalibrate `(v ~T0 @X0 1 ef ] +{ +[e :U _ETCCalibrate ] +[f ] +"274 +[; ;ETC.c: 274: GPIO_PWM2_Control(0, 600); +[e ( _GPIO_PWM2_Control (2 , -> -> 0 `i `ui -> -> 600 `i `ui ] +"276 +[; ;ETC.c: 276: _delay((unsigned long)((200)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 200 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"278 +[; ;ETC.c: 278: ANALOGRead(); +[e ( _ANALOGRead .. ] +"280 +[; ;ETC.c: 280: _delay((unsigned long)((200)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 200 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"281 +[; ;ETC.c: 281: uiTPS1min = uiTPS1 - 50; +[e = _uiTPS1min - _uiTPS1 -> -> 50 `i `ui ] +"282 +[; ;ETC.c: 282: uiTPS2min = uiTPS2 + 50; +[e = _uiTPS2min + _uiTPS2 -> -> 50 `i `ui ] +"283 +[; ;ETC.c: 283: uiTPS1TableIn[0]= uiTPS1 - 50; +[e = *U + &U _uiTPS1TableIn * -> -> -> 0 `i `ui `ux -> -> # *U &U _uiTPS1TableIn `ui `ux - _uiTPS1 -> -> 50 `i `ui ] +"284 +[; ;ETC.c: 284: uiTPS2TableIn[0]= uiTPS2 + 50; +[e = *U + &U _uiTPS2TableIn * -> -> -> 0 `i `ui `ux -> -> # *U &U _uiTPS2TableIn `ui `ux + _uiTPS2 -> -> 50 `i `ui ] +"285 +[; ;ETC.c: 285: __nop(); +[e ( ___nop .. ] +"288 +[; ;ETC.c: 288: GPIO_PWM2_Control(100, 600); +[e ( _GPIO_PWM2_Control (2 , -> -> 100 `i `ui -> -> 600 `i `ui ] +"290 +[; ;ETC.c: 290: _delay((unsigned long)((700)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 700 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"292 +[; ;ETC.c: 292: ANALOGRead(); +[e ( _ANALOGRead .. ] +"294 +[; ;ETC.c: 294: _delay((unsigned long)((200)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 200 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"295 +[; ;ETC.c: 295: uiTPS1max = uiTPS1 - 50; +[e = _uiTPS1max - _uiTPS1 -> -> 50 `i `ui ] +"296 +[; ;ETC.c: 296: uiTPS2max = uiTPS2 + 50; +[e = _uiTPS2max + _uiTPS2 -> -> 50 `i `ui ] +"297 +[; ;ETC.c: 297: uiTPS1TableIn[21 -1]= uiTPS1 - 50; +[e = *U + &U _uiTPS1TableIn * -> -> - -> 21 `i -> 1 `i `ui `ux -> -> # *U &U _uiTPS1TableIn `ui `ux - _uiTPS1 -> -> 50 `i `ui ] +"298 +[; ;ETC.c: 298: uiTPS2TableIn[21 -1]= uiTPS2 + 50; +[e = *U + &U _uiTPS2TableIn * -> -> - -> 21 `i -> 1 `i `ui `ux -> -> # *U &U _uiTPS2TableIn `ui `ux + _uiTPS2 -> -> 50 `i `ui ] +"299 +[; ;ETC.c: 299: __nop(); +[e ( ___nop .. ] +"302 +[; ;ETC.c: 302: GPIO_PWM2_Control(0, 300); +[e ( _GPIO_PWM2_Control (2 , -> -> 0 `i `ui -> -> 300 `i `ui ] +"303 +[; ;ETC.c: 303: } +[e :UE 3246 ] +} +"305 +[; ;ETC.c: 305: void TPSAnalysis(void) +[v _TPSAnalysis `(v ~T0 @X0 1 ef ] +"306 +[; ;ETC.c: 306: { +{ +[e :U _TPSAnalysis ] +[f ] +"331 +[; ;ETC.c: 331: ucTPS1Perc = ETCPercentCalc (uiTPS1, uiTPS1min, uiTPS1max); +[e = _ucTPS1Perc ( _ETCPercentCalc (3 , , -> _uiTPS1 `l -> _uiTPS1min `l -> _uiTPS1max `l ] +"332 +[; ;ETC.c: 332: ucTPS2Perc = ETCPercentCalc (uiTPS2, uiTPS2min, uiTPS2max); +[e = _ucTPS2Perc ( _ETCPercentCalc (3 , , -> _uiTPS2 `l -> _uiTPS2min `l -> _uiTPS2max `l ] +"335 +[; ;ETC.c: 335: ucTPS = ( ( ucTPS1Perc + ucTPS2Perc ) / 2 ); +[e = _ucTPS / + _ucTPS1Perc _ucTPS2Perc -> -> 2 `i `ui ] +"336 +[; ;ETC.c: 336: __nop(); +[e ( ___nop .. ] +"340 +[; ;ETC.c: 340: if ( ( ulTPS1calc > uiTPS1 + 50 ) || ( ulTPS1calc < uiTPS1 - 50 ) ) +[e $ ! || > _ulTPS1calc -> + _uiTPS1 -> -> 50 `i `ui `l < _ulTPS1calc -> - _uiTPS1 -> -> 50 `i `ui `l 3248 ] +"341 +[; ;ETC.c: 341: { +{ +"343 +[; ;ETC.c: 343: ucTPS_STATE |= 0x01; +[e =| _ucTPS_STATE -> -> 1 `i `uc ] +"344 +[; ;ETC.c: 344: } +} +[e $U 3249 ] +"345 +[; ;ETC.c: 345: else +[e :U 3248 ] +"346 +[; ;ETC.c: 346: { +{ +"348 +[; ;ETC.c: 348: ucTPS_STATE |= 0xFE; +[e =| _ucTPS_STATE -> -> 254 `i `uc ] +"349 +[; ;ETC.c: 349: } +} +[e :U 3249 ] +"351 +[; ;ETC.c: 351: if ( ( ulTPS2calc > uiTPS2 + 50 ) || ( ulTPS2calc < uiTPS2 - 50 ) ) +[e $ ! || > _ulTPS2calc -> + _uiTPS2 -> -> 50 `i `ui `l < _ulTPS2calc -> - _uiTPS2 -> -> 50 `i `ui `l 3250 ] +"352 +[; ;ETC.c: 352: { +{ +"354 +[; ;ETC.c: 354: ucTPS_STATE |= 0x02; +[e =| _ucTPS_STATE -> -> 2 `i `uc ] +"355 +[; ;ETC.c: 355: } +} +[e $U 3251 ] +"356 +[; ;ETC.c: 356: else +[e :U 3250 ] +"357 +[; ;ETC.c: 357: { +{ +"359 +[; ;ETC.c: 359: ucTPS_STATE |= 0xFD; +[e =| _ucTPS_STATE -> -> 253 `i `uc ] +"360 +[; ;ETC.c: 360: } +} +[e :U 3251 ] +"363 +[; ;ETC.c: 363: if ( ucTPS_Volts_STATE == 5 ) +[e $ ! == -> _ucTPS_Volts_STATE `i -> 5 `i 3252 ] +"364 +[; ;ETC.c: 364: { +{ +"365 +[; ;ETC.c: 365: ucTPS_STATE |= 0x04; +[e =| _ucTPS_STATE -> -> 4 `i `uc ] +"366 +[; ;ETC.c: 366: } +} +[e $U 3253 ] +"367 +[; ;ETC.c: 367: else if ( ucTPS_Volts_STATE == 9 ) +[e :U 3252 ] +[e $ ! == -> _ucTPS_Volts_STATE `i -> 9 `i 3254 ] +"368 +[; ;ETC.c: 368: { +{ +"370 +[; ;ETC.c: 370: ucTPS_STATE &= 0xFB; +[e =& _ucTPS_STATE -> -> 251 `i `uc ] +"371 +[; ;ETC.c: 371: } +} +[e $U 3255 ] +"372 +[; ;ETC.c: 372: else if ( ucTPS_Volts_STATE == 6 ) +[e :U 3254 ] +[e $ ! == -> _ucTPS_Volts_STATE `i -> 6 `i 3256 ] +"373 +[; ;ETC.c: 373: { +{ +"375 +[; ;ETC.c: 375: ucTPS_STATE &= 0xFB; +[e =& _ucTPS_STATE -> -> 251 `i `uc ] +"376 +[; ;ETC.c: 376: } +} +[e $U 3257 ] +"377 +[; ;ETC.c: 377: else if ( ucTPS_Volts_STATE == 10 ) +[e :U 3256 ] +[e $ ! == -> _ucTPS_Volts_STATE `i -> 10 `i 3258 ] +"378 +[; ;ETC.c: 378: { +{ +"379 +[; ;ETC.c: 379: ucTPS_STATE |= 0x04; +[e =| _ucTPS_STATE -> -> 4 `i `uc ] +"380 +[; ;ETC.c: 380: } +} +[e $U 3259 ] +"381 +[; ;ETC.c: 381: else +[e :U 3258 ] +"382 +[; ;ETC.c: 382: { +{ +"383 +[; ;ETC.c: 383: ucTPS_STATE |= 0x04; +[e =| _ucTPS_STATE -> -> 4 `i `uc ] +"384 +[; ;ETC.c: 384: } +} +[e :U 3259 ] +[e :U 3257 ] +[e :U 3255 ] +[e :U 3253 ] +"389 +[; ;ETC.c: 389: } +[e :UE 3247 ] +} +"391 +[; ;ETC.c: 391: void APPSAnalysis (void) +[v _APPSAnalysis `(v ~T0 @X0 1 ef ] +"392 +[; ;ETC.c: 392: { +{ +[e :U _APPSAnalysis ] +[f ] +"412 +[; ;ETC.c: 412: ucAPPS1Perc = ETCPercentCalc(uiAPPS1, uiAPPS1min, uiAPPS1max); +[e = _ucAPPS1Perc ( _ETCPercentCalc (3 , , -> _uiAPPS1 `l -> _uiAPPS1min `l -> _uiAPPS1max `l ] +"413 +[; ;ETC.c: 413: ucAPPS2Perc = ETCPercentCalc(uiAPPS2, uiAPPS2min, uiAPPS2max); +[e = _ucAPPS2Perc ( _ETCPercentCalc (3 , , -> _uiAPPS2 `l -> _uiAPPS2min `l -> _uiAPPS2max `l ] +"414 +[; ;ETC.c: 414: ucAPPS = ( ( ucAPPS1Perc + ucAPPS2Perc ) / 2 ); +[e = _ucAPPS / + _ucAPPS1Perc _ucAPPS2Perc -> -> 2 `i `ui ] +"415 +[; ;ETC.c: 415: __nop(); +[e ( ___nop .. ] +"416 +[; ;ETC.c: 416: } +[e :UE 3260 ] +} +"419 +[; ;ETC.c: 419: void ETCMove(unsigned char ucTargetMove, unsigned char ucMode) +[v _ETCMove `(v ~T0 @X0 1 ef2`uc`uc ] +"420 +[; ;ETC.c: 420: { +{ +[e :U _ETCMove ] +"419 +[; ;ETC.c: 419: void ETCMove(unsigned char ucTargetMove, unsigned char ucMode) +[v _ucTargetMove `uc ~T0 @X0 1 r1 ] +[v _ucMode `uc ~T0 @X0 1 r2 ] +"420 +[; ;ETC.c: 420: { +[f ] +"421 +[; ;ETC.c: 421: ETCRulesMotorSupervisor (ucTargetMove, ucTPS); +[e ( _ETCRulesMotorSupervisor (2 , _ucTargetMove -> _ucTPS `uc ] +"423 +[; ;ETC.c: 423: if ( ( ucETCFlagSupervisor == 0x01 ) && ( ucETCRuleSupervisor == 0x01 ) ) +[e $ ! && == -> _ucETCFlagSupervisor `i -> 1 `i == -> _ucETCRuleSupervisor `i -> 1 `i 3262 ] +"424 +[; ;ETC.c: 424: { +{ +"426 +[; ;ETC.c: 426: uiETCDuty = ucTargetMove; +[e = _uiETCDuty -> _ucTargetMove `ui ] +"428 +[; ;ETC.c: 428: if ( ucMode == ucASMode ) +[e $ ! == -> _ucMode `i -> _ucASMode `i 3263 ] +"429 +[; ;ETC.c: 429: { +{ +"430 +[; ;ETC.c: 430: if ( ucASMode == 1 ) +[e $ ! == -> _ucASMode `i -> 1 `i 3264 ] +"431 +[; ;ETC.c: 431: { +{ +"434 +[; ;ETC.c: 434: GPIO_PWM2_Control(PIDController_Update(&pid, (float)(ucTargetMove), (float)(ucTPS)), 600); +[e ( _GPIO_PWM2_Control (2 , -> ( _PIDController_Update (3 , , &U _pid -> _ucTargetMove `f -> _ucTPS `f `ui -> -> 600 `i `ui ] +"435 +[; ;ETC.c: 435: } +} +[e $U 3265 ] +"436 +[; ;ETC.c: 436: else if ( ucASMode == 0 ) +[e :U 3264 ] +[e $ ! == -> _ucASMode `i -> 0 `i 3266 ] +"437 +[; ;ETC.c: 437: { +{ +"440 +[; ;ETC.c: 440: GPIO_PWM2_Control(PIDController_Update(&pid, (float)(ucTargetMove), (float)(ucTPS)), 600); +[e ( _GPIO_PWM2_Control (2 , -> ( _PIDController_Update (3 , , &U _pid -> _ucTargetMove `f -> _ucTPS `f `ui -> -> 600 `i `ui ] +"441 +[; ;ETC.c: 441: } +} +[e $U 3267 ] +"442 +[; ;ETC.c: 442: else +[e :U 3266 ] +"443 +[; ;ETC.c: 443: { +{ +"445 +[; ;ETC.c: 445: } +} +[e :U 3267 ] +[e :U 3265 ] +"446 +[; ;ETC.c: 446: } +} +[e $U 3268 ] +"447 +[; ;ETC.c: 447: else +[e :U 3263 ] +"448 +[; ;ETC.c: 448: { +{ +"450 +[; ;ETC.c: 450: } +} +[e :U 3268 ] +"451 +[; ;ETC.c: 451: do { LATAbits.LATA0 = 0; } while(0); +[e :U 3271 ] +{ +[e = . . _LATAbits 0 0 -> -> 0 `i `uc ] +} +[e :U 3270 ] +"452 +[; ;ETC.c: 452: } +} +[e $U 3272 ] +"453 +[; ;ETC.c: 453: else +[e :U 3262 ] +"454 +[; ;ETC.c: 454: { +{ +"455 +[; ;ETC.c: 455: do { LATAbits.LATA0 = 1; } while(0); +[e :U 3275 ] +{ +[e = . . _LATAbits 0 0 -> -> 1 `i `uc ] +} +[e :U 3274 ] +"456 +[; ;ETC.c: 456: GPIO_PWM2_Control(0, 600); +[e ( _GPIO_PWM2_Control (2 , -> -> 0 `i `ui -> -> 600 `i `ui ] +"457 +[; ;ETC.c: 457: } +} +[e :U 3272 ] +"458 +[; ;ETC.c: 458: } +[e :UE 3261 ] +} +"460 +[; ;ETC.c: 460: void ETCXavierSupervisor (void) +[v _ETCXavierSupervisor `(v ~T0 @X0 1 ef ] +"461 +[; ;ETC.c: 461: { +{ +[e :U _ETCXavierSupervisor ] +[f ] +"462 +[; ;ETC.c: 462: __nop(); +[e ( ___nop .. ] +"463 +[; ;ETC.c: 463: if ( ucASMode == 1 ) +[e $ ! == -> _ucASMode `i -> 1 `i 3277 ] +"464 +[; ;ETC.c: 464: { +{ +"465 +[; ;ETC.c: 465: if ( ucETCBeatSupervisor == 0x01 ) +[e $ ! == -> _ucETCBeatSupervisor `i -> 1 `i 3278 ] +"466 +[; ;ETC.c: 466: { +{ +"467 +[; ;ETC.c: 467: ucETCFlagSupervisor = 0x01; +[e = _ucETCFlagSupervisor -> -> 1 `i `uc ] +"468 +[; ;ETC.c: 468: } +} +[e $U 3279 ] +"469 +[; ;ETC.c: 469: else +[e :U 3278 ] +"470 +[; ;ETC.c: 470: { +{ +"471 +[; ;ETC.c: 471: ucETCFlagSupervisor = 0x00; +[e = _ucETCFlagSupervisor -> -> 0 `i `uc ] +"473 +[; ;ETC.c: 473: GPIO_PWM1_Control(0, 300); +[e ( _GPIO_PWM1_Control (2 , -> -> 0 `i `ui -> -> 300 `i `ui ] +"474 +[; ;ETC.c: 474: GPIO_PWM2_Control(0, 600); +[e ( _GPIO_PWM2_Control (2 , -> -> 0 `i `ui -> -> 600 `i `ui ] +"475 +[; ;ETC.c: 475: } +} +[e :U 3279 ] +"476 +[; ;ETC.c: 476: } +} +[e $U 3280 ] +"477 +[; ;ETC.c: 477: else if ( ucASMode == 0 ) +[e :U 3277 ] +[e $ ! == -> _ucASMode `i -> 0 `i 3281 ] +"478 +[; ;ETC.c: 478: { +{ +"479 +[; ;ETC.c: 479: ucETCFlagSupervisor = 0x01; +[e = _ucETCFlagSupervisor -> -> 1 `i `uc ] +"480 +[; ;ETC.c: 480: } +} +[e :U 3281 ] +[e :U 3280 ] +"482 +[; ;ETC.c: 482: } +[e :UE 3276 ] +} +"485 +[; ;ETC.c: 485: void ETCManual (unsigned char ucTargetManual) +[v _ETCManual `(v ~T0 @X0 1 ef1`uc ] +"486 +[; ;ETC.c: 486: { +{ +[e :U _ETCManual ] +"485 +[; ;ETC.c: 485: void ETCManual (unsigned char ucTargetManual) +[v _ucTargetManual `uc ~T0 @X0 1 r1 ] +"486 +[; ;ETC.c: 486: { +[f ] +"487 +[; ;ETC.c: 487: if ( ucASMode == 0 ) +[e $ ! == -> _ucASMode `i -> 0 `i 3283 ] +"488 +[; ;ETC.c: 488: { +{ +"489 +[; ;ETC.c: 489: ETCMove(ucTargetManual, 0); +[e ( _ETCMove (2 , _ucTargetManual -> -> 0 `i `uc ] +"491 +[; ;ETC.c: 491: } +} +[e :U 3283 ] +"492 +[; ;ETC.c: 492: } +[e :UE 3282 ] +} +"495 +[; ;ETC.c: 495: unsigned int ETCPercentCalc(signed long val, signed long min, signed long max) +[v _ETCPercentCalc `(ui ~T0 @X0 1 ef3`l`l`l ] +"496 +[; ;ETC.c: 496: { +{ +[e :U _ETCPercentCalc ] +"495 +[; ;ETC.c: 495: unsigned int ETCPercentCalc(signed long val, signed long min, signed long max) +[v _val `l ~T0 @X0 1 r1 ] +[v _min `l ~T0 @X0 1 r2 ] +[v _max `l ~T0 @X0 1 r3 ] +"496 +[; ;ETC.c: 496: { +[f ] +"503 +[; ;ETC.c: 503: val = (100*(val - min))/(max - min); +[e = _val / * -> -> 100 `i `l - _val _min - _max _min ] +"504 +[; ;ETC.c: 504: if (val < 0) +[e $ ! < _val -> -> 0 `i `l 3285 ] +"505 +[; ;ETC.c: 505: { +{ +"506 +[; ;ETC.c: 506: val = 0; +[e = _val -> -> 0 `i `l ] +"507 +[; ;ETC.c: 507: } +} +[e $U 3286 ] +"508 +[; ;ETC.c: 508: else if (val > 100 ) +[e :U 3285 ] +[e $ ! > _val -> -> 100 `i `l 3287 ] +"509 +[; ;ETC.c: 509: { +{ +"510 +[; ;ETC.c: 510: val = 100; +[e = _val -> -> 100 `i `l ] +"511 +[; ;ETC.c: 511: } +} +[e :U 3287 ] +[e :U 3286 ] +"513 +[; ;ETC.c: 513: return val; +[e ) -> _val `ui ] +[e $UE 3284 ] +"514 +[; ;ETC.c: 514: } +[e :UE 3284 ] +} +"516 +[; ;ETC.c: 516: unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) +[v _ETCPercentMultiCalcTPS1 `(ui ~T0 @X0 1 ef4`l`*ui`*uc`uc ] +"517 +[; ;ETC.c: 517: { +{ +[e :U _ETCPercentMultiCalcTPS1 ] +"516 +[; ;ETC.c: 516: unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) +[v _value `l ~T0 @X0 1 r1 ] +[v _uiTab_in `*ui ~T0 @X0 1 r2 ] +[v _ucTab_out `*uc ~T0 @X0 1 r3 ] +[v _ucSize `uc ~T0 @X0 1 r4 ] +"517 +[; ;ETC.c: 517: { +[f ] +"518 +[; ;ETC.c: 518: unsigned char ucPos = 1; +[v _ucPos `uc ~T0 @X0 1 a ] +[e = _ucPos -> -> 1 `i `uc ] +"519 +[; ;ETC.c: 519: signed long slResult; +[v _slResult `l ~T0 @X0 1 a ] +"520 +[; ;ETC.c: 520: unsigned int ucValCero= uiTab_in[0]; +[v _ucValCero `ui ~T0 @X0 1 a ] +[e = _ucValCero *U + _uiTab_in * -> -> 0 `i `x -> -> # *U _uiTab_in `i `x ] +"521 +[; ;ETC.c: 521: unsigned int ucValMax= uiTab_in[ucSize-1]; +[v _ucValMax `ui ~T0 @X0 1 a ] +[e = _ucValMax *U + _uiTab_in * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _uiTab_in `i `x ] +"522 +[; ;ETC.c: 522: unsigned char ucValout=0; +[v _ucValout `uc ~T0 @X0 1 a ] +[e = _ucValout -> -> 0 `i `uc ] +"525 +[; ;ETC.c: 525: if (value <= ucValCero) return ucTab_out[0]; +[e $ ! <= _value -> _ucValCero `l 3289 ] +[e ) -> *U + _ucTab_out * -> -> 0 `i `x -> -> # *U _ucTab_out `i `x `ui ] +[e $UE 3288 ] +[e :U 3289 ] +"526 +[; ;ETC.c: 526: if (value >= ucValMax) return ucTab_out[ucSize-1]; +[e $ ! >= _value -> _ucValMax `l 3290 ] +[e ) -> *U + _ucTab_out * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `ui ] +[e $UE 3288 ] +[e :U 3290 ] +"530 +[; ;ETC.c: 530: while(value > uiTab_in[ucPos]) ucPos++; +[e $U 3291 ] +[e :U 3292 ] +[e ++ _ucPos -> -> 1 `i `uc ] +[e :U 3291 ] +[e $ > _value -> *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux `l 3292 ] +[e :U 3293 ] +"531 +[; ;ETC.c: 531: ucValout = ucTab_out[ucPos]; +[e = _ucValout *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux ] +"533 +[; ;ETC.c: 533: if (value == uiTab_in[ucPos]) return ucTab_out[ucPos]; +[e $ ! == _value -> *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux `l 3294 ] +[e ) -> *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux `ui ] +[e $UE 3288 ] +[e :U 3294 ] +"536 +[; ;ETC.c: 536: slResult = ( (value - uiTab_in[ucPos-1]) * (ucTab_out[ucPos] - ucTab_out[ucPos-1]) / (uiTab_in[ucPos] - uiTab_in[ucPos-1]) + ucTab_out[ucPos-1] ); +[e = _slResult + / * - _value -> *U + _uiTab_in * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _uiTab_in `i `x `l -> - -> *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux `i -> *U + _ucTab_out * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `i `l -> - *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux *U + _uiTab_in * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _uiTab_in `i `x `l -> *U + _ucTab_out * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `l ] +"538 +[; ;ETC.c: 538: if ( slResult < 0 ) slResult = ucTab_out[0]; +[e $ ! < _slResult -> -> 0 `i `l 3295 ] +[e = _slResult -> *U + _ucTab_out * -> -> 0 `i `x -> -> # *U _ucTab_out `i `x `l ] +[e :U 3295 ] +"539 +[; ;ETC.c: 539: if ( slResult > 100 ) slResult = ucTab_out[ucSize-1]; +[e $ ! > _slResult -> -> 100 `i `l 3296 ] +[e = _slResult -> *U + _ucTab_out * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `l ] +[e :U 3296 ] +"541 +[; ;ETC.c: 541: return slResult ; +[e ) -> _slResult `ui ] +[e $UE 3288 ] +"542 +[; ;ETC.c: 542: } +[e :UE 3288 ] +} +"544 +[; ;ETC.c: 544: unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) +[v _ETCPercentMultiCalcTPS2 `(ui ~T0 @X0 1 ef4`l`*ui`*uc`uc ] +"545 +[; ;ETC.c: 545: { +{ +[e :U _ETCPercentMultiCalcTPS2 ] +"544 +[; ;ETC.c: 544: unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) +[v _value `l ~T0 @X0 1 r1 ] +[v _uiTab_in `*ui ~T0 @X0 1 r2 ] +[v _ucTab_out `*uc ~T0 @X0 1 r3 ] +[v _ucSize `uc ~T0 @X0 1 r4 ] +"545 +[; ;ETC.c: 545: { +[f ] +"546 +[; ;ETC.c: 546: unsigned char ucPos = 1; +[v _ucPos `uc ~T0 @X0 1 a ] +[e = _ucPos -> -> 1 `i `uc ] +"547 +[; ;ETC.c: 547: signed long slResult; +[v _slResult `l ~T0 @X0 1 a ] +"548 +[; ;ETC.c: 548: unsigned int ucValCero= uiTab_in[0]; +[v _ucValCero `ui ~T0 @X0 1 a ] +[e = _ucValCero *U + _uiTab_in * -> -> 0 `i `x -> -> # *U _uiTab_in `i `x ] +"549 +[; ;ETC.c: 549: unsigned int ucValMax= uiTab_in[ucSize-1]; +[v _ucValMax `ui ~T0 @X0 1 a ] +[e = _ucValMax *U + _uiTab_in * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _uiTab_in `i `x ] +"550 +[; ;ETC.c: 550: unsigned char ucValout=0; +[v _ucValout `uc ~T0 @X0 1 a ] +[e = _ucValout -> -> 0 `i `uc ] +"553 +[; ;ETC.c: 553: if (value >= ucValCero) return ucTab_out[0]; +[e $ ! >= _value -> _ucValCero `l 3298 ] +[e ) -> *U + _ucTab_out * -> -> 0 `i `x -> -> # *U _ucTab_out `i `x `ui ] +[e $UE 3297 ] +[e :U 3298 ] +"554 +[; ;ETC.c: 554: if (value <= ucValMax) return ucTab_out[ucSize-1]; +[e $ ! <= _value -> _ucValMax `l 3299 ] +[e ) -> *U + _ucTab_out * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `ui ] +[e $UE 3297 ] +[e :U 3299 ] +"558 +[; ;ETC.c: 558: while(value < uiTab_in[ucPos]) ucPos++; +[e $U 3300 ] +[e :U 3301 ] +[e ++ _ucPos -> -> 1 `i `uc ] +[e :U 3300 ] +[e $ < _value -> *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux `l 3301 ] +[e :U 3302 ] +"559 +[; ;ETC.c: 559: ucValout = ucTab_out[ucPos]; +[e = _ucValout *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux ] +"561 +[; ;ETC.c: 561: if (value == uiTab_in[ucPos]) return ucTab_out[ucPos]; +[e $ ! == _value -> *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux `l 3303 ] +[e ) -> *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux `ui ] +[e $UE 3297 ] +[e :U 3303 ] +"564 +[; ;ETC.c: 564: slResult = ( ( (value - uiTab_in[ucPos-1]) * (ucTab_out[ucPos] - ucTab_out[ucPos-1]) / (uiTab_in[ucPos] - uiTab_in[ucPos-1]) ) + ucTab_out[ucPos-1] ); +[e = _slResult + / * - _value -> *U + _uiTab_in * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _uiTab_in `i `x `l -> - -> *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux `i -> *U + _ucTab_out * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `i `l -> - *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux *U + _uiTab_in * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _uiTab_in `i `x `l -> *U + _ucTab_out * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `l ] +"566 +[; ;ETC.c: 566: if ( slResult < 0 ) slResult = ucTab_out[0]; +[e $ ! < _slResult -> -> 0 `i `l 3304 ] +[e = _slResult -> *U + _ucTab_out * -> -> 0 `i `x -> -> # *U _ucTab_out `i `x `l ] +[e :U 3304 ] +"567 +[; ;ETC.c: 567: if ( slResult > 100 ) slResult = ucTab_out[ucSize-1]; +[e $ ! > _slResult -> -> 100 `i `l 3305 ] +[e = _slResult -> *U + _ucTab_out * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `l ] +[e :U 3305 ] +"569 +[; ;ETC.c: 569: return slResult ; +[e ) -> _slResult `ui ] +[e $UE 3297 ] +"570 +[; ;ETC.c: 570: } +[e :UE 3297 ] +} +"574 +[; ;ETC.c: 574: void PIDController_Init(PIDController *pid) { +[v _PIDController_Init `(v ~T0 @X0 1 ef1`*S3181 ] +{ +[e :U _PIDController_Init ] +[v _pid `*S3181 ~T0 @X0 1 r1 ] +[f ] +"577 +[; ;ETC.c: 577: pid->integrator = 0.0f; +[e = . *U _pid 9 -> .0.0 `f ] +"578 +[; ;ETC.c: 578: pid->prevError = 0.0f; +[e = . *U _pid 10 -> .0.0 `f ] +"580 +[; ;ETC.c: 580: pid->differentiator = 0.0f; +[e = . *U _pid 11 -> .0.0 `f ] +"581 +[; ;ETC.c: 581: pid->prevMeasurement = 0.0f; +[e = . *U _pid 12 -> .0.0 `f ] +"583 +[; ;ETC.c: 583: pid->out = 0.0f; +[e = . *U _pid 13 -> .0.0 `f ] +"585 +[; ;ETC.c: 585: } +[e :UE 3306 ] +} +"587 +[; ;ETC.c: 587: float PIDController_Update(PIDController *pid, float setpoint, float measurement) { +[v _PIDController_Update `(f ~T0 @X0 1 ef3`*S3181`f`f ] +{ +[e :U _PIDController_Update ] +[v _pid `*S3181 ~T0 @X0 1 r1 ] +[v _setpoint `f ~T0 @X0 1 r2 ] +[v _measurement `f ~T0 @X0 1 r3 ] +[f ] +"592 +[; ;ETC.c: 592: float error = setpoint - measurement; +[v _error `f ~T0 @X0 1 a ] +[e = _error - _setpoint _measurement ] +"598 +[; ;ETC.c: 598: float proportional = pid->Kp * error; +[v _proportional `f ~T0 @X0 1 a ] +[e = _proportional * . *U _pid 0 _error ] +"604 +[; ;ETC.c: 604: pid->integrator = pid->integrator + 0.5f * pid->Ki * pid->T * (error + pid->prevError); +[e = . *U _pid 9 + . *U _pid 9 * * * -> .0.5 `f . *U _pid 1 . *U _pid 8 + _error . *U _pid 10 ] +"624 +[; ;ETC.c: 624: pid->differentiator = -(2.0f * pid->Kd * (measurement - pid->prevMeasurement) +[e = . *U _pid 11 / -U + * * -> .2.0 `f . *U _pid 2 - _measurement . *U _pid 12 * - * -> .2.0 `f . *U _pid 3 . *U _pid 8 . *U _pid 11 + * -> .2.0 `f . *U _pid 3 . *U _pid 8 ] +"630 +[; ;ETC.c: 630: if ((pid->differentiator > 2.0f) || (pid->differentiator < -2.0f)){ +[e $ ! || > . *U _pid 11 -> .2.0 `f < . *U _pid 11 -U -> .2.0 `f 3308 ] +{ +"631 +[; ;ETC.c: 631: pid->integrator = 0; +[e = . *U _pid 9 -> -> 0 `i `f ] +"632 +[; ;ETC.c: 632: } +} +[e :U 3308 ] +"636 +[; ;ETC.c: 636: pid->out = proportional + pid->integrator + pid->differentiator; +[e = . *U _pid 13 + + _proportional . *U _pid 9 . *U _pid 11 ] +"638 +[; ;ETC.c: 638: if (pid->out > pid->limMax) { +[e $ ! > . *U _pid 13 . *U _pid 5 3309 ] +{ +"640 +[; ;ETC.c: 640: pid->out = pid->limMax; +[e = . *U _pid 13 . *U _pid 5 ] +"642 +[; ;ETC.c: 642: } else if (pid->out < pid->limMin) { +} +[e $U 3310 ] +[e :U 3309 ] +[e $ ! < . *U _pid 13 . *U _pid 4 3311 ] +{ +"644 +[; ;ETC.c: 644: pid->out = pid->limMin; +[e = . *U _pid 13 . *U _pid 4 ] +"646 +[; ;ETC.c: 646: } +} +[e :U 3311 ] +[e :U 3310 ] +"649 +[; ;ETC.c: 649: pid->prevError = error; +[e = . *U _pid 10 _error ] +"650 +[; ;ETC.c: 650: pid->prevMeasurement = measurement; +[e = . *U _pid 12 _measurement ] +"653 +[; ;ETC.c: 653: return pid->out; +[e ) . *U _pid 13 ] +[e $UE 3307 ] +"655 +[; ;ETC.c: 655: } +[e :UE 3307 ] +} diff --git a/ETC.X/build/default/debug/ETC.p1.d b/ETC.X/build/default/debug/ETC.p1.d new file mode 100644 index 0000000..f764758 --- /dev/null +++ b/ETC.X/build/default/debug/ETC.p1.d @@ -0,0 +1,22 @@ +build/default/debug/ETC.p1: \ +ETC.c \ +mcc_generated_files/DAC3.h \ +mcc_generated_files/drivers/i2c_simple_master.h \ +mcc_generated_files/drivers/.././i2c1_master.h \ +MESSAGES.h \ +mcc_generated_files/mcc.h \ +mcc_generated_files/device_config.h \ +mcc_generated_files/pin_manager.h \ +mcc_generated_files/interrupt_manager.h \ +mcc_generated_files/adc.h \ +mcc_generated_files/tmr1.h \ +mcc_generated_files/tmr0.h \ +mcc_generated_files/can1.h \ +mcc_generated_files/can_types.h \ +mcc_generated_files/pwm2_16bit.h \ +mcc_generated_files/pwm1_16bit.h \ +mcc_generated_files/DAC3_example.h \ +ETC.h \ +GPIO.h \ +PARAMETERS.h \ +ANALOG.h diff --git a/ETC.X/build/default/debug/GPIO.i b/ETC.X/build/default/debug/GPIO.i new file mode 100644 index 0000000..8218176 --- /dev/null +++ b/ETC.X/build/default/debug/GPIO.i @@ -0,0 +1,37712 @@ +# 1 "GPIO.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "GPIO.c" 2 + + + + + + + +# 1 "./GPIO.h" 1 +# 16 "./GPIO.h" +void GPIOInit (void); +void GPIO_PWM1_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +void GPIO_PWM2_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +void GPIO_INT2_desembragar (void); +# 8 "GPIO.c" 2 + +# 1 "./mcc_generated_files/pwm1_16bit.h" 1 +# 54 "./mcc_generated_files/pwm1_16bit.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; + + + + +typedef __int24 int24_t; + + + + +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; + + + + +typedef __uint24 uint24_t; + + + + +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 54 "./mcc_generated_files/pwm1_16bit.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 55 "./mcc_generated_files/pwm1_16bit.h" 2 + + + + + + + + +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 9 "GPIO.c" 2 + +# 1 "./mcc_generated_files/pwm2_16bit.h" 1 +# 63 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 10 "GPIO.c" 2 + +# 1 "./mcc_generated_files/pin_manager.h" 1 +# 54 "./mcc_generated_files/pin_manager.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + + + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 54 "./mcc_generated_files/pin_manager.h" 2 +# 402 "./mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "./mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 11 "GPIO.c" 2 + +# 1 "./../ETC.X/PARAMETERS.h" 1 +# 31 "./../ETC.X/PARAMETERS.h" +extern signed long sl_K; +extern signed long sl_K_P; +extern signed long sl_K_I; +extern signed long sl_K_D; +# 12 "GPIO.c" 2 + +# 1 "./CLUTCH.h" 1 +# 31 "./CLUTCH.h" +extern unsigned char ucCLUTCHlmin; +extern unsigned char ucCLUTCHlmax; +extern unsigned char ucCLUTCHDuty; +extern unsigned char ucCLUTCHState; + + + +void CLUTCH_Init (void); +void CLUTCH_Move (unsigned char ucTargetMove, unsigned char ucMode); +void CLUTCH_AnalyseState (void); +void CLUTCHInitMove(void); +void CLUTCH_HighLevelMovements (unsigned char ucClutchAction); +# 13 "GPIO.c" 2 + + + + +unsigned char ucCLUTCHlmin; +unsigned char ucCLUTCHlmax; +unsigned char ucCLUTCHDuty; +unsigned char ucCLUTCHState; + + + +void GPIOInit (void) +{ + do { TRISAbits.TRISA0 = 0; } while(0); + do { TRISBbits.TRISB2 = 1; } while(0); + do { TRISAbits.TRISA1 = 1; } while(0); + do { TRISAbits.TRISA5 = 0; } while(0); + do { TRISCbits.TRISC5 = 0; } while(0); + do { TRISCbits.TRISC6 = 0; } while(0); + do { TRISCbits.TRISC7 = 0; } while(0); + do { TRISBbits.TRISB5 = 0; } while(0); + GPIO_PWM1_Control( 0, 300 ); + GPIO_PWM2_Control( 0, 600 ); +} + + + + + + +void GPIO_PWM1_Control (unsigned int uiDutyCycle, unsigned int uiFreq) +{ + unsigned int uiConvertedPeriod; + unsigned int uiConvertedDC; + + + uiConvertedPeriod = ( 39241/uiFreq ); + uiConvertedPeriod = ( uiConvertedPeriod - 1.1508 ); + uiConvertedDC = ( uiDutyCycle * 4 ); + uiConvertedDC = ( uiConvertedDC * 100 ); + uiConvertedDC = ( uiConvertedDC / uiFreq ); + + PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uiConvertedDC); + PWM1_16BIT_WritePeriodRegister(uiConvertedPeriod); + PWM1_16BIT_LoadBufferRegisters(); +} + + + + + +void GPIO_PWM2_Control (unsigned int uiDutyCycle, unsigned int uiFreq) +{ + unsigned int uiConvertedPeriod; + unsigned int uiConvertedDC; + + + uiConvertedPeriod = ( 39241/uiFreq ); + uiConvertedPeriod = ( uiConvertedPeriod - 1.1508 ); + uiConvertedDC = ( uiDutyCycle * 4 ); + uiConvertedDC = ( uiConvertedDC * 100 ); + uiConvertedDC = ( uiConvertedDC / uiFreq ); + + PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uiConvertedDC); + PWM2_16BIT_WritePeriodRegister(uiConvertedPeriod); + PWM2_16BIT_LoadBufferRegisters(); +} + + + +void GPIO_INT2_desembragar (void) +{ + + + if ( PORTAbits.RA1 == 0x01 ) + { + ucCLUTCHlmax = ucCLUTCHDuty; + ucCLUTCHState = 2; + } +} diff --git a/ETC.X/build/default/debug/GPIO.p1 b/ETC.X/build/default/debug/GPIO.p1 new file mode 100644 index 0000000..6c2a938 --- /dev/null +++ b/ETC.X/build/default/debug/GPIO.p1 @@ -0,0 +1,3786 @@ +Version 4.0 HI-TECH Software Intermediate Code +"1666 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[s S3067 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3067 . TRISA0 TRISA1 TRISA2 TRISA3 TRISA4 TRISA5 TRISA6 TRISA7 ] +"1665 +[u S3066 `S3067 1 ] +[n S3066 . . ] +"1677 +[v _TRISAbits `VS3066 ~T0 @X0 0 e@1222 ] +"1728 +[s S3069 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3069 . TRISB0 TRISB1 TRISB2 TRISB3 TRISB4 TRISB5 TRISB6 TRISB7 ] +"1727 +[u S3068 `S3069 1 ] +[n S3068 . . ] +"1739 +[v _TRISBbits `VS3068 ~T0 @X0 0 e@1223 ] +"1790 +[s S3071 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3071 . TRISC0 TRISC1 TRISC2 TRISC3 TRISC4 TRISC5 TRISC6 TRISC7 ] +"1789 +[u S3070 `S3071 1 ] +[n S3070 . . ] +"1801 +[v _TRISCbits `VS3070 ~T0 @X0 0 e@1224 ] +"17 ./GPIO.h +[; ;./GPIO.h: 17: void GPIO_PWM1_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +[v _GPIO_PWM1_Control `(v ~T0 @X0 0 ef2`ui`ui ] +"18 +[; ;./GPIO.h: 18: void GPIO_PWM2_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +[v _GPIO_PWM2_Control `(v ~T0 @X0 0 ef2`ui`ui ] +"114 ./mcc_generated_files/pwm1_16bit.h +[; ;./mcc_generated_files/pwm1_16bit.h: 114: void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +[v _PWM1_16BIT_SetSlice1Output1DutyCycleRegister `(v ~T0 @X0 0 ef1`us ] +"96 +[; ;./mcc_generated_files/pwm1_16bit.h: 96: void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +[v _PWM1_16BIT_WritePeriodRegister `(v ~T0 @X0 0 ef1`us ] +"148 +[; ;./mcc_generated_files/pwm1_16bit.h: 148: void PWM1_16BIT_LoadBufferRegisters(void); +[v _PWM1_16BIT_LoadBufferRegisters `(v ~T0 @X0 0 ef ] +"114 ./mcc_generated_files/pwm2_16bit.h +[; ;./mcc_generated_files/pwm2_16bit.h: 114: void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +[v _PWM2_16BIT_SetSlice1Output1DutyCycleRegister `(v ~T0 @X0 0 ef1`us ] +"96 +[; ;./mcc_generated_files/pwm2_16bit.h: 96: void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +[v _PWM2_16BIT_WritePeriodRegister `(v ~T0 @X0 0 ef1`us ] +"148 +[; ;./mcc_generated_files/pwm2_16bit.h: 148: void PWM2_16BIT_LoadBufferRegisters(void); +[v _PWM2_16BIT_LoadBufferRegisters `(v ~T0 @X0 0 ef ] +"1873 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1873: unsigned OPOL :1; +[s S3075 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3075 . RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 ] +"1872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1872: unsigned :3; +[u S3074 `S3075 1 ] +[n S3074 . . ] +"1884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1884: unsigned MD1EN :1; +[v _PORTAbits `VS3074 ~T0 @X0 0 e@1230 ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"17 GPIO.c +[; ;GPIO.c: 17: unsigned char ucCLUTCHlmin; +[v _ucCLUTCHlmin `uc ~T0 @X0 1 e ] +"18 +[; ;GPIO.c: 18: unsigned char ucCLUTCHlmax; +[v _ucCLUTCHlmax `uc ~T0 @X0 1 e ] +"19 +[; ;GPIO.c: 19: unsigned char ucCLUTCHDuty; +[v _ucCLUTCHDuty `uc ~T0 @X0 1 e ] +"20 +[; ;GPIO.c: 20: unsigned char ucCLUTCHState; +[v _ucCLUTCHState `uc ~T0 @X0 1 e ] +"24 +[; ;GPIO.c: 24: void GPIOInit (void) +[v _GPIOInit `(v ~T0 @X0 1 ef ] +"25 +[; ;GPIO.c: 25: { +{ +[e :U _GPIOInit ] +[f ] +"26 +[; ;GPIO.c: 26: do { TRISAbits.TRISA0 = 0; } while(0); +[e :U 3179 ] +{ +[e = . . _TRISAbits 0 0 -> -> 0 `i `uc ] +} +[e :U 3178 ] +"27 +[; ;GPIO.c: 27: do { TRISBbits.TRISB2 = 1; } while(0); +[e :U 3182 ] +{ +[e = . . _TRISBbits 0 2 -> -> 1 `i `uc ] +} +[e :U 3181 ] +"28 +[; ;GPIO.c: 28: do { TRISAbits.TRISA1 = 1; } while(0); +[e :U 3185 ] +{ +[e = . . _TRISAbits 0 1 -> -> 1 `i `uc ] +} +[e :U 3184 ] +"29 +[; ;GPIO.c: 29: do { TRISAbits.TRISA5 = 0; } while(0); +[e :U 3188 ] +{ +[e = . . _TRISAbits 0 5 -> -> 0 `i `uc ] +} +[e :U 3187 ] +"30 +[; ;GPIO.c: 30: do { TRISCbits.TRISC5 = 0; } while(0); +[e :U 3191 ] +{ +[e = . . _TRISCbits 0 5 -> -> 0 `i `uc ] +} +[e :U 3190 ] +"31 +[; ;GPIO.c: 31: do { TRISCbits.TRISC6 = 0; } while(0); +[e :U 3194 ] +{ +[e = . . _TRISCbits 0 6 -> -> 0 `i `uc ] +} +[e :U 3193 ] +"32 +[; ;GPIO.c: 32: do { TRISCbits.TRISC7 = 0; } while(0); +[e :U 3197 ] +{ +[e = . . _TRISCbits 0 7 -> -> 0 `i `uc ] +} +[e :U 3196 ] +"33 +[; ;GPIO.c: 33: do { TRISBbits.TRISB5 = 0; } while(0); +[e :U 3200 ] +{ +[e = . . _TRISBbits 0 5 -> -> 0 `i `uc ] +} +[e :U 3199 ] +"34 +[; ;GPIO.c: 34: GPIO_PWM1_Control( 0, 300 ); +[e ( _GPIO_PWM1_Control (2 , -> -> 0 `i `ui -> -> 300 `i `ui ] +"35 +[; ;GPIO.c: 35: GPIO_PWM2_Control( 0, 600 ); +[e ( _GPIO_PWM2_Control (2 , -> -> 0 `i `ui -> -> 600 `i `ui ] +"36 +[; ;GPIO.c: 36: } +[e :UE 3176 ] +} +"43 +[; ;GPIO.c: 43: void GPIO_PWM1_Control (unsigned int uiDutyCycle, unsigned int uiFreq) +[v _GPIO_PWM1_Control `(v ~T0 @X0 1 ef2`ui`ui ] +"44 +[; ;GPIO.c: 44: { +{ +[e :U _GPIO_PWM1_Control ] +"43 +[; ;GPIO.c: 43: void GPIO_PWM1_Control (unsigned int uiDutyCycle, unsigned int uiFreq) +[v _uiDutyCycle `ui ~T0 @X0 1 r1 ] +[v _uiFreq `ui ~T0 @X0 1 r2 ] +"44 +[; ;GPIO.c: 44: { +[f ] +"45 +[; ;GPIO.c: 45: unsigned int uiConvertedPeriod; +[v _uiConvertedPeriod `ui ~T0 @X0 1 a ] +"46 +[; ;GPIO.c: 46: unsigned int uiConvertedDC; +[v _uiConvertedDC `ui ~T0 @X0 1 a ] +"49 +[; ;GPIO.c: 49: uiConvertedPeriod = ( 39241/uiFreq ); +[e = _uiConvertedPeriod -> / -> 39241 `l -> _uiFreq `l `ui ] +"50 +[; ;GPIO.c: 50: uiConvertedPeriod = ( uiConvertedPeriod - 1.1508 ); +[e = _uiConvertedPeriod -> - -> _uiConvertedPeriod `d .1.1508 `ui ] +"51 +[; ;GPIO.c: 51: uiConvertedDC = ( uiDutyCycle * 4 ); +[e = _uiConvertedDC * _uiDutyCycle -> -> 4 `i `ui ] +"52 +[; ;GPIO.c: 52: uiConvertedDC = ( uiConvertedDC * 100 ); +[e = _uiConvertedDC * _uiConvertedDC -> -> 100 `i `ui ] +"53 +[; ;GPIO.c: 53: uiConvertedDC = ( uiConvertedDC / uiFreq ); +[e = _uiConvertedDC / _uiConvertedDC _uiFreq ] +"55 +[; ;GPIO.c: 55: PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uiConvertedDC); +[e ( _PWM1_16BIT_SetSlice1Output1DutyCycleRegister (1 -> _uiConvertedDC `us ] +"56 +[; ;GPIO.c: 56: PWM1_16BIT_WritePeriodRegister(uiConvertedPeriod); +[e ( _PWM1_16BIT_WritePeriodRegister (1 -> _uiConvertedPeriod `us ] +"57 +[; ;GPIO.c: 57: PWM1_16BIT_LoadBufferRegisters(); +[e ( _PWM1_16BIT_LoadBufferRegisters .. ] +"58 +[; ;GPIO.c: 58: } +[e :UE 3201 ] +} +"64 +[; ;GPIO.c: 64: void GPIO_PWM2_Control (unsigned int uiDutyCycle, unsigned int uiFreq) +[v _GPIO_PWM2_Control `(v ~T0 @X0 1 ef2`ui`ui ] +"65 +[; ;GPIO.c: 65: { +{ +[e :U _GPIO_PWM2_Control ] +"64 +[; ;GPIO.c: 64: void GPIO_PWM2_Control (unsigned int uiDutyCycle, unsigned int uiFreq) +[v _uiDutyCycle `ui ~T0 @X0 1 r1 ] +[v _uiFreq `ui ~T0 @X0 1 r2 ] +"65 +[; ;GPIO.c: 65: { +[f ] +"66 +[; ;GPIO.c: 66: unsigned int uiConvertedPeriod; +[v _uiConvertedPeriod `ui ~T0 @X0 1 a ] +"67 +[; ;GPIO.c: 67: unsigned int uiConvertedDC; +[v _uiConvertedDC `ui ~T0 @X0 1 a ] +"70 +[; ;GPIO.c: 70: uiConvertedPeriod = ( 39241/uiFreq ); +[e = _uiConvertedPeriod -> / -> 39241 `l -> _uiFreq `l `ui ] +"71 +[; ;GPIO.c: 71: uiConvertedPeriod = ( uiConvertedPeriod - 1.1508 ); +[e = _uiConvertedPeriod -> - -> _uiConvertedPeriod `d .1.1508 `ui ] +"72 +[; ;GPIO.c: 72: uiConvertedDC = ( uiDutyCycle * 4 ); +[e = _uiConvertedDC * _uiDutyCycle -> -> 4 `i `ui ] +"73 +[; ;GPIO.c: 73: uiConvertedDC = ( uiConvertedDC * 100 ); +[e = _uiConvertedDC * _uiConvertedDC -> -> 100 `i `ui ] +"74 +[; ;GPIO.c: 74: uiConvertedDC = ( uiConvertedDC / uiFreq ); +[e = _uiConvertedDC / _uiConvertedDC _uiFreq ] +"76 +[; ;GPIO.c: 76: PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uiConvertedDC); +[e ( _PWM2_16BIT_SetSlice1Output1DutyCycleRegister (1 -> _uiConvertedDC `us ] +"77 +[; ;GPIO.c: 77: PWM2_16BIT_WritePeriodRegister(uiConvertedPeriod); +[e ( _PWM2_16BIT_WritePeriodRegister (1 -> _uiConvertedPeriod `us ] +"78 +[; ;GPIO.c: 78: PWM2_16BIT_LoadBufferRegisters(); +[e ( _PWM2_16BIT_LoadBufferRegisters .. ] +"79 +[; ;GPIO.c: 79: } +[e :UE 3202 ] +} +"83 +[; ;GPIO.c: 83: void GPIO_INT2_desembragar (void) +[v _GPIO_INT2_desembragar `(v ~T0 @X0 1 ef ] +"84 +[; ;GPIO.c: 84: { +{ +[e :U _GPIO_INT2_desembragar ] +[f ] +"87 +[; ;GPIO.c: 87: if ( PORTAbits.RA1 == 0x01 ) +[e $ ! == -> . . _PORTAbits 0 1 `i -> 1 `i 3204 ] +"88 +[; ;GPIO.c: 88: { +{ +"89 +[; ;GPIO.c: 89: ucCLUTCHlmax = ucCLUTCHDuty; +[e = _ucCLUTCHlmax _ucCLUTCHDuty ] +"90 +[; ;GPIO.c: 90: ucCLUTCHState = 2; +[e = _ucCLUTCHState -> -> 2 `i `uc ] +"91 +[; ;GPIO.c: 91: } +} +[e :U 3204 ] +"92 +[; ;GPIO.c: 92: } +[e :UE 3203 ] +} diff --git a/ETC.X/build/default/debug/GPIO.p1.d b/ETC.X/build/default/debug/GPIO.p1.d new file mode 100644 index 0000000..c155ba7 --- /dev/null +++ b/ETC.X/build/default/debug/GPIO.p1.d @@ -0,0 +1,8 @@ +build/default/debug/GPIO.p1: \ +GPIO.c \ +GPIO.h \ +mcc_generated_files/pwm1_16bit.h \ +mcc_generated_files/pwm2_16bit.h \ +mcc_generated_files/pin_manager.h \ +../ETC.X/PARAMETERS.h \ +CLUTCH.h diff --git a/ETC.X/build/default/debug/MESSAGES.i b/ETC.X/build/default/debug/MESSAGES.i new file mode 100644 index 0000000..84c5fe4 --- /dev/null +++ b/ETC.X/build/default/debug/MESSAGES.i @@ -0,0 +1,38653 @@ +# 1 "MESSAGES.C" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "MESSAGES.C" 2 + + + + + + + +# 1 "./MESSAGES.h" 1 +# 16 "./MESSAGES.h" +# 1 "./mcc_generated_files/mcc.h" 1 +# 49 "./mcc_generated_files/mcc.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 49 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/device_config.h" 1 +# 50 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/pin_manager.h" 1 +# 402 "./mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "./mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 51 "./mcc_generated_files/mcc.h" 2 + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 53 "./mcc_generated_files/mcc.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 1 3 + + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 1 3 +# 12 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 3 +extern int errno; +# 8 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__null.h" 1 3 +# 9 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + + + +extern void init_uart(void); + +extern char getch(void); +extern char getche(void); +extern void putch(char); +extern void ungetch(char); + +extern __bit kbhit(void); + + + +extern char * cgets(char *); +extern void cputs(const char *); +# 54 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/interrupt_manager.h" 1 +# 87 "./mcc_generated_files/interrupt_manager.h" +void INTERRUPT_Initialize (void); +# 55 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/i2c1_master.h" 1 +# 54 "./mcc_generated_files/i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "./mcc_generated_files/i2c1_master.h" 2 + + + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "./mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "./mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "./mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 56 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/adc.h" 1 +# 65 "./mcc_generated_files/adc.h" +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "./mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "./mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "./mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "./mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "./mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "./mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "./mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "./mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "./mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "./mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "./mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "./mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "./mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "./mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "./mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "./mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "./mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "./mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "./mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "./mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "./mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "./mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "./mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "./mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "./mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "./mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "./mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 57 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/tmr1.h" 1 +# 101 "./mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "./mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "./mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "./mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "./mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "./mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "./mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "./mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "./mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "./mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "./mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "./mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "./mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 58 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/tmr0.h" 1 +# 106 "./mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "./mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "./mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "./mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "./mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "./mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "./mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "./mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "./mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "./mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "./mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 59 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/can1.h" 1 +# 56 "./mcc_generated_files/can1.h" +# 1 "./mcc_generated_files/can_types.h" 1 +# 65 "./mcc_generated_files/can_types.h" +typedef union +{ + uint8_t msgfields; + struct + { + uint8_t idType:1; + uint8_t frameType:1; + uint8_t dlc:4; + uint8_t formatType:1; + uint8_t brs:1; + }; +} CAN_MSG_FIELD; + +typedef struct +{ + uint32_t msgId; + CAN_MSG_FIELD field; + uint8_t *data; +} CAN_MSG_OBJ; +# 94 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NON_BRS_MODE = 0, + CAN_BRS_MODE = 1 +} CAN_MSG_OBJ_BRS_MODE; +# 109 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_STD = 0, + CAN_FRAME_EXT = 1, +} CAN_MSG_OBJ_ID_TYPE; +# 124 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_DATA = 0, + CAN_FRAME_RTR = 1, +} CAN_MSG_OBJ_FRAME_TYPE; +# 139 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_2_0_FORMAT = 0, + CAN_FD_FORMAT = 1 +} CAN_MSG_OBJ_TYPE; +# 154 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_MSG_REQUEST_SUCCESS = 0, + CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR = 1, + CAN_TX_MSG_REQUEST_BRS_ERROR = 2, + CAN_TX_MSG_REQUEST_FIFO_FULL = 3, +} CAN_TX_MSG_REQUEST_STATUS; +# 171 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NORMAL_FD_MODE = 0, + CAN_DISABLE_MODE = 1, + CAN_INTERNAL_LOOPBACK_MODE = 2, + CAN_LISTEN_ONLY_MODE = 3, + CAN_CONFIGURATION_MODE = 4, + CAN_EXTERNAL_LOOPBACK_MODE = 5, + CAN_NORMAL_2_0_MODE = 6, + CAN_RESTRICTED_OPERATION_MODE =7, +} CAN_OP_MODES; +# 192 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_OP_MODE_REQUEST_SUCCESS, + CAN_OP_MODE_REQUEST_FAIL, + CAN_OP_MODE_SYS_ERROR_OCCURED +} CAN_OP_MODE_STATUS; +# 208 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_FIFO_FULL, + CAN_TX_FIFO_AVAILABLE, +} CAN_TX_FIFO_STATUS; +# 223 "./mcc_generated_files/can_types.h" +typedef enum +{ + + DLC_0, + DLC_1, + DLC_2, + DLC_3, + DLC_4, + DLC_5, + DLC_6, + DLC_7, + DLC_8, + + + + DLC_12, + DLC_16, + DLC_20, + DLC_24, + DLC_32, + DLC_48, + DLC_64, +} CAN_DLC; +# 56 "./mcc_generated_files/can1.h" 2 + + + + + +typedef enum +{ + TXQ = 0 +} CAN1_TX_FIFO_CHANNELS; + +typedef enum +{ + FIFO1 = 1 +} CAN1_RX_FIFO_CHANNELS; +# 106 "./mcc_generated_files/can1.h" +void CAN1_Initialize(void); +# 147 "./mcc_generated_files/can1.h" +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +# 185 "./mcc_generated_files/can1.h" +CAN_OP_MODES CAN1_OperationModeGet(void); +# 235 "./mcc_generated_files/can1.h" +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +# 275 "./mcc_generated_files/can1.h" +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *rxCanMsg); +# 334 "./mcc_generated_files/can1.h" +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +# 390 "./mcc_generated_files/can1.h" +_Bool CAN1_IsBusOff(void); +# 448 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorPassive(void); +# 507 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorWarning(void); +# 566 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorActive(void); +# 614 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorPassive(void); +# 662 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorWarning(void); +# 710 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorActive(void); +# 761 "./mcc_generated_files/can1.h" +void CAN1_Sleep(void); +# 815 "./mcc_generated_files/can1.h" +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +# 857 "./mcc_generated_files/can1.h" +uint8_t CAN1_ReceivedMessageCountGet(void); +# 924 "./mcc_generated_files/can1.h" +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +# 981 "./mcc_generated_files/can1.h" +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +# 1049 "./mcc_generated_files/can1.h" +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +# 1100 "./mcc_generated_files/can1.h" +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +# 1169 "./mcc_generated_files/can1.h" +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +# 1237 "./mcc_generated_files/can1.h" +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +# 1289 "./mcc_generated_files/can1.h" +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +# 1324 "./mcc_generated_files/can1.h" +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +# 1368 "./mcc_generated_files/can1.h" +void CAN1_SetTXQnullHandler(void (*handler)(void)); + + +void CAN1_ISR(void); +void CAN1_RXI_ISR(void); +# 60 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 37 "./mcc_generated_files/drivers/i2c_simple_master.h" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 61 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/pwm2_16bit.h" 1 +# 63 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 62 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/DAC3.h" 1 +# 29 "./mcc_generated_files/DAC3.h" +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 63 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/pwm1_16bit.h" 1 +# 63 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 64 "./mcc_generated_files/mcc.h" 2 +# 79 "./mcc_generated_files/mcc.h" +void SYSTEM_Initialize(void); +# 92 "./mcc_generated_files/mcc.h" +void OSCILLATOR_Initialize(void); +# 105 "./mcc_generated_files/mcc.h" +void PMD_Initialize(void); +# 16 "./MESSAGES.h" 2 + + + + + + +CAN_MSG_OBJ msgTransmit; +CAN_MSG_OBJ msgReceipt; +uint8_t CANDATAdata[8]; + + +extern unsigned char CANDATAdata[8]; + +extern unsigned char ucTargetAccelerator; +extern unsigned char ucTargetClutch; +extern unsigned char ucTargetClutch_PREV; +extern unsigned char ucTargetBrake; +extern unsigned char ucTargetDirection; +extern unsigned char ucTargetGear; + +extern unsigned char ucAS_state; +extern unsigned char ucEBS_state; +extern unsigned char ucAMI_state; +extern unsigned char ucSteering_state; +extern unsigned char ucService_brake; +extern unsigned char ucLap_counter; +extern unsigned char ucCones_count_actual; +extern unsigned char ucCones_count_all; + +extern unsigned char ucSpeed_actual; +extern unsigned char ucSpeed_target; +extern unsigned char ucSteering_angle_actual; +extern unsigned char ucSteering_angle_target; +extern unsigned char ucBrake_hydr_actual; +extern unsigned char ucBrake_hydr_target; +extern unsigned char ucMotor_moment_actual; +extern unsigned char ucMotor_moment_target; + +extern unsigned int uiAcc_longitudinal; +extern unsigned int uiAcc_lateral; +extern unsigned int uiYaw_rate; + +extern unsigned char ucASBState; +extern unsigned char ucASRequesState; + +extern unsigned char ucASMode; + +extern unsigned char ucSTEER_WH_Clutch; +# 98 "./MESSAGES.h" +void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8); +void CANReadMessage (void); +void CANDisableErrorInterrupt (unsigned char ucInterruptSet); +# 8 "MESSAGES.C" 2 + + +# 1 "./ETC.h" 1 +# 65 "./ETC.h" +unsigned int uiTPS1TableIn [21]; +unsigned char ucTPS1TableOut [21]; +unsigned int uiTPS2TableIn [21]; +unsigned char ucTPS2TableOut [21]; + +typedef struct { + + + float Kp; + float Ki; + float Kd; + + + float tau; + + + float limMin; + float limMax; + + + float limMinInt; + float limMaxInt; + + + float T; + + + float integrator; + float prevError; + float differentiator; + float prevMeasurement; + + + float out; + +} PIDController; + +PIDController pid = { 2.4f, 1.4f, 0.0f, + 0.02f, + 0.0f, 100.0f, + -10.0f, 10.0f, + 0.01f }; + + + +extern unsigned int uiAPPS1min; +extern unsigned int uiAPPS1max; +extern unsigned int uiAPPS2min; +extern unsigned int uiAPPS2max; +extern unsigned int uiTPS1min; +extern unsigned int uiTPS1max; +extern unsigned int uiTPS2min; +extern unsigned int uiTPS2max; +extern unsigned int uiAPPS1; +extern unsigned int uiAPPS2; +extern unsigned char ucAPPS_STATE; +extern unsigned long ulAPPS1calc; +extern unsigned long ulAPPS2calc; +extern unsigned int ucAPPS1Perc; +extern unsigned int ucAPPS2Perc; +extern unsigned int ucAPPS; +extern unsigned int uiTPS1; +extern unsigned int uiTPS2; +extern signed long ulTPS1calc; +extern signed long ulTPS2calc; +extern unsigned int ucTPS1Perc; +extern unsigned int ucTPS2Perc; +extern unsigned int ucTPS; +extern unsigned char ucTPS_STATE; +extern unsigned char ucTPS1_STATE; +extern unsigned char ucTPS2_STATE; +extern unsigned char ucTPS_Volts_STATE; +extern unsigned int uiETCDuty; +extern unsigned char ucETB_STATE; +extern unsigned char ucETCBeatSupervisor; +extern unsigned char ucETCFlagSupervisor; +extern unsigned char ucAPPSManual; +extern unsigned char ucETCTimerRuleTPS; +extern unsigned char ucETCTimerRuleAPPS; +extern unsigned char ucCount100msTPSError; +extern unsigned char ucCount100msAPPSError; +extern unsigned char ucETCRuleSupervisor; +extern unsigned char ucETCTargetTPSDiff; +extern unsigned char ucCount500msTPSDiff; +extern unsigned char ucETCMotorNotClose; +extern unsigned char ucETCResolveNotCloseError; +extern unsigned char ucCount500msResolveNotCloseError; + +extern unsigned int ucAPPSTargetPruebas; + +void ETCInit(void); +void APPSSend (unsigned char ucPercent); +void APPSReadmin (void); +void APPSReadmax (void); +void ETCModeSelect (unsigned char ucModeSelect); +void ETCRulesSupervision(void); +void ETCMove(unsigned char ucTargetMove, unsigned char ucMode); +void ETC_PID(signed long slTargetMove, unsigned char ucMode); +void ETCCalibrate(void); +void TPSAnalysis (void); +void APPSAnalysis (void); +void ETCXavierSupervisor (void); +void ETCManual (unsigned char ucTargetManual); +unsigned int ETCPercentCalc(signed long val, signed long min, signed long max); +void ETCRulesSensorsSupervision(void); +void ETC100msSupervisor (void); +void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactual); +void ETC500msSupervisor (void); +void PIDController_Init(PIDController *pid); +float PIDController_Update(PIDController *pid, float setpoint, float measurement); +unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +# 10 "MESSAGES.C" 2 + +# 1 "./CLUTCH.h" 1 +# 31 "./CLUTCH.h" +extern unsigned char ucCLUTCHlmin; +extern unsigned char ucCLUTCHlmax; +extern unsigned char ucCLUTCHDuty; +extern unsigned char ucCLUTCHState; + + + +void CLUTCH_Init (void); +void CLUTCH_Move (unsigned char ucTargetMove, unsigned char ucMode); +void CLUTCH_AnalyseState (void); +void CLUTCHInitMove(void); +void CLUTCH_HighLevelMovements (unsigned char ucClutchAction); +# 11 "MESSAGES.C" 2 + +# 1 "./PARAMETERS.h" 1 +# 31 "./PARAMETERS.h" +extern signed long sl_K; +extern signed long sl_K_P; +extern signed long sl_K_I; +extern signed long sl_K_D; +# 12 "MESSAGES.C" 2 + + + + +uint8_t CANDATAdata[8]; + + +unsigned char ucTargetAccelerator; +unsigned char ucTargetClutch; +unsigned char ucTargetClutch_PREV; +unsigned char ucTargetBrake; +unsigned char ucTargetDirection; +unsigned char ucTargetGear; + +unsigned char ucAS_state; +unsigned char ucEBS_state; +unsigned char ucAMI_state; +unsigned char ucSteering_state; +unsigned char ucService_brake; +unsigned char ucLap_counter; +unsigned char ucCones_count_actual; +unsigned int uiCones_count_all; + +unsigned char ucSpeed_actual; +unsigned char ucSpeed_target; +unsigned char ucSteering_angle_actual; +unsigned char ucSteering_angle_target; +unsigned char ucBrake_hydr_actual; +unsigned char ucBrake_hydr_target; +unsigned char ucMotor_moment_actual; +unsigned char ucMotor_moment_target; + +unsigned int uiAcc_longitudinal; +unsigned int uiAcc_lateral; +unsigned int uiYaw_rate; + +unsigned char ucASBState; +unsigned char ucASRequesState; + +unsigned char ucASMode; + +unsigned char ucSTEER_WH_Clutch; + + +void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8) +{ + CANDATAdata [0] = data1; + CANDATAdata [1] = data2; + CANDATAdata [2] = data3; + CANDATAdata [3] = data4; + CANDATAdata [4] = data5; + CANDATAdata [5] = data6; + CANDATAdata [6] = data7; + CANDATAdata [7] = data8; + + msgTransmit.msgId = id; + msgTransmit.field.formatType = CAN_2_0_FORMAT; + msgTransmit.field.brs = CAN_NON_BRS_MODE; + msgTransmit.field.frameType = CAN_FRAME_DATA; + msgTransmit.field.idType = CAN_FRAME_STD; + msgTransmit.field.dlc = ( dataLength & 0x0F ); + msgTransmit.data = CANDATAdata; + + if(CAN1_IsBusOff() == 0x01) + { + __nop(); + } + if(CAN1_IsTxErrorPassive() == 0x01) + { + __nop(); + } + if(CAN1_IsTxErrorWarning() == 0x01) + { + __nop(); + } + if(CAN1_IsTxErrorActive() == 0x01) + { + __nop(); + } + + if(CAN_TX_FIFO_AVAILABLE == (CAN1_TransmitFIFOStatusGet(TXQ) & CAN_TX_FIFO_AVAILABLE)) + { + CAN1_Transmit(TXQ, &msgTransmit); + __nop(); + } +} + + + +void CANReadMessage (void) +{ + uint32_t id; + unsigned char idType; + unsigned char dlc; + unsigned char data1; + unsigned char data2; + unsigned char data3; + unsigned char data4; + unsigned char data5; + unsigned char data6; + unsigned char data7; + unsigned char data8; + + if(CAN1_ReceivedMessageCountGet() > 0) + { + if(1 == CAN1_Receive(&msgReceipt)) + { + __nop(); + id = msgReceipt.msgId; + idType = msgReceipt.field.idType; + dlc = msgReceipt.field.dlc; + data1 = msgReceipt.data[0]; + data2 = msgReceipt.data[1]; + data3 = msgReceipt.data[2]; + data4 = msgReceipt.data[3]; + data5 = msgReceipt.data[4]; + data6 = msgReceipt.data[5]; + data7 = msgReceipt.data[6]; + data8 = msgReceipt.data[7]; + + switch (id) + { + case 0x320: + ucTargetAccelerator = data1; + ucTargetClutch = data2; + ucTargetBrake = data3; + ucTargetDirection = data4; + ucTargetGear = data5; + + if ( ucASMode == 1 ) + { + + + + + ucETCBeatSupervisor = 0x01; + } + + break; + case 0x500: + ucAS_state = ( data1 & 0x07 ); + ucEBS_state = ( data1 & 0x18 ); + ucAMI_state = ( data1 & 0xE0 ); + ucSteering_state = ( data2 & 0x01 ); + ucService_brake = ( data2 & 0x06 ); + ucLap_counter = ( data2 & 0x78 ); + + + break; + case 0x501: + ucSpeed_actual = data1; + ucSpeed_target = data2; + ucSteering_angle_actual = data3; + ucSteering_angle_target = data4; + ucBrake_hydr_actual = data5; + ucBrake_hydr_target = data6; + ucMotor_moment_actual = data7; + ucMotor_moment_target = data8; + break; + case 0x502: + + + + break; + case 0x347: + ucASMode = data1; + ETCModeSelect(ucASMode); + break; + case 0x412: + ucSTEER_WH_Clutch = data1; + + + + + break; + default: + __nop(); + break; + } + } + } +} + + +void CANDisableErrorInterrupt (unsigned char ucInterruptSet) +{ + if (ucInterruptSet == 0x01) + { + PIE0bits.CANIE = 1; + } + else if (ucInterruptSet == 0x00) + { + PIE0bits.CANIE = 0; + } + +} diff --git a/ETC.X/build/default/debug/MESSAGES.p1 b/ETC.X/build/default/debug/MESSAGES.p1 new file mode 100644 index 0000000..900bb6c --- /dev/null +++ b/ETC.X/build/default/debug/MESSAGES.p1 @@ -0,0 +1,4160 @@ +Version 4.0 HI-TECH Software Intermediate Code +"69 ./mcc_generated_files/can_types.h +[; ;./mcc_generated_files/can_types.h: 69: { +[s S3179 :1 `uc 1 :1 `uc 1 :4 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3179 . idType frameType dlc formatType brs ] +"66 +[; ;./mcc_generated_files/can_types.h: 66: { +[u S3178 `uc 1 `S3179 1 ] +[n S3178 . msgfields . ] +"79 +[; ;./mcc_generated_files/can_types.h: 79: { +[s S3180 `ul 1 `S3178 1 `*uc 1 ] +[n S3180 . msgId field data ] +"70 ./ETC.h +[; ;./ETC.h: 70: typedef struct { +[s S3181 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 ] +[n S3181 . Kp Ki Kd tau limMin limMax limMinInt limMaxInt T integrator prevError differentiator prevMeasurement out ] +"68 MESSAGES.C +[; ;MESSAGES.C: 68: msgTransmit.field.formatType = CAN_2_0_FORMAT; +[c E22718 0 1 .. ] +[n E22718 . CAN_2_0_FORMAT CAN_FD_FORMAT ] +"69 +[; ;MESSAGES.C: 69: msgTransmit.field.brs = CAN_NON_BRS_MODE; +[c E22706 0 1 .. ] +[n E22706 . CAN_NON_BRS_MODE CAN_BRS_MODE ] +"70 +[; ;MESSAGES.C: 70: msgTransmit.field.frameType = CAN_FRAME_DATA; +[c E22714 0 1 .. ] +[n E22714 . CAN_FRAME_DATA CAN_FRAME_RTR ] +"71 +[; ;MESSAGES.C: 71: msgTransmit.field.idType = CAN_FRAME_STD; +[c E22710 0 1 .. ] +[n E22710 . CAN_FRAME_STD CAN_FRAME_EXT ] +"390 ./mcc_generated_files/can1.h +[; ;./mcc_generated_files/can1.h: 390: _Bool CAN1_IsBusOff(void); +[v _CAN1_IsBusOff `(a ~T0 @X0 0 ef ] +"8 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\builtins.h +[v ___nop `(v ~T0 @X0 0 ef ] +[p i ___nop ] +"448 ./mcc_generated_files/can1.h +[; ;./mcc_generated_files/can1.h: 448: _Bool CAN1_IsTxErrorPassive(void); +[v _CAN1_IsTxErrorPassive `(a ~T0 @X0 0 ef ] +"507 +[; ;./mcc_generated_files/can1.h: 507: _Bool CAN1_IsTxErrorWarning(void); +[v _CAN1_IsTxErrorWarning `(a ~T0 @X0 0 ef ] +"566 +[; ;./mcc_generated_files/can1.h: 566: _Bool CAN1_IsTxErrorActive(void); +[v _CAN1_IsTxErrorActive `(a ~T0 @X0 0 ef ] +"92 MESSAGES.C +[; ;MESSAGES.C: 92: if(CAN_TX_FIFO_AVAILABLE == (CAN1_TransmitFIFOStatusGet(TXQ) & CAN_TX_FIFO_AVAILABLE)) +[c E22743 0 1 .. ] +[n E22743 . CAN_TX_FIFO_FULL CAN_TX_FIFO_AVAILABLE ] +[c E22765 0 .. ] +[n E22765 . TXQ ] +"815 ./mcc_generated_files/can1.h +[; ;./mcc_generated_files/can1.h: 815: CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +[v _CAN1_TransmitFIFOStatusGet `(E22743 ~T0 @X0 0 ef1`CE22765 ] +"94 MESSAGES.C +[; ;MESSAGES.C: 94: CAN1_Transmit(TXQ, &msgTransmit); +[c E22722 0 1 2 3 .. ] +[n E22722 . CAN_TX_MSG_REQUEST_SUCCESS CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR CAN_TX_MSG_REQUEST_BRS_ERROR CAN_TX_MSG_REQUEST_FIFO_FULL ] +"334 ./mcc_generated_files/can1.h +[; ;./mcc_generated_files/can1.h: 334: CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +[v _CAN1_Transmit `(E22722 ~T0 @X0 0 ef2`CE22765`*S3180 ] +"857 +[; ;./mcc_generated_files/can1.h: 857: uint8_t CAN1_ReceivedMessageCountGet(void); +[v _CAN1_ReceivedMessageCountGet `(uc ~T0 @X0 0 ef ] +"235 +[; ;./mcc_generated_files/can1.h: 235: _Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +[v _CAN1_Receive `(a ~T0 @X0 0 ef1`*S3180 ] +"139 ./ETC.h +[; ;./ETC.h: 139: extern unsigned char ucETCBeatSupervisor; +[v _ucETCBeatSupervisor `uc ~T0 @X0 0 e ] +"159 +[; ;./ETC.h: 159: void ETCModeSelect (unsigned char ucModeSelect); +[v _ETCModeSelect `(v ~T0 @X0 0 ef1`uc ] +"65046 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65046: struct { +[s S2995 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2995 . SWIE HLVDIE OSFIE CSWIE TU16AIE CLC1IE CANIE IOCIE ] +"65045 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65045: typedef union { +[u S2994 `S2995 1 ] +[n S2994 . . ] +"65057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65057: extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +[v _PIE0bits `VS2994 ~T0 @X0 0 e@1182 ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"22 ./MESSAGES.h +[; ;./MESSAGES.h: 22: CAN_MSG_OBJ msgTransmit; +[v _msgTransmit `S3180 ~T0 @X0 1 e ] +"23 +[; ;./MESSAGES.h: 23: CAN_MSG_OBJ msgReceipt; +[v _msgReceipt `S3180 ~T0 @X0 1 e ] +"24 +[; ;./MESSAGES.h: 24: uint8_t CANDATAdata[8]; +[v _CANDATAdata `uc ~T0 @X0 -> 8 `i e ] +"65 ./ETC.h +[; ;./ETC.h: 65: unsigned int uiTPS1TableIn [21]; +[v _uiTPS1TableIn `ui ~T0 @X0 -> 21 `i e ] +"66 +[; ;./ETC.h: 66: unsigned char ucTPS1TableOut [21]; +[v _ucTPS1TableOut `uc ~T0 @X0 -> 21 `i e ] +"67 +[; ;./ETC.h: 67: unsigned int uiTPS2TableIn [21]; +[v _uiTPS2TableIn `ui ~T0 @X0 -> 21 `i e ] +"68 +[; ;./ETC.h: 68: unsigned char ucTPS2TableOut [21]; +[v _ucTPS2TableOut `uc ~T0 @X0 -> 21 `i e ] +"102 +[; ;./ETC.h: 102: PIDController pid = { 2.4f, 1.4f, 0.0f, +[v _pid `S3181 ~T0 @X0 1 e ] +[i _pid +:U .. +:U .. +-> .2.4 `f +-> .1.4 `f +-> .0.0 `f +-> .0.02 `f +-> .0.0 `f +-> .100.0 `f +-U -> .10.0 `f +-> .10.0 `f +-> .0.01 `f +.. +.. +] +"16 MESSAGES.C +[; ;MESSAGES.C: 16: uint8_t CANDATAdata[8]; +[v _CANDATAdata `uc ~T0 @X0 -> 8 `i e ] +"19 +[; ;MESSAGES.C: 19: unsigned char ucTargetAccelerator; +[v _ucTargetAccelerator `uc ~T0 @X0 1 e ] +"20 +[; ;MESSAGES.C: 20: unsigned char ucTargetClutch; +[v _ucTargetClutch `uc ~T0 @X0 1 e ] +"21 +[; ;MESSAGES.C: 21: unsigned char ucTargetClutch_PREV; +[v _ucTargetClutch_PREV `uc ~T0 @X0 1 e ] +"22 +[; ;MESSAGES.C: 22: unsigned char ucTargetBrake; +[v _ucTargetBrake `uc ~T0 @X0 1 e ] +"23 +[; ;MESSAGES.C: 23: unsigned char ucTargetDirection; +[v _ucTargetDirection `uc ~T0 @X0 1 e ] +"24 +[; ;MESSAGES.C: 24: unsigned char ucTargetGear; +[v _ucTargetGear `uc ~T0 @X0 1 e ] +"26 +[; ;MESSAGES.C: 26: unsigned char ucAS_state; +[v _ucAS_state `uc ~T0 @X0 1 e ] +"27 +[; ;MESSAGES.C: 27: unsigned char ucEBS_state; +[v _ucEBS_state `uc ~T0 @X0 1 e ] +"28 +[; ;MESSAGES.C: 28: unsigned char ucAMI_state; +[v _ucAMI_state `uc ~T0 @X0 1 e ] +"29 +[; ;MESSAGES.C: 29: unsigned char ucSteering_state; +[v _ucSteering_state `uc ~T0 @X0 1 e ] +"30 +[; ;MESSAGES.C: 30: unsigned char ucService_brake; +[v _ucService_brake `uc ~T0 @X0 1 e ] +"31 +[; ;MESSAGES.C: 31: unsigned char ucLap_counter; +[v _ucLap_counter `uc ~T0 @X0 1 e ] +"32 +[; ;MESSAGES.C: 32: unsigned char ucCones_count_actual; +[v _ucCones_count_actual `uc ~T0 @X0 1 e ] +"33 +[; ;MESSAGES.C: 33: unsigned int uiCones_count_all; +[v _uiCones_count_all `ui ~T0 @X0 1 e ] +"35 +[; ;MESSAGES.C: 35: unsigned char ucSpeed_actual; +[v _ucSpeed_actual `uc ~T0 @X0 1 e ] +"36 +[; ;MESSAGES.C: 36: unsigned char ucSpeed_target; +[v _ucSpeed_target `uc ~T0 @X0 1 e ] +"37 +[; ;MESSAGES.C: 37: unsigned char ucSteering_angle_actual; +[v _ucSteering_angle_actual `uc ~T0 @X0 1 e ] +"38 +[; ;MESSAGES.C: 38: unsigned char ucSteering_angle_target; +[v _ucSteering_angle_target `uc ~T0 @X0 1 e ] +"39 +[; ;MESSAGES.C: 39: unsigned char ucBrake_hydr_actual; +[v _ucBrake_hydr_actual `uc ~T0 @X0 1 e ] +"40 +[; ;MESSAGES.C: 40: unsigned char ucBrake_hydr_target; +[v _ucBrake_hydr_target `uc ~T0 @X0 1 e ] +"41 +[; ;MESSAGES.C: 41: unsigned char ucMotor_moment_actual; +[v _ucMotor_moment_actual `uc ~T0 @X0 1 e ] +"42 +[; ;MESSAGES.C: 42: unsigned char ucMotor_moment_target; +[v _ucMotor_moment_target `uc ~T0 @X0 1 e ] +"44 +[; ;MESSAGES.C: 44: unsigned int uiAcc_longitudinal; +[v _uiAcc_longitudinal `ui ~T0 @X0 1 e ] +"45 +[; ;MESSAGES.C: 45: unsigned int uiAcc_lateral; +[v _uiAcc_lateral `ui ~T0 @X0 1 e ] +"46 +[; ;MESSAGES.C: 46: unsigned int uiYaw_rate; +[v _uiYaw_rate `ui ~T0 @X0 1 e ] +"48 +[; ;MESSAGES.C: 48: unsigned char ucASBState; +[v _ucASBState `uc ~T0 @X0 1 e ] +"49 +[; ;MESSAGES.C: 49: unsigned char ucASRequesState; +[v _ucASRequesState `uc ~T0 @X0 1 e ] +"51 +[; ;MESSAGES.C: 51: unsigned char ucASMode; +[v _ucASMode `uc ~T0 @X0 1 e ] +"53 +[; ;MESSAGES.C: 53: unsigned char ucSTEER_WH_Clutch; +[v _ucSTEER_WH_Clutch `uc ~T0 @X0 1 e ] +"56 +[; ;MESSAGES.C: 56: void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8) +[v _CANWriteMessage `(v ~T0 @X0 1 ef10`ul`uc`uc`uc`uc`uc`uc`uc`uc`uc ] +"57 +[; ;MESSAGES.C: 57: { +{ +[e :U _CANWriteMessage ] +"56 +[; ;MESSAGES.C: 56: void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8) +[v _id `ul ~T0 @X0 1 r1 ] +[v _dataLength `uc ~T0 @X0 1 r2 ] +[v _data1 `uc ~T0 @X0 1 r3 ] +[v _data2 `uc ~T0 @X0 1 r4 ] +[v _data3 `uc ~T0 @X0 1 r5 ] +[v _data4 `uc ~T0 @X0 1 r6 ] +[v _data5 `uc ~T0 @X0 1 r7 ] +[v _data6 `uc ~T0 @X0 1 r8 ] +[v _data7 `uc ~T0 @X0 1 r9 ] +[v _data8 `uc ~T0 @X0 1 r10 ] +"57 +[; ;MESSAGES.C: 57: { +[f ] +"58 +[; ;MESSAGES.C: 58: CANDATAdata [0] = data1; +[e = *U + &U _CANDATAdata * -> -> -> 0 `i `ui `ux -> -> # *U &U _CANDATAdata `ui `ux _data1 ] +"59 +[; ;MESSAGES.C: 59: CANDATAdata [1] = data2; +[e = *U + &U _CANDATAdata * -> -> -> 1 `i `ui `ux -> -> # *U &U _CANDATAdata `ui `ux _data2 ] +"60 +[; ;MESSAGES.C: 60: CANDATAdata [2] = data3; +[e = *U + &U _CANDATAdata * -> -> -> 2 `i `ui `ux -> -> # *U &U _CANDATAdata `ui `ux _data3 ] +"61 +[; ;MESSAGES.C: 61: CANDATAdata [3] = data4; +[e = *U + &U _CANDATAdata * -> -> -> 3 `i `ui `ux -> -> # *U &U _CANDATAdata `ui `ux _data4 ] +"62 +[; ;MESSAGES.C: 62: CANDATAdata [4] = data5; +[e = *U + &U _CANDATAdata * -> -> -> 4 `i `ui `ux -> -> # *U &U _CANDATAdata `ui `ux _data5 ] +"63 +[; ;MESSAGES.C: 63: CANDATAdata [5] = data6; +[e = *U + &U _CANDATAdata * -> -> -> 5 `i `ui `ux -> -> # *U &U _CANDATAdata `ui `ux _data6 ] +"64 +[; ;MESSAGES.C: 64: CANDATAdata [6] = data7; +[e = *U + &U _CANDATAdata * -> -> -> 6 `i `ui `ux -> -> # *U &U _CANDATAdata `ui `ux _data7 ] +"65 +[; ;MESSAGES.C: 65: CANDATAdata [7] = data8; +[e = *U + &U _CANDATAdata * -> -> -> 7 `i `ui `ux -> -> # *U &U _CANDATAdata `ui `ux _data8 ] +"67 +[; ;MESSAGES.C: 67: msgTransmit.msgId = id; +[e = . _msgTransmit 0 _id ] +"68 +[; ;MESSAGES.C: 68: msgTransmit.field.formatType = CAN_2_0_FORMAT; +[e = . . . _msgTransmit 1 1 3 -> . `E22718 0 `uc ] +"69 +[; ;MESSAGES.C: 69: msgTransmit.field.brs = CAN_NON_BRS_MODE; +[e = . . . _msgTransmit 1 1 4 -> . `E22706 0 `uc ] +"70 +[; ;MESSAGES.C: 70: msgTransmit.field.frameType = CAN_FRAME_DATA; +[e = . . . _msgTransmit 1 1 1 -> . `E22714 0 `uc ] +"71 +[; ;MESSAGES.C: 71: msgTransmit.field.idType = CAN_FRAME_STD; +[e = . . . _msgTransmit 1 1 0 -> . `E22710 0 `uc ] +"72 +[; ;MESSAGES.C: 72: msgTransmit.field.dlc = ( dataLength & 0x0F ); +[e = . . . _msgTransmit 1 1 2 -> & -> _dataLength `i -> 15 `i `uc ] +"73 +[; ;MESSAGES.C: 73: msgTransmit.data = CANDATAdata; +[e = . _msgTransmit 2 &U _CANDATAdata ] +"75 +[; ;MESSAGES.C: 75: if(CAN1_IsBusOff() == 0x01) +[e $ ! == -> ( _CAN1_IsBusOff .. `i -> 1 `i 3183 ] +"76 +[; ;MESSAGES.C: 76: { +{ +"77 +[; ;MESSAGES.C: 77: __nop(); +[e ( ___nop .. ] +"78 +[; ;MESSAGES.C: 78: } +} +[e :U 3183 ] +"79 +[; ;MESSAGES.C: 79: if(CAN1_IsTxErrorPassive() == 0x01) +[e $ ! == -> ( _CAN1_IsTxErrorPassive .. `i -> 1 `i 3184 ] +"80 +[; ;MESSAGES.C: 80: { +{ +"81 +[; ;MESSAGES.C: 81: __nop(); +[e ( ___nop .. ] +"82 +[; ;MESSAGES.C: 82: } +} +[e :U 3184 ] +"83 +[; ;MESSAGES.C: 83: if(CAN1_IsTxErrorWarning() == 0x01) +[e $ ! == -> ( _CAN1_IsTxErrorWarning .. `i -> 1 `i 3185 ] +"84 +[; ;MESSAGES.C: 84: { +{ +"85 +[; ;MESSAGES.C: 85: __nop(); +[e ( ___nop .. ] +"86 +[; ;MESSAGES.C: 86: } +} +[e :U 3185 ] +"87 +[; ;MESSAGES.C: 87: if(CAN1_IsTxErrorActive() == 0x01) +[e $ ! == -> ( _CAN1_IsTxErrorActive .. `i -> 1 `i 3186 ] +"88 +[; ;MESSAGES.C: 88: { +{ +"89 +[; ;MESSAGES.C: 89: __nop(); +[e ( ___nop .. ] +"90 +[; ;MESSAGES.C: 90: } +} +[e :U 3186 ] +"92 +[; ;MESSAGES.C: 92: if(CAN_TX_FIFO_AVAILABLE == (CAN1_TransmitFIFOStatusGet(TXQ) & CAN_TX_FIFO_AVAILABLE)) +[e $ ! == -> . `E22743 1 `ui & -> ( _CAN1_TransmitFIFOStatusGet (1 . `E22765 0 `ui -> . `E22743 1 `ui 3187 ] +"93 +[; ;MESSAGES.C: 93: { +{ +"94 +[; ;MESSAGES.C: 94: CAN1_Transmit(TXQ, &msgTransmit); +[e ( _CAN1_Transmit (2 , . `E22765 0 &U _msgTransmit ] +"95 +[; ;MESSAGES.C: 95: __nop(); +[e ( ___nop .. ] +"96 +[; ;MESSAGES.C: 96: } +} +[e :U 3187 ] +"97 +[; ;MESSAGES.C: 97: } +[e :UE 3182 ] +} +"101 +[; ;MESSAGES.C: 101: void CANReadMessage (void) +[v _CANReadMessage `(v ~T0 @X0 1 ef ] +"102 +[; ;MESSAGES.C: 102: { +{ +[e :U _CANReadMessage ] +[f ] +"103 +[; ;MESSAGES.C: 103: uint32_t id; +[v _id `ul ~T0 @X0 1 a ] +"104 +[; ;MESSAGES.C: 104: unsigned char idType; +[v _idType `uc ~T0 @X0 1 a ] +"105 +[; ;MESSAGES.C: 105: unsigned char dlc; +[v _dlc `uc ~T0 @X0 1 a ] +"106 +[; ;MESSAGES.C: 106: unsigned char data1; +[v _data1 `uc ~T0 @X0 1 a ] +"107 +[; ;MESSAGES.C: 107: unsigned char data2; +[v _data2 `uc ~T0 @X0 1 a ] +"108 +[; ;MESSAGES.C: 108: unsigned char data3; +[v _data3 `uc ~T0 @X0 1 a ] +"109 +[; ;MESSAGES.C: 109: unsigned char data4; +[v _data4 `uc ~T0 @X0 1 a ] +"110 +[; ;MESSAGES.C: 110: unsigned char data5; +[v _data5 `uc ~T0 @X0 1 a ] +"111 +[; ;MESSAGES.C: 111: unsigned char data6; +[v _data6 `uc ~T0 @X0 1 a ] +"112 +[; ;MESSAGES.C: 112: unsigned char data7; +[v _data7 `uc ~T0 @X0 1 a ] +"113 +[; ;MESSAGES.C: 113: unsigned char data8; +[v _data8 `uc ~T0 @X0 1 a ] +"115 +[; ;MESSAGES.C: 115: if(CAN1_ReceivedMessageCountGet() > 0) +[e $ ! > -> ( _CAN1_ReceivedMessageCountGet .. `i -> 0 `i 3189 ] +"116 +[; ;MESSAGES.C: 116: { +{ +"117 +[; ;MESSAGES.C: 117: if(1 == CAN1_Receive(&msgReceipt)) +[e $ ! == -> 1 `i -> ( _CAN1_Receive (1 &U _msgReceipt `i 3190 ] +"118 +[; ;MESSAGES.C: 118: { +{ +"119 +[; ;MESSAGES.C: 119: __nop(); +[e ( ___nop .. ] +"120 +[; ;MESSAGES.C: 120: id = msgReceipt.msgId; +[e = _id . _msgReceipt 0 ] +"121 +[; ;MESSAGES.C: 121: idType = msgReceipt.field.idType; +[e = _idType . . . _msgReceipt 1 1 0 ] +"122 +[; ;MESSAGES.C: 122: dlc = msgReceipt.field.dlc; +[e = _dlc . . . _msgReceipt 1 1 2 ] +"123 +[; ;MESSAGES.C: 123: data1 = msgReceipt.data[0]; +[e = _data1 *U + . _msgReceipt 2 * -> -> 0 `i `x -> -> # *U . _msgReceipt 2 `i `x ] +"124 +[; ;MESSAGES.C: 124: data2 = msgReceipt.data[1]; +[e = _data2 *U + . _msgReceipt 2 * -> -> 1 `i `x -> -> # *U . _msgReceipt 2 `i `x ] +"125 +[; ;MESSAGES.C: 125: data3 = msgReceipt.data[2]; +[e = _data3 *U + . _msgReceipt 2 * -> -> 2 `i `x -> -> # *U . _msgReceipt 2 `i `x ] +"126 +[; ;MESSAGES.C: 126: data4 = msgReceipt.data[3]; +[e = _data4 *U + . _msgReceipt 2 * -> -> 3 `i `x -> -> # *U . _msgReceipt 2 `i `x ] +"127 +[; ;MESSAGES.C: 127: data5 = msgReceipt.data[4]; +[e = _data5 *U + . _msgReceipt 2 * -> -> 4 `i `x -> -> # *U . _msgReceipt 2 `i `x ] +"128 +[; ;MESSAGES.C: 128: data6 = msgReceipt.data[5]; +[e = _data6 *U + . _msgReceipt 2 * -> -> 5 `i `x -> -> # *U . _msgReceipt 2 `i `x ] +"129 +[; ;MESSAGES.C: 129: data7 = msgReceipt.data[6]; +[e = _data7 *U + . _msgReceipt 2 * -> -> 6 `i `x -> -> # *U . _msgReceipt 2 `i `x ] +"130 +[; ;MESSAGES.C: 130: data8 = msgReceipt.data[7]; +[e = _data8 *U + . _msgReceipt 2 * -> -> 7 `i `x -> -> # *U . _msgReceipt 2 `i `x ] +"132 +[; ;MESSAGES.C: 132: switch (id) +[e $U 3192 ] +"133 +[; ;MESSAGES.C: 133: { +{ +"134 +[; ;MESSAGES.C: 134: case 0x320: +[e :U 3193 ] +"135 +[; ;MESSAGES.C: 135: ucTargetAccelerator = data1; +[e = _ucTargetAccelerator _data1 ] +"136 +[; ;MESSAGES.C: 136: ucTargetClutch = data2; +[e = _ucTargetClutch _data2 ] +"137 +[; ;MESSAGES.C: 137: ucTargetBrake = data3; +[e = _ucTargetBrake _data3 ] +"138 +[; ;MESSAGES.C: 138: ucTargetDirection = data4; +[e = _ucTargetDirection _data4 ] +"139 +[; ;MESSAGES.C: 139: ucTargetGear = data5; +[e = _ucTargetGear _data5 ] +"141 +[; ;MESSAGES.C: 141: if ( ucASMode == 1 ) +[e $ ! == -> _ucASMode `i -> 1 `i 3194 ] +"142 +[; ;MESSAGES.C: 142: { +{ +"147 +[; ;MESSAGES.C: 147: ucETCBeatSupervisor = 0x01; +[e = _ucETCBeatSupervisor -> -> 1 `i `uc ] +"148 +[; ;MESSAGES.C: 148: } +} +[e :U 3194 ] +"150 +[; ;MESSAGES.C: 150: break; +[e $U 3191 ] +"151 +[; ;MESSAGES.C: 151: case 0x500: +[e :U 3195 ] +"152 +[; ;MESSAGES.C: 152: ucAS_state = ( data1 & 0x07 ); +[e = _ucAS_state -> & -> _data1 `i -> 7 `i `uc ] +"153 +[; ;MESSAGES.C: 153: ucEBS_state = ( data1 & 0x18 ); +[e = _ucEBS_state -> & -> _data1 `i -> 24 `i `uc ] +"154 +[; ;MESSAGES.C: 154: ucAMI_state = ( data1 & 0xE0 ); +[e = _ucAMI_state -> & -> _data1 `i -> 224 `i `uc ] +"155 +[; ;MESSAGES.C: 155: ucSteering_state = ( data2 & 0x01 ); +[e = _ucSteering_state -> & -> _data2 `i -> 1 `i `uc ] +"156 +[; ;MESSAGES.C: 156: ucService_brake = ( data2 & 0x06 ); +[e = _ucService_brake -> & -> _data2 `i -> 6 `i `uc ] +"157 +[; ;MESSAGES.C: 157: ucLap_counter = ( data2 & 0x78 ); +[e = _ucLap_counter -> & -> _data2 `i -> 120 `i `uc ] +"160 +[; ;MESSAGES.C: 160: break; +[e $U 3191 ] +"161 +[; ;MESSAGES.C: 161: case 0x501: +[e :U 3196 ] +"162 +[; ;MESSAGES.C: 162: ucSpeed_actual = data1; +[e = _ucSpeed_actual _data1 ] +"163 +[; ;MESSAGES.C: 163: ucSpeed_target = data2; +[e = _ucSpeed_target _data2 ] +"164 +[; ;MESSAGES.C: 164: ucSteering_angle_actual = data3; +[e = _ucSteering_angle_actual _data3 ] +"165 +[; ;MESSAGES.C: 165: ucSteering_angle_target = data4; +[e = _ucSteering_angle_target _data4 ] +"166 +[; ;MESSAGES.C: 166: ucBrake_hydr_actual = data5; +[e = _ucBrake_hydr_actual _data5 ] +"167 +[; ;MESSAGES.C: 167: ucBrake_hydr_target = data6; +[e = _ucBrake_hydr_target _data6 ] +"168 +[; ;MESSAGES.C: 168: ucMotor_moment_actual = data7; +[e = _ucMotor_moment_actual _data7 ] +"169 +[; ;MESSAGES.C: 169: ucMotor_moment_target = data8; +[e = _ucMotor_moment_target _data8 ] +"170 +[; ;MESSAGES.C: 170: break; +[e $U 3191 ] +"171 +[; ;MESSAGES.C: 171: case 0x502: +[e :U 3197 ] +"175 +[; ;MESSAGES.C: 175: break; +[e $U 3191 ] +"176 +[; ;MESSAGES.C: 176: case 0x347: +[e :U 3198 ] +"177 +[; ;MESSAGES.C: 177: ucASMode = data1; +[e = _ucASMode _data1 ] +"178 +[; ;MESSAGES.C: 178: ETCModeSelect(ucASMode); +[e ( _ETCModeSelect (1 _ucASMode ] +"179 +[; ;MESSAGES.C: 179: break; +[e $U 3191 ] +"180 +[; ;MESSAGES.C: 180: case 0x412: +[e :U 3199 ] +"181 +[; ;MESSAGES.C: 181: ucSTEER_WH_Clutch = data1; +[e = _ucSTEER_WH_Clutch _data1 ] +"186 +[; ;MESSAGES.C: 186: break; +[e $U 3191 ] +"187 +[; ;MESSAGES.C: 187: default: +[e :U 3200 ] +"188 +[; ;MESSAGES.C: 188: __nop(); +[e ( ___nop .. ] +"189 +[; ;MESSAGES.C: 189: break; +[e $U 3191 ] +"190 +[; ;MESSAGES.C: 190: } +} +[e $U 3191 ] +[e :U 3192 ] +[e [\ _id , $ -> -> -> 800 `i `l `ul 3193 + , $ -> -> -> 1280 `i `l `ul 3195 + , $ -> -> -> 1281 `i `l `ul 3196 + , $ -> -> -> 1282 `i `l `ul 3197 + , $ -> -> -> 839 `i `l `ul 3198 + , $ -> -> -> 1042 `i `l `ul 3199 + 3200 ] +[e :U 3191 ] +"191 +[; ;MESSAGES.C: 191: } +} +[e :U 3190 ] +"192 +[; ;MESSAGES.C: 192: } +} +[e :U 3189 ] +"193 +[; ;MESSAGES.C: 193: } +[e :UE 3188 ] +} +"196 +[; ;MESSAGES.C: 196: void CANDisableErrorInterrupt (unsigned char ucInterruptSet) +[v _CANDisableErrorInterrupt `(v ~T0 @X0 1 ef1`uc ] +"197 +[; ;MESSAGES.C: 197: { +{ +[e :U _CANDisableErrorInterrupt ] +"196 +[; ;MESSAGES.C: 196: void CANDisableErrorInterrupt (unsigned char ucInterruptSet) +[v _ucInterruptSet `uc ~T0 @X0 1 r1 ] +"197 +[; ;MESSAGES.C: 197: { +[f ] +"198 +[; ;MESSAGES.C: 198: if (ucInterruptSet == 0x01) +[e $ ! == -> _ucInterruptSet `i -> 1 `i 3202 ] +"199 +[; ;MESSAGES.C: 199: { +{ +"200 +[; ;MESSAGES.C: 200: PIE0bits.CANIE = 1; +[e = . . _PIE0bits 0 6 -> -> 1 `i `uc ] +"201 +[; ;MESSAGES.C: 201: } +} +[e $U 3203 ] +"202 +[; ;MESSAGES.C: 202: else if (ucInterruptSet == 0x00) +[e :U 3202 ] +[e $ ! == -> _ucInterruptSet `i -> 0 `i 3204 ] +"203 +[; ;MESSAGES.C: 203: { +{ +"204 +[; ;MESSAGES.C: 204: PIE0bits.CANIE = 0; +[e = . . _PIE0bits 0 6 -> -> 0 `i `uc ] +"205 +[; ;MESSAGES.C: 205: } +} +[e :U 3204 ] +[e :U 3203 ] +"207 +[; ;MESSAGES.C: 207: } +[e :UE 3201 ] +} diff --git a/ETC.X/build/default/debug/MESSAGES.p1.d b/ETC.X/build/default/debug/MESSAGES.p1.d new file mode 100644 index 0000000..dab2ac3 --- /dev/null +++ b/ETC.X/build/default/debug/MESSAGES.p1.d @@ -0,0 +1,20 @@ +build/default/debug/MESSAGES.p1: \ +MESSAGES.C \ +MESSAGES.h \ +mcc_generated_files/mcc.h \ +mcc_generated_files/device_config.h \ +mcc_generated_files/pin_manager.h \ +mcc_generated_files/interrupt_manager.h \ +mcc_generated_files/i2c1_master.h \ +mcc_generated_files/adc.h \ +mcc_generated_files/tmr1.h \ +mcc_generated_files/tmr0.h \ +mcc_generated_files/can1.h \ +mcc_generated_files/can_types.h \ +mcc_generated_files/drivers/i2c_simple_master.h \ +mcc_generated_files/pwm2_16bit.h \ +mcc_generated_files/DAC3.h \ +mcc_generated_files/pwm1_16bit.h \ +ETC.h \ +CLUTCH.h \ +PARAMETERS.h diff --git a/ETC.X/build/default/debug/TEMPORIZATIONS.i b/ETC.X/build/default/debug/TEMPORIZATIONS.i new file mode 100644 index 0000000..6481f81 --- /dev/null +++ b/ETC.X/build/default/debug/TEMPORIZATIONS.i @@ -0,0 +1,38548 @@ +# 1 "TEMPORIZATIONS.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "TEMPORIZATIONS.c" 2 + + + + + + + +# 1 "./../ETC.X/mcc_generated_files/pin_manager.h" 1 +# 54 "./../ETC.X/mcc_generated_files/pin_manager.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 54 "./../ETC.X/mcc_generated_files/pin_manager.h" 2 +# 402 "./../ETC.X/mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "./../ETC.X/mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 8 "TEMPORIZATIONS.c" 2 + +# 1 "./CLUTCH.h" 1 +# 31 "./CLUTCH.h" +extern unsigned char ucCLUTCHlmin; +extern unsigned char ucCLUTCHlmax; +extern unsigned char ucCLUTCHDuty; +extern unsigned char ucCLUTCHState; + + + +void CLUTCH_Init (void); +void CLUTCH_Move (unsigned char ucTargetMove, unsigned char ucMode); +void CLUTCH_AnalyseState (void); +void CLUTCHInitMove(void); +void CLUTCH_HighLevelMovements (unsigned char ucClutchAction); +# 9 "TEMPORIZATIONS.c" 2 + +# 1 "./TEMPORIZATIONS.h" 1 +# 23 "./TEMPORIZATIONS.h" +extern unsigned char ucCount500ms; +extern unsigned char ucCount1s; +extern unsigned char ucCount10s; +extern unsigned int uiCount30s; +extern unsigned int uiCount1min; +extern unsigned char ucCount50ms; + + + +void TEMPORIZATION_10ms (void); +void TEMPORIZATION_100ms (void); +void TEMPORIZATION_500ms (void); +void TEMPORIZATION_1s (void); +void TEMPORIZATION_10s (void); +void TEMPORIZATION_30s (void); +void TEMPORIZATION_1mins (void); +# 10 "TEMPORIZATIONS.c" 2 + +# 1 "./ANALOG.h" 1 +# 22 "./ANALOG.h" +unsigned int ANALOG_GetVoltage (unsigned char ucEntradaAnalogica); +void ANALOGRead (void); +# 11 "TEMPORIZATIONS.c" 2 + +# 1 "./MESSAGES.h" 1 +# 16 "./MESSAGES.h" +# 1 "./mcc_generated_files/mcc.h" 1 +# 50 "./mcc_generated_files/mcc.h" +# 1 "./../ETC.X/mcc_generated_files/device_config.h" 1 +# 50 "./mcc_generated_files/mcc.h" 2 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 53 "./mcc_generated_files/mcc.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 1 3 + + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 1 3 +# 12 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 3 +extern int errno; +# 8 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__null.h" 1 3 +# 9 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + + + +extern void init_uart(void); + +extern char getch(void); +extern char getche(void); +extern void putch(char); +extern void ungetch(char); + +extern __bit kbhit(void); + + + +extern char * cgets(char *); +extern void cputs(const char *); +# 54 "./mcc_generated_files/mcc.h" 2 + +# 1 "./../ETC.X/mcc_generated_files/interrupt_manager.h" 1 +# 87 "./../ETC.X/mcc_generated_files/interrupt_manager.h" +void INTERRUPT_Initialize (void); +# 55 "./mcc_generated_files/mcc.h" 2 + +# 1 "./../ETC.X/mcc_generated_files/i2c1_master.h" 1 +# 54 "./../ETC.X/mcc_generated_files/i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "./../ETC.X/mcc_generated_files/i2c1_master.h" 2 + + + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "./../ETC.X/mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "./../ETC.X/mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "./../ETC.X/mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "./../ETC.X/mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "./../ETC.X/mcc_generated_files/i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "./../ETC.X/mcc_generated_files/i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "./../ETC.X/mcc_generated_files/i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "./../ETC.X/mcc_generated_files/i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "./../ETC.X/mcc_generated_files/i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "./../ETC.X/mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 56 "./mcc_generated_files/mcc.h" 2 + +# 1 "./../ETC.X/mcc_generated_files/adc.h" 1 +# 65 "./../ETC.X/mcc_generated_files/adc.h" +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "./../ETC.X/mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "./../ETC.X/mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "./../ETC.X/mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "./../ETC.X/mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "./../ETC.X/mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "./../ETC.X/mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "./../ETC.X/mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "./../ETC.X/mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "./../ETC.X/mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "./../ETC.X/mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "./../ETC.X/mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "./../ETC.X/mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "./../ETC.X/mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "./../ETC.X/mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 57 "./mcc_generated_files/mcc.h" 2 + +# 1 "./../ETC.X/mcc_generated_files/tmr1.h" 1 +# 101 "./../ETC.X/mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "./../ETC.X/mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "./../ETC.X/mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "./../ETC.X/mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "./../ETC.X/mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "./../ETC.X/mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "./../ETC.X/mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "./../ETC.X/mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "./../ETC.X/mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "./../ETC.X/mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "./../ETC.X/mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "./../ETC.X/mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "./../ETC.X/mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 58 "./mcc_generated_files/mcc.h" 2 + +# 1 "./../ETC.X/mcc_generated_files/tmr0.h" 1 +# 106 "./../ETC.X/mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "./../ETC.X/mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "./../ETC.X/mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "./../ETC.X/mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "./../ETC.X/mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "./../ETC.X/mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "./../ETC.X/mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "./../ETC.X/mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "./../ETC.X/mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "./../ETC.X/mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "./../ETC.X/mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 59 "./mcc_generated_files/mcc.h" 2 + +# 1 "./../ETC.X/mcc_generated_files/can1.h" 1 +# 56 "./../ETC.X/mcc_generated_files/can1.h" +# 1 "./../ETC.X/mcc_generated_files/can_types.h" 1 +# 65 "./../ETC.X/mcc_generated_files/can_types.h" +typedef union +{ + uint8_t msgfields; + struct + { + uint8_t idType:1; + uint8_t frameType:1; + uint8_t dlc:4; + uint8_t formatType:1; + uint8_t brs:1; + }; +} CAN_MSG_FIELD; + +typedef struct +{ + uint32_t msgId; + CAN_MSG_FIELD field; + uint8_t *data; +} CAN_MSG_OBJ; +# 94 "./../ETC.X/mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NON_BRS_MODE = 0, + CAN_BRS_MODE = 1 +} CAN_MSG_OBJ_BRS_MODE; +# 109 "./../ETC.X/mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_STD = 0, + CAN_FRAME_EXT = 1, +} CAN_MSG_OBJ_ID_TYPE; +# 124 "./../ETC.X/mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_DATA = 0, + CAN_FRAME_RTR = 1, +} CAN_MSG_OBJ_FRAME_TYPE; +# 139 "./../ETC.X/mcc_generated_files/can_types.h" +typedef enum +{ + CAN_2_0_FORMAT = 0, + CAN_FD_FORMAT = 1 +} CAN_MSG_OBJ_TYPE; +# 154 "./../ETC.X/mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_MSG_REQUEST_SUCCESS = 0, + CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR = 1, + CAN_TX_MSG_REQUEST_BRS_ERROR = 2, + CAN_TX_MSG_REQUEST_FIFO_FULL = 3, +} CAN_TX_MSG_REQUEST_STATUS; +# 171 "./../ETC.X/mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NORMAL_FD_MODE = 0, + CAN_DISABLE_MODE = 1, + CAN_INTERNAL_LOOPBACK_MODE = 2, + CAN_LISTEN_ONLY_MODE = 3, + CAN_CONFIGURATION_MODE = 4, + CAN_EXTERNAL_LOOPBACK_MODE = 5, + CAN_NORMAL_2_0_MODE = 6, + CAN_RESTRICTED_OPERATION_MODE =7, +} CAN_OP_MODES; +# 192 "./../ETC.X/mcc_generated_files/can_types.h" +typedef enum +{ + CAN_OP_MODE_REQUEST_SUCCESS, + CAN_OP_MODE_REQUEST_FAIL, + CAN_OP_MODE_SYS_ERROR_OCCURED +} CAN_OP_MODE_STATUS; +# 208 "./../ETC.X/mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_FIFO_FULL, + CAN_TX_FIFO_AVAILABLE, +} CAN_TX_FIFO_STATUS; +# 223 "./../ETC.X/mcc_generated_files/can_types.h" +typedef enum +{ + + DLC_0, + DLC_1, + DLC_2, + DLC_3, + DLC_4, + DLC_5, + DLC_6, + DLC_7, + DLC_8, + + + + DLC_12, + DLC_16, + DLC_20, + DLC_24, + DLC_32, + DLC_48, + DLC_64, +} CAN_DLC; +# 56 "./../ETC.X/mcc_generated_files/can1.h" 2 + + + + + +typedef enum +{ + TXQ = 0 +} CAN1_TX_FIFO_CHANNELS; + +typedef enum +{ + FIFO1 = 1 +} CAN1_RX_FIFO_CHANNELS; +# 106 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_Initialize(void); +# 147 "./../ETC.X/mcc_generated_files/can1.h" +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +# 185 "./../ETC.X/mcc_generated_files/can1.h" +CAN_OP_MODES CAN1_OperationModeGet(void); +# 235 "./../ETC.X/mcc_generated_files/can1.h" +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +# 275 "./../ETC.X/mcc_generated_files/can1.h" +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *rxCanMsg); +# 334 "./../ETC.X/mcc_generated_files/can1.h" +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +# 390 "./../ETC.X/mcc_generated_files/can1.h" +_Bool CAN1_IsBusOff(void); +# 448 "./../ETC.X/mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorPassive(void); +# 507 "./../ETC.X/mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorWarning(void); +# 566 "./../ETC.X/mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorActive(void); +# 614 "./../ETC.X/mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorPassive(void); +# 662 "./../ETC.X/mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorWarning(void); +# 710 "./../ETC.X/mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorActive(void); +# 761 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_Sleep(void); +# 815 "./../ETC.X/mcc_generated_files/can1.h" +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +# 857 "./../ETC.X/mcc_generated_files/can1.h" +uint8_t CAN1_ReceivedMessageCountGet(void); +# 924 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +# 981 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +# 1049 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +# 1100 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +# 1169 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +# 1237 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +# 1289 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +# 1324 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +# 1368 "./../ETC.X/mcc_generated_files/can1.h" +void CAN1_SetTXQnullHandler(void (*handler)(void)); + + +void CAN1_ISR(void); +void CAN1_RXI_ISR(void); +# 60 "./mcc_generated_files/mcc.h" 2 + +# 1 "./../ETC.X/mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 37 "./../ETC.X/mcc_generated_files/drivers/i2c_simple_master.h" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 61 "./mcc_generated_files/mcc.h" 2 + +# 1 "./../ETC.X/mcc_generated_files/pwm2_16bit.h" 1 +# 63 "./../ETC.X/mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "./../ETC.X/mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "./../ETC.X/mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./../ETC.X/mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./../ETC.X/mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./../ETC.X/mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "./../ETC.X/mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./../ETC.X/mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./../ETC.X/mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 62 "./mcc_generated_files/mcc.h" 2 + +# 1 "./../ETC.X/mcc_generated_files/DAC3.h" 1 +# 29 "./../ETC.X/mcc_generated_files/DAC3.h" +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 63 "./mcc_generated_files/mcc.h" 2 + +# 1 "./../ETC.X/mcc_generated_files/pwm1_16bit.h" 1 +# 63 "./../ETC.X/mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "./../ETC.X/mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "./../ETC.X/mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./../ETC.X/mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./../ETC.X/mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./../ETC.X/mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "./../ETC.X/mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./../ETC.X/mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./../ETC.X/mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 64 "./mcc_generated_files/mcc.h" 2 +# 79 "./mcc_generated_files/mcc.h" +void SYSTEM_Initialize(void); +# 92 "./mcc_generated_files/mcc.h" +void OSCILLATOR_Initialize(void); +# 105 "./mcc_generated_files/mcc.h" +void PMD_Initialize(void); +# 16 "./MESSAGES.h" 2 + + + + + + +CAN_MSG_OBJ msgTransmit; +CAN_MSG_OBJ msgReceipt; +uint8_t CANDATAdata[8]; + + +extern unsigned char CANDATAdata[8]; + +extern unsigned char ucTargetAccelerator; +extern unsigned char ucTargetClutch; +extern unsigned char ucTargetClutch_PREV; +extern unsigned char ucTargetBrake; +extern unsigned char ucTargetDirection; +extern unsigned char ucTargetGear; + +extern unsigned char ucAS_state; +extern unsigned char ucEBS_state; +extern unsigned char ucAMI_state; +extern unsigned char ucSteering_state; +extern unsigned char ucService_brake; +extern unsigned char ucLap_counter; +extern unsigned char ucCones_count_actual; +extern unsigned char ucCones_count_all; + +extern unsigned char ucSpeed_actual; +extern unsigned char ucSpeed_target; +extern unsigned char ucSteering_angle_actual; +extern unsigned char ucSteering_angle_target; +extern unsigned char ucBrake_hydr_actual; +extern unsigned char ucBrake_hydr_target; +extern unsigned char ucMotor_moment_actual; +extern unsigned char ucMotor_moment_target; + +extern unsigned int uiAcc_longitudinal; +extern unsigned int uiAcc_lateral; +extern unsigned int uiYaw_rate; + +extern unsigned char ucASBState; +extern unsigned char ucASRequesState; + +extern unsigned char ucASMode; + +extern unsigned char ucSTEER_WH_Clutch; +# 98 "./MESSAGES.h" +void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8); +void CANReadMessage (void); +void CANDisableErrorInterrupt (unsigned char ucInterruptSet); +# 12 "TEMPORIZATIONS.c" 2 + +# 1 "./ETC.h" 1 +# 65 "./ETC.h" +unsigned int uiTPS1TableIn [21]; +unsigned char ucTPS1TableOut [21]; +unsigned int uiTPS2TableIn [21]; +unsigned char ucTPS2TableOut [21]; + +typedef struct { + + + float Kp; + float Ki; + float Kd; + + + float tau; + + + float limMin; + float limMax; + + + float limMinInt; + float limMaxInt; + + + float T; + + + float integrator; + float prevError; + float differentiator; + float prevMeasurement; + + + float out; + +} PIDController; + +PIDController pid = { 2.4f, 1.4f, 0.0f, + 0.02f, + 0.0f, 100.0f, + -10.0f, 10.0f, + 0.01f }; + + + +extern unsigned int uiAPPS1min; +extern unsigned int uiAPPS1max; +extern unsigned int uiAPPS2min; +extern unsigned int uiAPPS2max; +extern unsigned int uiTPS1min; +extern unsigned int uiTPS1max; +extern unsigned int uiTPS2min; +extern unsigned int uiTPS2max; +extern unsigned int uiAPPS1; +extern unsigned int uiAPPS2; +extern unsigned char ucAPPS_STATE; +extern unsigned long ulAPPS1calc; +extern unsigned long ulAPPS2calc; +extern unsigned int ucAPPS1Perc; +extern unsigned int ucAPPS2Perc; +extern unsigned int ucAPPS; +extern unsigned int uiTPS1; +extern unsigned int uiTPS2; +extern signed long ulTPS1calc; +extern signed long ulTPS2calc; +extern unsigned int ucTPS1Perc; +extern unsigned int ucTPS2Perc; +extern unsigned int ucTPS; +extern unsigned char ucTPS_STATE; +extern unsigned char ucTPS1_STATE; +extern unsigned char ucTPS2_STATE; +extern unsigned char ucTPS_Volts_STATE; +extern unsigned int uiETCDuty; +extern unsigned char ucETB_STATE; +extern unsigned char ucETCBeatSupervisor; +extern unsigned char ucETCFlagSupervisor; +extern unsigned char ucAPPSManual; +extern unsigned char ucETCTimerRuleTPS; +extern unsigned char ucETCTimerRuleAPPS; +extern unsigned char ucCount100msTPSError; +extern unsigned char ucCount100msAPPSError; +extern unsigned char ucETCRuleSupervisor; +extern unsigned char ucETCTargetTPSDiff; +extern unsigned char ucCount500msTPSDiff; +extern unsigned char ucETCMotorNotClose; +extern unsigned char ucETCResolveNotCloseError; +extern unsigned char ucCount500msResolveNotCloseError; + +extern unsigned int ucAPPSTargetPruebas; + +void ETCInit(void); +void APPSSend (unsigned char ucPercent); +void APPSReadmin (void); +void APPSReadmax (void); +void ETCModeSelect (unsigned char ucModeSelect); +void ETCRulesSupervision(void); +void ETCMove(unsigned char ucTargetMove, unsigned char ucMode); +void ETC_PID(signed long slTargetMove, unsigned char ucMode); +void ETCCalibrate(void); +void TPSAnalysis (void); +void APPSAnalysis (void); +void ETCXavierSupervisor (void); +void ETCManual (unsigned char ucTargetManual); +unsigned int ETCPercentCalc(signed long val, signed long min, signed long max); +void ETCRulesSensorsSupervision(void); +void ETC100msSupervisor (void); +void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactual); +void ETC500msSupervisor (void); +void PIDController_Init(PIDController *pid); +float PIDController_Update(PIDController *pid, float setpoint, float measurement); +unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +# 13 "TEMPORIZATIONS.c" 2 + +# 1 "./PARAMETERS.h" 1 +# 31 "./PARAMETERS.h" +extern signed long sl_K; +extern signed long sl_K_P; +extern signed long sl_K_I; +extern signed long sl_K_D; +# 14 "TEMPORIZATIONS.c" 2 + + + +unsigned char ucCount500ms; +unsigned char ucCount1s; +unsigned char ucCount10s; +unsigned int uiCount30s; +unsigned int uiCount1min; +unsigned char ucCount50ms; + + + +void TEMPORIZATION_10ms (void) +{ + + if (ucCount50ms++ == 5 ) + { + TPSAnalysis(); + APPSAnalysis(); + ucCount50ms = 0; + } +} + +void TEMPORIZATION_100ms (void) +{ + + + + + ETC100msSupervisor(); + CANWriteMessage(0x330, 6, ucAPPS1Perc, ucAPPS2Perc, ucTPS1Perc, ucTPS2Perc, ucAPPS, ucTPS, 0, 0); + +} + +void TEMPORIZATION_500ms (void) +{ + + + CLUTCH_AnalyseState(); + + ETCXavierSupervisor(); + ucETCBeatSupervisor = 0x00; + ETC500msSupervisor(); +} + +void TEMPORIZATION_1s (void) +{ + CANWriteMessage(0x331, 4, ucTPS_STATE, ucAPPS_STATE, ucCLUTCHState, ucETB_STATE, 0, 0, 0, 0); + +} + +void TEMPORIZATION_10s (void) +{ + +} + +void TEMPORIZATION_30s (void) +{ + +} + +void TEMPORIZATION_1mins (void) +{ + +} diff --git a/ETC.X/build/default/debug/TEMPORIZATIONS.p1 b/ETC.X/build/default/debug/TEMPORIZATIONS.p1 new file mode 100644 index 0000000..9a12bba --- /dev/null +++ b/ETC.X/build/default/debug/TEMPORIZATIONS.p1 @@ -0,0 +1,3768 @@ +Version 4.0 HI-TECH Software Intermediate Code +"69 ./../ETC.X/mcc_generated_files/can_types.h +[; ;./../ETC.X/mcc_generated_files/can_types.h: 69: { +[s S3179 :1 `uc 1 :1 `uc 1 :4 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3179 . idType frameType dlc formatType brs ] +"66 +[; ;./../ETC.X/mcc_generated_files/can_types.h: 66: { +[u S3178 `uc 1 `S3179 1 ] +[n S3178 . msgfields . ] +"79 +[; ;./../ETC.X/mcc_generated_files/can_types.h: 79: { +[s S3180 `ul 1 `S3178 1 `*uc 1 ] +[n S3180 . msgId field data ] +"70 ./ETC.h +[; ;./ETC.h: 70: typedef struct { +[s S3181 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 ] +[n S3181 . Kp Ki Kd tau limMin limMax limMinInt limMaxInt T integrator prevError differentiator prevMeasurement out ] +"164 +[; ;./ETC.h: 164: void TPSAnalysis (void); +[v _TPSAnalysis `(v ~T0 @X0 0 ef ] +"165 +[; ;./ETC.h: 165: void APPSAnalysis (void); +[v _APPSAnalysis `(v ~T0 @X0 0 ef ] +"170 +[; ;./ETC.h: 170: void ETC100msSupervisor (void); +[v _ETC100msSupervisor `(v ~T0 @X0 0 ef ] +"98 ./MESSAGES.h +[; ;./MESSAGES.h: 98: void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8); +[v _CANWriteMessage `(v ~T0 @X0 0 ef10`ul`uc`uc`uc`uc`uc`uc`uc`uc`uc ] +"123 ./ETC.h +[; ;./ETC.h: 123: extern unsigned int ucAPPS1Perc; +[v _ucAPPS1Perc `ui ~T0 @X0 0 e ] +"124 +[; ;./ETC.h: 124: extern unsigned int ucAPPS2Perc; +[v _ucAPPS2Perc `ui ~T0 @X0 0 e ] +"130 +[; ;./ETC.h: 130: extern unsigned int ucTPS1Perc; +[v _ucTPS1Perc `ui ~T0 @X0 0 e ] +"131 +[; ;./ETC.h: 131: extern unsigned int ucTPS2Perc; +[v _ucTPS2Perc `ui ~T0 @X0 0 e ] +"125 +[; ;./ETC.h: 125: extern unsigned int ucAPPS; +[v _ucAPPS `ui ~T0 @X0 0 e ] +"132 +[; ;./ETC.h: 132: extern unsigned int ucTPS; +[v _ucTPS `ui ~T0 @X0 0 e ] +"40 ./CLUTCH.h +[; ;./CLUTCH.h: 40: void CLUTCH_AnalyseState (void); +[v _CLUTCH_AnalyseState `(v ~T0 @X0 0 ef ] +"166 ./ETC.h +[; ;./ETC.h: 166: void ETCXavierSupervisor (void); +[v _ETCXavierSupervisor `(v ~T0 @X0 0 ef ] +"139 +[; ;./ETC.h: 139: extern unsigned char ucETCBeatSupervisor; +[v _ucETCBeatSupervisor `uc ~T0 @X0 0 e ] +"172 +[; ;./ETC.h: 172: void ETC500msSupervisor (void); +[v _ETC500msSupervisor `(v ~T0 @X0 0 ef ] +"133 +[; ;./ETC.h: 133: extern unsigned char ucTPS_STATE; +[v _ucTPS_STATE `uc ~T0 @X0 0 e ] +"120 +[; ;./ETC.h: 120: extern unsigned char ucAPPS_STATE; +[v _ucAPPS_STATE `uc ~T0 @X0 0 e ] +"34 ./CLUTCH.h +[; ;./CLUTCH.h: 34: extern unsigned char ucCLUTCHState; +[v _ucCLUTCHState `uc ~T0 @X0 0 e ] +"138 ./ETC.h +[; ;./ETC.h: 138: extern unsigned char ucETB_STATE; +[v _ucETB_STATE `uc ~T0 @X0 0 e ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"22 ./MESSAGES.h +[; ;./MESSAGES.h: 22: CAN_MSG_OBJ msgTransmit; +[v _msgTransmit `S3180 ~T0 @X0 1 e ] +"23 +[; ;./MESSAGES.h: 23: CAN_MSG_OBJ msgReceipt; +[v _msgReceipt `S3180 ~T0 @X0 1 e ] +"24 +[; ;./MESSAGES.h: 24: uint8_t CANDATAdata[8]; +[v _CANDATAdata `uc ~T0 @X0 -> 8 `i e ] +"65 ./ETC.h +[; ;./ETC.h: 65: unsigned int uiTPS1TableIn [21]; +[v _uiTPS1TableIn `ui ~T0 @X0 -> 21 `i e ] +"66 +[; ;./ETC.h: 66: unsigned char ucTPS1TableOut [21]; +[v _ucTPS1TableOut `uc ~T0 @X0 -> 21 `i e ] +"67 +[; ;./ETC.h: 67: unsigned int uiTPS2TableIn [21]; +[v _uiTPS2TableIn `ui ~T0 @X0 -> 21 `i e ] +"68 +[; ;./ETC.h: 68: unsigned char ucTPS2TableOut [21]; +[v _ucTPS2TableOut `uc ~T0 @X0 -> 21 `i e ] +"102 +[; ;./ETC.h: 102: PIDController pid = { 2.4f, 1.4f, 0.0f, +[v _pid `S3181 ~T0 @X0 1 e ] +[i _pid +:U .. +:U .. +-> .2.4 `f +-> .1.4 `f +-> .0.0 `f +-> .0.02 `f +-> .0.0 `f +-> .100.0 `f +-U -> .10.0 `f +-> .10.0 `f +-> .0.01 `f +.. +.. +] +"17 TEMPORIZATIONS.c +[; ;TEMPORIZATIONS.c: 17: unsigned char ucCount500ms; +[v _ucCount500ms `uc ~T0 @X0 1 e ] +"18 +[; ;TEMPORIZATIONS.c: 18: unsigned char ucCount1s; +[v _ucCount1s `uc ~T0 @X0 1 e ] +"19 +[; ;TEMPORIZATIONS.c: 19: unsigned char ucCount10s; +[v _ucCount10s `uc ~T0 @X0 1 e ] +"20 +[; ;TEMPORIZATIONS.c: 20: unsigned int uiCount30s; +[v _uiCount30s `ui ~T0 @X0 1 e ] +"21 +[; ;TEMPORIZATIONS.c: 21: unsigned int uiCount1min; +[v _uiCount1min `ui ~T0 @X0 1 e ] +"22 +[; ;TEMPORIZATIONS.c: 22: unsigned char ucCount50ms; +[v _ucCount50ms `uc ~T0 @X0 1 e ] +"26 +[; ;TEMPORIZATIONS.c: 26: void TEMPORIZATION_10ms (void) +[v _TEMPORIZATION_10ms `(v ~T0 @X0 1 ef ] +"27 +[; ;TEMPORIZATIONS.c: 27: { +{ +[e :U _TEMPORIZATION_10ms ] +[f ] +"29 +[; ;TEMPORIZATIONS.c: 29: if (ucCount50ms++ == 5 ) +[e $ ! == -> ++ _ucCount50ms -> -> 1 `i `uc `i -> 5 `i 3183 ] +"30 +[; ;TEMPORIZATIONS.c: 30: { +{ +"31 +[; ;TEMPORIZATIONS.c: 31: TPSAnalysis(); +[e ( _TPSAnalysis .. ] +"32 +[; ;TEMPORIZATIONS.c: 32: APPSAnalysis(); +[e ( _APPSAnalysis .. ] +"33 +[; ;TEMPORIZATIONS.c: 33: ucCount50ms = 0; +[e = _ucCount50ms -> -> 0 `i `uc ] +"34 +[; ;TEMPORIZATIONS.c: 34: } +} +[e :U 3183 ] +"35 +[; ;TEMPORIZATIONS.c: 35: } +[e :UE 3182 ] +} +"37 +[; ;TEMPORIZATIONS.c: 37: void TEMPORIZATION_100ms (void) +[v _TEMPORIZATION_100ms `(v ~T0 @X0 1 ef ] +"38 +[; ;TEMPORIZATIONS.c: 38: { +{ +[e :U _TEMPORIZATION_100ms ] +[f ] +"43 +[; ;TEMPORIZATIONS.c: 43: ETC100msSupervisor(); +[e ( _ETC100msSupervisor .. ] +"44 +[; ;TEMPORIZATIONS.c: 44: CANWriteMessage(0x330, 6, ucAPPS1Perc, ucAPPS2Perc, ucTPS1Perc, ucTPS2Perc, ucAPPS, ucTPS, 0, 0); +[e ( _CANWriteMessage (4 , , , , , , , , , -> -> -> 816 `i `l `ul -> -> 6 `i `uc -> _ucAPPS1Perc `uc -> _ucAPPS2Perc `uc -> _ucTPS1Perc `uc -> _ucTPS2Perc `uc -> _ucAPPS `uc -> _ucTPS `uc -> -> 0 `i `uc -> -> 0 `i `uc ] +"46 +[; ;TEMPORIZATIONS.c: 46: } +[e :UE 3184 ] +} +"48 +[; ;TEMPORIZATIONS.c: 48: void TEMPORIZATION_500ms (void) +[v _TEMPORIZATION_500ms `(v ~T0 @X0 1 ef ] +"49 +[; ;TEMPORIZATIONS.c: 49: { +{ +[e :U _TEMPORIZATION_500ms ] +[f ] +"52 +[; ;TEMPORIZATIONS.c: 52: CLUTCH_AnalyseState(); +[e ( _CLUTCH_AnalyseState .. ] +"54 +[; ;TEMPORIZATIONS.c: 54: ETCXavierSupervisor(); +[e ( _ETCXavierSupervisor .. ] +"55 +[; ;TEMPORIZATIONS.c: 55: ucETCBeatSupervisor = 0x00; +[e = _ucETCBeatSupervisor -> -> 0 `i `uc ] +"56 +[; ;TEMPORIZATIONS.c: 56: ETC500msSupervisor(); +[e ( _ETC500msSupervisor .. ] +"57 +[; ;TEMPORIZATIONS.c: 57: } +[e :UE 3185 ] +} +"59 +[; ;TEMPORIZATIONS.c: 59: void TEMPORIZATION_1s (void) +[v _TEMPORIZATION_1s `(v ~T0 @X0 1 ef ] +"60 +[; ;TEMPORIZATIONS.c: 60: { +{ +[e :U _TEMPORIZATION_1s ] +[f ] +"61 +[; ;TEMPORIZATIONS.c: 61: CANWriteMessage(0x331, 4, ucTPS_STATE, ucAPPS_STATE, ucCLUTCHState, ucETB_STATE, 0, 0, 0, 0); +[e ( _CANWriteMessage (4 , , , , , , , , , -> -> -> 817 `i `l `ul -> -> 4 `i `uc _ucTPS_STATE _ucAPPS_STATE _ucCLUTCHState _ucETB_STATE -> -> 0 `i `uc -> -> 0 `i `uc -> -> 0 `i `uc -> -> 0 `i `uc ] +"63 +[; ;TEMPORIZATIONS.c: 63: } +[e :UE 3186 ] +} +"65 +[; ;TEMPORIZATIONS.c: 65: void TEMPORIZATION_10s (void) +[v _TEMPORIZATION_10s `(v ~T0 @X0 1 ef ] +"66 +[; ;TEMPORIZATIONS.c: 66: { +{ +[e :U _TEMPORIZATION_10s ] +[f ] +"68 +[; ;TEMPORIZATIONS.c: 68: } +[e :UE 3187 ] +} +"70 +[; ;TEMPORIZATIONS.c: 70: void TEMPORIZATION_30s (void) +[v _TEMPORIZATION_30s `(v ~T0 @X0 1 ef ] +"71 +[; ;TEMPORIZATIONS.c: 71: { +{ +[e :U _TEMPORIZATION_30s ] +[f ] +"73 +[; ;TEMPORIZATIONS.c: 73: } +[e :UE 3188 ] +} +"75 +[; ;TEMPORIZATIONS.c: 75: void TEMPORIZATION_1mins (void) +[v _TEMPORIZATION_1mins `(v ~T0 @X0 1 ef ] +"76 +[; ;TEMPORIZATIONS.c: 76: { +{ +[e :U _TEMPORIZATION_1mins ] +[f ] +"78 +[; ;TEMPORIZATIONS.c: 78: } +[e :UE 3189 ] +} diff --git a/ETC.X/build/default/debug/TEMPORIZATIONS.p1.d b/ETC.X/build/default/debug/TEMPORIZATIONS.p1.d new file mode 100644 index 0000000..289e719 --- /dev/null +++ b/ETC.X/build/default/debug/TEMPORIZATIONS.p1.d @@ -0,0 +1,22 @@ +build/default/debug/TEMPORIZATIONS.p1: \ +TEMPORIZATIONS.c \ +../ETC.X/mcc_generated_files/pin_manager.h \ +CLUTCH.h \ +TEMPORIZATIONS.h \ +ANALOG.h \ +MESSAGES.h \ +mcc_generated_files/mcc.h \ +../ETC.X/mcc_generated_files/device_config.h \ +../ETC.X/mcc_generated_files/interrupt_manager.h \ +../ETC.X/mcc_generated_files/i2c1_master.h \ +../ETC.X/mcc_generated_files/adc.h \ +../ETC.X/mcc_generated_files/tmr1.h \ +../ETC.X/mcc_generated_files/tmr0.h \ +../ETC.X/mcc_generated_files/can1.h \ +../ETC.X/mcc_generated_files/can_types.h \ +../ETC.X/mcc_generated_files/drivers/i2c_simple_master.h \ +../ETC.X/mcc_generated_files/pwm2_16bit.h \ +../ETC.X/mcc_generated_files/DAC3.h \ +../ETC.X/mcc_generated_files/pwm1_16bit.h \ +ETC.h \ +PARAMETERS.h diff --git a/ETC.X/build/default/debug/main.i b/ETC.X/build/default/debug/main.i new file mode 100644 index 0000000..db4b423 --- /dev/null +++ b/ETC.X/build/default/debug/main.i @@ -0,0 +1,38523 @@ +# 1 "main.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "main.c" 2 +# 44 "main.c" +# 1 "./mcc_generated_files/mcc.h" 1 +# 49 "./mcc_generated_files/mcc.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 49 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/device_config.h" 1 +# 50 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/pin_manager.h" 1 +# 402 "./mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "./mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 51 "./mcc_generated_files/mcc.h" 2 + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 53 "./mcc_generated_files/mcc.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 1 3 + + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 1 3 +# 12 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 3 +extern int errno; +# 8 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__null.h" 1 3 +# 9 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + + + +extern void init_uart(void); + +extern char getch(void); +extern char getche(void); +extern void putch(char); +extern void ungetch(char); + +extern __bit kbhit(void); + + + +extern char * cgets(char *); +extern void cputs(const char *); +# 54 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/interrupt_manager.h" 1 +# 87 "./mcc_generated_files/interrupt_manager.h" +void INTERRUPT_Initialize (void); +# 55 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/i2c1_master.h" 1 +# 54 "./mcc_generated_files/i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "./mcc_generated_files/i2c1_master.h" 2 + + + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "./mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "./mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "./mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "./mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 56 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/adc.h" 1 +# 65 "./mcc_generated_files/adc.h" +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "./mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "./mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "./mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "./mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "./mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "./mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "./mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "./mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "./mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "./mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "./mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "./mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "./mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "./mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "./mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "./mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "./mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "./mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "./mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "./mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "./mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "./mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "./mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "./mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "./mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "./mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "./mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "./mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 57 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/tmr1.h" 1 +# 101 "./mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "./mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "./mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "./mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "./mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "./mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "./mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "./mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "./mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "./mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "./mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "./mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "./mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 58 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/tmr0.h" 1 +# 106 "./mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "./mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "./mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "./mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "./mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "./mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "./mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "./mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "./mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "./mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "./mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 59 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/can1.h" 1 +# 56 "./mcc_generated_files/can1.h" +# 1 "./mcc_generated_files/can_types.h" 1 +# 65 "./mcc_generated_files/can_types.h" +typedef union +{ + uint8_t msgfields; + struct + { + uint8_t idType:1; + uint8_t frameType:1; + uint8_t dlc:4; + uint8_t formatType:1; + uint8_t brs:1; + }; +} CAN_MSG_FIELD; + +typedef struct +{ + uint32_t msgId; + CAN_MSG_FIELD field; + uint8_t *data; +} CAN_MSG_OBJ; +# 94 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NON_BRS_MODE = 0, + CAN_BRS_MODE = 1 +} CAN_MSG_OBJ_BRS_MODE; +# 109 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_STD = 0, + CAN_FRAME_EXT = 1, +} CAN_MSG_OBJ_ID_TYPE; +# 124 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_DATA = 0, + CAN_FRAME_RTR = 1, +} CAN_MSG_OBJ_FRAME_TYPE; +# 139 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_2_0_FORMAT = 0, + CAN_FD_FORMAT = 1 +} CAN_MSG_OBJ_TYPE; +# 154 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_MSG_REQUEST_SUCCESS = 0, + CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR = 1, + CAN_TX_MSG_REQUEST_BRS_ERROR = 2, + CAN_TX_MSG_REQUEST_FIFO_FULL = 3, +} CAN_TX_MSG_REQUEST_STATUS; +# 171 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NORMAL_FD_MODE = 0, + CAN_DISABLE_MODE = 1, + CAN_INTERNAL_LOOPBACK_MODE = 2, + CAN_LISTEN_ONLY_MODE = 3, + CAN_CONFIGURATION_MODE = 4, + CAN_EXTERNAL_LOOPBACK_MODE = 5, + CAN_NORMAL_2_0_MODE = 6, + CAN_RESTRICTED_OPERATION_MODE =7, +} CAN_OP_MODES; +# 192 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_OP_MODE_REQUEST_SUCCESS, + CAN_OP_MODE_REQUEST_FAIL, + CAN_OP_MODE_SYS_ERROR_OCCURED +} CAN_OP_MODE_STATUS; +# 208 "./mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_FIFO_FULL, + CAN_TX_FIFO_AVAILABLE, +} CAN_TX_FIFO_STATUS; +# 223 "./mcc_generated_files/can_types.h" +typedef enum +{ + + DLC_0, + DLC_1, + DLC_2, + DLC_3, + DLC_4, + DLC_5, + DLC_6, + DLC_7, + DLC_8, + + + + DLC_12, + DLC_16, + DLC_20, + DLC_24, + DLC_32, + DLC_48, + DLC_64, +} CAN_DLC; +# 56 "./mcc_generated_files/can1.h" 2 + + + + + +typedef enum +{ + TXQ = 0 +} CAN1_TX_FIFO_CHANNELS; + +typedef enum +{ + FIFO1 = 1 +} CAN1_RX_FIFO_CHANNELS; +# 106 "./mcc_generated_files/can1.h" +void CAN1_Initialize(void); +# 147 "./mcc_generated_files/can1.h" +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +# 185 "./mcc_generated_files/can1.h" +CAN_OP_MODES CAN1_OperationModeGet(void); +# 235 "./mcc_generated_files/can1.h" +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +# 275 "./mcc_generated_files/can1.h" +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *rxCanMsg); +# 334 "./mcc_generated_files/can1.h" +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +# 390 "./mcc_generated_files/can1.h" +_Bool CAN1_IsBusOff(void); +# 448 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorPassive(void); +# 507 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorWarning(void); +# 566 "./mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorActive(void); +# 614 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorPassive(void); +# 662 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorWarning(void); +# 710 "./mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorActive(void); +# 761 "./mcc_generated_files/can1.h" +void CAN1_Sleep(void); +# 815 "./mcc_generated_files/can1.h" +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +# 857 "./mcc_generated_files/can1.h" +uint8_t CAN1_ReceivedMessageCountGet(void); +# 924 "./mcc_generated_files/can1.h" +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +# 981 "./mcc_generated_files/can1.h" +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +# 1049 "./mcc_generated_files/can1.h" +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +# 1100 "./mcc_generated_files/can1.h" +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +# 1169 "./mcc_generated_files/can1.h" +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +# 1237 "./mcc_generated_files/can1.h" +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +# 1289 "./mcc_generated_files/can1.h" +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +# 1324 "./mcc_generated_files/can1.h" +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +# 1368 "./mcc_generated_files/can1.h" +void CAN1_SetTXQnullHandler(void (*handler)(void)); + + +void CAN1_ISR(void); +void CAN1_RXI_ISR(void); +# 60 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 37 "./mcc_generated_files/drivers/i2c_simple_master.h" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 61 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/pwm2_16bit.h" 1 +# 63 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 62 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/DAC3.h" 1 +# 29 "./mcc_generated_files/DAC3.h" +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 63 "./mcc_generated_files/mcc.h" 2 + +# 1 "./mcc_generated_files/pwm1_16bit.h" 1 +# 63 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "./mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 64 "./mcc_generated_files/mcc.h" 2 +# 79 "./mcc_generated_files/mcc.h" +void SYSTEM_Initialize(void); +# 92 "./mcc_generated_files/mcc.h" +void OSCILLATOR_Initialize(void); +# 105 "./mcc_generated_files/mcc.h" +void PMD_Initialize(void); +# 44 "main.c" 2 + +# 1 "./MESSAGES.h" 1 +# 22 "./MESSAGES.h" +CAN_MSG_OBJ msgTransmit; +CAN_MSG_OBJ msgReceipt; +uint8_t CANDATAdata[8]; + + +extern unsigned char CANDATAdata[8]; + +extern unsigned char ucTargetAccelerator; +extern unsigned char ucTargetClutch; +extern unsigned char ucTargetClutch_PREV; +extern unsigned char ucTargetBrake; +extern unsigned char ucTargetDirection; +extern unsigned char ucTargetGear; + +extern unsigned char ucAS_state; +extern unsigned char ucEBS_state; +extern unsigned char ucAMI_state; +extern unsigned char ucSteering_state; +extern unsigned char ucService_brake; +extern unsigned char ucLap_counter; +extern unsigned char ucCones_count_actual; +extern unsigned char ucCones_count_all; + +extern unsigned char ucSpeed_actual; +extern unsigned char ucSpeed_target; +extern unsigned char ucSteering_angle_actual; +extern unsigned char ucSteering_angle_target; +extern unsigned char ucBrake_hydr_actual; +extern unsigned char ucBrake_hydr_target; +extern unsigned char ucMotor_moment_actual; +extern unsigned char ucMotor_moment_target; + +extern unsigned int uiAcc_longitudinal; +extern unsigned int uiAcc_lateral; +extern unsigned int uiYaw_rate; + +extern unsigned char ucASBState; +extern unsigned char ucASRequesState; + +extern unsigned char ucASMode; + +extern unsigned char ucSTEER_WH_Clutch; +# 98 "./MESSAGES.h" +void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8); +void CANReadMessage (void); +void CANDisableErrorInterrupt (unsigned char ucInterruptSet); +# 45 "main.c" 2 + +# 1 "./CLUTCH.h" 1 +# 31 "./CLUTCH.h" +extern unsigned char ucCLUTCHlmin; +extern unsigned char ucCLUTCHlmax; +extern unsigned char ucCLUTCHDuty; +extern unsigned char ucCLUTCHState; + + + +void CLUTCH_Init (void); +void CLUTCH_Move (unsigned char ucTargetMove, unsigned char ucMode); +void CLUTCH_AnalyseState (void); +void CLUTCHInitMove(void); +void CLUTCH_HighLevelMovements (unsigned char ucClutchAction); +# 46 "main.c" 2 + +# 1 "./GPIO.h" 1 +# 16 "./GPIO.h" +void GPIOInit (void); +void GPIO_PWM1_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +void GPIO_PWM2_Control (unsigned int uiDutyCycle, unsigned int uiFreq); +void GPIO_INT2_desembragar (void); +# 47 "main.c" 2 + +# 1 "./ETC.h" 1 +# 65 "./ETC.h" +unsigned int uiTPS1TableIn [21]; +unsigned char ucTPS1TableOut [21]; +unsigned int uiTPS2TableIn [21]; +unsigned char ucTPS2TableOut [21]; + +typedef struct { + + + float Kp; + float Ki; + float Kd; + + + float tau; + + + float limMin; + float limMax; + + + float limMinInt; + float limMaxInt; + + + float T; + + + float integrator; + float prevError; + float differentiator; + float prevMeasurement; + + + float out; + +} PIDController; + +PIDController pid = { 2.4f, 1.4f, 0.0f, + 0.02f, + 0.0f, 100.0f, + -10.0f, 10.0f, + 0.01f }; + + + +extern unsigned int uiAPPS1min; +extern unsigned int uiAPPS1max; +extern unsigned int uiAPPS2min; +extern unsigned int uiAPPS2max; +extern unsigned int uiTPS1min; +extern unsigned int uiTPS1max; +extern unsigned int uiTPS2min; +extern unsigned int uiTPS2max; +extern unsigned int uiAPPS1; +extern unsigned int uiAPPS2; +extern unsigned char ucAPPS_STATE; +extern unsigned long ulAPPS1calc; +extern unsigned long ulAPPS2calc; +extern unsigned int ucAPPS1Perc; +extern unsigned int ucAPPS2Perc; +extern unsigned int ucAPPS; +extern unsigned int uiTPS1; +extern unsigned int uiTPS2; +extern signed long ulTPS1calc; +extern signed long ulTPS2calc; +extern unsigned int ucTPS1Perc; +extern unsigned int ucTPS2Perc; +extern unsigned int ucTPS; +extern unsigned char ucTPS_STATE; +extern unsigned char ucTPS1_STATE; +extern unsigned char ucTPS2_STATE; +extern unsigned char ucTPS_Volts_STATE; +extern unsigned int uiETCDuty; +extern unsigned char ucETB_STATE; +extern unsigned char ucETCBeatSupervisor; +extern unsigned char ucETCFlagSupervisor; +extern unsigned char ucAPPSManual; +extern unsigned char ucETCTimerRuleTPS; +extern unsigned char ucETCTimerRuleAPPS; +extern unsigned char ucCount100msTPSError; +extern unsigned char ucCount100msAPPSError; +extern unsigned char ucETCRuleSupervisor; +extern unsigned char ucETCTargetTPSDiff; +extern unsigned char ucCount500msTPSDiff; +extern unsigned char ucETCMotorNotClose; +extern unsigned char ucETCResolveNotCloseError; +extern unsigned char ucCount500msResolveNotCloseError; + +extern unsigned int ucAPPSTargetPruebas; + +void ETCInit(void); +void APPSSend (unsigned char ucPercent); +void APPSReadmin (void); +void APPSReadmax (void); +void ETCModeSelect (unsigned char ucModeSelect); +void ETCRulesSupervision(void); +void ETCMove(unsigned char ucTargetMove, unsigned char ucMode); +void ETC_PID(signed long slTargetMove, unsigned char ucMode); +void ETCCalibrate(void); +void TPSAnalysis (void); +void APPSAnalysis (void); +void ETCXavierSupervisor (void); +void ETCManual (unsigned char ucTargetManual); +unsigned int ETCPercentCalc(signed long val, signed long min, signed long max); +void ETCRulesSensorsSupervision(void); +void ETC100msSupervisor (void); +void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactual); +void ETC500msSupervisor (void); +void PIDController_Init(PIDController *pid); +float PIDController_Update(PIDController *pid, float setpoint, float measurement); +unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize); +# 48 "main.c" 2 + +# 1 "./ANALOG.h" 1 +# 22 "./ANALOG.h" +unsigned int ANALOG_GetVoltage (unsigned char ucEntradaAnalogica); +void ANALOGRead (void); +# 49 "main.c" 2 + +# 1 "./PARAMETERS.h" 1 +# 31 "./PARAMETERS.h" +extern signed long sl_K; +extern signed long sl_K_P; +extern signed long sl_K_I; +extern signed long sl_K_D; +# 50 "main.c" 2 + + + + +void main(void) +{ + + SYSTEM_Initialize(); + + + + + GPIOInit(); + ETCInit(); + + + ANALOGRead(); + + APPSReadmin(); + APPSReadmax(); + + (INTCON0bits.GIE = 1); + CANDisableErrorInterrupt(0x00); + + + + + CLUTCH_Init(); + + + ucAPPSTargetPruebas=0; + + while (1) + { + + + + ANALOGRead(); + TPSAnalysis(); + APPSAnalysis(); + ETCRulesSensorsSupervision(); + + + if (ucASMode == 0) + { + ETCMove(ucAPPS,0); + + CLUTCH_Move(ucSTEER_WH_Clutch, 0); + } + else if (ucASMode == 1) + { + ETCMove(ucTargetAccelerator,1); + + ucCLUTCHState = 0; + + CLUTCH_HighLevelMovements(ucTargetClutch); + } + + + + + + } +} diff --git a/ETC.X/build/default/debug/main.p1 b/ETC.X/build/default/debug/main.p1 new file mode 100644 index 0000000..4f54f5c --- /dev/null +++ b/ETC.X/build/default/debug/main.p1 @@ -0,0 +1,3751 @@ +Version 4.0 HI-TECH Software Intermediate Code +"69 ./mcc_generated_files/can_types.h +[; ;./mcc_generated_files/can_types.h: 69: { +[s S3179 :1 `uc 1 :1 `uc 1 :4 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3179 . idType frameType dlc formatType brs ] +"66 +[; ;./mcc_generated_files/can_types.h: 66: { +[u S3178 `uc 1 `S3179 1 ] +[n S3178 . msgfields . ] +"79 +[; ;./mcc_generated_files/can_types.h: 79: { +[s S3180 `ul 1 `S3178 1 `*uc 1 ] +[n S3180 . msgId field data ] +"70 ./ETC.h +[; ;./ETC.h: 70: typedef struct { +[s S3181 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 `f 1 ] +[n S3181 . Kp Ki Kd tau limMin limMax limMinInt limMaxInt T integrator prevError differentiator prevMeasurement out ] +[p mainexit ] +"79 ./mcc_generated_files/mcc.h +[; ;./mcc_generated_files/mcc.h: 79: void SYSTEM_Initialize(void); +[v _SYSTEM_Initialize `(v ~T0 @X0 0 ef ] +"16 ./GPIO.h +[; ;./GPIO.h: 16: void GPIOInit (void); +[v _GPIOInit `(v ~T0 @X0 0 ef ] +"155 ./ETC.h +[; ;./ETC.h: 155: void ETCInit(void); +[v _ETCInit `(v ~T0 @X0 0 ef ] +"23 ./ANALOG.h +[; ;./ANALOG.h: 23: void ANALOGRead (void); +[v _ANALOGRead `(v ~T0 @X0 0 ef ] +"157 ./ETC.h +[; ;./ETC.h: 157: void APPSReadmin (void); +[v _APPSReadmin `(v ~T0 @X0 0 ef ] +"158 +[; ;./ETC.h: 158: void APPSReadmax (void); +[v _APPSReadmax `(v ~T0 @X0 0 ef ] +"2080 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[s S3083 :1 `uc 1 :1 `uc 1 :1 `uc 1 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3083 . INT0EDG INT1EDG INT2EDG . IPEN GIEL GIE ] +"2089 +[s S3084 :7 `uc 1 :1 `uc 1 ] +[n S3084 . . GIEH ] +"2079 +[u S3082 `S3083 1 `S3084 1 ] +[n S3082 . . . ] +"2094 +[v _INTCON0bits `VS3082 ~T0 @X0 0 e@1238 ] +"100 ./MESSAGES.h +[; ;./MESSAGES.h: 100: void CANDisableErrorInterrupt (unsigned char ucInterruptSet); +[v _CANDisableErrorInterrupt `(v ~T0 @X0 0 ef1`uc ] +"38 ./CLUTCH.h +[; ;./CLUTCH.h: 38: void CLUTCH_Init (void); +[v _CLUTCH_Init `(v ~T0 @X0 0 ef ] +"153 ./ETC.h +[; ;./ETC.h: 153: extern unsigned int ucAPPSTargetPruebas; +[v _ucAPPSTargetPruebas `ui ~T0 @X0 0 e ] +"164 +[; ;./ETC.h: 164: void TPSAnalysis (void); +[v _TPSAnalysis `(v ~T0 @X0 0 ef ] +"165 +[; ;./ETC.h: 165: void APPSAnalysis (void); +[v _APPSAnalysis `(v ~T0 @X0 0 ef ] +"169 +[; ;./ETC.h: 169: void ETCRulesSensorsSupervision(void); +[v _ETCRulesSensorsSupervision `(v ~T0 @X0 0 ef ] +"61 ./MESSAGES.h +[; ;./MESSAGES.h: 61: extern unsigned char ucASMode; +[v _ucASMode `uc ~T0 @X0 0 e ] +"161 ./ETC.h +[; ;./ETC.h: 161: void ETCMove(unsigned char ucTargetMove, unsigned char ucMode); +[v _ETCMove `(v ~T0 @X0 0 ef2`uc`uc ] +"125 +[; ;./ETC.h: 125: extern unsigned int ucAPPS; +[v _ucAPPS `ui ~T0 @X0 0 e ] +"39 ./CLUTCH.h +[; ;./CLUTCH.h: 39: void CLUTCH_Move (unsigned char ucTargetMove, unsigned char ucMode); +[v _CLUTCH_Move `(v ~T0 @X0 0 ef2`uc`uc ] +"63 ./MESSAGES.h +[; ;./MESSAGES.h: 63: extern unsigned char ucSTEER_WH_Clutch; +[v _ucSTEER_WH_Clutch `uc ~T0 @X0 0 e ] +"29 +[; ;./MESSAGES.h: 29: extern unsigned char ucTargetAccelerator; +[v _ucTargetAccelerator `uc ~T0 @X0 0 e ] +"34 ./CLUTCH.h +[; ;./CLUTCH.h: 34: extern unsigned char ucCLUTCHState; +[v _ucCLUTCHState `uc ~T0 @X0 0 e ] +"42 +[; ;./CLUTCH.h: 42: void CLUTCH_HighLevelMovements (unsigned char ucClutchAction); +[v _CLUTCH_HighLevelMovements `(v ~T0 @X0 0 ef1`uc ] +"30 ./MESSAGES.h +[; ;./MESSAGES.h: 30: extern unsigned char ucTargetClutch; +[v _ucTargetClutch `uc ~T0 @X0 0 e ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"22 ./MESSAGES.h +[; ;./MESSAGES.h: 22: CAN_MSG_OBJ msgTransmit; +[v _msgTransmit `S3180 ~T0 @X0 1 e ] +"23 +[; ;./MESSAGES.h: 23: CAN_MSG_OBJ msgReceipt; +[v _msgReceipt `S3180 ~T0 @X0 1 e ] +"24 +[; ;./MESSAGES.h: 24: uint8_t CANDATAdata[8]; +[v _CANDATAdata `uc ~T0 @X0 -> 8 `i e ] +"65 ./ETC.h +[; ;./ETC.h: 65: unsigned int uiTPS1TableIn [21]; +[v _uiTPS1TableIn `ui ~T0 @X0 -> 21 `i e ] +"66 +[; ;./ETC.h: 66: unsigned char ucTPS1TableOut [21]; +[v _ucTPS1TableOut `uc ~T0 @X0 -> 21 `i e ] +"67 +[; ;./ETC.h: 67: unsigned int uiTPS2TableIn [21]; +[v _uiTPS2TableIn `ui ~T0 @X0 -> 21 `i e ] +"68 +[; ;./ETC.h: 68: unsigned char ucTPS2TableOut [21]; +[v _ucTPS2TableOut `uc ~T0 @X0 -> 21 `i e ] +"102 +[; ;./ETC.h: 102: PIDController pid = { 2.4f, 1.4f, 0.0f, +[v _pid `S3181 ~T0 @X0 1 e ] +[i _pid +:U .. +:U .. +-> .2.4 `f +-> .1.4 `f +-> .0.0 `f +-> .0.02 `f +-> .0.0 `f +-> .100.0 `f +-U -> .10.0 `f +-> .10.0 `f +-> .0.01 `f +.. +.. +] +[v $root$_main `(v ~T0 @X0 0 e ] +"54 main.c +[; ;main.c: 54: void main(void) +[v _main `(v ~T0 @X0 1 ef ] +"55 +[; ;main.c: 55: { +{ +[e :U _main ] +[f ] +"57 +[; ;main.c: 57: SYSTEM_Initialize(); +[e ( _SYSTEM_Initialize .. ] +"62 +[; ;main.c: 62: GPIOInit(); +[e ( _GPIOInit .. ] +"63 +[; ;main.c: 63: ETCInit(); +[e ( _ETCInit .. ] +"66 +[; ;main.c: 66: ANALOGRead(); +[e ( _ANALOGRead .. ] +"68 +[; ;main.c: 68: APPSReadmin(); +[e ( _APPSReadmin .. ] +"69 +[; ;main.c: 69: APPSReadmax(); +[e ( _APPSReadmax .. ] +"71 +[; ;main.c: 71: (INTCON0bits.GIE = 1); +[e = . . _INTCON0bits 0 6 -> -> 1 `i `uc ] +"72 +[; ;main.c: 72: CANDisableErrorInterrupt(0x00); +[e ( _CANDisableErrorInterrupt (1 -> -> 0 `i `uc ] +"77 +[; ;main.c: 77: CLUTCH_Init(); +[e ( _CLUTCH_Init .. ] +"80 +[; ;main.c: 80: ucAPPSTargetPruebas=0; +[e = _ucAPPSTargetPruebas -> -> 0 `i `ui ] +"82 +[; ;main.c: 82: while (1) +[e :U 3184 ] +"83 +[; ;main.c: 83: { +{ +"87 +[; ;main.c: 87: ANALOGRead(); +[e ( _ANALOGRead .. ] +"88 +[; ;main.c: 88: TPSAnalysis(); +[e ( _TPSAnalysis .. ] +"89 +[; ;main.c: 89: APPSAnalysis(); +[e ( _APPSAnalysis .. ] +"90 +[; ;main.c: 90: ETCRulesSensorsSupervision(); +[e ( _ETCRulesSensorsSupervision .. ] +"93 +[; ;main.c: 93: if (ucASMode == 0) +[e $ ! == -> _ucASMode `i -> 0 `i 3186 ] +"94 +[; ;main.c: 94: { +{ +"95 +[; ;main.c: 95: ETCMove(ucAPPS,0); +[e ( _ETCMove (2 , -> _ucAPPS `uc -> -> 0 `i `uc ] +"97 +[; ;main.c: 97: CLUTCH_Move(ucSTEER_WH_Clutch, 0); +[e ( _CLUTCH_Move (2 , _ucSTEER_WH_Clutch -> -> 0 `i `uc ] +"98 +[; ;main.c: 98: } +} +[e $U 3187 ] +"99 +[; ;main.c: 99: else if (ucASMode == 1) +[e :U 3186 ] +[e $ ! == -> _ucASMode `i -> 1 `i 3188 ] +"100 +[; ;main.c: 100: { +{ +"101 +[; ;main.c: 101: ETCMove(ucTargetAccelerator,1); +[e ( _ETCMove (2 , _ucTargetAccelerator -> -> 1 `i `uc ] +"103 +[; ;main.c: 103: ucCLUTCHState = 0; +[e = _ucCLUTCHState -> -> 0 `i `uc ] +"105 +[; ;main.c: 105: CLUTCH_HighLevelMovements(ucTargetClutch); +[e ( _CLUTCH_HighLevelMovements (1 _ucTargetClutch ] +"106 +[; ;main.c: 106: } +} +[e :U 3188 ] +[e :U 3187 ] +"112 +[; ;main.c: 112: } +} +[e :U 3183 ] +[e $U 3184 ] +[e :U 3185 ] +"113 +[; ;main.c: 113: } +[e :UE 3182 ] +} diff --git a/ETC.X/build/default/debug/main.p1.d b/ETC.X/build/default/debug/main.p1.d new file mode 100644 index 0000000..dcbbab0 --- /dev/null +++ b/ETC.X/build/default/debug/main.p1.d @@ -0,0 +1,22 @@ +build/default/debug/main.p1: \ +main.c \ +mcc_generated_files/mcc.h \ +mcc_generated_files/device_config.h \ +mcc_generated_files/pin_manager.h \ +mcc_generated_files/interrupt_manager.h \ +mcc_generated_files/i2c1_master.h \ +mcc_generated_files/adc.h \ +mcc_generated_files/tmr1.h \ +mcc_generated_files/tmr0.h \ +mcc_generated_files/can1.h \ +mcc_generated_files/can_types.h \ +mcc_generated_files/drivers/i2c_simple_master.h \ +mcc_generated_files/pwm2_16bit.h \ +mcc_generated_files/DAC3.h \ +mcc_generated_files/pwm1_16bit.h \ +MESSAGES.h \ +CLUTCH.h \ +GPIO.h \ +ETC.h \ +ANALOG.h \ +PARAMETERS.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/DAC3.i b/ETC.X/build/default/debug/mcc_generated_files/DAC3.i new file mode 100644 index 0000000..d4f9766 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/DAC3.i @@ -0,0 +1,386 @@ +# 1 "mcc_generated_files/DAC3.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/DAC3.c" 2 +# 23 "mcc_generated_files/DAC3.c" +# 1 "mcc_generated_files/DAC3.h" 1 +# 26 "mcc_generated_files/DAC3.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; + + + + +typedef __int24 int24_t; + + + + +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; + + + + +typedef __uint24 uint24_t; + + + + +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 26 "mcc_generated_files/DAC3.h" 2 + + + +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 23 "mcc_generated_files/DAC3.c" 2 + +# 1 "mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 34 "mcc_generated_files/drivers/i2c_simple_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 34 "mcc_generated_files/drivers/i2c_simple_master.h" 2 + +# 1 "mcc_generated_files/drivers/.././i2c1_master.h" 1 +# 56 "mcc_generated_files/drivers/.././i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 56 "mcc_generated_files/drivers/.././i2c1_master.h" 2 + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "mcc_generated_files/drivers/.././i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "mcc_generated_files/drivers/.././i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "mcc_generated_files/drivers/.././i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 35 "mcc_generated_files/drivers/i2c_simple_master.h" 2 + + +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 24 "mcc_generated_files/DAC3.c" 2 + + +void DAC3_Set(uint16_t dacValue) +{ + i2c_write1ByteRegister(0x60,(dacValue>>8),dacValue); +} + +void DAC3_SetNonvolatile(uint16_t dacValue) +{ + i2c_write2ByteRegister(0x60,0x60,dacValue); +} + +uint16_t DAC3_Read(uint16_t *dacNonvolatile) +{ + uint16_t dacVolatile; + struct {uint8_t volStatus, volatileVoltByte1, volatileVoltByte2, nvStatus, nonvolatileVoltByte1, nonvolatileVoltByte2; } data; + + i2c_readNBytes(0x60, &data, sizeof(data)); + + + + dacVolatile = (data.volatileVoltByte1 << 4) + (data.volatileVoltByte2 >> 4); + + if(dacNonvolatile) + { + *dacNonvolatile = (data.nonvolatileVoltByte1 << 4) + (data.nonvolatileVoltByte2 >> 4); + } + return dacVolatile; +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/DAC3.p1 b/ETC.X/build/default/debug/mcc_generated_files/DAC3.p1 new file mode 100644 index 0000000..414d63f --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/DAC3.p1 @@ -0,0 +1,100 @@ +Version 4.0 HI-TECH Software Intermediate Code +"39 mcc_generated_files/drivers/i2c_simple_master.h +[; ;mcc_generated_files/drivers/i2c_simple_master.h: 39: void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +[v _i2c_write1ByteRegister `(v ~T0 @X0 0 ef3`uc`uc`uc ] +"40 +[; ;mcc_generated_files/drivers/i2c_simple_master.h: 40: void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); +[v _i2c_write2ByteRegister `(v ~T0 @X0 0 ef3`uc`uc`us ] +"39 mcc_generated_files/DAC3.c +[; ;mcc_generated_files/DAC3.c: 39: struct {uint8_t volStatus, volatileVoltByte1, volatileVoltByte2, nvStatus, nonvolatileVoltByte1, nonvolatileVoltByte2; } data; +[s S6 `uc 1 `uc 1 `uc 1 `uc 1 `uc 1 `uc 1 ] +[n S6 . volStatus volatileVoltByte1 volatileVoltByte2 nvStatus nonvolatileVoltByte1 nonvolatileVoltByte2 ] +"44 mcc_generated_files/drivers/i2c_simple_master.h +[; ;mcc_generated_files/drivers/i2c_simple_master.h: 44: void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +[v _i2c_readNBytes `(v ~T0 @X0 0 ef3`uc`*v`ui ] +"26 mcc_generated_files/DAC3.c +[; ;mcc_generated_files/DAC3.c: 26: void DAC3_Set(uint16_t dacValue) +[v _DAC3_Set `(v ~T0 @X0 1 ef1`us ] +"27 +[; ;mcc_generated_files/DAC3.c: 27: { +{ +[e :U _DAC3_Set ] +"26 +[; ;mcc_generated_files/DAC3.c: 26: void DAC3_Set(uint16_t dacValue) +[v _dacValue `us ~T0 @X0 1 r1 ] +"27 +[; ;mcc_generated_files/DAC3.c: 27: { +[f ] +"28 +[; ;mcc_generated_files/DAC3.c: 28: i2c_write1ByteRegister(0x60,(dacValue>>8),dacValue); +[e ( _i2c_write1ByteRegister (3 , , -> -> 96 `i `uc -> >> -> _dacValue `ui -> 8 `i `uc -> _dacValue `uc ] +"29 +[; ;mcc_generated_files/DAC3.c: 29: } +[e :UE 3 ] +} +"31 +[; ;mcc_generated_files/DAC3.c: 31: void DAC3_SetNonvolatile(uint16_t dacValue) +[v _DAC3_SetNonvolatile `(v ~T0 @X0 1 ef1`us ] +"32 +[; ;mcc_generated_files/DAC3.c: 32: { +{ +[e :U _DAC3_SetNonvolatile ] +"31 +[; ;mcc_generated_files/DAC3.c: 31: void DAC3_SetNonvolatile(uint16_t dacValue) +[v _dacValue `us ~T0 @X0 1 r1 ] +"32 +[; ;mcc_generated_files/DAC3.c: 32: { +[f ] +"33 +[; ;mcc_generated_files/DAC3.c: 33: i2c_write2ByteRegister(0x60,0x60,dacValue); +[e ( _i2c_write2ByteRegister (3 , , -> -> 96 `i `uc -> -> 96 `i `uc _dacValue ] +"34 +[; ;mcc_generated_files/DAC3.c: 34: } +[e :UE 4 ] +} +"36 +[; ;mcc_generated_files/DAC3.c: 36: uint16_t DAC3_Read(uint16_t *dacNonvolatile) +[v _DAC3_Read `(us ~T0 @X0 1 ef1`*us ] +"37 +[; ;mcc_generated_files/DAC3.c: 37: { +{ +[e :U _DAC3_Read ] +"36 +[; ;mcc_generated_files/DAC3.c: 36: uint16_t DAC3_Read(uint16_t *dacNonvolatile) +[v _dacNonvolatile `*us ~T0 @X0 1 r1 ] +"37 +[; ;mcc_generated_files/DAC3.c: 37: { +[f ] +"38 +[; ;mcc_generated_files/DAC3.c: 38: uint16_t dacVolatile; +[v _dacVolatile `us ~T0 @X0 1 a ] +"39 +[; ;mcc_generated_files/DAC3.c: 39: struct {uint8_t volStatus, volatileVoltByte1, volatileVoltByte2, nvStatus, nonvolatileVoltByte1, nonvolatileVoltByte2; } data; +[v _data `S6 ~T0 @X0 1 a ] +"41 +[; ;mcc_generated_files/DAC3.c: 41: i2c_readNBytes(0x60, &data, sizeof(data)); +[e ( _i2c_readNBytes (3 , , -> -> 96 `i `uc -> &U _data `*v -> # _data `ui ] +"45 +[; ;mcc_generated_files/DAC3.c: 45: dacVolatile = (data.volatileVoltByte1 << 4) + (data.volatileVoltByte2 >> 4); +[e = _dacVolatile -> + << -> . _data 1 `i -> 4 `i >> -> . _data 2 `i -> 4 `i `us ] +"47 +[; ;mcc_generated_files/DAC3.c: 47: if(dacNonvolatile) +[e $ ! != _dacNonvolatile -> -> 0 `i `*us 7 ] +"48 +[; ;mcc_generated_files/DAC3.c: 48: { +{ +"49 +[; ;mcc_generated_files/DAC3.c: 49: *dacNonvolatile = (data.nonvolatileVoltByte1 << 4) + (data.nonvolatileVoltByte2 >> 4); +[e = *U _dacNonvolatile -> + << -> . _data 4 `i -> 4 `i >> -> . _data 5 `i -> 4 `i `us ] +"50 +[; ;mcc_generated_files/DAC3.c: 50: } +} +[e :U 7 ] +"51 +[; ;mcc_generated_files/DAC3.c: 51: return dacVolatile; +[e ) _dacVolatile ] +[e $UE 5 ] +"52 +[; ;mcc_generated_files/DAC3.c: 52: } +[e :UE 5 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/DAC3.p1.d b/ETC.X/build/default/debug/mcc_generated_files/DAC3.p1.d new file mode 100644 index 0000000..de0dec6 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/DAC3.p1.d @@ -0,0 +1,5 @@ +build/default/debug/mcc_generated_files/DAC3.p1: \ +mcc_generated_files/DAC3.c \ +mcc_generated_files/DAC3.h \ +mcc_generated_files/drivers/i2c_simple_master.h \ +mcc_generated_files/drivers/.././i2c1_master.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/DAC3_example.i b/ETC.X/build/default/debug/mcc_generated_files/DAC3_example.i new file mode 100644 index 0000000..fe521ba --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/DAC3_example.i @@ -0,0 +1,38300 @@ +# 1 "mcc_generated_files/DAC3_example.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/DAC3_example.c" 2 +# 23 "mcc_generated_files/DAC3_example.c" +# 1 "mcc_generated_files/mcc.h" 1 +# 49 "mcc_generated_files/mcc.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 49 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/device_config.h" 1 +# 50 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pin_manager.h" 1 +# 402 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 51 "mcc_generated_files/mcc.h" 2 + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 53 "mcc_generated_files/mcc.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 1 3 + + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 1 3 +# 12 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 3 +extern int errno; +# 8 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__null.h" 1 3 +# 9 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + + + +extern void init_uart(void); + +extern char getch(void); +extern char getche(void); +extern void putch(char); +extern void ungetch(char); + +extern __bit kbhit(void); + + + +extern char * cgets(char *); +extern void cputs(const char *); +# 54 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/interrupt_manager.h" 1 +# 87 "mcc_generated_files/interrupt_manager.h" +void INTERRUPT_Initialize (void); +# 55 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/i2c1_master.h" 1 +# 54 "mcc_generated_files/i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "mcc_generated_files/i2c1_master.h" 2 + + + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "mcc_generated_files/i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "mcc_generated_files/i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "mcc_generated_files/i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 56 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/adc.h" 1 +# 65 "mcc_generated_files/adc.h" +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 57 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/tmr1.h" 1 +# 101 "mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 58 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/tmr0.h" 1 +# 106 "mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 59 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/can1.h" 1 +# 56 "mcc_generated_files/can1.h" +# 1 "mcc_generated_files/can_types.h" 1 +# 65 "mcc_generated_files/can_types.h" +typedef union +{ + uint8_t msgfields; + struct + { + uint8_t idType:1; + uint8_t frameType:1; + uint8_t dlc:4; + uint8_t formatType:1; + uint8_t brs:1; + }; +} CAN_MSG_FIELD; + +typedef struct +{ + uint32_t msgId; + CAN_MSG_FIELD field; + uint8_t *data; +} CAN_MSG_OBJ; +# 94 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NON_BRS_MODE = 0, + CAN_BRS_MODE = 1 +} CAN_MSG_OBJ_BRS_MODE; +# 109 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_STD = 0, + CAN_FRAME_EXT = 1, +} CAN_MSG_OBJ_ID_TYPE; +# 124 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_DATA = 0, + CAN_FRAME_RTR = 1, +} CAN_MSG_OBJ_FRAME_TYPE; +# 139 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_2_0_FORMAT = 0, + CAN_FD_FORMAT = 1 +} CAN_MSG_OBJ_TYPE; +# 154 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_MSG_REQUEST_SUCCESS = 0, + CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR = 1, + CAN_TX_MSG_REQUEST_BRS_ERROR = 2, + CAN_TX_MSG_REQUEST_FIFO_FULL = 3, +} CAN_TX_MSG_REQUEST_STATUS; +# 171 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NORMAL_FD_MODE = 0, + CAN_DISABLE_MODE = 1, + CAN_INTERNAL_LOOPBACK_MODE = 2, + CAN_LISTEN_ONLY_MODE = 3, + CAN_CONFIGURATION_MODE = 4, + CAN_EXTERNAL_LOOPBACK_MODE = 5, + CAN_NORMAL_2_0_MODE = 6, + CAN_RESTRICTED_OPERATION_MODE =7, +} CAN_OP_MODES; +# 192 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_OP_MODE_REQUEST_SUCCESS, + CAN_OP_MODE_REQUEST_FAIL, + CAN_OP_MODE_SYS_ERROR_OCCURED +} CAN_OP_MODE_STATUS; +# 208 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_FIFO_FULL, + CAN_TX_FIFO_AVAILABLE, +} CAN_TX_FIFO_STATUS; +# 223 "mcc_generated_files/can_types.h" +typedef enum +{ + + DLC_0, + DLC_1, + DLC_2, + DLC_3, + DLC_4, + DLC_5, + DLC_6, + DLC_7, + DLC_8, + + + + DLC_12, + DLC_16, + DLC_20, + DLC_24, + DLC_32, + DLC_48, + DLC_64, +} CAN_DLC; +# 56 "mcc_generated_files/can1.h" 2 + + + + + +typedef enum +{ + TXQ = 0 +} CAN1_TX_FIFO_CHANNELS; + +typedef enum +{ + FIFO1 = 1 +} CAN1_RX_FIFO_CHANNELS; +# 106 "mcc_generated_files/can1.h" +void CAN1_Initialize(void); +# 147 "mcc_generated_files/can1.h" +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +# 185 "mcc_generated_files/can1.h" +CAN_OP_MODES CAN1_OperationModeGet(void); +# 235 "mcc_generated_files/can1.h" +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +# 275 "mcc_generated_files/can1.h" +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *rxCanMsg); +# 334 "mcc_generated_files/can1.h" +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +# 390 "mcc_generated_files/can1.h" +_Bool CAN1_IsBusOff(void); +# 448 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorPassive(void); +# 507 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorWarning(void); +# 566 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorActive(void); +# 614 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorPassive(void); +# 662 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorWarning(void); +# 710 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorActive(void); +# 761 "mcc_generated_files/can1.h" +void CAN1_Sleep(void); +# 815 "mcc_generated_files/can1.h" +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +# 857 "mcc_generated_files/can1.h" +uint8_t CAN1_ReceivedMessageCountGet(void); +# 924 "mcc_generated_files/can1.h" +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +# 981 "mcc_generated_files/can1.h" +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +# 1049 "mcc_generated_files/can1.h" +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +# 1100 "mcc_generated_files/can1.h" +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +# 1169 "mcc_generated_files/can1.h" +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +# 1237 "mcc_generated_files/can1.h" +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +# 1289 "mcc_generated_files/can1.h" +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +# 1324 "mcc_generated_files/can1.h" +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +# 1368 "mcc_generated_files/can1.h" +void CAN1_SetTXQnullHandler(void (*handler)(void)); + + +void CAN1_ISR(void); +void CAN1_RXI_ISR(void); +# 60 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 37 "mcc_generated_files/drivers/i2c_simple_master.h" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 61 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pwm2_16bit.h" 1 +# 63 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 62 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/DAC3.h" 1 +# 29 "mcc_generated_files/DAC3.h" +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 63 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pwm1_16bit.h" 1 +# 63 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 64 "mcc_generated_files/mcc.h" 2 +# 79 "mcc_generated_files/mcc.h" +void SYSTEM_Initialize(void); +# 92 "mcc_generated_files/mcc.h" +void OSCILLATOR_Initialize(void); +# 105 "mcc_generated_files/mcc.h" +void PMD_Initialize(void); +# 23 "mcc_generated_files/DAC3_example.c" 2 + + +# 1 "mcc_generated_files/DAC3_example.h" 1 +# 27 "mcc_generated_files/DAC3_example.h" +void DAC3_example(void); +# 25 "mcc_generated_files/DAC3_example.c" 2 + + + +void DAC3_example(void) +{ + float voltage; + float readVoltage, readNonvolatileVoltage; + + uint16_t dacVoltage, dacNonvolatileVoltage; + + + voltage = 1; + + dacNonvolatileVoltage = (4096*voltage)/5; + DAC3_SetNonvolatile(dacNonvolatileVoltage); + + printf("Set the non-volatile voltage to 1V \n"); + + _delay((unsigned long)((100)*(10000000/4000.0))); + + + voltage = 2; + dacVoltage = (4096*voltage)/5; + DAC3_Set(dacVoltage); + + _delay((unsigned long)((100)*(10000000/4000.0))); + + printf("Set the volatile voltage to 2V \n"); + + dacVoltage = DAC3_Read(&dacNonvolatileVoltage); + + + readVoltage = dacVoltage / 819.2; + readNonvolatileVoltage = dacNonvolatileVoltage / 819.2; + + printf("Read: non-volatile voltage value %f, and volatile voltage value %f", readNonvolatileVoltage, readVoltage); + + _delay((unsigned long)((100)*(10000000/4000.0))); +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/DAC3_example.p1 b/ETC.X/build/default/debug/mcc_generated_files/DAC3_example.p1 new file mode 100644 index 0000000..28c5fae --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/DAC3_example.p1 @@ -0,0 +1,3604 @@ +Version 4.0 HI-TECH Software Intermediate Code +"29 mcc_generated_files/DAC3.h +[; ;mcc_generated_files/DAC3.h: 29: void DAC3_SetNonvolatile(uint16_t dacValue); +[v _DAC3_SetNonvolatile `(v ~T0 @X0 0 ef1`us ] +"111 C:\Program Files\Microchip\xc8\v2.31\pic\include\c99\stdio.h +[v _printf `(i ~T0 @X0 0 ev`*Cuc ] +[v F183 `(v ~T0 @X0 1 tf1`ul ] +"12 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\builtins.h +[v __delay `JF183 ~T0 @X0 0 e ] +[p i __delay ] +"32 mcc_generated_files/DAC3.h +[; ;mcc_generated_files/DAC3.h: 32: void DAC3_Set(uint16_t dacValue); +[v _DAC3_Set `(v ~T0 @X0 0 ef1`us ] +"34 +[; ;mcc_generated_files/DAC3.h: 34: uint16_t DAC3_Read(uint16_t *dacNonvolatile); +[v _DAC3_Read `(us ~T0 @X0 0 ef1`*us ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"28 mcc_generated_files/DAC3_example.c +[; ;mcc_generated_files/DAC3_example.c: 28: void DAC3_example(void) +[v _DAC3_example `(v ~T0 @X0 1 ef ] +"29 +[; ;mcc_generated_files/DAC3_example.c: 29: { +{ +[e :U _DAC3_example ] +[f ] +"30 +[; ;mcc_generated_files/DAC3_example.c: 30: float voltage; +[v _voltage `f ~T0 @X0 1 a ] +"31 +[; ;mcc_generated_files/DAC3_example.c: 31: float readVoltage, readNonvolatileVoltage; +[v _readVoltage `f ~T0 @X0 1 a ] +[v _readNonvolatileVoltage `f ~T0 @X0 1 a ] +"33 +[; ;mcc_generated_files/DAC3_example.c: 33: uint16_t dacVoltage, dacNonvolatileVoltage; +[v _dacVoltage `us ~T0 @X0 1 a ] +[v _dacNonvolatileVoltage `us ~T0 @X0 1 a ] +"36 +[; ;mcc_generated_files/DAC3_example.c: 36: voltage = 1; +[e = _voltage -> -> 1 `i `f ] +"38 +[; ;mcc_generated_files/DAC3_example.c: 38: dacNonvolatileVoltage = (4096*voltage)/5; +[e = _dacNonvolatileVoltage -> / * -> -> 4096 `i `f _voltage -> -> 5 `i `f `us ] +"39 +[; ;mcc_generated_files/DAC3_example.c: 39: DAC3_SetNonvolatile(dacNonvolatileVoltage); +[e ( _DAC3_SetNonvolatile (1 _dacNonvolatileVoltage ] +"41 +[; ;mcc_generated_files/DAC3_example.c: 41: printf("Set the non-volatile voltage to 1V \n"); +[e ( _printf :s 1C ] +"43 +[; ;mcc_generated_files/DAC3_example.c: 43: _delay((unsigned long)((100)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 100 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"46 +[; ;mcc_generated_files/DAC3_example.c: 46: voltage = 2; +[e = _voltage -> -> 2 `i `f ] +"47 +[; ;mcc_generated_files/DAC3_example.c: 47: dacVoltage = (4096*voltage)/5; +[e = _dacVoltage -> / * -> -> 4096 `i `f _voltage -> -> 5 `i `f `us ] +"48 +[; ;mcc_generated_files/DAC3_example.c: 48: DAC3_Set(dacVoltage); +[e ( _DAC3_Set (1 _dacVoltage ] +"50 +[; ;mcc_generated_files/DAC3_example.c: 50: _delay((unsigned long)((100)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 100 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"52 +[; ;mcc_generated_files/DAC3_example.c: 52: printf("Set the volatile voltage to 2V \n"); +[e ( _printf :s 2C ] +"54 +[; ;mcc_generated_files/DAC3_example.c: 54: dacVoltage = DAC3_Read(&dacNonvolatileVoltage); +[e = _dacVoltage ( _DAC3_Read (1 &U _dacNonvolatileVoltage ] +"57 +[; ;mcc_generated_files/DAC3_example.c: 57: readVoltage = dacVoltage / 819.2; +[e = _readVoltage -> / -> -> _dacVoltage `ui `d .819.2 `f ] +"58 +[; ;mcc_generated_files/DAC3_example.c: 58: readNonvolatileVoltage = dacNonvolatileVoltage / 819.2; +[e = _readNonvolatileVoltage -> / -> -> _dacNonvolatileVoltage `ui `d .819.2 `f ] +"60 +[; ;mcc_generated_files/DAC3_example.c: 60: printf("Read: non-volatile voltage value %f, and volatile voltage value %f", readNonvolatileVoltage, readVoltage); +[e ( _printf , , (. :s 3C -> _readNonvolatileVoltage `d -> _readVoltage `d ] +"62 +[; ;mcc_generated_files/DAC3_example.c: 62: _delay((unsigned long)((100)*(10000000/4000.0))); +[e ( __delay (1 -> * -> -> 100 `i `d / -> -> 10000000 `l `d .4000.0 `ul ] +"63 +[; ;mcc_generated_files/DAC3_example.c: 63: } +[e :UE 3181 ] +} +[p f _printf 8396800 ] +[a 3C 82 101 97 100 58 32 110 111 110 45 118 111 108 97 116 105 108 101 32 118 111 108 116 97 103 101 32 118 97 108 117 101 32 37 102 44 32 97 110 100 32 118 111 108 97 116 105 108 101 32 118 111 108 116 97 103 101 32 118 97 108 117 101 32 37 102 0 ] +[a 2C 83 101 116 32 116 104 101 32 118 111 108 97 116 105 108 101 32 118 111 108 116 97 103 101 32 116 111 32 50 86 32 10 0 ] +[a 1C 83 101 116 32 116 104 101 32 110 111 110 45 118 111 108 97 116 105 108 101 32 118 111 108 116 97 103 101 32 116 111 32 49 86 32 10 0 ] diff --git a/ETC.X/build/default/debug/mcc_generated_files/DAC3_example.p1.d b/ETC.X/build/default/debug/mcc_generated_files/DAC3_example.p1.d new file mode 100644 index 0000000..a5b40da --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/DAC3_example.p1.d @@ -0,0 +1,17 @@ +build/default/debug/mcc_generated_files/DAC3_example.p1: \ +mcc_generated_files/DAC3_example.c \ +mcc_generated_files/mcc.h \ +mcc_generated_files/device_config.h \ +mcc_generated_files/pin_manager.h \ +mcc_generated_files/interrupt_manager.h \ +mcc_generated_files/i2c1_master.h \ +mcc_generated_files/adc.h \ +mcc_generated_files/tmr1.h \ +mcc_generated_files/tmr0.h \ +mcc_generated_files/can1.h \ +mcc_generated_files/can_types.h \ +mcc_generated_files/drivers/i2c_simple_master.h \ +mcc_generated_files/pwm2_16bit.h \ +mcc_generated_files/DAC3.h \ +mcc_generated_files/pwm1_16bit.h \ +mcc_generated_files/DAC3_example.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/adc.i b/ETC.X/build/default/debug/mcc_generated_files/adc.i new file mode 100644 index 0000000..b4463fc --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/adc.i @@ -0,0 +1,38391 @@ +# 1 "mcc_generated_files/adc.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/adc.c" 2 +# 51 "mcc_generated_files/adc.c" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 51 "mcc_generated_files/adc.c" 2 + +# 1 "mcc_generated_files/adc.h" 1 +# 58 "mcc_generated_files/adc.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 58 "mcc_generated_files/adc.h" 2 + + + + + + + +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 52 "mcc_generated_files/adc.c" 2 + + + + +static void (*ADC_ConversionComplete_ISR)(void); +static void (*ADC_Context1Thereshld_ISR)(void); +static void (*ADC_Context2Thereshld_ISR)(void); +static void (*ADC_Context3Thereshld_ISR)(void); +static void (*ADC_Context4Thereshld_ISR)(void); +static void (*ADC_ActiveClockTuning_ISR)(void); + +static void ADC_DefaultADI_ISR(void); +static void ADC_DefaultContext1Threshold_ISR(void); +static void ADC_DefaultContext2Threshold_ISR(void); +static void ADC_DefaultContext3Threshold_ISR(void); +static void ADC_DefaultContext4Threshold_ISR(void); +static void ADC_DefaultActiveClockTuning_ISR(void); + + +void ADC_Initialize(void) +{ + + ADACT = 0x02; + + + ADCLK = 0x3F; + + + ADCP = 0x00; + + + + + + ADCTX = 0x0; + + + ADLTHL = 0x00; + + + ADLTHH = 0x00; + + + ADUTHL = 0x00; + + + ADUTHH = 0x00; + + + ADSTPTL = 0x00; + + + ADSTPTH = 0x00; + + + ADACCL = 0x00; + + + ADACCH = 0x00; + + + ADACCU = 0x00; + + + ADCNT = 0x00; + + + ADRPT = 0x00; + + + ADRESL = 0x00; + + + ADRESH = 0x00; + + + ADPCH = 0x10; + + + ADACQL = 0xE8; + + + ADACQH = 0x03; + + + ADCAP = 0x00; + + + ADPREL = 0x00; + + + ADPREH = 0x00; + + + ADCON0 = 0x00; + + + ADCON1 = 0x00; + + + ADCON2 = 0x10; + + + ADCON3 = 0x00; + + + ADSTAT = 0x00; + + + ADREF = 0x00; + + + ADCSEL1 = 0x00; + + + + + ADCTX = 0x1; + + + ADLTHL = 0x00; + + + ADLTHH = 0x00; + + + ADUTHL = 0x00; + + + ADUTHH = 0x00; + + + ADSTPTL = 0x00; + + + ADSTPTH = 0x00; + + + ADACCL = 0x00; + + + ADACCH = 0x00; + + + ADACCU = 0x00; + + + ADCNT = 0x00; + + + ADRPT = 0x00; + + + ADRESL = 0x00; + + + ADRESH = 0x00; + + + ADPCH = 0x04; + + + ADACQL = 0xE8; + + + ADACQH = 0x03; + + + ADCAP = 0x00; + + + ADPREL = 0x00; + + + ADPREH = 0x00; + + + ADCON0 = 0x00; + + + ADCON1 = 0x00; + + + ADCON2 = 0x10; + + + ADCON3 = 0x00; + + + ADSTAT = 0x00; + + + ADREF = 0x00; + + + ADCSEL2 = 0x00; + + + + + ADCTX = 0x2; + + + ADLTHL = 0x00; + + + ADLTHH = 0x00; + + + ADUTHL = 0x00; + + + ADUTHH = 0x00; + + + ADSTPTL = 0x00; + + + ADSTPTH = 0x00; + + + ADACCL = 0x00; + + + ADACCH = 0x00; + + + ADACCU = 0x00; + + + ADCNT = 0x00; + + + ADRPT = 0x00; + + + ADRESL = 0x00; + + + ADRESH = 0x00; + + + ADPCH = 0x12; + + + ADACQL = 0xE8; + + + ADACQH = 0x03; + + + ADCAP = 0x00; + + + ADPREL = 0x00; + + + ADPREH = 0x00; + + + ADCON0 = 0x00; + + + ADCON1 = 0x00; + + + ADCON2 = 0x10; + + + ADCON3 = 0x00; + + + ADSTAT = 0x00; + + + ADREF = 0x00; + + + ADCSEL3 = 0x00; + + + + + ADCTX = 0x3; + + + ADLTHL = 0x00; + + + ADLTHH = 0x00; + + + ADUTHL = 0x00; + + + ADUTHH = 0x00; + + + ADSTPTL = 0x00; + + + ADSTPTH = 0x00; + + + ADACCL = 0x00; + + + ADACCH = 0x00; + + + ADACCU = 0x00; + + + ADCNT = 0x00; + + + ADRPT = 0x00; + + + ADRESL = 0x00; + + + ADRESH = 0x00; + + + ADPCH = 0x11; + + + ADACQL = 0xE8; + + + ADACQH = 0x03; + + + ADCAP = 0x00; + + + ADPREL = 0x00; + + + ADPREH = 0x00; + + + ADCON0 = 0x00; + + + ADCON1 = 0x00; + + + ADCON2 = 0x10; + + + ADCON3 = 0x00; + + + ADSTAT = 0x00; + + + ADREF = 0x00; + + + ADCSEL4 = 0x00; + + + PIR1bits.ADIF = 0; + + + PIR1bits.ACTIF = 0; + + + PIR2bits.ADCH1IF = 0; + PIR2bits.ADCH2IF = 0; + PIR2bits.ADCH3IF = 0; + PIR2bits.ADCH4IF = 0; + + + + ADC_SetADIInterruptHandler(ADC_DefaultADI_ISR); + ADC_SetContext1ThresholdInterruptHandler(ADC_DefaultContext1Threshold_ISR); + ADC_SetContext2ThresholdInterruptHandler(ADC_DefaultContext2Threshold_ISR); + ADC_SetContext3ThresholdInterruptHandler(ADC_DefaultContext3Threshold_ISR); + ADC_SetContext4ThresholdInterruptHandler(ADC_DefaultContext4Threshold_ISR); + ADC_SetActiveClockTuningInterruptHandler(ADC_DefaultActiveClockTuning_ISR); + + + ADCON0 = 0x84; +} + +__attribute__((inline)) void ADC_EnableChannelSequencer(void) +{ + ADCON0bits.CSEN = 1; +} + +__attribute__((inline)) void ADC_DisableChannelSequencer(void) +{ + ADCON0bits.CSEN = 0; +} + +__attribute__((inline)) void ADC_StartChannelSequencer(void) +{ + ADCON0bits.GO = 1; +} + +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context) +{ + ADCTX = context; +} + +void ADC_EnableChannelScan(ADC_context_t context) +{ + switch (context) + { + case CONTEXT_TPS1: + ADCSEL1bits.CHEN = 1; + break; + case CONTEXT_TPS2: + ADCSEL2bits.CHEN = 1; + break; + case CONTEXT_APPS1: + ADCSEL3bits.CHEN = 1; + break; + case CONTEXT_APPS2: + ADCSEL4bits.CHEN = 1; + break; + default: + break; + } +} + +void ADC_DisableChannelScan(ADC_context_t context) +{ + switch (context) + { + case CONTEXT_TPS1: + ADCSEL1bits.CHEN = 0; + break; + case CONTEXT_TPS2: + ADCSEL2bits.CHEN = 0; + break; + case CONTEXT_APPS1: + ADCSEL3bits.CHEN = 0; + break; + case CONTEXT_APPS2: + ADCSEL4bits.CHEN = 0; + break; + default: + break; + } +} + +void ADC_StartConversion(ADC_channel_t channel) +{ + + ADPCH = channel; + + + ADCON0bits.ON = 1; + + + ADCON0bits.GO = 1; +} + +_Bool ADC_IsConversionDone(void) +{ + return (_Bool) (!ADCON0bits.GO); +} + +adc_result_t ADC_GetConversionResult(void) +{ + + return ((adc_result_t) ((ADRESH << 8) + ADRESL)); +} + +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel) +{ + + ADPCH = channel; + + + ADCON0bits.ON = 1; + + + ADCON0bits.CONT = 0; + + + ADCON0bits.GO = 1; + + + while(ADCON0bits.GO) + { + + } + + return ((adc_result_t) ((ADRESH << 8) + ADRESL)); +} + +__attribute__((inline)) void ADC_StopConversion(void) +{ + + ADCON0bits.GO = 0; +} + +__attribute__((inline)) void ADC_SetStopOnInterrupt(void) +{ + ADCON3bits.SOI = 1; +} + +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void) +{ + + ADPCH = 0x3b; +} + +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue) +{ + ADACQH = acquisitionValue >> 8; + ADACQL = acquisitionValue; +} + +void ADC_SetPrechargeTime(uint16_t prechargeTime) +{ + ADPREH = prechargeTime >> 8; + ADPREL = prechargeTime; +} + +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount) +{ + ADRPT = repeatCount; +} + +uint8_t ADC_GetCurrentCountofConversions(void) +{ + return ADCNT; +} + +__attribute__((inline)) void ADC_ClearAccumulator(void) +{ + ADCON2bits.ACLR = 1; +} + +uint24_t ADC_GetAccumulatorValue(void) +{ + return ((uint24_t) ((ADACCH << 8) + ADACCL)); +} + +_Bool ADC_HasAccumulatorOverflowed(void) +{ + return ADSTATbits.ADAOV; +} + +uint16_t ADC_GetFilterValue(void) +{ + return ((uint16_t) ((ADFLTRH << 8) + ADFLTRL)); +} + +uint16_t ADC_GetPreviousResult(void) +{ + return ((uint16_t) ((ADPREVH << 8) + ADPREVL)); +} + +void ADC_DefineSetPoint(uint16_t setPoint) +{ + ADSTPTH = setPoint >> 8; + ADSTPTL = setPoint; +} + +void ADC_SetUpperThreshold(uint16_t upperThreshold) +{ + ADUTHH = upperThreshold >> 8; + ADUTHL = upperThreshold; +} + +void ADC_SetLowerThreshold(uint16_t lowerThreshold) +{ + ADLTHH = lowerThreshold >> 8; + ADLTHL = lowerThreshold; +} + +uint16_t ADC_GetErrorCalculation(void) +{ + return ((uint16_t) ((ADERRH << 8) + ADERRL)); +} + +__attribute__((inline)) void ADC_EnableDoubleSampling(void) +{ + ADCON1bits.DSEN = 1; +} + +__attribute__((inline)) void ADC_EnableContinuousConversion(void) +{ + ADCON0bits.CONT = 1; +} + +__attribute__((inline)) void ADC_DisableContinuousConversion(void) +{ + ADCON0bits.CONT = 0; +} + +_Bool ADC_HasErrorCrossedUpperThreshold(void) +{ + return ADSTATbits.ADUTHR; +} + +_Bool ADC_HasErrorCrossedLowerThreshold(void) +{ + return ADSTATbits.ADLTHR; +} + +uint8_t ADC_GetConversionStageStatus(void) +{ + return ADSTATbits.ADSTAT; +} + +__attribute__((inline)) void ADC_EnableChargePump(void) +{ + ADCPbits.CPON = 1; +} + +__attribute__((inline)) void ADC_DisableChargePump(void) +{ + ADCPbits.CPON = 0; +} + +void ADC_ADI_ISR(void) +{ + PIR1bits.ADIF = 0; + if (ADC_ConversionComplete_ISR != ((void*)0)) + ADC_ConversionComplete_ISR(); +} + +void ADC_ACTI_ISR(void) +{ + PIR1bits.ACTIF = 0; + if (ADC_ActiveClockTuning_ISR != ((void*)0)) + ADC_ActiveClockTuning_ISR(); +} + + +void ADC_ADCH1_ISR(void) +{ + PIR2bits.ADCH1IF = 0; + if (ADC_Context1Thereshld_ISR != ((void*)0)) + ADC_Context1Thereshld_ISR(); +} + +void ADC_ADCH2_ISR(void) +{ + PIR2bits.ADCH2IF = 0; + if (ADC_Context2Thereshld_ISR != ((void*)0)) + ADC_Context2Thereshld_ISR(); +} + +void ADC_ADCH3_ISR(void) +{ + PIR2bits.ADCH3IF = 0; + if (ADC_Context3Thereshld_ISR != ((void*)0)) + ADC_Context3Thereshld_ISR(); +} + +void ADC_ADCH4_ISR(void) +{ + PIR2bits.ADCH4IF = 0; + if (ADC_Context4Thereshld_ISR != ((void*)0)) + ADC_Context4Thereshld_ISR(); +} + +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)) +{ + ADC_ConversionComplete_ISR = InterruptHandler; +} + +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)) +{ + ADC_Context1Thereshld_ISR = InterruptHandler; +} + +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)) +{ + ADC_Context2Thereshld_ISR = InterruptHandler; +} + +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)) +{ + ADC_Context3Thereshld_ISR = InterruptHandler; +} + +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)) +{ + ADC_Context4Thereshld_ISR = InterruptHandler; +} + +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)) +{ + ADC_ActiveClockTuning_ISR = InterruptHandler; +} + +static void ADC_DefaultADI_ISR(void) +{ + + +} + + +static void ADC_DefaultContext1Threshold_ISR(void) +{ + + +} + +static void ADC_DefaultContext2Threshold_ISR(void) +{ + + +} + +static void ADC_DefaultContext3Threshold_ISR(void) +{ + + +} + +static void ADC_DefaultContext4Threshold_ISR(void) +{ + + +} + +static void ADC_DefaultActiveClockTuning_ISR(void) +{ + + +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/adc.p1 b/ETC.X/build/default/debug/mcc_generated_files/adc.p1 new file mode 100644 index 0000000..fbebda5 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/adc.p1 @@ -0,0 +1,5393 @@ +Version 4.0 HI-TECH Software Intermediate Code +[v F22251 `(v ~T0 @X0 0 tf ] +[v F22253 `(v ~T0 @X0 0 tf ] +[v F22255 `(v ~T0 @X0 0 tf ] +[v F22257 `(v ~T0 @X0 0 tf ] +[v F22259 `(v ~T0 @X0 0 tf ] +[v F22261 `(v ~T0 @X0 0 tf ] +"58039 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58039: extern volatile unsigned char ADACT __attribute__((address(0x3F9))); +[v _ADACT `Vuc ~T0 @X0 0 e@1017 ] +"58143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58143: extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); +[v _ADCLK `Vuc ~T0 @X0 0 e@1018 ] +"54261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54261: extern volatile unsigned char ADCP __attribute__((address(0x3D8))); +[v _ADCP `Vuc ~T0 @X0 0 e@984 ] +"58247 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58247: extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); +[v _ADCTX `Vuc ~T0 @X0 0 e@1019 ] +"54363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54363: extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); +[v _ADLTHL `Vuc ~T0 @X0 0 e@985 ] +"54491 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54491: extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); +[v _ADLTHH `Vuc ~T0 @X0 0 e@986 ] +"54626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54626: extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); +[v _ADUTHL `Vuc ~T0 @X0 0 e@987 ] +"54754 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54754: extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); +[v _ADUTHH `Vuc ~T0 @X0 0 e@988 ] +"55152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55152: extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); +[v _ADSTPTL `Vuc ~T0 @X0 0 e@991 ] +"55280 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55280: extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); +[v _ADSTPTH `Vuc ~T0 @X0 0 e@992 ] +"55680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55680: extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); +[v _ADACCL `Vuc ~T0 @X0 0 e@995 ] +"55808 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55808: extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); +[v _ADACCH `Vuc ~T0 @X0 0 e@996 ] +"55936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55936: extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); +[v _ADACCU `Vuc ~T0 @X0 0 e@997 ] +"55992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55992: extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); +[v _ADCNT `Vuc ~T0 @X0 0 e@998 ] +"56120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56120: extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); +[v _ADRPT `Vuc ~T0 @X0 0 e@999 ] +"56518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56518: extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); +[v _ADRESL `Vuc ~T0 @X0 0 e@1002 ] +"56646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56646: extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); +[v _ADRESH `Vuc ~T0 @X0 0 e@1003 ] +"56766 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56766: extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); +[v _ADPCH `Vuc ~T0 @X0 0 e@1004 ] +"56831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56831: extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); +[v _ADACQL `Vuc ~T0 @X0 0 e@1006 ] +"56959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56959: extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); +[v _ADACQH `Vuc ~T0 @X0 0 e@1007 ] +"57051 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57051: extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); +[v _ADCAP `Vuc ~T0 @X0 0 e@1008 ] +"57110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57110: extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); +[v _ADPREL `Vuc ~T0 @X0 0 e@1009 ] +"57238 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57238: extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); +[v _ADPREH `Vuc ~T0 @X0 0 e@1010 ] +"57330 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57330: extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); +[v _ADCON0 `Vuc ~T0 @X0 0 e@1011 ] +"57458 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57458: extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); +[v _ADCON1 `Vuc ~T0 @X0 0 e@1012 ] +"57524 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57524: extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); +[v _ADCON2 `Vuc ~T0 @X0 0 e@1013 ] +"57702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57702: extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); +[v _ADCON3 `Vuc ~T0 @X0 0 e@1014 ] +"57832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57832: extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); +[v _ADSTAT `Vuc ~T0 @X0 0 e@1015 ] +"57957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57957: extern volatile unsigned char ADREF __attribute__((address(0x3F8))); +[v _ADREF `Vuc ~T0 @X0 0 e@1016 ] +"58317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58317: extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); +[v _ADCSEL1 `Vuc ~T0 @X0 0 e@1020 ] +"58344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58344: extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); +[v _ADCSEL2 `Vuc ~T0 @X0 0 e@1021 ] +"58371 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58371: extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); +[v _ADCSEL3 `Vuc ~T0 @X0 0 e@1022 ] +"58398 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58398: extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); +[v _ADCSEL4 `Vuc ~T0 @X0 0 e@1023 ] +"557 +[s S3030 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3030 . INT0IF ZCDIF ADIF ACTIF C1IF SMT1IF SMT1PRAIF SMT1PWAIF ] +"556 +[u S3029 `S3030 1 ] +[n S3029 . . ] +"568 +[v _PIR1bits `VS3029 ~T0 @X0 0 e@1199 ] +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[s S3032 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3032 . ADTIF ADCH2IF ADCH3IF ADCH4IF DMA1SCNTIF DMA1DCNTIF DMA1ORIF DMA1AIF ] +"629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 629: unsigned NVMCMD :3; +[s S3033 :1 `uc 1 ] +[n S3033 . ADCH1IF ] +"618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 618: +[u S3031 `S3032 1 `S3033 1 ] +[n S3031 . . . ] +"633 +[v _PIR2bits `VS3031 ~T0 @X0 0 e@1200 ] +[v F22222 `(v ~T0 @X0 0 tf ] +"999 mcc_generated_files/adc.h +[; ;mcc_generated_files/adc.h: 999: void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); +[v _ADC_SetADIInterruptHandler `(v ~T0 @X0 0 ef1`*F22222 ] +"63 mcc_generated_files/adc.c +[; ;mcc_generated_files/adc.c: 63: static void ADC_DefaultADI_ISR(void); +[v _ADC_DefaultADI_ISR `(v ~T0 @X0 0 sf ] +[v F22232 `(v ~T0 @X0 0 tf ] +"1071 mcc_generated_files/adc.h +[; ;mcc_generated_files/adc.h: 1071: void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); +[v _ADC_SetContext1ThresholdInterruptHandler `(v ~T0 @X0 0 ef1`*F22232 ] +"64 mcc_generated_files/adc.c +[; ;mcc_generated_files/adc.c: 64: static void ADC_DefaultContext1Threshold_ISR(void); +[v _ADC_DefaultContext1Threshold_ISR `(v ~T0 @X0 0 sf ] +[v F22237 `(v ~T0 @X0 0 tf ] +"1107 mcc_generated_files/adc.h +[; ;mcc_generated_files/adc.h: 1107: void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); +[v _ADC_SetContext2ThresholdInterruptHandler `(v ~T0 @X0 0 ef1`*F22237 ] +"65 mcc_generated_files/adc.c +[; ;mcc_generated_files/adc.c: 65: static void ADC_DefaultContext2Threshold_ISR(void); +[v _ADC_DefaultContext2Threshold_ISR `(v ~T0 @X0 0 sf ] +[v F22242 `(v ~T0 @X0 0 tf ] +"1143 mcc_generated_files/adc.h +[; ;mcc_generated_files/adc.h: 1143: void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); +[v _ADC_SetContext3ThresholdInterruptHandler `(v ~T0 @X0 0 ef1`*F22242 ] +"66 mcc_generated_files/adc.c +[; ;mcc_generated_files/adc.c: 66: static void ADC_DefaultContext3Threshold_ISR(void); +[v _ADC_DefaultContext3Threshold_ISR `(v ~T0 @X0 0 sf ] +[v F22247 `(v ~T0 @X0 0 tf ] +"1179 mcc_generated_files/adc.h +[; ;mcc_generated_files/adc.h: 1179: void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +[v _ADC_SetContext4ThresholdInterruptHandler `(v ~T0 @X0 0 ef1`*F22247 ] +"67 mcc_generated_files/adc.c +[; ;mcc_generated_files/adc.c: 67: static void ADC_DefaultContext4Threshold_ISR(void); +[v _ADC_DefaultContext4Threshold_ISR `(v ~T0 @X0 0 sf ] +[v F22227 `(v ~T0 @X0 0 tf ] +"1035 mcc_generated_files/adc.h +[; ;mcc_generated_files/adc.h: 1035: void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); +[v _ADC_SetActiveClockTuningInterruptHandler `(v ~T0 @X0 0 ef1`*F22227 ] +"68 mcc_generated_files/adc.c +[; ;mcc_generated_files/adc.c: 68: static void ADC_DefaultActiveClockTuning_ISR(void); +[v _ADC_DefaultActiveClockTuning_ISR `(v ~T0 @X0 0 sf ] +"57336 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57336: struct { +[s S2624 :1 `uc 1 :1 `uc 1 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2624 . GO . FM CS CSEN CONT ON ] +"57345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57345: struct { +[s S2625 :1 `uc 1 :1 `uc 1 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2625 . ADGO . ADFM ADCS ADCSEN ADCONT ADON ] +"57354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57354: struct { +[s S2626 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2626 . DONE . FM0 ] +"57359 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57359: struct { +[s S2627 :1 `uc 1 ] +[n S2627 . GO_NOT_DONE ] +"57362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57362: struct { +[s S2628 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2628 . GO_nDONE . ADFM0 ] +"57335 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57335: typedef union { +[u S2623 `S2624 1 `S2625 1 `S2626 1 `S2627 1 `S2628 1 ] +[n S2623 . . . . . . ] +"57368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57368: extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +[v _ADCON0bits `VS2623 ~T0 @X0 0 e@1011 ] +"455 mcc_generated_files/adc.c +[; ;mcc_generated_files/adc.c: 455: __attribute__((inline)) void ADC_SelectContext(ADC_context_t context) +[c E22154 0 1 2 3 .. ] +[n E22154 . CONTEXT_TPS1 CONTEXT_TPS2 CONTEXT_APPS1 CONTEXT_APPS2 ] +"58323 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58323: struct { +[s S2671 :6 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2671 . . SSI CHEN ] +"58322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58322: typedef union { +[u S2670 `S2671 1 ] +[n S2670 . . ] +"58329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58329: extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +[v _ADCSEL1bits `VS2670 ~T0 @X0 0 e@1020 ] +"58350 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58350: struct { +[s S2673 :6 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2673 . . SSI CHEN ] +"58349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58349: typedef union { +[u S2672 `S2673 1 ] +[n S2672 . . ] +"58356 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58356: extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +[v _ADCSEL2bits `VS2672 ~T0 @X0 0 e@1021 ] +"58377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58377: struct { +[s S2675 :6 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2675 . . SSI CHEN ] +"58376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58376: typedef union { +[u S2674 `S2675 1 ] +[n S2674 . . ] +"58383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58383: extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +[v _ADCSEL3bits `VS2674 ~T0 @X0 0 e@1022 ] +"58404 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58404: struct { +[s S2677 :6 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2677 . . SSI CHEN ] +"58403 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58403: typedef union { +[u S2676 `S2677 1 ] +[n S2676 . . ] +"58410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58410: extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +[v _ADCSEL4bits `VS2676 ~T0 @X0 0 e@1023 ] +"502 mcc_generated_files/adc.c +[; ;mcc_generated_files/adc.c: 502: void ADC_StartConversion(ADC_channel_t channel) +[c E22143 4 16 17 18 59 60 61 62 63 .. ] +[n E22143 . TPS2 TPS1 APPS2 APPS1 channel_VSS channel_Temp channel_DAC1 channel_FVR_Buffer1 channel_FVR_Buffer2 ] +"57708 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57708: struct { +[s S2641 :3 `uc 1 :1 `uc 1 :3 `uc 1 ] +[n S2641 . TMD SOI CALC ] +"57713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57713: struct { +[s S2642 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2642 . ADTMD0 ADTMD1 ADTMD2 ADSOI ADCALC0 ADCALC1 ADCALC2 ] +"57722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57722: struct { +[s S2643 :3 `uc 1 :1 `uc 1 :3 `uc 1 ] +[n S2643 . ADTMD . ADCALC ] +"57727 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57727: struct { +[s S2644 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2644 . TMD0 TMD1 TMD2 . CALC0 CALC1 CALC2 ] +"57707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57707: typedef union { +[u S2640 `S2641 1 `S2642 1 `S2643 1 `S2644 1 ] +[n S2640 . . . . . ] +"57737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57737: extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +[v _ADCON3bits `VS2640 ~T0 @X0 0 e@1014 ] +"57530 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57530: struct { +[s S2633 :3 `uc 1 :1 `uc 1 :3 `uc 1 :1 `uc 1 ] +[n S2633 . MODE ACLR CRS PSIS ] +"57536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57536: struct { +[s S2634 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2634 . ADMD0 ADMD1 ADMD2 ADACLR ADCRS0 ADCRS1 ADCRS2 ADPSIS ] +"57546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57546: struct { +[s S2635 :3 `uc 1 :1 `uc 1 :3 `uc 1 ] +[n S2635 . ADMD . ADCRS ] +"57551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57551: struct { +[s S2636 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2636 . MODE0 MODE1 MODE2 . CRS0 CRS1 CRS2 ] +"57560 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57560: struct { +[s S2637 :3 `uc 1 ] +[n S2637 . MD ] +"57563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57563: struct { +[s S2638 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2638 . MD0 MD1 MD2 ] +"57568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57568: struct { +[s S2639 :3 `uc 1 ] +[n S2639 . ADMODE ] +"57529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57529: typedef union { +[u S2632 `S2633 1 `S2634 1 `S2635 1 `S2636 1 `S2637 1 `S2638 1 `S2639 1 ] +[n S2632 . . . . . . . . ] +"57572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57572: extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +[v _ADCON2bits `VS2632 ~T0 @X0 0 e@1013 ] +"57838 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57838: struct { +[s S2646 :3 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2646 . STAT . MATH LTHR UTHR OV ] +"57846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57846: struct { +[s S2647 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2647 . ADSTAT0 ADSTAT1 ADSTAT2 . ADMATH ADLTHR ADUTHR ADAOV ] +"57856 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57856: struct { +[s S2648 :3 `uc 1 :4 `uc 1 :1 `uc 1 ] +[n S2648 . ADSTAT . ADOV ] +"57861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57861: struct { +[s S2649 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2649 . STAT0 STAT1 STAT2 ] +"57837 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57837: typedef union { +[u S2645 `S2646 1 `S2647 1 `S2648 1 `S2649 1 ] +[n S2645 . . . . . ] +"57867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57867: extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +[v _ADSTATbits `VS2645 ~T0 @X0 0 e@1015 ] +"55543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55543: extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); +[v _ADFLTRH `Vuc ~T0 @X0 0 e@994 ] +"55415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55415: extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); +[v _ADFLTRL `Vuc ~T0 @X0 0 e@993 ] +"56383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56383: extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); +[v _ADPREVH `Vuc ~T0 @X0 0 e@1001 ] +"56255 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56255: extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); +[v _ADPREVL `Vuc ~T0 @X0 0 e@1000 ] +"55017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55017: extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); +[v _ADERRH `Vuc ~T0 @X0 0 e@990 ] +"54889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54889: extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); +[v _ADERRL `Vuc ~T0 @X0 0 e@989 ] +"57464 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57464: struct { +[s S2630 :1 `uc 1 :4 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2630 . DSEN . GPOL IPEN PPOL ] +"57471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57471: struct { +[s S2631 :1 `uc 1 :4 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2631 . ADDSEN . ADGPOL ADIPEN ADPPOL ] +"57463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57463: typedef union { +[u S2629 `S2630 1 `S2631 1 ] +[n S2629 . . . ] +"57479 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57479: extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +[v _ADCON1bits `VS2629 ~T0 @X0 0 e@1012 ] +"54311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54311: struct { +[s S2500 :1 `uc 1 :6 `uc 1 :1 `uc 1 ] +[n S2500 . CPRDY . ON ] +"54316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54316: struct { +[s S2501 :1 `uc 1 :6 `uc 1 :1 `uc 1 ] +[n S2501 . ADCPRDY . CPON ] +"54321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54321: struct { +[s S2502 :7 `uc 1 :1 `uc 1 ] +[n S2502 . . ADCPON ] +"54310 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54310: typedef union { +[u S2499 `S2500 1 `S2501 1 `S2502 1 ] +[n S2499 . . . . ] +"54326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54326: extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +[v _ADCPbits `VS2499 ~T0 @X0 0 e@984 ] +[v F22335 `(v ~T0 @X0 0 tf ] +[v F22337 `(v ~T0 @X0 0 tf ] +[v F22339 `(v ~T0 @X0 0 tf ] +[v F22341 `(v ~T0 @X0 0 tf ] +[v F22343 `(v ~T0 @X0 0 tf ] +[v F22345 `(v ~T0 @X0 0 tf ] +[v F22347 `(v ~T0 @X0 0 tf ] +[v F22349 `(v ~T0 @X0 0 tf ] +[v F22352 `(v ~T0 @X0 0 tf ] +[v F22354 `(v ~T0 @X0 0 tf ] +[v F22357 `(v ~T0 @X0 0 tf ] +[v F22359 `(v ~T0 @X0 0 tf ] +[v F22362 `(v ~T0 @X0 0 tf ] +[v F22364 `(v ~T0 @X0 0 tf ] +[v F22367 `(v ~T0 @X0 0 tf ] +[v F22369 `(v ~T0 @X0 0 tf ] +[v F22372 `(v ~T0 @X0 0 tf ] +[v F22374 `(v ~T0 @X0 0 tf ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"56 mcc_generated_files/adc.c +[; ;mcc_generated_files/adc.c: 56: static void (*ADC_ConversionComplete_ISR)(void); +[v _ADC_ConversionComplete_ISR `*F22251 ~T0 @X0 1 s ] +"57 +[; ;mcc_generated_files/adc.c: 57: static void (*ADC_Context1Thereshld_ISR)(void); +[v _ADC_Context1Thereshld_ISR `*F22253 ~T0 @X0 1 s ] +"58 +[; ;mcc_generated_files/adc.c: 58: static void (*ADC_Context2Thereshld_ISR)(void); +[v _ADC_Context2Thereshld_ISR `*F22255 ~T0 @X0 1 s ] +"59 +[; ;mcc_generated_files/adc.c: 59: static void (*ADC_Context3Thereshld_ISR)(void); +[v _ADC_Context3Thereshld_ISR `*F22257 ~T0 @X0 1 s ] +"60 +[; ;mcc_generated_files/adc.c: 60: static void (*ADC_Context4Thereshld_ISR)(void); +[v _ADC_Context4Thereshld_ISR `*F22259 ~T0 @X0 1 s ] +"61 +[; ;mcc_generated_files/adc.c: 61: static void (*ADC_ActiveClockTuning_ISR)(void); +[v _ADC_ActiveClockTuning_ISR `*F22261 ~T0 @X0 1 s ] +"71 +[; ;mcc_generated_files/adc.c: 71: void ADC_Initialize(void) +[v _ADC_Initialize `(v ~T0 @X0 1 ef ] +"72 +[; ;mcc_generated_files/adc.c: 72: { +{ +[e :U _ADC_Initialize ] +[f ] +"74 +[; ;mcc_generated_files/adc.c: 74: ADACT = 0x02; +[e = _ADACT -> -> 2 `i `uc ] +"77 +[; ;mcc_generated_files/adc.c: 77: ADCLK = 0x3F; +[e = _ADCLK -> -> 63 `i `uc ] +"80 +[; ;mcc_generated_files/adc.c: 80: ADCP = 0x00; +[e = _ADCP -> -> 0 `i `uc ] +"86 +[; ;mcc_generated_files/adc.c: 86: ADCTX = 0x0; +[e = _ADCTX -> -> 0 `i `uc ] +"89 +[; ;mcc_generated_files/adc.c: 89: ADLTHL = 0x00; +[e = _ADLTHL -> -> 0 `i `uc ] +"92 +[; ;mcc_generated_files/adc.c: 92: ADLTHH = 0x00; +[e = _ADLTHH -> -> 0 `i `uc ] +"95 +[; ;mcc_generated_files/adc.c: 95: ADUTHL = 0x00; +[e = _ADUTHL -> -> 0 `i `uc ] +"98 +[; ;mcc_generated_files/adc.c: 98: ADUTHH = 0x00; +[e = _ADUTHH -> -> 0 `i `uc ] +"101 +[; ;mcc_generated_files/adc.c: 101: ADSTPTL = 0x00; +[e = _ADSTPTL -> -> 0 `i `uc ] +"104 +[; ;mcc_generated_files/adc.c: 104: ADSTPTH = 0x00; +[e = _ADSTPTH -> -> 0 `i `uc ] +"107 +[; ;mcc_generated_files/adc.c: 107: ADACCL = 0x00; +[e = _ADACCL -> -> 0 `i `uc ] +"110 +[; ;mcc_generated_files/adc.c: 110: ADACCH = 0x00; +[e = _ADACCH -> -> 0 `i `uc ] +"113 +[; ;mcc_generated_files/adc.c: 113: ADACCU = 0x00; +[e = _ADACCU -> -> 0 `i `uc ] +"116 +[; ;mcc_generated_files/adc.c: 116: ADCNT = 0x00; +[e = _ADCNT -> -> 0 `i `uc ] +"119 +[; ;mcc_generated_files/adc.c: 119: ADRPT = 0x00; +[e = _ADRPT -> -> 0 `i `uc ] +"122 +[; ;mcc_generated_files/adc.c: 122: ADRESL = 0x00; +[e = _ADRESL -> -> 0 `i `uc ] +"125 +[; ;mcc_generated_files/adc.c: 125: ADRESH = 0x00; +[e = _ADRESH -> -> 0 `i `uc ] +"128 +[; ;mcc_generated_files/adc.c: 128: ADPCH = 0x10; +[e = _ADPCH -> -> 16 `i `uc ] +"131 +[; ;mcc_generated_files/adc.c: 131: ADACQL = 0xE8; +[e = _ADACQL -> -> 232 `i `uc ] +"134 +[; ;mcc_generated_files/adc.c: 134: ADACQH = 0x03; +[e = _ADACQH -> -> 3 `i `uc ] +"137 +[; ;mcc_generated_files/adc.c: 137: ADCAP = 0x00; +[e = _ADCAP -> -> 0 `i `uc ] +"140 +[; ;mcc_generated_files/adc.c: 140: ADPREL = 0x00; +[e = _ADPREL -> -> 0 `i `uc ] +"143 +[; ;mcc_generated_files/adc.c: 143: ADPREH = 0x00; +[e = _ADPREH -> -> 0 `i `uc ] +"146 +[; ;mcc_generated_files/adc.c: 146: ADCON0 = 0x00; +[e = _ADCON0 -> -> 0 `i `uc ] +"149 +[; ;mcc_generated_files/adc.c: 149: ADCON1 = 0x00; +[e = _ADCON1 -> -> 0 `i `uc ] +"152 +[; ;mcc_generated_files/adc.c: 152: ADCON2 = 0x10; +[e = _ADCON2 -> -> 16 `i `uc ] +"155 +[; ;mcc_generated_files/adc.c: 155: ADCON3 = 0x00; +[e = _ADCON3 -> -> 0 `i `uc ] +"158 +[; ;mcc_generated_files/adc.c: 158: ADSTAT = 0x00; +[e = _ADSTAT -> -> 0 `i `uc ] +"161 +[; ;mcc_generated_files/adc.c: 161: ADREF = 0x00; +[e = _ADREF -> -> 0 `i `uc ] +"164 +[; ;mcc_generated_files/adc.c: 164: ADCSEL1 = 0x00; +[e = _ADCSEL1 -> -> 0 `i `uc ] +"169 +[; ;mcc_generated_files/adc.c: 169: ADCTX = 0x1; +[e = _ADCTX -> -> 1 `i `uc ] +"172 +[; ;mcc_generated_files/adc.c: 172: ADLTHL = 0x00; +[e = _ADLTHL -> -> 0 `i `uc ] +"175 +[; ;mcc_generated_files/adc.c: 175: ADLTHH = 0x00; +[e = _ADLTHH -> -> 0 `i `uc ] +"178 +[; ;mcc_generated_files/adc.c: 178: ADUTHL = 0x00; +[e = _ADUTHL -> -> 0 `i `uc ] +"181 +[; ;mcc_generated_files/adc.c: 181: ADUTHH = 0x00; +[e = _ADUTHH -> -> 0 `i `uc ] +"184 +[; ;mcc_generated_files/adc.c: 184: ADSTPTL = 0x00; +[e = _ADSTPTL -> -> 0 `i `uc ] +"187 +[; ;mcc_generated_files/adc.c: 187: ADSTPTH = 0x00; +[e = _ADSTPTH -> -> 0 `i `uc ] +"190 +[; ;mcc_generated_files/adc.c: 190: ADACCL = 0x00; +[e = _ADACCL -> -> 0 `i `uc ] +"193 +[; ;mcc_generated_files/adc.c: 193: ADACCH = 0x00; +[e = _ADACCH -> -> 0 `i `uc ] +"196 +[; ;mcc_generated_files/adc.c: 196: ADACCU = 0x00; +[e = _ADACCU -> -> 0 `i `uc ] +"199 +[; ;mcc_generated_files/adc.c: 199: ADCNT = 0x00; +[e = _ADCNT -> -> 0 `i `uc ] +"202 +[; ;mcc_generated_files/adc.c: 202: ADRPT = 0x00; +[e = _ADRPT -> -> 0 `i `uc ] +"205 +[; ;mcc_generated_files/adc.c: 205: ADRESL = 0x00; +[e = _ADRESL -> -> 0 `i `uc ] +"208 +[; ;mcc_generated_files/adc.c: 208: ADRESH = 0x00; +[e = _ADRESH -> -> 0 `i `uc ] +"211 +[; ;mcc_generated_files/adc.c: 211: ADPCH = 0x04; +[e = _ADPCH -> -> 4 `i `uc ] +"214 +[; ;mcc_generated_files/adc.c: 214: ADACQL = 0xE8; +[e = _ADACQL -> -> 232 `i `uc ] +"217 +[; ;mcc_generated_files/adc.c: 217: ADACQH = 0x03; +[e = _ADACQH -> -> 3 `i `uc ] +"220 +[; ;mcc_generated_files/adc.c: 220: ADCAP = 0x00; +[e = _ADCAP -> -> 0 `i `uc ] +"223 +[; ;mcc_generated_files/adc.c: 223: ADPREL = 0x00; +[e = _ADPREL -> -> 0 `i `uc ] +"226 +[; ;mcc_generated_files/adc.c: 226: ADPREH = 0x00; +[e = _ADPREH -> -> 0 `i `uc ] +"229 +[; ;mcc_generated_files/adc.c: 229: ADCON0 = 0x00; +[e = _ADCON0 -> -> 0 `i `uc ] +"232 +[; ;mcc_generated_files/adc.c: 232: ADCON1 = 0x00; +[e = _ADCON1 -> -> 0 `i `uc ] +"235 +[; ;mcc_generated_files/adc.c: 235: ADCON2 = 0x10; +[e = _ADCON2 -> -> 16 `i `uc ] +"238 +[; ;mcc_generated_files/adc.c: 238: ADCON3 = 0x00; +[e = _ADCON3 -> -> 0 `i `uc ] +"241 +[; ;mcc_generated_files/adc.c: 241: ADSTAT = 0x00; +[e = _ADSTAT -> -> 0 `i `uc ] +"244 +[; ;mcc_generated_files/adc.c: 244: ADREF = 0x00; +[e = _ADREF -> -> 0 `i `uc ] +"247 +[; ;mcc_generated_files/adc.c: 247: ADCSEL2 = 0x00; +[e = _ADCSEL2 -> -> 0 `i `uc ] +"252 +[; ;mcc_generated_files/adc.c: 252: ADCTX = 0x2; +[e = _ADCTX -> -> 2 `i `uc ] +"255 +[; ;mcc_generated_files/adc.c: 255: ADLTHL = 0x00; +[e = _ADLTHL -> -> 0 `i `uc ] +"258 +[; ;mcc_generated_files/adc.c: 258: ADLTHH = 0x00; +[e = _ADLTHH -> -> 0 `i `uc ] +"261 +[; ;mcc_generated_files/adc.c: 261: ADUTHL = 0x00; +[e = _ADUTHL -> -> 0 `i `uc ] +"264 +[; ;mcc_generated_files/adc.c: 264: ADUTHH = 0x00; +[e = _ADUTHH -> -> 0 `i `uc ] +"267 +[; ;mcc_generated_files/adc.c: 267: ADSTPTL = 0x00; +[e = _ADSTPTL -> -> 0 `i `uc ] +"270 +[; ;mcc_generated_files/adc.c: 270: ADSTPTH = 0x00; +[e = _ADSTPTH -> -> 0 `i `uc ] +"273 +[; ;mcc_generated_files/adc.c: 273: ADACCL = 0x00; +[e = _ADACCL -> -> 0 `i `uc ] +"276 +[; ;mcc_generated_files/adc.c: 276: ADACCH = 0x00; +[e = _ADACCH -> -> 0 `i `uc ] +"279 +[; ;mcc_generated_files/adc.c: 279: ADACCU = 0x00; +[e = _ADACCU -> -> 0 `i `uc ] +"282 +[; ;mcc_generated_files/adc.c: 282: ADCNT = 0x00; +[e = _ADCNT -> -> 0 `i `uc ] +"285 +[; ;mcc_generated_files/adc.c: 285: ADRPT = 0x00; +[e = _ADRPT -> -> 0 `i `uc ] +"288 +[; ;mcc_generated_files/adc.c: 288: ADRESL = 0x00; +[e = _ADRESL -> -> 0 `i `uc ] +"291 +[; ;mcc_generated_files/adc.c: 291: ADRESH = 0x00; +[e = _ADRESH -> -> 0 `i `uc ] +"294 +[; ;mcc_generated_files/adc.c: 294: ADPCH = 0x12; +[e = _ADPCH -> -> 18 `i `uc ] +"297 +[; ;mcc_generated_files/adc.c: 297: ADACQL = 0xE8; +[e = _ADACQL -> -> 232 `i `uc ] +"300 +[; ;mcc_generated_files/adc.c: 300: ADACQH = 0x03; +[e = _ADACQH -> -> 3 `i `uc ] +"303 +[; ;mcc_generated_files/adc.c: 303: ADCAP = 0x00; +[e = _ADCAP -> -> 0 `i `uc ] +"306 +[; ;mcc_generated_files/adc.c: 306: ADPREL = 0x00; +[e = _ADPREL -> -> 0 `i `uc ] +"309 +[; ;mcc_generated_files/adc.c: 309: ADPREH = 0x00; +[e = _ADPREH -> -> 0 `i `uc ] +"312 +[; ;mcc_generated_files/adc.c: 312: ADCON0 = 0x00; +[e = _ADCON0 -> -> 0 `i `uc ] +"315 +[; ;mcc_generated_files/adc.c: 315: ADCON1 = 0x00; +[e = _ADCON1 -> -> 0 `i `uc ] +"318 +[; ;mcc_generated_files/adc.c: 318: ADCON2 = 0x10; +[e = _ADCON2 -> -> 16 `i `uc ] +"321 +[; ;mcc_generated_files/adc.c: 321: ADCON3 = 0x00; +[e = _ADCON3 -> -> 0 `i `uc ] +"324 +[; ;mcc_generated_files/adc.c: 324: ADSTAT = 0x00; +[e = _ADSTAT -> -> 0 `i `uc ] +"327 +[; ;mcc_generated_files/adc.c: 327: ADREF = 0x00; +[e = _ADREF -> -> 0 `i `uc ] +"330 +[; ;mcc_generated_files/adc.c: 330: ADCSEL3 = 0x00; +[e = _ADCSEL3 -> -> 0 `i `uc ] +"335 +[; ;mcc_generated_files/adc.c: 335: ADCTX = 0x3; +[e = _ADCTX -> -> 3 `i `uc ] +"338 +[; ;mcc_generated_files/adc.c: 338: ADLTHL = 0x00; +[e = _ADLTHL -> -> 0 `i `uc ] +"341 +[; ;mcc_generated_files/adc.c: 341: ADLTHH = 0x00; +[e = _ADLTHH -> -> 0 `i `uc ] +"344 +[; ;mcc_generated_files/adc.c: 344: ADUTHL = 0x00; +[e = _ADUTHL -> -> 0 `i `uc ] +"347 +[; ;mcc_generated_files/adc.c: 347: ADUTHH = 0x00; +[e = _ADUTHH -> -> 0 `i `uc ] +"350 +[; ;mcc_generated_files/adc.c: 350: ADSTPTL = 0x00; +[e = _ADSTPTL -> -> 0 `i `uc ] +"353 +[; ;mcc_generated_files/adc.c: 353: ADSTPTH = 0x00; +[e = _ADSTPTH -> -> 0 `i `uc ] +"356 +[; ;mcc_generated_files/adc.c: 356: ADACCL = 0x00; +[e = _ADACCL -> -> 0 `i `uc ] +"359 +[; ;mcc_generated_files/adc.c: 359: ADACCH = 0x00; +[e = _ADACCH -> -> 0 `i `uc ] +"362 +[; ;mcc_generated_files/adc.c: 362: ADACCU = 0x00; +[e = _ADACCU -> -> 0 `i `uc ] +"365 +[; ;mcc_generated_files/adc.c: 365: ADCNT = 0x00; +[e = _ADCNT -> -> 0 `i `uc ] +"368 +[; ;mcc_generated_files/adc.c: 368: ADRPT = 0x00; +[e = _ADRPT -> -> 0 `i `uc ] +"371 +[; ;mcc_generated_files/adc.c: 371: ADRESL = 0x00; +[e = _ADRESL -> -> 0 `i `uc ] +"374 +[; ;mcc_generated_files/adc.c: 374: ADRESH = 0x00; +[e = _ADRESH -> -> 0 `i `uc ] +"377 +[; ;mcc_generated_files/adc.c: 377: ADPCH = 0x11; +[e = _ADPCH -> -> 17 `i `uc ] +"380 +[; ;mcc_generated_files/adc.c: 380: ADACQL = 0xE8; +[e = _ADACQL -> -> 232 `i `uc ] +"383 +[; ;mcc_generated_files/adc.c: 383: ADACQH = 0x03; +[e = _ADACQH -> -> 3 `i `uc ] +"386 +[; ;mcc_generated_files/adc.c: 386: ADCAP = 0x00; +[e = _ADCAP -> -> 0 `i `uc ] +"389 +[; ;mcc_generated_files/adc.c: 389: ADPREL = 0x00; +[e = _ADPREL -> -> 0 `i `uc ] +"392 +[; ;mcc_generated_files/adc.c: 392: ADPREH = 0x00; +[e = _ADPREH -> -> 0 `i `uc ] +"395 +[; ;mcc_generated_files/adc.c: 395: ADCON0 = 0x00; +[e = _ADCON0 -> -> 0 `i `uc ] +"398 +[; ;mcc_generated_files/adc.c: 398: ADCON1 = 0x00; +[e = _ADCON1 -> -> 0 `i `uc ] +"401 +[; ;mcc_generated_files/adc.c: 401: ADCON2 = 0x10; +[e = _ADCON2 -> -> 16 `i `uc ] +"404 +[; ;mcc_generated_files/adc.c: 404: ADCON3 = 0x00; +[e = _ADCON3 -> -> 0 `i `uc ] +"407 +[; ;mcc_generated_files/adc.c: 407: ADSTAT = 0x00; +[e = _ADSTAT -> -> 0 `i `uc ] +"410 +[; ;mcc_generated_files/adc.c: 410: ADREF = 0x00; +[e = _ADREF -> -> 0 `i `uc ] +"413 +[; ;mcc_generated_files/adc.c: 413: ADCSEL4 = 0x00; +[e = _ADCSEL4 -> -> 0 `i `uc ] +"416 +[; ;mcc_generated_files/adc.c: 416: PIR1bits.ADIF = 0; +[e = . . _PIR1bits 0 2 -> -> 0 `i `uc ] +"419 +[; ;mcc_generated_files/adc.c: 419: PIR1bits.ACTIF = 0; +[e = . . _PIR1bits 0 3 -> -> 0 `i `uc ] +"422 +[; ;mcc_generated_files/adc.c: 422: PIR2bits.ADCH1IF = 0; +[e = . . _PIR2bits 1 0 -> -> 0 `i `uc ] +"423 +[; ;mcc_generated_files/adc.c: 423: PIR2bits.ADCH2IF = 0; +[e = . . _PIR2bits 0 1 -> -> 0 `i `uc ] +"424 +[; ;mcc_generated_files/adc.c: 424: PIR2bits.ADCH3IF = 0; +[e = . . _PIR2bits 0 2 -> -> 0 `i `uc ] +"425 +[; ;mcc_generated_files/adc.c: 425: PIR2bits.ADCH4IF = 0; +[e = . . _PIR2bits 0 3 -> -> 0 `i `uc ] +"429 +[; ;mcc_generated_files/adc.c: 429: ADC_SetADIInterruptHandler(ADC_DefaultADI_ISR); +[e ( _ADC_SetADIInterruptHandler (1 &U _ADC_DefaultADI_ISR ] +"430 +[; ;mcc_generated_files/adc.c: 430: ADC_SetContext1ThresholdInterruptHandler(ADC_DefaultContext1Threshold_ISR); +[e ( _ADC_SetContext1ThresholdInterruptHandler (1 &U _ADC_DefaultContext1Threshold_ISR ] +"431 +[; ;mcc_generated_files/adc.c: 431: ADC_SetContext2ThresholdInterruptHandler(ADC_DefaultContext2Threshold_ISR); +[e ( _ADC_SetContext2ThresholdInterruptHandler (1 &U _ADC_DefaultContext2Threshold_ISR ] +"432 +[; ;mcc_generated_files/adc.c: 432: ADC_SetContext3ThresholdInterruptHandler(ADC_DefaultContext3Threshold_ISR); +[e ( _ADC_SetContext3ThresholdInterruptHandler (1 &U _ADC_DefaultContext3Threshold_ISR ] +"433 +[; ;mcc_generated_files/adc.c: 433: ADC_SetContext4ThresholdInterruptHandler(ADC_DefaultContext4Threshold_ISR); +[e ( _ADC_SetContext4ThresholdInterruptHandler (1 &U _ADC_DefaultContext4Threshold_ISR ] +"434 +[; ;mcc_generated_files/adc.c: 434: ADC_SetActiveClockTuningInterruptHandler(ADC_DefaultActiveClockTuning_ISR); +[e ( _ADC_SetActiveClockTuningInterruptHandler (1 &U _ADC_DefaultActiveClockTuning_ISR ] +"437 +[; ;mcc_generated_files/adc.c: 437: ADCON0 = 0x84; +[e = _ADCON0 -> -> 132 `i `uc ] +"438 +[; ;mcc_generated_files/adc.c: 438: } +[e :UE 3176 ] +} +[v F22276 `(v ~T0 @X0 1 tf ] +"440 +[; ;mcc_generated_files/adc.c: 440: __attribute__((inline)) void ADC_EnableChannelSequencer(void) +[v _ADC_EnableChannelSequencer `TF22276 ~T0 @X0 1 e ] +"441 +[; ;mcc_generated_files/adc.c: 441: { +{ +[e :U _ADC_EnableChannelSequencer ] +[f ] +"442 +[; ;mcc_generated_files/adc.c: 442: ADCON0bits.CSEN = 1; +[e = . . _ADCON0bits 0 4 -> -> 1 `i `uc ] +"443 +[; ;mcc_generated_files/adc.c: 443: } +[e :UE 3177 ] +} +[v F22278 `(v ~T0 @X0 1 tf ] +"445 +[; ;mcc_generated_files/adc.c: 445: __attribute__((inline)) void ADC_DisableChannelSequencer(void) +[v _ADC_DisableChannelSequencer `TF22278 ~T0 @X0 1 e ] +"446 +[; ;mcc_generated_files/adc.c: 446: { +{ +[e :U _ADC_DisableChannelSequencer ] +[f ] +"447 +[; ;mcc_generated_files/adc.c: 447: ADCON0bits.CSEN = 0; +[e = . . _ADCON0bits 0 4 -> -> 0 `i `uc ] +"448 +[; ;mcc_generated_files/adc.c: 448: } +[e :UE 3178 ] +} +[v F22280 `(v ~T0 @X0 1 tf ] +"450 +[; ;mcc_generated_files/adc.c: 450: __attribute__((inline)) void ADC_StartChannelSequencer(void) +[v _ADC_StartChannelSequencer `TF22280 ~T0 @X0 1 e ] +"451 +[; ;mcc_generated_files/adc.c: 451: { +{ +[e :U _ADC_StartChannelSequencer ] +[f ] +"452 +[; ;mcc_generated_files/adc.c: 452: ADCON0bits.GO = 1; +[e = . . _ADCON0bits 0 0 -> -> 1 `i `uc ] +"453 +[; ;mcc_generated_files/adc.c: 453: } +[e :UE 3179 ] +} +[v F22282 `(v ~T0 @X0 1 tf1`E22154 ] +"455 +[; ;mcc_generated_files/adc.c: 455: __attribute__((inline)) void ADC_SelectContext(ADC_context_t context) +[v _ADC_SelectContext `TF22282 ~T0 @X0 1 e ] +"456 +[; ;mcc_generated_files/adc.c: 456: { +{ +[e :U _ADC_SelectContext ] +"455 +[; ;mcc_generated_files/adc.c: 455: __attribute__((inline)) void ADC_SelectContext(ADC_context_t context) +[v _context `E22154 ~T0 @X0 1 r1 ] +"456 +[; ;mcc_generated_files/adc.c: 456: { +[f ] +"457 +[; ;mcc_generated_files/adc.c: 457: ADCTX = context; +[e = _ADCTX -> _context `uc ] +"458 +[; ;mcc_generated_files/adc.c: 458: } +[e :UE 3180 ] +} +"460 +[; ;mcc_generated_files/adc.c: 460: void ADC_EnableChannelScan(ADC_context_t context) +[v _ADC_EnableChannelScan `(v ~T0 @X0 1 ef1`E22154 ] +"461 +[; ;mcc_generated_files/adc.c: 461: { +{ +[e :U _ADC_EnableChannelScan ] +"460 +[; ;mcc_generated_files/adc.c: 460: void ADC_EnableChannelScan(ADC_context_t context) +[v _context `E22154 ~T0 @X0 1 r1 ] +"461 +[; ;mcc_generated_files/adc.c: 461: { +[f ] +"462 +[; ;mcc_generated_files/adc.c: 462: switch (context) +[e $U 3183 ] +"463 +[; ;mcc_generated_files/adc.c: 463: { +{ +"464 +[; ;mcc_generated_files/adc.c: 464: case CONTEXT_TPS1: +[e :U 3184 ] +"465 +[; ;mcc_generated_files/adc.c: 465: ADCSEL1bits.CHEN = 1; +[e = . . _ADCSEL1bits 0 2 -> -> 1 `i `uc ] +"466 +[; ;mcc_generated_files/adc.c: 466: break; +[e $U 3182 ] +"467 +[; ;mcc_generated_files/adc.c: 467: case CONTEXT_TPS2: +[e :U 3185 ] +"468 +[; ;mcc_generated_files/adc.c: 468: ADCSEL2bits.CHEN = 1; +[e = . . _ADCSEL2bits 0 2 -> -> 1 `i `uc ] +"469 +[; ;mcc_generated_files/adc.c: 469: break; +[e $U 3182 ] +"470 +[; ;mcc_generated_files/adc.c: 470: case CONTEXT_APPS1: +[e :U 3186 ] +"471 +[; ;mcc_generated_files/adc.c: 471: ADCSEL3bits.CHEN = 1; +[e = . . _ADCSEL3bits 0 2 -> -> 1 `i `uc ] +"472 +[; ;mcc_generated_files/adc.c: 472: break; +[e $U 3182 ] +"473 +[; ;mcc_generated_files/adc.c: 473: case CONTEXT_APPS2: +[e :U 3187 ] +"474 +[; ;mcc_generated_files/adc.c: 474: ADCSEL4bits.CHEN = 1; +[e = . . _ADCSEL4bits 0 2 -> -> 1 `i `uc ] +"475 +[; ;mcc_generated_files/adc.c: 475: break; +[e $U 3182 ] +"476 +[; ;mcc_generated_files/adc.c: 476: default: +[e :U 3188 ] +"477 +[; ;mcc_generated_files/adc.c: 477: break; +[e $U 3182 ] +"478 +[; ;mcc_generated_files/adc.c: 478: } +} +[e $U 3182 ] +[e :U 3183 ] +[e [\ -> _context `ui , $ -> . `E22154 0 `ui 3184 + , $ -> . `E22154 1 `ui 3185 + , $ -> . `E22154 2 `ui 3186 + , $ -> . `E22154 3 `ui 3187 + 3188 ] +[e :U 3182 ] +"479 +[; ;mcc_generated_files/adc.c: 479: } +[e :UE 3181 ] +} +"481 +[; ;mcc_generated_files/adc.c: 481: void ADC_DisableChannelScan(ADC_context_t context) +[v _ADC_DisableChannelScan `(v ~T0 @X0 1 ef1`E22154 ] +"482 +[; ;mcc_generated_files/adc.c: 482: { +{ +[e :U _ADC_DisableChannelScan ] +"481 +[; ;mcc_generated_files/adc.c: 481: void ADC_DisableChannelScan(ADC_context_t context) +[v _context `E22154 ~T0 @X0 1 r1 ] +"482 +[; ;mcc_generated_files/adc.c: 482: { +[f ] +"483 +[; ;mcc_generated_files/adc.c: 483: switch (context) +[e $U 3191 ] +"484 +[; ;mcc_generated_files/adc.c: 484: { +{ +"485 +[; ;mcc_generated_files/adc.c: 485: case CONTEXT_TPS1: +[e :U 3192 ] +"486 +[; ;mcc_generated_files/adc.c: 486: ADCSEL1bits.CHEN = 0; +[e = . . _ADCSEL1bits 0 2 -> -> 0 `i `uc ] +"487 +[; ;mcc_generated_files/adc.c: 487: break; +[e $U 3190 ] +"488 +[; ;mcc_generated_files/adc.c: 488: case CONTEXT_TPS2: +[e :U 3193 ] +"489 +[; ;mcc_generated_files/adc.c: 489: ADCSEL2bits.CHEN = 0; +[e = . . _ADCSEL2bits 0 2 -> -> 0 `i `uc ] +"490 +[; ;mcc_generated_files/adc.c: 490: break; +[e $U 3190 ] +"491 +[; ;mcc_generated_files/adc.c: 491: case CONTEXT_APPS1: +[e :U 3194 ] +"492 +[; ;mcc_generated_files/adc.c: 492: ADCSEL3bits.CHEN = 0; +[e = . . _ADCSEL3bits 0 2 -> -> 0 `i `uc ] +"493 +[; ;mcc_generated_files/adc.c: 493: break; +[e $U 3190 ] +"494 +[; ;mcc_generated_files/adc.c: 494: case CONTEXT_APPS2: +[e :U 3195 ] +"495 +[; ;mcc_generated_files/adc.c: 495: ADCSEL4bits.CHEN = 0; +[e = . . _ADCSEL4bits 0 2 -> -> 0 `i `uc ] +"496 +[; ;mcc_generated_files/adc.c: 496: break; +[e $U 3190 ] +"497 +[; ;mcc_generated_files/adc.c: 497: default: +[e :U 3196 ] +"498 +[; ;mcc_generated_files/adc.c: 498: break; +[e $U 3190 ] +"499 +[; ;mcc_generated_files/adc.c: 499: } +} +[e $U 3190 ] +[e :U 3191 ] +[e [\ -> _context `ui , $ -> . `E22154 0 `ui 3192 + , $ -> . `E22154 1 `ui 3193 + , $ -> . `E22154 2 `ui 3194 + , $ -> . `E22154 3 `ui 3195 + 3196 ] +[e :U 3190 ] +"500 +[; ;mcc_generated_files/adc.c: 500: } +[e :UE 3189 ] +} +"502 +[; ;mcc_generated_files/adc.c: 502: void ADC_StartConversion(ADC_channel_t channel) +[v _ADC_StartConversion `(v ~T0 @X0 1 ef1`E22143 ] +"503 +[; ;mcc_generated_files/adc.c: 503: { +{ +[e :U _ADC_StartConversion ] +"502 +[; ;mcc_generated_files/adc.c: 502: void ADC_StartConversion(ADC_channel_t channel) +[v _channel `E22143 ~T0 @X0 1 r1 ] +"503 +[; ;mcc_generated_files/adc.c: 503: { +[f ] +"505 +[; ;mcc_generated_files/adc.c: 505: ADPCH = channel; +[e = _ADPCH -> _channel `uc ] +"508 +[; ;mcc_generated_files/adc.c: 508: ADCON0bits.ON = 1; +[e = . . _ADCON0bits 0 6 -> -> 1 `i `uc ] +"511 +[; ;mcc_generated_files/adc.c: 511: ADCON0bits.GO = 1; +[e = . . _ADCON0bits 0 0 -> -> 1 `i `uc ] +"512 +[; ;mcc_generated_files/adc.c: 512: } +[e :UE 3197 ] +} +"514 +[; ;mcc_generated_files/adc.c: 514: _Bool ADC_IsConversionDone(void) +[v _ADC_IsConversionDone `(a ~T0 @X0 1 ef ] +"515 +[; ;mcc_generated_files/adc.c: 515: { +{ +[e :U _ADC_IsConversionDone ] +[f ] +"516 +[; ;mcc_generated_files/adc.c: 516: return (_Bool) (!ADCON0bits.GO); +[e ) -> -> ! != -> . . _ADCON0bits 0 0 `i -> 0 `i `i `a ] +[e $UE 3198 ] +"517 +[; ;mcc_generated_files/adc.c: 517: } +[e :UE 3198 ] +} +"519 +[; ;mcc_generated_files/adc.c: 519: adc_result_t ADC_GetConversionResult(void) +[v _ADC_GetConversionResult `(us ~T0 @X0 1 ef ] +"520 +[; ;mcc_generated_files/adc.c: 520: { +{ +[e :U _ADC_GetConversionResult ] +[f ] +"522 +[; ;mcc_generated_files/adc.c: 522: return ((adc_result_t) ((ADRESH << 8) + ADRESL)); +[e ) -> + << -> _ADRESH `i -> 8 `i -> _ADRESL `i `us ] +[e $UE 3199 ] +"523 +[; ;mcc_generated_files/adc.c: 523: } +[e :UE 3199 ] +} +"525 +[; ;mcc_generated_files/adc.c: 525: adc_result_t ADC_GetSingleConversion(ADC_channel_t channel) +[v _ADC_GetSingleConversion `(us ~T0 @X0 1 ef1`E22143 ] +"526 +[; ;mcc_generated_files/adc.c: 526: { +{ +[e :U _ADC_GetSingleConversion ] +"525 +[; ;mcc_generated_files/adc.c: 525: adc_result_t ADC_GetSingleConversion(ADC_channel_t channel) +[v _channel `E22143 ~T0 @X0 1 r1 ] +"526 +[; ;mcc_generated_files/adc.c: 526: { +[f ] +"528 +[; ;mcc_generated_files/adc.c: 528: ADPCH = channel; +[e = _ADPCH -> _channel `uc ] +"531 +[; ;mcc_generated_files/adc.c: 531: ADCON0bits.ON = 1; +[e = . . _ADCON0bits 0 6 -> -> 1 `i `uc ] +"534 +[; ;mcc_generated_files/adc.c: 534: ADCON0bits.CONT = 0; +[e = . . _ADCON0bits 0 5 -> -> 0 `i `uc ] +"537 +[; ;mcc_generated_files/adc.c: 537: ADCON0bits.GO = 1; +[e = . . _ADCON0bits 0 0 -> -> 1 `i `uc ] +"540 +[; ;mcc_generated_files/adc.c: 540: while(ADCON0bits.GO) +[e $U 3201 ] +[e :U 3202 ] +"541 +[; ;mcc_generated_files/adc.c: 541: { +{ +"543 +[; ;mcc_generated_files/adc.c: 543: } +} +[e :U 3201 ] +"540 +[; ;mcc_generated_files/adc.c: 540: while(ADCON0bits.GO) +[e $ != -> . . _ADCON0bits 0 0 `i -> 0 `i 3202 ] +[e :U 3203 ] +"545 +[; ;mcc_generated_files/adc.c: 545: return ((adc_result_t) ((ADRESH << 8) + ADRESL)); +[e ) -> + << -> _ADRESH `i -> 8 `i -> _ADRESL `i `us ] +[e $UE 3200 ] +"546 +[; ;mcc_generated_files/adc.c: 546: } +[e :UE 3200 ] +} +[v F22295 `(v ~T0 @X0 1 tf ] +"548 +[; ;mcc_generated_files/adc.c: 548: __attribute__((inline)) void ADC_StopConversion(void) +[v _ADC_StopConversion `TF22295 ~T0 @X0 1 e ] +"549 +[; ;mcc_generated_files/adc.c: 549: { +{ +[e :U _ADC_StopConversion ] +[f ] +"551 +[; ;mcc_generated_files/adc.c: 551: ADCON0bits.GO = 0; +[e = . . _ADCON0bits 0 0 -> -> 0 `i `uc ] +"552 +[; ;mcc_generated_files/adc.c: 552: } +[e :UE 3204 ] +} +[v F22297 `(v ~T0 @X0 1 tf ] +"554 +[; ;mcc_generated_files/adc.c: 554: __attribute__((inline)) void ADC_SetStopOnInterrupt(void) +[v _ADC_SetStopOnInterrupt `TF22297 ~T0 @X0 1 e ] +"555 +[; ;mcc_generated_files/adc.c: 555: { +{ +[e :U _ADC_SetStopOnInterrupt ] +[f ] +"556 +[; ;mcc_generated_files/adc.c: 556: ADCON3bits.SOI = 1; +[e = . . _ADCON3bits 0 1 -> -> 1 `i `uc ] +"557 +[; ;mcc_generated_files/adc.c: 557: } +[e :UE 3205 ] +} +[v F22299 `(v ~T0 @X0 1 tf ] +"559 +[; ;mcc_generated_files/adc.c: 559: __attribute__((inline)) void ADC_DischargeSampleCapacitor(void) +[v _ADC_DischargeSampleCapacitor `TF22299 ~T0 @X0 1 e ] +"560 +[; ;mcc_generated_files/adc.c: 560: { +{ +[e :U _ADC_DischargeSampleCapacitor ] +[f ] +"562 +[; ;mcc_generated_files/adc.c: 562: ADPCH = 0x3b; +[e = _ADPCH -> -> 59 `i `uc ] +"563 +[; ;mcc_generated_files/adc.c: 563: } +[e :UE 3206 ] +} +"565 +[; ;mcc_generated_files/adc.c: 565: void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue) +[v _ADC_LoadAcquisitionRegister `(v ~T0 @X0 1 ef1`us ] +"566 +[; ;mcc_generated_files/adc.c: 566: { +{ +[e :U _ADC_LoadAcquisitionRegister ] +"565 +[; ;mcc_generated_files/adc.c: 565: void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue) +[v _acquisitionValue `us ~T0 @X0 1 r1 ] +"566 +[; ;mcc_generated_files/adc.c: 566: { +[f ] +"567 +[; ;mcc_generated_files/adc.c: 567: ADACQH = acquisitionValue >> 8; +[e = _ADACQH -> >> -> _acquisitionValue `ui -> 8 `i `uc ] +"568 +[; ;mcc_generated_files/adc.c: 568: ADACQL = acquisitionValue; +[e = _ADACQL -> _acquisitionValue `uc ] +"569 +[; ;mcc_generated_files/adc.c: 569: } +[e :UE 3207 ] +} +"571 +[; ;mcc_generated_files/adc.c: 571: void ADC_SetPrechargeTime(uint16_t prechargeTime) +[v _ADC_SetPrechargeTime `(v ~T0 @X0 1 ef1`us ] +"572 +[; ;mcc_generated_files/adc.c: 572: { +{ +[e :U _ADC_SetPrechargeTime ] +"571 +[; ;mcc_generated_files/adc.c: 571: void ADC_SetPrechargeTime(uint16_t prechargeTime) +[v _prechargeTime `us ~T0 @X0 1 r1 ] +"572 +[; ;mcc_generated_files/adc.c: 572: { +[f ] +"573 +[; ;mcc_generated_files/adc.c: 573: ADPREH = prechargeTime >> 8; +[e = _ADPREH -> >> -> _prechargeTime `ui -> 8 `i `uc ] +"574 +[; ;mcc_generated_files/adc.c: 574: ADPREL = prechargeTime; +[e = _ADPREL -> _prechargeTime `uc ] +"575 +[; ;mcc_generated_files/adc.c: 575: } +[e :UE 3208 ] +} +[v F22305 `(v ~T0 @X0 1 tf1`uc ] +"577 +[; ;mcc_generated_files/adc.c: 577: __attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount) +[v _ADC_SetRepeatCount `TF22305 ~T0 @X0 1 e ] +"578 +[; ;mcc_generated_files/adc.c: 578: { +{ +[e :U _ADC_SetRepeatCount ] +"577 +[; ;mcc_generated_files/adc.c: 577: __attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount) +[v _repeatCount `uc ~T0 @X0 1 r1 ] +"578 +[; ;mcc_generated_files/adc.c: 578: { +[f ] +"579 +[; ;mcc_generated_files/adc.c: 579: ADRPT = repeatCount; +[e = _ADRPT _repeatCount ] +"580 +[; ;mcc_generated_files/adc.c: 580: } +[e :UE 3209 ] +} +"582 +[; ;mcc_generated_files/adc.c: 582: uint8_t ADC_GetCurrentCountofConversions(void) +[v _ADC_GetCurrentCountofConversions `(uc ~T0 @X0 1 ef ] +"583 +[; ;mcc_generated_files/adc.c: 583: { +{ +[e :U _ADC_GetCurrentCountofConversions ] +[f ] +"584 +[; ;mcc_generated_files/adc.c: 584: return ADCNT; +[e ) _ADCNT ] +[e $UE 3210 ] +"585 +[; ;mcc_generated_files/adc.c: 585: } +[e :UE 3210 ] +} +[v F22309 `(v ~T0 @X0 1 tf ] +"587 +[; ;mcc_generated_files/adc.c: 587: __attribute__((inline)) void ADC_ClearAccumulator(void) +[v _ADC_ClearAccumulator `TF22309 ~T0 @X0 1 e ] +"588 +[; ;mcc_generated_files/adc.c: 588: { +{ +[e :U _ADC_ClearAccumulator ] +[f ] +"589 +[; ;mcc_generated_files/adc.c: 589: ADCON2bits.ACLR = 1; +[e = . . _ADCON2bits 0 1 -> -> 1 `i `uc ] +"590 +[; ;mcc_generated_files/adc.c: 590: } +[e :UE 3211 ] +} +"592 +[; ;mcc_generated_files/adc.c: 592: uint24_t ADC_GetAccumulatorValue(void) +[v _ADC_GetAccumulatorValue `(um ~T0 @X0 1 ef ] +"593 +[; ;mcc_generated_files/adc.c: 593: { +{ +[e :U _ADC_GetAccumulatorValue ] +[f ] +"594 +[; ;mcc_generated_files/adc.c: 594: return ((uint24_t) ((ADACCH << 8) + ADACCL)); +[e ) -> + << -> _ADACCH `i -> 8 `i -> _ADACCL `i `um ] +[e $UE 3212 ] +"595 +[; ;mcc_generated_files/adc.c: 595: } +[e :UE 3212 ] +} +"597 +[; ;mcc_generated_files/adc.c: 597: _Bool ADC_HasAccumulatorOverflowed(void) +[v _ADC_HasAccumulatorOverflowed `(a ~T0 @X0 1 ef ] +"598 +[; ;mcc_generated_files/adc.c: 598: { +{ +[e :U _ADC_HasAccumulatorOverflowed ] +[f ] +"599 +[; ;mcc_generated_files/adc.c: 599: return ADSTATbits.ADAOV; +[e ) -> . . _ADSTATbits 1 7 `a ] +[e $UE 3213 ] +"600 +[; ;mcc_generated_files/adc.c: 600: } +[e :UE 3213 ] +} +"602 +[; ;mcc_generated_files/adc.c: 602: uint16_t ADC_GetFilterValue(void) +[v _ADC_GetFilterValue `(us ~T0 @X0 1 ef ] +"603 +[; ;mcc_generated_files/adc.c: 603: { +{ +[e :U _ADC_GetFilterValue ] +[f ] +"604 +[; ;mcc_generated_files/adc.c: 604: return ((uint16_t) ((ADFLTRH << 8) + ADFLTRL)); +[e ) -> + << -> _ADFLTRH `i -> 8 `i -> _ADFLTRL `i `us ] +[e $UE 3214 ] +"605 +[; ;mcc_generated_files/adc.c: 605: } +[e :UE 3214 ] +} +"607 +[; ;mcc_generated_files/adc.c: 607: uint16_t ADC_GetPreviousResult(void) +[v _ADC_GetPreviousResult `(us ~T0 @X0 1 ef ] +"608 +[; ;mcc_generated_files/adc.c: 608: { +{ +[e :U _ADC_GetPreviousResult ] +[f ] +"609 +[; ;mcc_generated_files/adc.c: 609: return ((uint16_t) ((ADPREVH << 8) + ADPREVL)); +[e ) -> + << -> _ADPREVH `i -> 8 `i -> _ADPREVL `i `us ] +[e $UE 3215 ] +"610 +[; ;mcc_generated_files/adc.c: 610: } +[e :UE 3215 ] +} +"612 +[; ;mcc_generated_files/adc.c: 612: void ADC_DefineSetPoint(uint16_t setPoint) +[v _ADC_DefineSetPoint `(v ~T0 @X0 1 ef1`us ] +"613 +[; ;mcc_generated_files/adc.c: 613: { +{ +[e :U _ADC_DefineSetPoint ] +"612 +[; ;mcc_generated_files/adc.c: 612: void ADC_DefineSetPoint(uint16_t setPoint) +[v _setPoint `us ~T0 @X0 1 r1 ] +"613 +[; ;mcc_generated_files/adc.c: 613: { +[f ] +"614 +[; ;mcc_generated_files/adc.c: 614: ADSTPTH = setPoint >> 8; +[e = _ADSTPTH -> >> -> _setPoint `ui -> 8 `i `uc ] +"615 +[; ;mcc_generated_files/adc.c: 615: ADSTPTL = setPoint; +[e = _ADSTPTL -> _setPoint `uc ] +"616 +[; ;mcc_generated_files/adc.c: 616: } +[e :UE 3216 ] +} +"618 +[; ;mcc_generated_files/adc.c: 618: void ADC_SetUpperThreshold(uint16_t upperThreshold) +[v _ADC_SetUpperThreshold `(v ~T0 @X0 1 ef1`us ] +"619 +[; ;mcc_generated_files/adc.c: 619: { +{ +[e :U _ADC_SetUpperThreshold ] +"618 +[; ;mcc_generated_files/adc.c: 618: void ADC_SetUpperThreshold(uint16_t upperThreshold) +[v _upperThreshold `us ~T0 @X0 1 r1 ] +"619 +[; ;mcc_generated_files/adc.c: 619: { +[f ] +"620 +[; ;mcc_generated_files/adc.c: 620: ADUTHH = upperThreshold >> 8; +[e = _ADUTHH -> >> -> _upperThreshold `ui -> 8 `i `uc ] +"621 +[; ;mcc_generated_files/adc.c: 621: ADUTHL = upperThreshold; +[e = _ADUTHL -> _upperThreshold `uc ] +"622 +[; ;mcc_generated_files/adc.c: 622: } +[e :UE 3217 ] +} +"624 +[; ;mcc_generated_files/adc.c: 624: void ADC_SetLowerThreshold(uint16_t lowerThreshold) +[v _ADC_SetLowerThreshold `(v ~T0 @X0 1 ef1`us ] +"625 +[; ;mcc_generated_files/adc.c: 625: { +{ +[e :U _ADC_SetLowerThreshold ] +"624 +[; ;mcc_generated_files/adc.c: 624: void ADC_SetLowerThreshold(uint16_t lowerThreshold) +[v _lowerThreshold `us ~T0 @X0 1 r1 ] +"625 +[; ;mcc_generated_files/adc.c: 625: { +[f ] +"626 +[; ;mcc_generated_files/adc.c: 626: ADLTHH = lowerThreshold >> 8; +[e = _ADLTHH -> >> -> _lowerThreshold `ui -> 8 `i `uc ] +"627 +[; ;mcc_generated_files/adc.c: 627: ADLTHL = lowerThreshold; +[e = _ADLTHL -> _lowerThreshold `uc ] +"628 +[; ;mcc_generated_files/adc.c: 628: } +[e :UE 3218 ] +} +"630 +[; ;mcc_generated_files/adc.c: 630: uint16_t ADC_GetErrorCalculation(void) +[v _ADC_GetErrorCalculation `(us ~T0 @X0 1 ef ] +"631 +[; ;mcc_generated_files/adc.c: 631: { +{ +[e :U _ADC_GetErrorCalculation ] +[f ] +"632 +[; ;mcc_generated_files/adc.c: 632: return ((uint16_t) ((ADERRH << 8) + ADERRL)); +[e ) -> + << -> _ADERRH `i -> 8 `i -> _ADERRL `i `us ] +[e $UE 3219 ] +"633 +[; ;mcc_generated_files/adc.c: 633: } +[e :UE 3219 ] +} +[v F22322 `(v ~T0 @X0 1 tf ] +"635 +[; ;mcc_generated_files/adc.c: 635: __attribute__((inline)) void ADC_EnableDoubleSampling(void) +[v _ADC_EnableDoubleSampling `TF22322 ~T0 @X0 1 e ] +"636 +[; ;mcc_generated_files/adc.c: 636: { +{ +[e :U _ADC_EnableDoubleSampling ] +[f ] +"637 +[; ;mcc_generated_files/adc.c: 637: ADCON1bits.DSEN = 1; +[e = . . _ADCON1bits 0 0 -> -> 1 `i `uc ] +"638 +[; ;mcc_generated_files/adc.c: 638: } +[e :UE 3220 ] +} +[v F22324 `(v ~T0 @X0 1 tf ] +"640 +[; ;mcc_generated_files/adc.c: 640: __attribute__((inline)) void ADC_EnableContinuousConversion(void) +[v _ADC_EnableContinuousConversion `TF22324 ~T0 @X0 1 e ] +"641 +[; ;mcc_generated_files/adc.c: 641: { +{ +[e :U _ADC_EnableContinuousConversion ] +[f ] +"642 +[; ;mcc_generated_files/adc.c: 642: ADCON0bits.CONT = 1; +[e = . . _ADCON0bits 0 5 -> -> 1 `i `uc ] +"643 +[; ;mcc_generated_files/adc.c: 643: } +[e :UE 3221 ] +} +[v F22326 `(v ~T0 @X0 1 tf ] +"645 +[; ;mcc_generated_files/adc.c: 645: __attribute__((inline)) void ADC_DisableContinuousConversion(void) +[v _ADC_DisableContinuousConversion `TF22326 ~T0 @X0 1 e ] +"646 +[; ;mcc_generated_files/adc.c: 646: { +{ +[e :U _ADC_DisableContinuousConversion ] +[f ] +"647 +[; ;mcc_generated_files/adc.c: 647: ADCON0bits.CONT = 0; +[e = . . _ADCON0bits 0 5 -> -> 0 `i `uc ] +"648 +[; ;mcc_generated_files/adc.c: 648: } +[e :UE 3222 ] +} +"650 +[; ;mcc_generated_files/adc.c: 650: _Bool ADC_HasErrorCrossedUpperThreshold(void) +[v _ADC_HasErrorCrossedUpperThreshold `(a ~T0 @X0 1 ef ] +"651 +[; ;mcc_generated_files/adc.c: 651: { +{ +[e :U _ADC_HasErrorCrossedUpperThreshold ] +[f ] +"652 +[; ;mcc_generated_files/adc.c: 652: return ADSTATbits.ADUTHR; +[e ) -> . . _ADSTATbits 1 6 `a ] +[e $UE 3223 ] +"653 +[; ;mcc_generated_files/adc.c: 653: } +[e :UE 3223 ] +} +"655 +[; ;mcc_generated_files/adc.c: 655: _Bool ADC_HasErrorCrossedLowerThreshold(void) +[v _ADC_HasErrorCrossedLowerThreshold `(a ~T0 @X0 1 ef ] +"656 +[; ;mcc_generated_files/adc.c: 656: { +{ +[e :U _ADC_HasErrorCrossedLowerThreshold ] +[f ] +"657 +[; ;mcc_generated_files/adc.c: 657: return ADSTATbits.ADLTHR; +[e ) -> . . _ADSTATbits 1 5 `a ] +[e $UE 3224 ] +"658 +[; ;mcc_generated_files/adc.c: 658: } +[e :UE 3224 ] +} +"660 +[; ;mcc_generated_files/adc.c: 660: uint8_t ADC_GetConversionStageStatus(void) +[v _ADC_GetConversionStageStatus `(uc ~T0 @X0 1 ef ] +"661 +[; ;mcc_generated_files/adc.c: 661: { +{ +[e :U _ADC_GetConversionStageStatus ] +[f ] +"662 +[; ;mcc_generated_files/adc.c: 662: return ADSTATbits.ADSTAT; +[e ) . . _ADSTATbits 2 0 ] +[e $UE 3225 ] +"663 +[; ;mcc_generated_files/adc.c: 663: } +[e :UE 3225 ] +} +[v F22331 `(v ~T0 @X0 1 tf ] +"665 +[; ;mcc_generated_files/adc.c: 665: __attribute__((inline)) void ADC_EnableChargePump(void) +[v _ADC_EnableChargePump `TF22331 ~T0 @X0 1 e ] +"666 +[; ;mcc_generated_files/adc.c: 666: { +{ +[e :U _ADC_EnableChargePump ] +[f ] +"667 +[; ;mcc_generated_files/adc.c: 667: ADCPbits.CPON = 1; +[e = . . _ADCPbits 1 2 -> -> 1 `i `uc ] +"668 +[; ;mcc_generated_files/adc.c: 668: } +[e :UE 3226 ] +} +[v F22333 `(v ~T0 @X0 1 tf ] +"670 +[; ;mcc_generated_files/adc.c: 670: __attribute__((inline)) void ADC_DisableChargePump(void) +[v _ADC_DisableChargePump `TF22333 ~T0 @X0 1 e ] +"671 +[; ;mcc_generated_files/adc.c: 671: { +{ +[e :U _ADC_DisableChargePump ] +[f ] +"672 +[; ;mcc_generated_files/adc.c: 672: ADCPbits.CPON = 0; +[e = . . _ADCPbits 1 2 -> -> 0 `i `uc ] +"673 +[; ;mcc_generated_files/adc.c: 673: } +[e :UE 3227 ] +} +"675 +[; ;mcc_generated_files/adc.c: 675: void ADC_ADI_ISR(void) +[v _ADC_ADI_ISR `(v ~T0 @X0 1 ef ] +"676 +[; ;mcc_generated_files/adc.c: 676: { +{ +[e :U _ADC_ADI_ISR ] +[f ] +"677 +[; ;mcc_generated_files/adc.c: 677: PIR1bits.ADIF = 0; +[e = . . _PIR1bits 0 2 -> -> 0 `i `uc ] +"678 +[; ;mcc_generated_files/adc.c: 678: if (ADC_ConversionComplete_ISR != ((void*)0)) +[e $ ! != _ADC_ConversionComplete_ISR -> -> -> 0 `i `*v `*F22335 3229 ] +"679 +[; ;mcc_generated_files/adc.c: 679: ADC_ConversionComplete_ISR(); +[e ( *U _ADC_ConversionComplete_ISR .. ] +[e :U 3229 ] +"680 +[; ;mcc_generated_files/adc.c: 680: } +[e :UE 3228 ] +} +"682 +[; ;mcc_generated_files/adc.c: 682: void ADC_ACTI_ISR(void) +[v _ADC_ACTI_ISR `(v ~T0 @X0 1 ef ] +"683 +[; ;mcc_generated_files/adc.c: 683: { +{ +[e :U _ADC_ACTI_ISR ] +[f ] +"684 +[; ;mcc_generated_files/adc.c: 684: PIR1bits.ACTIF = 0; +[e = . . _PIR1bits 0 3 -> -> 0 `i `uc ] +"685 +[; ;mcc_generated_files/adc.c: 685: if (ADC_ActiveClockTuning_ISR != ((void*)0)) +[e $ ! != _ADC_ActiveClockTuning_ISR -> -> -> 0 `i `*v `*F22337 3231 ] +"686 +[; ;mcc_generated_files/adc.c: 686: ADC_ActiveClockTuning_ISR(); +[e ( *U _ADC_ActiveClockTuning_ISR .. ] +[e :U 3231 ] +"687 +[; ;mcc_generated_files/adc.c: 687: } +[e :UE 3230 ] +} +"690 +[; ;mcc_generated_files/adc.c: 690: void ADC_ADCH1_ISR(void) +[v _ADC_ADCH1_ISR `(v ~T0 @X0 1 ef ] +"691 +[; ;mcc_generated_files/adc.c: 691: { +{ +[e :U _ADC_ADCH1_ISR ] +[f ] +"692 +[; ;mcc_generated_files/adc.c: 692: PIR2bits.ADCH1IF = 0; +[e = . . _PIR2bits 1 0 -> -> 0 `i `uc ] +"693 +[; ;mcc_generated_files/adc.c: 693: if (ADC_Context1Thereshld_ISR != ((void*)0)) +[e $ ! != _ADC_Context1Thereshld_ISR -> -> -> 0 `i `*v `*F22339 3233 ] +"694 +[; ;mcc_generated_files/adc.c: 694: ADC_Context1Thereshld_ISR(); +[e ( *U _ADC_Context1Thereshld_ISR .. ] +[e :U 3233 ] +"695 +[; ;mcc_generated_files/adc.c: 695: } +[e :UE 3232 ] +} +"697 +[; ;mcc_generated_files/adc.c: 697: void ADC_ADCH2_ISR(void) +[v _ADC_ADCH2_ISR `(v ~T0 @X0 1 ef ] +"698 +[; ;mcc_generated_files/adc.c: 698: { +{ +[e :U _ADC_ADCH2_ISR ] +[f ] +"699 +[; ;mcc_generated_files/adc.c: 699: PIR2bits.ADCH2IF = 0; +[e = . . _PIR2bits 0 1 -> -> 0 `i `uc ] +"700 +[; ;mcc_generated_files/adc.c: 700: if (ADC_Context2Thereshld_ISR != ((void*)0)) +[e $ ! != _ADC_Context2Thereshld_ISR -> -> -> 0 `i `*v `*F22341 3235 ] +"701 +[; ;mcc_generated_files/adc.c: 701: ADC_Context2Thereshld_ISR(); +[e ( *U _ADC_Context2Thereshld_ISR .. ] +[e :U 3235 ] +"702 +[; ;mcc_generated_files/adc.c: 702: } +[e :UE 3234 ] +} +"704 +[; ;mcc_generated_files/adc.c: 704: void ADC_ADCH3_ISR(void) +[v _ADC_ADCH3_ISR `(v ~T0 @X0 1 ef ] +"705 +[; ;mcc_generated_files/adc.c: 705: { +{ +[e :U _ADC_ADCH3_ISR ] +[f ] +"706 +[; ;mcc_generated_files/adc.c: 706: PIR2bits.ADCH3IF = 0; +[e = . . _PIR2bits 0 2 -> -> 0 `i `uc ] +"707 +[; ;mcc_generated_files/adc.c: 707: if (ADC_Context3Thereshld_ISR != ((void*)0)) +[e $ ! != _ADC_Context3Thereshld_ISR -> -> -> 0 `i `*v `*F22343 3237 ] +"708 +[; ;mcc_generated_files/adc.c: 708: ADC_Context3Thereshld_ISR(); +[e ( *U _ADC_Context3Thereshld_ISR .. ] +[e :U 3237 ] +"709 +[; ;mcc_generated_files/adc.c: 709: } +[e :UE 3236 ] +} +"711 +[; ;mcc_generated_files/adc.c: 711: void ADC_ADCH4_ISR(void) +[v _ADC_ADCH4_ISR `(v ~T0 @X0 1 ef ] +"712 +[; ;mcc_generated_files/adc.c: 712: { +{ +[e :U _ADC_ADCH4_ISR ] +[f ] +"713 +[; ;mcc_generated_files/adc.c: 713: PIR2bits.ADCH4IF = 0; +[e = . . _PIR2bits 0 3 -> -> 0 `i `uc ] +"714 +[; ;mcc_generated_files/adc.c: 714: if (ADC_Context4Thereshld_ISR != ((void*)0)) +[e $ ! != _ADC_Context4Thereshld_ISR -> -> -> 0 `i `*v `*F22345 3239 ] +"715 +[; ;mcc_generated_files/adc.c: 715: ADC_Context4Thereshld_ISR(); +[e ( *U _ADC_Context4Thereshld_ISR .. ] +[e :U 3239 ] +"716 +[; ;mcc_generated_files/adc.c: 716: } +[e :UE 3238 ] +} +"718 +[; ;mcc_generated_files/adc.c: 718: void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)) +[v _ADC_SetADIInterruptHandler `(v ~T0 @X0 1 ef1`*F22347 ] +"719 +[; ;mcc_generated_files/adc.c: 719: { +{ +[e :U _ADC_SetADIInterruptHandler ] +"718 +[; ;mcc_generated_files/adc.c: 718: void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22349 ~T0 @X0 1 r1 ] +"719 +[; ;mcc_generated_files/adc.c: 719: { +[f ] +"720 +[; ;mcc_generated_files/adc.c: 720: ADC_ConversionComplete_ISR = InterruptHandler; +[e = _ADC_ConversionComplete_ISR _InterruptHandler ] +"721 +[; ;mcc_generated_files/adc.c: 721: } +[e :UE 3240 ] +} +"723 +[; ;mcc_generated_files/adc.c: 723: void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)) +[v _ADC_SetContext1ThresholdInterruptHandler `(v ~T0 @X0 1 ef1`*F22352 ] +"724 +[; ;mcc_generated_files/adc.c: 724: { +{ +[e :U _ADC_SetContext1ThresholdInterruptHandler ] +"723 +[; ;mcc_generated_files/adc.c: 723: void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22354 ~T0 @X0 1 r1 ] +"724 +[; ;mcc_generated_files/adc.c: 724: { +[f ] +"725 +[; ;mcc_generated_files/adc.c: 725: ADC_Context1Thereshld_ISR = InterruptHandler; +[e = _ADC_Context1Thereshld_ISR _InterruptHandler ] +"726 +[; ;mcc_generated_files/adc.c: 726: } +[e :UE 3241 ] +} +"728 +[; ;mcc_generated_files/adc.c: 728: void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)) +[v _ADC_SetContext2ThresholdInterruptHandler `(v ~T0 @X0 1 ef1`*F22357 ] +"729 +[; ;mcc_generated_files/adc.c: 729: { +{ +[e :U _ADC_SetContext2ThresholdInterruptHandler ] +"728 +[; ;mcc_generated_files/adc.c: 728: void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22359 ~T0 @X0 1 r1 ] +"729 +[; ;mcc_generated_files/adc.c: 729: { +[f ] +"730 +[; ;mcc_generated_files/adc.c: 730: ADC_Context2Thereshld_ISR = InterruptHandler; +[e = _ADC_Context2Thereshld_ISR _InterruptHandler ] +"731 +[; ;mcc_generated_files/adc.c: 731: } +[e :UE 3242 ] +} +"733 +[; ;mcc_generated_files/adc.c: 733: void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)) +[v _ADC_SetContext3ThresholdInterruptHandler `(v ~T0 @X0 1 ef1`*F22362 ] +"734 +[; ;mcc_generated_files/adc.c: 734: { +{ +[e :U _ADC_SetContext3ThresholdInterruptHandler ] +"733 +[; ;mcc_generated_files/adc.c: 733: void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22364 ~T0 @X0 1 r1 ] +"734 +[; ;mcc_generated_files/adc.c: 734: { +[f ] +"735 +[; ;mcc_generated_files/adc.c: 735: ADC_Context3Thereshld_ISR = InterruptHandler; +[e = _ADC_Context3Thereshld_ISR _InterruptHandler ] +"736 +[; ;mcc_generated_files/adc.c: 736: } +[e :UE 3243 ] +} +"738 +[; ;mcc_generated_files/adc.c: 738: void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)) +[v _ADC_SetContext4ThresholdInterruptHandler `(v ~T0 @X0 1 ef1`*F22367 ] +"739 +[; ;mcc_generated_files/adc.c: 739: { +{ +[e :U _ADC_SetContext4ThresholdInterruptHandler ] +"738 +[; ;mcc_generated_files/adc.c: 738: void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22369 ~T0 @X0 1 r1 ] +"739 +[; ;mcc_generated_files/adc.c: 739: { +[f ] +"740 +[; ;mcc_generated_files/adc.c: 740: ADC_Context4Thereshld_ISR = InterruptHandler; +[e = _ADC_Context4Thereshld_ISR _InterruptHandler ] +"741 +[; ;mcc_generated_files/adc.c: 741: } +[e :UE 3244 ] +} +"743 +[; ;mcc_generated_files/adc.c: 743: void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)) +[v _ADC_SetActiveClockTuningInterruptHandler `(v ~T0 @X0 1 ef1`*F22372 ] +"744 +[; ;mcc_generated_files/adc.c: 744: { +{ +[e :U _ADC_SetActiveClockTuningInterruptHandler ] +"743 +[; ;mcc_generated_files/adc.c: 743: void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22374 ~T0 @X0 1 r1 ] +"744 +[; ;mcc_generated_files/adc.c: 744: { +[f ] +"745 +[; ;mcc_generated_files/adc.c: 745: ADC_ActiveClockTuning_ISR = InterruptHandler; +[e = _ADC_ActiveClockTuning_ISR _InterruptHandler ] +"746 +[; ;mcc_generated_files/adc.c: 746: } +[e :UE 3245 ] +} +"748 +[; ;mcc_generated_files/adc.c: 748: static void ADC_DefaultADI_ISR(void) +[v _ADC_DefaultADI_ISR `(v ~T0 @X0 1 sf ] +"749 +[; ;mcc_generated_files/adc.c: 749: { +{ +[e :U _ADC_DefaultADI_ISR ] +[f ] +"752 +[; ;mcc_generated_files/adc.c: 752: } +[e :UE 3246 ] +} +"755 +[; ;mcc_generated_files/adc.c: 755: static void ADC_DefaultContext1Threshold_ISR(void) +[v _ADC_DefaultContext1Threshold_ISR `(v ~T0 @X0 1 sf ] +"756 +[; ;mcc_generated_files/adc.c: 756: { +{ +[e :U _ADC_DefaultContext1Threshold_ISR ] +[f ] +"759 +[; ;mcc_generated_files/adc.c: 759: } +[e :UE 3247 ] +} +"761 +[; ;mcc_generated_files/adc.c: 761: static void ADC_DefaultContext2Threshold_ISR(void) +[v _ADC_DefaultContext2Threshold_ISR `(v ~T0 @X0 1 sf ] +"762 +[; ;mcc_generated_files/adc.c: 762: { +{ +[e :U _ADC_DefaultContext2Threshold_ISR ] +[f ] +"765 +[; ;mcc_generated_files/adc.c: 765: } +[e :UE 3248 ] +} +"767 +[; ;mcc_generated_files/adc.c: 767: static void ADC_DefaultContext3Threshold_ISR(void) +[v _ADC_DefaultContext3Threshold_ISR `(v ~T0 @X0 1 sf ] +"768 +[; ;mcc_generated_files/adc.c: 768: { +{ +[e :U _ADC_DefaultContext3Threshold_ISR ] +[f ] +"771 +[; ;mcc_generated_files/adc.c: 771: } +[e :UE 3249 ] +} +"773 +[; ;mcc_generated_files/adc.c: 773: static void ADC_DefaultContext4Threshold_ISR(void) +[v _ADC_DefaultContext4Threshold_ISR `(v ~T0 @X0 1 sf ] +"774 +[; ;mcc_generated_files/adc.c: 774: { +{ +[e :U _ADC_DefaultContext4Threshold_ISR ] +[f ] +"777 +[; ;mcc_generated_files/adc.c: 777: } +[e :UE 3250 ] +} +"779 +[; ;mcc_generated_files/adc.c: 779: static void ADC_DefaultActiveClockTuning_ISR(void) +[v _ADC_DefaultActiveClockTuning_ISR `(v ~T0 @X0 1 sf ] +"780 +[; ;mcc_generated_files/adc.c: 780: { +{ +[e :U _ADC_DefaultActiveClockTuning_ISR ] +[f ] +"783 +[; ;mcc_generated_files/adc.c: 783: } +[e :UE 3251 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/adc.p1.d b/ETC.X/build/default/debug/mcc_generated_files/adc.p1.d new file mode 100644 index 0000000..8f6837d --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/adc.p1.d @@ -0,0 +1,3 @@ +build/default/debug/mcc_generated_files/adc.p1: \ +mcc_generated_files/adc.c \ +mcc_generated_files/adc.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/can1.i b/ETC.X/build/default/debug/mcc_generated_files/can1.i new file mode 100644 index 0000000..477641d --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/can1.i @@ -0,0 +1,39038 @@ +# 1 "mcc_generated_files/can1.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/can1.c" 2 +# 47 "mcc_generated_files/can1.c" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 47 "mcc_generated_files/can1.c" 2 + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\string.h" 1 3 +# 25 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\string.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 411 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct __locale_struct * locale_t; +# 25 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\string.h" 2 3 + + +void *memcpy (void *restrict, const void *restrict, size_t); +void *memmove (void *, const void *, size_t); +void *memset (void *, int, size_t); +int memcmp (const void *, const void *, size_t); +void *memchr (const void *, int, size_t); + +char *strcpy (char *restrict, const char *restrict); +char *strncpy (char *restrict, const char *restrict, size_t); + +char *strcat (char *restrict, const char *restrict); +char *strncat (char *restrict, const char *restrict, size_t); + +int strcmp (const char *, const char *); +int strncmp (const char *, const char *, size_t); + +int strcoll (const char *, const char *); +size_t strxfrm (char *restrict, const char *restrict, size_t); + +char *strchr (const char *, int); +char *strrchr (const char *, int); + +size_t strcspn (const char *, const char *); +size_t strspn (const char *, const char *); +char *strpbrk (const char *, const char *); +char *strstr (const char *, const char *); +char *strtok (char *restrict, const char *restrict); + +size_t strlen (const char *); + +char *strerror (int); +# 65 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\string.h" 3 +char *strtok_r (char *restrict, const char *restrict, char **restrict); +int strerror_r (int, char *, size_t); +char *stpcpy(char *restrict, const char *restrict); +char *stpncpy(char *restrict, const char *restrict, size_t); +size_t strnlen (const char *, size_t); +char *strdup (const char *); +char *strndup (const char *, size_t); +char *strsignal(int); +char *strerror_l (int, locale_t); +int strcoll_l (const char *, const char *, locale_t); +size_t strxfrm_l (char *restrict, const char *restrict, size_t, locale_t); + + + + +void *memccpy (void *restrict, const void *restrict, int, size_t); +# 49 "mcc_generated_files/can1.c" 2 + +# 1 "mcc_generated_files/can1.h" 1 +# 54 "mcc_generated_files/can1.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 54 "mcc_generated_files/can1.h" 2 + + +# 1 "mcc_generated_files/can_types.h" 1 +# 65 "mcc_generated_files/can_types.h" +typedef union +{ + uint8_t msgfields; + struct + { + uint8_t idType:1; + uint8_t frameType:1; + uint8_t dlc:4; + uint8_t formatType:1; + uint8_t brs:1; + }; +} CAN_MSG_FIELD; + +typedef struct +{ + uint32_t msgId; + CAN_MSG_FIELD field; + uint8_t *data; +} CAN_MSG_OBJ; +# 94 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NON_BRS_MODE = 0, + CAN_BRS_MODE = 1 +} CAN_MSG_OBJ_BRS_MODE; +# 109 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_STD = 0, + CAN_FRAME_EXT = 1, +} CAN_MSG_OBJ_ID_TYPE; +# 124 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_DATA = 0, + CAN_FRAME_RTR = 1, +} CAN_MSG_OBJ_FRAME_TYPE; +# 139 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_2_0_FORMAT = 0, + CAN_FD_FORMAT = 1 +} CAN_MSG_OBJ_TYPE; +# 154 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_MSG_REQUEST_SUCCESS = 0, + CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR = 1, + CAN_TX_MSG_REQUEST_BRS_ERROR = 2, + CAN_TX_MSG_REQUEST_FIFO_FULL = 3, +} CAN_TX_MSG_REQUEST_STATUS; +# 171 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NORMAL_FD_MODE = 0, + CAN_DISABLE_MODE = 1, + CAN_INTERNAL_LOOPBACK_MODE = 2, + CAN_LISTEN_ONLY_MODE = 3, + CAN_CONFIGURATION_MODE = 4, + CAN_EXTERNAL_LOOPBACK_MODE = 5, + CAN_NORMAL_2_0_MODE = 6, + CAN_RESTRICTED_OPERATION_MODE =7, +} CAN_OP_MODES; +# 192 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_OP_MODE_REQUEST_SUCCESS, + CAN_OP_MODE_REQUEST_FAIL, + CAN_OP_MODE_SYS_ERROR_OCCURED +} CAN_OP_MODE_STATUS; +# 208 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_FIFO_FULL, + CAN_TX_FIFO_AVAILABLE, +} CAN_TX_FIFO_STATUS; +# 223 "mcc_generated_files/can_types.h" +typedef enum +{ + + DLC_0, + DLC_1, + DLC_2, + DLC_3, + DLC_4, + DLC_5, + DLC_6, + DLC_7, + DLC_8, + + + + DLC_12, + DLC_16, + DLC_20, + DLC_24, + DLC_32, + DLC_48, + DLC_64, +} CAN_DLC; +# 56 "mcc_generated_files/can1.h" 2 + + + + + +typedef enum +{ + TXQ = 0 +} CAN1_TX_FIFO_CHANNELS; + +typedef enum +{ + FIFO1 = 1 +} CAN1_RX_FIFO_CHANNELS; +# 106 "mcc_generated_files/can1.h" +void CAN1_Initialize(void); +# 147 "mcc_generated_files/can1.h" +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +# 185 "mcc_generated_files/can1.h" +CAN_OP_MODES CAN1_OperationModeGet(void); +# 235 "mcc_generated_files/can1.h" +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +# 275 "mcc_generated_files/can1.h" +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *rxCanMsg); +# 334 "mcc_generated_files/can1.h" +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +# 390 "mcc_generated_files/can1.h" +_Bool CAN1_IsBusOff(void); +# 448 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorPassive(void); +# 507 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorWarning(void); +# 566 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorActive(void); +# 614 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorPassive(void); +# 662 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorWarning(void); +# 710 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorActive(void); +# 761 "mcc_generated_files/can1.h" +void CAN1_Sleep(void); +# 815 "mcc_generated_files/can1.h" +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +# 857 "mcc_generated_files/can1.h" +uint8_t CAN1_ReceivedMessageCountGet(void); +# 924 "mcc_generated_files/can1.h" +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +# 981 "mcc_generated_files/can1.h" +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +# 1049 "mcc_generated_files/can1.h" +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +# 1100 "mcc_generated_files/can1.h" +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +# 1169 "mcc_generated_files/can1.h" +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +# 1237 "mcc_generated_files/can1.h" +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +# 1289 "mcc_generated_files/can1.h" +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +# 1324 "mcc_generated_files/can1.h" +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +# 1368 "mcc_generated_files/can1.h" +void CAN1_SetTXQnullHandler(void (*handler)(void)); + + +void CAN1_ISR(void); +void CAN1_RXI_ISR(void); +# 50 "mcc_generated_files/can1.c" 2 + +# 1 "mcc_generated_files/../MESSAGES.h" 1 +# 16 "mcc_generated_files/../MESSAGES.h" +# 1 "./mcc_generated_files/mcc.h" 1 +# 50 "./mcc_generated_files/mcc.h" +# 1 "mcc_generated_files/device_config.h" 1 +# 50 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pin_manager.h" 1 +# 402 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 51 "./mcc_generated_files/mcc.h" 2 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 1 3 + + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 1 3 +# 12 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 3 +extern int errno; +# 8 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__null.h" 1 3 +# 9 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + + + +extern void init_uart(void); + +extern char getch(void); +extern char getche(void); +extern void putch(char); +extern void ungetch(char); + +extern __bit kbhit(void); + + + +extern char * cgets(char *); +extern void cputs(const char *); +# 54 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/interrupt_manager.h" 1 +# 87 "mcc_generated_files/interrupt_manager.h" +void INTERRUPT_Initialize (void); +# 55 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/i2c1_master.h" 1 +# 54 "mcc_generated_files/i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "mcc_generated_files/i2c1_master.h" 2 + + + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "mcc_generated_files/i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "mcc_generated_files/i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "mcc_generated_files/i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 56 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/adc.h" 1 +# 65 "mcc_generated_files/adc.h" +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 57 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/tmr1.h" 1 +# 101 "mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 58 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/tmr0.h" 1 +# 106 "mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 59 "./mcc_generated_files/mcc.h" 2 + + +# 1 "mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 37 "mcc_generated_files/drivers/i2c_simple_master.h" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 61 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pwm2_16bit.h" 1 +# 63 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 62 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/DAC3.h" 1 +# 29 "mcc_generated_files/DAC3.h" +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 63 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pwm1_16bit.h" 1 +# 63 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 64 "./mcc_generated_files/mcc.h" 2 +# 79 "./mcc_generated_files/mcc.h" +void SYSTEM_Initialize(void); +# 92 "./mcc_generated_files/mcc.h" +void OSCILLATOR_Initialize(void); +# 105 "./mcc_generated_files/mcc.h" +void PMD_Initialize(void); +# 16 "mcc_generated_files/../MESSAGES.h" 2 + + + + + + +CAN_MSG_OBJ msgTransmit; +CAN_MSG_OBJ msgReceipt; +uint8_t CANDATAdata[8]; + + +extern unsigned char CANDATAdata[8]; + +extern unsigned char ucTargetAccelerator; +extern unsigned char ucTargetClutch; +extern unsigned char ucTargetClutch_PREV; +extern unsigned char ucTargetBrake; +extern unsigned char ucTargetDirection; +extern unsigned char ucTargetGear; + +extern unsigned char ucAS_state; +extern unsigned char ucEBS_state; +extern unsigned char ucAMI_state; +extern unsigned char ucSteering_state; +extern unsigned char ucService_brake; +extern unsigned char ucLap_counter; +extern unsigned char ucCones_count_actual; +extern unsigned char ucCones_count_all; + +extern unsigned char ucSpeed_actual; +extern unsigned char ucSpeed_target; +extern unsigned char ucSteering_angle_actual; +extern unsigned char ucSteering_angle_target; +extern unsigned char ucBrake_hydr_actual; +extern unsigned char ucBrake_hydr_target; +extern unsigned char ucMotor_moment_actual; +extern unsigned char ucMotor_moment_target; + +extern unsigned int uiAcc_longitudinal; +extern unsigned int uiAcc_lateral; +extern unsigned int uiYaw_rate; + +extern unsigned char ucASBState; +extern unsigned char ucASRequesState; + +extern unsigned char ucASMode; + +extern unsigned char ucSTEER_WH_Clutch; +# 98 "mcc_generated_files/../MESSAGES.h" +void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8); +void CANReadMessage (void); +void CANDisableErrorInterrupt (unsigned char ucInterruptSet); +# 51 "mcc_generated_files/can1.c" 2 +# 73 "mcc_generated_files/can1.c" +struct CAN_FIFOREG +{ + uint8_t CONL; + uint8_t CONH; + uint8_t CONU; + uint8_t CONT; + uint8_t STAL; + uint8_t STAH; + uint8_t STAU; + uint8_t STAT; + uint32_t UA; +}; + +typedef enum +{ + CAN_RX_MSG_NOT_AVAILABLE = 0U, + CAN_RX_MSG_AVAILABLE = 1U, + CAN_RX_MSG_OVERFLOW = 8U +} CAN_RX_FIFO_STATUS; + + +struct CAN1_RX_FIFO +{ + CAN1_RX_FIFO_CHANNELS channel; + volatile uint8_t fifoHead; +}; + + +static volatile uint8_t rxMsgData[(8U)]; + +static struct CAN1_RX_FIFO rxFifos[] = +{ + {FIFO1, 0u} +}; + +static volatile struct CAN_FIFOREG * const FIFO = (struct CAN_FIFOREG *)&C1TXQCONL; +static const uint8_t DLC_BYTES[] = {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U}; + +static void (*CAN1_FIFO1NotEmptyHandler)(void); +static void (*CAN1_InvalidMessageHandler)(void); +static void (*CAN1_BusWakeUpActivityHandler)(void); +static void (*CAN1_BusErrorHandler)(void); +static void (*CAN1_ModeChangeHandler)(void); +static void (*CAN1_SystemErrorHandler)(void); +static void (*CAN1_TxAttemptHandler)(void); +static void (*CAN1_RxBufferOverflowHandler)(void); + +static void DefaultFIFO1NotEmptyHandler(void) +{ + CANReadMessage(); +} + +static void DefaultInvalidMessageHandler(void) +{ +} + +static void DefaultBusWakeUpActivityHandler(void) +{ +} + +static void DefaultBusErrorHandler(void) +{ +} + +static void DefaultModeChangeHandler(void) +{ +} + +static void DefaultSystemErrorHandler(void) +{ +} + +static void DefaultTxAttemptHandler(void) +{ +} + +static void DefaultRxBufferOverflowHandler(void) +{ +} + +void CAN1_RX_FIFO_ResetInfo(void) +{ + uint8_t index; + + for (index = 0; index < (1U); index++) + { + rxFifos[index].fifoHead = 0; + } +} + +static void CAN1_RX_FIFO_Configuration(void) +{ + + C1FIFOCON1L = 0x19; + + + C1FIFOCON1H = 0x04; + + + C1FIFOCON1U = 0x60; + + + C1FIFOCON1T = 0x05; + + CAN1_SetFIFO1NotEmptyHandler(DefaultFIFO1NotEmptyHandler); + + C1INTUbits.RXIE = 1; + + PIR4bits.CANRXIF = 0; + PIE4bits.CANRXIE = 1; +} + +static void CAN1_RX_FIFO_FilterMaskConfiguration(void) +{ +# 199 "mcc_generated_files/can1.c" + C1FLTOBJ1L = 0x5F; + C1FLTOBJ1H = 0xFF; + C1FLTOBJ1U = 0xFF; + C1FLTOBJ1T = 0xFF; + + C1MASK1L = 0x00; + C1MASK1H = 0x00; + C1MASK1U = 0x00; + C1MASK1T = 0x00; + C1FLTCON0H = 0x81; +} + +static void CAN1_TX_FIFO_Configuration(void) +{ + + C1TXQCONL = 0x10; + + + C1TXQCONH = 0x04; + + + C1TXQCONU = 0x61; + + + C1TXQCONT = 0x05; + +} + +static void CAN1_BitRateConfiguration(void) +{ + + C1NBTCFGL = 0x01; + + + C1NBTCFGH = 0x01; + + + C1NBTCFGU = 0x06; + + + C1NBTCFGT = 0x00; + +} + +static void CAN1_ErrorNotificationInterruptEnable(void) +{ + CAN1_SetInvalidMessageInterruptHandler(DefaultInvalidMessageHandler); + CAN1_SetBusWakeUpActivityInterruptHandler(DefaultBusWakeUpActivityHandler); + CAN1_SetBusErrorInterruptHandler(DefaultBusErrorHandler); + CAN1_SetModeChangeInterruptHandler(DefaultModeChangeHandler); + CAN1_SetSystemErrorInterruptHandler(DefaultSystemErrorHandler); + CAN1_SetTxAttemptInterruptHandler(DefaultTxAttemptHandler); + CAN1_SetRxBufferOverFlowInterruptHandler(DefaultRxBufferOverflowHandler); + PIR0bits.CANIF = 0; + + + C1INTL = 0x00; + + + C1INTH = 0x00; + + + C1INTU = 0x0A; + + + C1INTT = 0xFC; + + PIE0bits.CANIE = 1; +} + +void CAN1_Initialize(void) +{ + + C1CONHbits.ON = 1; + + if (CAN_OP_MODE_REQUEST_SUCCESS == CAN1_OperationModeSet(CAN_CONFIGURATION_MODE)) + { + + C1FIFOBA = 0x2600; + + + C1CONL = 0x60; + + + C1CONH = 0x97; + + + C1CONU = 0x10; + + CAN1_BitRateConfiguration(); + CAN1_TX_FIFO_Configuration(); + CAN1_RX_FIFO_Configuration(); + CAN1_RX_FIFO_FilterMaskConfiguration(); + CAN1_RX_FIFO_ResetInfo(); + CAN1_ErrorNotificationInterruptEnable(); + CAN1_OperationModeSet(CAN_NORMAL_2_0_MODE); + + + do { TRISBbits.TRISB5 = 0; } while(0); + do { LATBbits.LATB5 = 0; } while(0); + } +} + +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES requestMode) +{ + CAN_OP_MODE_STATUS status = CAN_OP_MODE_REQUEST_SUCCESS; + CAN_OP_MODES opMode = CAN1_OperationModeGet(); + + if (CAN_CONFIGURATION_MODE == opMode + || CAN_DISABLE_MODE == requestMode + || CAN_CONFIGURATION_MODE == requestMode) + { + C1CONTbits.REQOP = requestMode; + + while (C1CONUbits.OPMOD != requestMode) + { + + if (1 == C1INTHbits.SERRIF) + { + status = CAN_OP_MODE_SYS_ERROR_OCCURED; + break; + } + } + } + else + { + status = CAN_OP_MODE_REQUEST_FAIL; + } + + return status; +} + +CAN_OP_MODES CAN1_OperationModeGet(void) +{ + return C1CONUbits.OPMOD; +} + +static uint8_t GetRxFifoDepth(uint8_t validChannel) +{ + return 1U + (FIFO[validChannel].CONT & 0x1F); +} + +static CAN_RX_FIFO_STATUS GetRxFifoStatus(uint8_t validChannel) +{ + return FIFO[validChannel].STAL & (CAN_RX_MSG_AVAILABLE | CAN_RX_MSG_OVERFLOW); +} + +static void ReadMessageFromFifo(uint8_t *rxFifoObj, CAN_MSG_OBJ *rxCanMsg) +{ + uint32_t msgId; + uint8_t status = rxFifoObj[4]; + const uint8_t payloadOffsetBytes = + 4U + + 1U + + 1U + + 2U; + + rxCanMsg->field.dlc = status; + rxCanMsg->field.idType = (status & (1UL << (4U))) ? CAN_FRAME_EXT : CAN_FRAME_STD; + rxCanMsg->field.frameType = (status & (1UL << (5U))) ? CAN_FRAME_RTR : CAN_FRAME_DATA; + rxCanMsg->field.brs = (status & (1UL << (6U))) ? CAN_BRS_MODE : CAN_NON_BRS_MODE; + rxCanMsg->field.formatType = (status & (1UL << (7U))) ? CAN_FRAME_EXT : CAN_FRAME_STD; + + msgId = rxFifoObj[1] & (0x07U); + msgId <<= (8U); + msgId |= rxFifoObj[0]; + if (CAN_FRAME_EXT == rxCanMsg->field.idType) + { + msgId <<= (5U); + msgId |= (rxFifoObj[3] & (0x1FU)); + msgId <<= (8U); + msgId |= rxFifoObj[2]; + msgId <<= (5U); + msgId |= (rxFifoObj[1] & (0xF8U)) >> (3U); + } + rxCanMsg->msgId = msgId; + + memcpy(rxMsgData, rxFifoObj + payloadOffsetBytes, (DLC_BYTES[(rxCanMsg->field.dlc)])); + rxCanMsg->data = rxMsgData; +} + +static _Bool Receive(uint8_t index, CAN1_RX_FIFO_CHANNELS channel, CAN_MSG_OBJ *rxCanMsg) +{ + _Bool status = 0; + CAN_RX_FIFO_STATUS rxMsgStatus = GetRxFifoStatus(channel); + + if (CAN_RX_MSG_AVAILABLE == (rxMsgStatus & CAN_RX_MSG_AVAILABLE)) + { + uint8_t *rxFifoObj = (uint8_t *) FIFO[channel].UA; + + if (rxFifoObj != ((void*)0)) + { + ReadMessageFromFifo(rxFifoObj, rxCanMsg); + FIFO[channel].CONH |= 0x1; + + rxFifos[index].fifoHead += 1; + if (rxFifos[index].fifoHead >= GetRxFifoDepth(channel)) + { + rxFifos[index].fifoHead = 0; + } + + if (CAN_RX_MSG_OVERFLOW == (rxMsgStatus & CAN_RX_MSG_OVERFLOW)) + { + FIFO[channel].STAL &= ~0x8; + } + + status = 1; + } + } + + return status; +} + +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg) +{ + uint8_t index; + _Bool status = 0; + + for (index = 0; index < (1U); index++) + { + status = Receive(index, rxFifos[index].channel, rxCanMsg); + + if (status) + { + break; + } + } + + return status; +} + +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS channel, CAN_MSG_OBJ *rxCanMsg) +{ + uint8_t index; + _Bool status = 0; + + for (index = 0; index < (1U); index++) + { + if (channel == rxFifos[index].channel) + { + status = Receive(index, channel, rxCanMsg); + break; + } + } + + return status; +} + +uint8_t CAN1_ReceivedMessageCountGet(void) +{ + uint8_t index, totalMsgObj = 0; + + for (index = 0; index < (1U); index++) + { + CAN1_RX_FIFO_CHANNELS channel = rxFifos[index].channel; + CAN_RX_FIFO_STATUS rxMsgStatus = GetRxFifoStatus(channel); + + if (CAN_RX_MSG_AVAILABLE == (rxMsgStatus & CAN_RX_MSG_AVAILABLE)) + { + uint8_t numOfMsg, fifoDepth = GetRxFifoDepth(channel); + + if (CAN_RX_MSG_OVERFLOW == (rxMsgStatus & CAN_RX_MSG_OVERFLOW)) + { + numOfMsg = fifoDepth; + } + else + { + uint8_t fifoTail = FIFO[channel].STAH & 0x1F; + uint8_t fifoHead = rxFifos[index].fifoHead; + + if (fifoTail < fifoHead) + { + numOfMsg = ((fifoTail + fifoDepth) - fifoHead); + } + else if (fifoTail > fifoHead) + { + numOfMsg = fifoTail - fifoHead; + } + else + { + numOfMsg = fifoDepth; + } + } + + totalMsgObj += numOfMsg; + } + } + + return totalMsgObj; +} + +static _Bool isTxChannel(uint8_t channel) +{ + return channel < 4u && (FIFO[channel].CONL & 0x80); +} + +static CAN_TX_FIFO_STATUS GetTxFifoStatus(uint8_t validChannel) +{ + return (FIFO[validChannel].STAL & 0x1); +} + +static void WriteMessageToFifo(uint8_t *txFifoObj, CAN_MSG_OBJ *txCanMsg) +{ + uint32_t msgId = txCanMsg->msgId; + uint8_t status; + const uint8_t payloadOffsetBytes = + 4U + + 1U + + 1U + + 2U; + + if (CAN_FRAME_EXT == txCanMsg->field.idType) + { + txFifoObj[1] = (msgId << (3U)) & (0xF8U); + msgId >>= (5U); + txFifoObj[2] = msgId; + msgId >>= (8U); + txFifoObj[3] = (msgId & (0x1FU)); + msgId >>= (5U); + } + else + { + txFifoObj[1] = txFifoObj[2] = txFifoObj[3] = 0; + } + + txFifoObj[0] = msgId; + msgId >>= (8U); + txFifoObj[1] |= (msgId & (0x07U)); + + status = txCanMsg->field.dlc; + status |= (txCanMsg->field.idType << (4U)); + status |= (txCanMsg->field.frameType << (5U)); + status |= (txCanMsg->field.brs << (6U)); + status |= (txCanMsg->field.formatType << (7U)); + txFifoObj[4] = status; + + if (CAN_FRAME_DATA == txCanMsg->field.frameType) + { + memcpy(txFifoObj + payloadOffsetBytes, txCanMsg->data, (DLC_BYTES[(txCanMsg->field.dlc)])); + } +} + +static CAN_TX_MSG_REQUEST_STATUS ValidateTransmission(uint8_t validChannel, CAN_MSG_OBJ *txCanMsg) +{ + CAN_TX_MSG_REQUEST_STATUS txMsgStatus = CAN_TX_MSG_REQUEST_SUCCESS; + CAN_MSG_FIELD field = txCanMsg->field; + uint8_t plsize = 0; + + if (CAN_BRS_MODE == field.brs && (CAN_NORMAL_2_0_MODE == CAN1_OperationModeGet())) + { + txMsgStatus |= CAN_TX_MSG_REQUEST_BRS_ERROR; + } + + if (field.dlc > DLC_8 && (CAN_2_0_FORMAT == field.formatType || CAN_NORMAL_2_0_MODE == CAN1_OperationModeGet())) + { + txMsgStatus |= CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR; + } + + if ((DLC_BYTES[(field.dlc)]) > ((DLC_BYTES[(8u + (plsize))]))) + { + txMsgStatus |= CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR; + } + + if (CAN_TX_FIFO_FULL == GetTxFifoStatus(validChannel)) + { + txMsgStatus |= CAN_TX_MSG_REQUEST_FIFO_FULL; + } + + return txMsgStatus; +} + +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg) +{ + CAN_TX_MSG_REQUEST_STATUS status = CAN_TX_MSG_REQUEST_FIFO_FULL; + + if (isTxChannel(fifoChannel)) + { + status = ValidateTransmission(fifoChannel, txCanMsg); + if (CAN_TX_MSG_REQUEST_SUCCESS == status) + { + uint8_t *txFifoObj = (uint8_t *) FIFO[fifoChannel].UA; + + if (txFifoObj != ((void*)0)) + { + WriteMessageToFifo(txFifoObj, txCanMsg); + FIFO[fifoChannel].CONH |= (0x2 | 0x1); + } + } + } + + return status; +} + +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel) +{ + CAN_TX_FIFO_STATUS status = CAN_TX_FIFO_FULL; + + if (isTxChannel(fifoChannel)) + { + status = GetTxFifoStatus(fifoChannel); + } + + return status; +} + +_Bool CAN1_IsBusOff(void) +{ + return C1TRECUbits.TXBO; +} + +_Bool CAN1_IsRxErrorPassive(void) +{ + return C1TRECUbits.RXBP; +} + +_Bool CAN1_IsRxErrorWarning(void) +{ + return C1TRECUbits.RXWARN; +} + +_Bool CAN1_IsRxErrorActive(void) +{ + return !CAN1_IsRxErrorPassive(); +} + +_Bool CAN1_IsTxErrorPassive(void) +{ + return C1TRECUbits.TXBP; +} + +_Bool CAN1_IsTxErrorWarning(void) +{ + return C1TRECUbits.TXWARN; +} + +_Bool CAN1_IsTxErrorActive(void) +{ + return !CAN1_IsTxErrorPassive(); +} + +void CAN1_Sleep(void) +{ + C1INTHbits.WAKIF = 0; + C1INTTbits.WAKIE = 1; + + CAN1_OperationModeSet(CAN_DISABLE_MODE); +} + +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)) +{ + CAN1_InvalidMessageHandler = handler; +} + +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)) +{ + CAN1_BusWakeUpActivityHandler = handler; +} + +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)) +{ + CAN1_BusErrorHandler = handler; +} + +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)) +{ + CAN1_ModeChangeHandler = handler; +} + +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)) +{ + CAN1_SystemErrorHandler = handler; +} + +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)) +{ + CAN1_TxAttemptHandler = handler; +} + +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)) +{ + CAN1_RxBufferOverflowHandler = handler; +} + +void CAN1_ISR(void) +{ + if (1 == C1INTHbits.IVMIF) + { + CAN1_InvalidMessageHandler(); + C1INTHbits.IVMIF = 0; + } + + if (1 == C1INTHbits.WAKIF) + { + CAN1_BusWakeUpActivityHandler(); + C1INTHbits.WAKIF = 0; + } + + if (1 == C1INTHbits.CERRIF) + { + CAN1_BusErrorHandler(); + C1INTHbits.CERRIF = 0; + } + + if (1 == C1INTLbits.MODIF) + { + CAN1_ModeChangeHandler(); + C1INTLbits.MODIF = 0; + } + + if (1 == C1INTHbits.SERRIF) + { + CAN1_SystemErrorHandler(); + C1INTHbits.SERRIF = 0; + } + + if (1 == C1INTHbits.TXATIF) + { + CAN1_TxAttemptHandler(); + if (1 == C1TXQSTALbits.TXATIF) + { + C1TXQSTALbits.TXATIF = 0; + } + } + + if (1 == C1INTHbits.RXOVIF) + { + CAN1_RxBufferOverflowHandler(); + if (1 == C1FIFOSTA1Lbits.RXOVIF) + { + C1FIFOSTA1Lbits.RXOVIF = 0; + } + } + + PIR0bits.CANIF = 0; +} + +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)) +{ + CAN1_FIFO1NotEmptyHandler = handler; +} + + +void CAN1_RXI_ISR(void) +{ + if (1 == C1FIFOSTA1Lbits.TFNRFNIF) + { + CAN1_FIFO1NotEmptyHandler(); + + } + +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/can1.i-8e07095c b/ETC.X/build/default/debug/mcc_generated_files/can1.i-8e07095c new file mode 100644 index 0000000..477641d --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/can1.i-8e07095c @@ -0,0 +1,39038 @@ +# 1 "mcc_generated_files/can1.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/can1.c" 2 +# 47 "mcc_generated_files/can1.c" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 47 "mcc_generated_files/can1.c" 2 + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\string.h" 1 3 +# 25 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\string.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 411 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct __locale_struct * locale_t; +# 25 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\string.h" 2 3 + + +void *memcpy (void *restrict, const void *restrict, size_t); +void *memmove (void *, const void *, size_t); +void *memset (void *, int, size_t); +int memcmp (const void *, const void *, size_t); +void *memchr (const void *, int, size_t); + +char *strcpy (char *restrict, const char *restrict); +char *strncpy (char *restrict, const char *restrict, size_t); + +char *strcat (char *restrict, const char *restrict); +char *strncat (char *restrict, const char *restrict, size_t); + +int strcmp (const char *, const char *); +int strncmp (const char *, const char *, size_t); + +int strcoll (const char *, const char *); +size_t strxfrm (char *restrict, const char *restrict, size_t); + +char *strchr (const char *, int); +char *strrchr (const char *, int); + +size_t strcspn (const char *, const char *); +size_t strspn (const char *, const char *); +char *strpbrk (const char *, const char *); +char *strstr (const char *, const char *); +char *strtok (char *restrict, const char *restrict); + +size_t strlen (const char *); + +char *strerror (int); +# 65 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\string.h" 3 +char *strtok_r (char *restrict, const char *restrict, char **restrict); +int strerror_r (int, char *, size_t); +char *stpcpy(char *restrict, const char *restrict); +char *stpncpy(char *restrict, const char *restrict, size_t); +size_t strnlen (const char *, size_t); +char *strdup (const char *); +char *strndup (const char *, size_t); +char *strsignal(int); +char *strerror_l (int, locale_t); +int strcoll_l (const char *, const char *, locale_t); +size_t strxfrm_l (char *restrict, const char *restrict, size_t, locale_t); + + + + +void *memccpy (void *restrict, const void *restrict, int, size_t); +# 49 "mcc_generated_files/can1.c" 2 + +# 1 "mcc_generated_files/can1.h" 1 +# 54 "mcc_generated_files/can1.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 54 "mcc_generated_files/can1.h" 2 + + +# 1 "mcc_generated_files/can_types.h" 1 +# 65 "mcc_generated_files/can_types.h" +typedef union +{ + uint8_t msgfields; + struct + { + uint8_t idType:1; + uint8_t frameType:1; + uint8_t dlc:4; + uint8_t formatType:1; + uint8_t brs:1; + }; +} CAN_MSG_FIELD; + +typedef struct +{ + uint32_t msgId; + CAN_MSG_FIELD field; + uint8_t *data; +} CAN_MSG_OBJ; +# 94 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NON_BRS_MODE = 0, + CAN_BRS_MODE = 1 +} CAN_MSG_OBJ_BRS_MODE; +# 109 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_STD = 0, + CAN_FRAME_EXT = 1, +} CAN_MSG_OBJ_ID_TYPE; +# 124 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_DATA = 0, + CAN_FRAME_RTR = 1, +} CAN_MSG_OBJ_FRAME_TYPE; +# 139 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_2_0_FORMAT = 0, + CAN_FD_FORMAT = 1 +} CAN_MSG_OBJ_TYPE; +# 154 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_MSG_REQUEST_SUCCESS = 0, + CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR = 1, + CAN_TX_MSG_REQUEST_BRS_ERROR = 2, + CAN_TX_MSG_REQUEST_FIFO_FULL = 3, +} CAN_TX_MSG_REQUEST_STATUS; +# 171 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NORMAL_FD_MODE = 0, + CAN_DISABLE_MODE = 1, + CAN_INTERNAL_LOOPBACK_MODE = 2, + CAN_LISTEN_ONLY_MODE = 3, + CAN_CONFIGURATION_MODE = 4, + CAN_EXTERNAL_LOOPBACK_MODE = 5, + CAN_NORMAL_2_0_MODE = 6, + CAN_RESTRICTED_OPERATION_MODE =7, +} CAN_OP_MODES; +# 192 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_OP_MODE_REQUEST_SUCCESS, + CAN_OP_MODE_REQUEST_FAIL, + CAN_OP_MODE_SYS_ERROR_OCCURED +} CAN_OP_MODE_STATUS; +# 208 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_FIFO_FULL, + CAN_TX_FIFO_AVAILABLE, +} CAN_TX_FIFO_STATUS; +# 223 "mcc_generated_files/can_types.h" +typedef enum +{ + + DLC_0, + DLC_1, + DLC_2, + DLC_3, + DLC_4, + DLC_5, + DLC_6, + DLC_7, + DLC_8, + + + + DLC_12, + DLC_16, + DLC_20, + DLC_24, + DLC_32, + DLC_48, + DLC_64, +} CAN_DLC; +# 56 "mcc_generated_files/can1.h" 2 + + + + + +typedef enum +{ + TXQ = 0 +} CAN1_TX_FIFO_CHANNELS; + +typedef enum +{ + FIFO1 = 1 +} CAN1_RX_FIFO_CHANNELS; +# 106 "mcc_generated_files/can1.h" +void CAN1_Initialize(void); +# 147 "mcc_generated_files/can1.h" +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +# 185 "mcc_generated_files/can1.h" +CAN_OP_MODES CAN1_OperationModeGet(void); +# 235 "mcc_generated_files/can1.h" +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +# 275 "mcc_generated_files/can1.h" +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *rxCanMsg); +# 334 "mcc_generated_files/can1.h" +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +# 390 "mcc_generated_files/can1.h" +_Bool CAN1_IsBusOff(void); +# 448 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorPassive(void); +# 507 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorWarning(void); +# 566 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorActive(void); +# 614 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorPassive(void); +# 662 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorWarning(void); +# 710 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorActive(void); +# 761 "mcc_generated_files/can1.h" +void CAN1_Sleep(void); +# 815 "mcc_generated_files/can1.h" +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +# 857 "mcc_generated_files/can1.h" +uint8_t CAN1_ReceivedMessageCountGet(void); +# 924 "mcc_generated_files/can1.h" +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +# 981 "mcc_generated_files/can1.h" +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +# 1049 "mcc_generated_files/can1.h" +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +# 1100 "mcc_generated_files/can1.h" +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +# 1169 "mcc_generated_files/can1.h" +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +# 1237 "mcc_generated_files/can1.h" +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +# 1289 "mcc_generated_files/can1.h" +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +# 1324 "mcc_generated_files/can1.h" +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +# 1368 "mcc_generated_files/can1.h" +void CAN1_SetTXQnullHandler(void (*handler)(void)); + + +void CAN1_ISR(void); +void CAN1_RXI_ISR(void); +# 50 "mcc_generated_files/can1.c" 2 + +# 1 "mcc_generated_files/../MESSAGES.h" 1 +# 16 "mcc_generated_files/../MESSAGES.h" +# 1 "./mcc_generated_files/mcc.h" 1 +# 50 "./mcc_generated_files/mcc.h" +# 1 "mcc_generated_files/device_config.h" 1 +# 50 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pin_manager.h" 1 +# 402 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 51 "./mcc_generated_files/mcc.h" 2 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 1 3 + + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 1 3 +# 12 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 3 +extern int errno; +# 8 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__null.h" 1 3 +# 9 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + + + +extern void init_uart(void); + +extern char getch(void); +extern char getche(void); +extern void putch(char); +extern void ungetch(char); + +extern __bit kbhit(void); + + + +extern char * cgets(char *); +extern void cputs(const char *); +# 54 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/interrupt_manager.h" 1 +# 87 "mcc_generated_files/interrupt_manager.h" +void INTERRUPT_Initialize (void); +# 55 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/i2c1_master.h" 1 +# 54 "mcc_generated_files/i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "mcc_generated_files/i2c1_master.h" 2 + + + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "mcc_generated_files/i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "mcc_generated_files/i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "mcc_generated_files/i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 56 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/adc.h" 1 +# 65 "mcc_generated_files/adc.h" +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 57 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/tmr1.h" 1 +# 101 "mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 58 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/tmr0.h" 1 +# 106 "mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 59 "./mcc_generated_files/mcc.h" 2 + + +# 1 "mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 37 "mcc_generated_files/drivers/i2c_simple_master.h" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 61 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pwm2_16bit.h" 1 +# 63 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 62 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/DAC3.h" 1 +# 29 "mcc_generated_files/DAC3.h" +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 63 "./mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pwm1_16bit.h" 1 +# 63 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 64 "./mcc_generated_files/mcc.h" 2 +# 79 "./mcc_generated_files/mcc.h" +void SYSTEM_Initialize(void); +# 92 "./mcc_generated_files/mcc.h" +void OSCILLATOR_Initialize(void); +# 105 "./mcc_generated_files/mcc.h" +void PMD_Initialize(void); +# 16 "mcc_generated_files/../MESSAGES.h" 2 + + + + + + +CAN_MSG_OBJ msgTransmit; +CAN_MSG_OBJ msgReceipt; +uint8_t CANDATAdata[8]; + + +extern unsigned char CANDATAdata[8]; + +extern unsigned char ucTargetAccelerator; +extern unsigned char ucTargetClutch; +extern unsigned char ucTargetClutch_PREV; +extern unsigned char ucTargetBrake; +extern unsigned char ucTargetDirection; +extern unsigned char ucTargetGear; + +extern unsigned char ucAS_state; +extern unsigned char ucEBS_state; +extern unsigned char ucAMI_state; +extern unsigned char ucSteering_state; +extern unsigned char ucService_brake; +extern unsigned char ucLap_counter; +extern unsigned char ucCones_count_actual; +extern unsigned char ucCones_count_all; + +extern unsigned char ucSpeed_actual; +extern unsigned char ucSpeed_target; +extern unsigned char ucSteering_angle_actual; +extern unsigned char ucSteering_angle_target; +extern unsigned char ucBrake_hydr_actual; +extern unsigned char ucBrake_hydr_target; +extern unsigned char ucMotor_moment_actual; +extern unsigned char ucMotor_moment_target; + +extern unsigned int uiAcc_longitudinal; +extern unsigned int uiAcc_lateral; +extern unsigned int uiYaw_rate; + +extern unsigned char ucASBState; +extern unsigned char ucASRequesState; + +extern unsigned char ucASMode; + +extern unsigned char ucSTEER_WH_Clutch; +# 98 "mcc_generated_files/../MESSAGES.h" +void CANWriteMessage(unsigned long id, unsigned char dataLength, unsigned char data1, unsigned char data2, unsigned char data3, unsigned char data4, unsigned char data5, unsigned char data6, unsigned char data7, unsigned char data8); +void CANReadMessage (void); +void CANDisableErrorInterrupt (unsigned char ucInterruptSet); +# 51 "mcc_generated_files/can1.c" 2 +# 73 "mcc_generated_files/can1.c" +struct CAN_FIFOREG +{ + uint8_t CONL; + uint8_t CONH; + uint8_t CONU; + uint8_t CONT; + uint8_t STAL; + uint8_t STAH; + uint8_t STAU; + uint8_t STAT; + uint32_t UA; +}; + +typedef enum +{ + CAN_RX_MSG_NOT_AVAILABLE = 0U, + CAN_RX_MSG_AVAILABLE = 1U, + CAN_RX_MSG_OVERFLOW = 8U +} CAN_RX_FIFO_STATUS; + + +struct CAN1_RX_FIFO +{ + CAN1_RX_FIFO_CHANNELS channel; + volatile uint8_t fifoHead; +}; + + +static volatile uint8_t rxMsgData[(8U)]; + +static struct CAN1_RX_FIFO rxFifos[] = +{ + {FIFO1, 0u} +}; + +static volatile struct CAN_FIFOREG * const FIFO = (struct CAN_FIFOREG *)&C1TXQCONL; +static const uint8_t DLC_BYTES[] = {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U}; + +static void (*CAN1_FIFO1NotEmptyHandler)(void); +static void (*CAN1_InvalidMessageHandler)(void); +static void (*CAN1_BusWakeUpActivityHandler)(void); +static void (*CAN1_BusErrorHandler)(void); +static void (*CAN1_ModeChangeHandler)(void); +static void (*CAN1_SystemErrorHandler)(void); +static void (*CAN1_TxAttemptHandler)(void); +static void (*CAN1_RxBufferOverflowHandler)(void); + +static void DefaultFIFO1NotEmptyHandler(void) +{ + CANReadMessage(); +} + +static void DefaultInvalidMessageHandler(void) +{ +} + +static void DefaultBusWakeUpActivityHandler(void) +{ +} + +static void DefaultBusErrorHandler(void) +{ +} + +static void DefaultModeChangeHandler(void) +{ +} + +static void DefaultSystemErrorHandler(void) +{ +} + +static void DefaultTxAttemptHandler(void) +{ +} + +static void DefaultRxBufferOverflowHandler(void) +{ +} + +void CAN1_RX_FIFO_ResetInfo(void) +{ + uint8_t index; + + for (index = 0; index < (1U); index++) + { + rxFifos[index].fifoHead = 0; + } +} + +static void CAN1_RX_FIFO_Configuration(void) +{ + + C1FIFOCON1L = 0x19; + + + C1FIFOCON1H = 0x04; + + + C1FIFOCON1U = 0x60; + + + C1FIFOCON1T = 0x05; + + CAN1_SetFIFO1NotEmptyHandler(DefaultFIFO1NotEmptyHandler); + + C1INTUbits.RXIE = 1; + + PIR4bits.CANRXIF = 0; + PIE4bits.CANRXIE = 1; +} + +static void CAN1_RX_FIFO_FilterMaskConfiguration(void) +{ +# 199 "mcc_generated_files/can1.c" + C1FLTOBJ1L = 0x5F; + C1FLTOBJ1H = 0xFF; + C1FLTOBJ1U = 0xFF; + C1FLTOBJ1T = 0xFF; + + C1MASK1L = 0x00; + C1MASK1H = 0x00; + C1MASK1U = 0x00; + C1MASK1T = 0x00; + C1FLTCON0H = 0x81; +} + +static void CAN1_TX_FIFO_Configuration(void) +{ + + C1TXQCONL = 0x10; + + + C1TXQCONH = 0x04; + + + C1TXQCONU = 0x61; + + + C1TXQCONT = 0x05; + +} + +static void CAN1_BitRateConfiguration(void) +{ + + C1NBTCFGL = 0x01; + + + C1NBTCFGH = 0x01; + + + C1NBTCFGU = 0x06; + + + C1NBTCFGT = 0x00; + +} + +static void CAN1_ErrorNotificationInterruptEnable(void) +{ + CAN1_SetInvalidMessageInterruptHandler(DefaultInvalidMessageHandler); + CAN1_SetBusWakeUpActivityInterruptHandler(DefaultBusWakeUpActivityHandler); + CAN1_SetBusErrorInterruptHandler(DefaultBusErrorHandler); + CAN1_SetModeChangeInterruptHandler(DefaultModeChangeHandler); + CAN1_SetSystemErrorInterruptHandler(DefaultSystemErrorHandler); + CAN1_SetTxAttemptInterruptHandler(DefaultTxAttemptHandler); + CAN1_SetRxBufferOverFlowInterruptHandler(DefaultRxBufferOverflowHandler); + PIR0bits.CANIF = 0; + + + C1INTL = 0x00; + + + C1INTH = 0x00; + + + C1INTU = 0x0A; + + + C1INTT = 0xFC; + + PIE0bits.CANIE = 1; +} + +void CAN1_Initialize(void) +{ + + C1CONHbits.ON = 1; + + if (CAN_OP_MODE_REQUEST_SUCCESS == CAN1_OperationModeSet(CAN_CONFIGURATION_MODE)) + { + + C1FIFOBA = 0x2600; + + + C1CONL = 0x60; + + + C1CONH = 0x97; + + + C1CONU = 0x10; + + CAN1_BitRateConfiguration(); + CAN1_TX_FIFO_Configuration(); + CAN1_RX_FIFO_Configuration(); + CAN1_RX_FIFO_FilterMaskConfiguration(); + CAN1_RX_FIFO_ResetInfo(); + CAN1_ErrorNotificationInterruptEnable(); + CAN1_OperationModeSet(CAN_NORMAL_2_0_MODE); + + + do { TRISBbits.TRISB5 = 0; } while(0); + do { LATBbits.LATB5 = 0; } while(0); + } +} + +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES requestMode) +{ + CAN_OP_MODE_STATUS status = CAN_OP_MODE_REQUEST_SUCCESS; + CAN_OP_MODES opMode = CAN1_OperationModeGet(); + + if (CAN_CONFIGURATION_MODE == opMode + || CAN_DISABLE_MODE == requestMode + || CAN_CONFIGURATION_MODE == requestMode) + { + C1CONTbits.REQOP = requestMode; + + while (C1CONUbits.OPMOD != requestMode) + { + + if (1 == C1INTHbits.SERRIF) + { + status = CAN_OP_MODE_SYS_ERROR_OCCURED; + break; + } + } + } + else + { + status = CAN_OP_MODE_REQUEST_FAIL; + } + + return status; +} + +CAN_OP_MODES CAN1_OperationModeGet(void) +{ + return C1CONUbits.OPMOD; +} + +static uint8_t GetRxFifoDepth(uint8_t validChannel) +{ + return 1U + (FIFO[validChannel].CONT & 0x1F); +} + +static CAN_RX_FIFO_STATUS GetRxFifoStatus(uint8_t validChannel) +{ + return FIFO[validChannel].STAL & (CAN_RX_MSG_AVAILABLE | CAN_RX_MSG_OVERFLOW); +} + +static void ReadMessageFromFifo(uint8_t *rxFifoObj, CAN_MSG_OBJ *rxCanMsg) +{ + uint32_t msgId; + uint8_t status = rxFifoObj[4]; + const uint8_t payloadOffsetBytes = + 4U + + 1U + + 1U + + 2U; + + rxCanMsg->field.dlc = status; + rxCanMsg->field.idType = (status & (1UL << (4U))) ? CAN_FRAME_EXT : CAN_FRAME_STD; + rxCanMsg->field.frameType = (status & (1UL << (5U))) ? CAN_FRAME_RTR : CAN_FRAME_DATA; + rxCanMsg->field.brs = (status & (1UL << (6U))) ? CAN_BRS_MODE : CAN_NON_BRS_MODE; + rxCanMsg->field.formatType = (status & (1UL << (7U))) ? CAN_FRAME_EXT : CAN_FRAME_STD; + + msgId = rxFifoObj[1] & (0x07U); + msgId <<= (8U); + msgId |= rxFifoObj[0]; + if (CAN_FRAME_EXT == rxCanMsg->field.idType) + { + msgId <<= (5U); + msgId |= (rxFifoObj[3] & (0x1FU)); + msgId <<= (8U); + msgId |= rxFifoObj[2]; + msgId <<= (5U); + msgId |= (rxFifoObj[1] & (0xF8U)) >> (3U); + } + rxCanMsg->msgId = msgId; + + memcpy(rxMsgData, rxFifoObj + payloadOffsetBytes, (DLC_BYTES[(rxCanMsg->field.dlc)])); + rxCanMsg->data = rxMsgData; +} + +static _Bool Receive(uint8_t index, CAN1_RX_FIFO_CHANNELS channel, CAN_MSG_OBJ *rxCanMsg) +{ + _Bool status = 0; + CAN_RX_FIFO_STATUS rxMsgStatus = GetRxFifoStatus(channel); + + if (CAN_RX_MSG_AVAILABLE == (rxMsgStatus & CAN_RX_MSG_AVAILABLE)) + { + uint8_t *rxFifoObj = (uint8_t *) FIFO[channel].UA; + + if (rxFifoObj != ((void*)0)) + { + ReadMessageFromFifo(rxFifoObj, rxCanMsg); + FIFO[channel].CONH |= 0x1; + + rxFifos[index].fifoHead += 1; + if (rxFifos[index].fifoHead >= GetRxFifoDepth(channel)) + { + rxFifos[index].fifoHead = 0; + } + + if (CAN_RX_MSG_OVERFLOW == (rxMsgStatus & CAN_RX_MSG_OVERFLOW)) + { + FIFO[channel].STAL &= ~0x8; + } + + status = 1; + } + } + + return status; +} + +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg) +{ + uint8_t index; + _Bool status = 0; + + for (index = 0; index < (1U); index++) + { + status = Receive(index, rxFifos[index].channel, rxCanMsg); + + if (status) + { + break; + } + } + + return status; +} + +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS channel, CAN_MSG_OBJ *rxCanMsg) +{ + uint8_t index; + _Bool status = 0; + + for (index = 0; index < (1U); index++) + { + if (channel == rxFifos[index].channel) + { + status = Receive(index, channel, rxCanMsg); + break; + } + } + + return status; +} + +uint8_t CAN1_ReceivedMessageCountGet(void) +{ + uint8_t index, totalMsgObj = 0; + + for (index = 0; index < (1U); index++) + { + CAN1_RX_FIFO_CHANNELS channel = rxFifos[index].channel; + CAN_RX_FIFO_STATUS rxMsgStatus = GetRxFifoStatus(channel); + + if (CAN_RX_MSG_AVAILABLE == (rxMsgStatus & CAN_RX_MSG_AVAILABLE)) + { + uint8_t numOfMsg, fifoDepth = GetRxFifoDepth(channel); + + if (CAN_RX_MSG_OVERFLOW == (rxMsgStatus & CAN_RX_MSG_OVERFLOW)) + { + numOfMsg = fifoDepth; + } + else + { + uint8_t fifoTail = FIFO[channel].STAH & 0x1F; + uint8_t fifoHead = rxFifos[index].fifoHead; + + if (fifoTail < fifoHead) + { + numOfMsg = ((fifoTail + fifoDepth) - fifoHead); + } + else if (fifoTail > fifoHead) + { + numOfMsg = fifoTail - fifoHead; + } + else + { + numOfMsg = fifoDepth; + } + } + + totalMsgObj += numOfMsg; + } + } + + return totalMsgObj; +} + +static _Bool isTxChannel(uint8_t channel) +{ + return channel < 4u && (FIFO[channel].CONL & 0x80); +} + +static CAN_TX_FIFO_STATUS GetTxFifoStatus(uint8_t validChannel) +{ + return (FIFO[validChannel].STAL & 0x1); +} + +static void WriteMessageToFifo(uint8_t *txFifoObj, CAN_MSG_OBJ *txCanMsg) +{ + uint32_t msgId = txCanMsg->msgId; + uint8_t status; + const uint8_t payloadOffsetBytes = + 4U + + 1U + + 1U + + 2U; + + if (CAN_FRAME_EXT == txCanMsg->field.idType) + { + txFifoObj[1] = (msgId << (3U)) & (0xF8U); + msgId >>= (5U); + txFifoObj[2] = msgId; + msgId >>= (8U); + txFifoObj[3] = (msgId & (0x1FU)); + msgId >>= (5U); + } + else + { + txFifoObj[1] = txFifoObj[2] = txFifoObj[3] = 0; + } + + txFifoObj[0] = msgId; + msgId >>= (8U); + txFifoObj[1] |= (msgId & (0x07U)); + + status = txCanMsg->field.dlc; + status |= (txCanMsg->field.idType << (4U)); + status |= (txCanMsg->field.frameType << (5U)); + status |= (txCanMsg->field.brs << (6U)); + status |= (txCanMsg->field.formatType << (7U)); + txFifoObj[4] = status; + + if (CAN_FRAME_DATA == txCanMsg->field.frameType) + { + memcpy(txFifoObj + payloadOffsetBytes, txCanMsg->data, (DLC_BYTES[(txCanMsg->field.dlc)])); + } +} + +static CAN_TX_MSG_REQUEST_STATUS ValidateTransmission(uint8_t validChannel, CAN_MSG_OBJ *txCanMsg) +{ + CAN_TX_MSG_REQUEST_STATUS txMsgStatus = CAN_TX_MSG_REQUEST_SUCCESS; + CAN_MSG_FIELD field = txCanMsg->field; + uint8_t plsize = 0; + + if (CAN_BRS_MODE == field.brs && (CAN_NORMAL_2_0_MODE == CAN1_OperationModeGet())) + { + txMsgStatus |= CAN_TX_MSG_REQUEST_BRS_ERROR; + } + + if (field.dlc > DLC_8 && (CAN_2_0_FORMAT == field.formatType || CAN_NORMAL_2_0_MODE == CAN1_OperationModeGet())) + { + txMsgStatus |= CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR; + } + + if ((DLC_BYTES[(field.dlc)]) > ((DLC_BYTES[(8u + (plsize))]))) + { + txMsgStatus |= CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR; + } + + if (CAN_TX_FIFO_FULL == GetTxFifoStatus(validChannel)) + { + txMsgStatus |= CAN_TX_MSG_REQUEST_FIFO_FULL; + } + + return txMsgStatus; +} + +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg) +{ + CAN_TX_MSG_REQUEST_STATUS status = CAN_TX_MSG_REQUEST_FIFO_FULL; + + if (isTxChannel(fifoChannel)) + { + status = ValidateTransmission(fifoChannel, txCanMsg); + if (CAN_TX_MSG_REQUEST_SUCCESS == status) + { + uint8_t *txFifoObj = (uint8_t *) FIFO[fifoChannel].UA; + + if (txFifoObj != ((void*)0)) + { + WriteMessageToFifo(txFifoObj, txCanMsg); + FIFO[fifoChannel].CONH |= (0x2 | 0x1); + } + } + } + + return status; +} + +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel) +{ + CAN_TX_FIFO_STATUS status = CAN_TX_FIFO_FULL; + + if (isTxChannel(fifoChannel)) + { + status = GetTxFifoStatus(fifoChannel); + } + + return status; +} + +_Bool CAN1_IsBusOff(void) +{ + return C1TRECUbits.TXBO; +} + +_Bool CAN1_IsRxErrorPassive(void) +{ + return C1TRECUbits.RXBP; +} + +_Bool CAN1_IsRxErrorWarning(void) +{ + return C1TRECUbits.RXWARN; +} + +_Bool CAN1_IsRxErrorActive(void) +{ + return !CAN1_IsRxErrorPassive(); +} + +_Bool CAN1_IsTxErrorPassive(void) +{ + return C1TRECUbits.TXBP; +} + +_Bool CAN1_IsTxErrorWarning(void) +{ + return C1TRECUbits.TXWARN; +} + +_Bool CAN1_IsTxErrorActive(void) +{ + return !CAN1_IsTxErrorPassive(); +} + +void CAN1_Sleep(void) +{ + C1INTHbits.WAKIF = 0; + C1INTTbits.WAKIE = 1; + + CAN1_OperationModeSet(CAN_DISABLE_MODE); +} + +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)) +{ + CAN1_InvalidMessageHandler = handler; +} + +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)) +{ + CAN1_BusWakeUpActivityHandler = handler; +} + +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)) +{ + CAN1_BusErrorHandler = handler; +} + +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)) +{ + CAN1_ModeChangeHandler = handler; +} + +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)) +{ + CAN1_SystemErrorHandler = handler; +} + +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)) +{ + CAN1_TxAttemptHandler = handler; +} + +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)) +{ + CAN1_RxBufferOverflowHandler = handler; +} + +void CAN1_ISR(void) +{ + if (1 == C1INTHbits.IVMIF) + { + CAN1_InvalidMessageHandler(); + C1INTHbits.IVMIF = 0; + } + + if (1 == C1INTHbits.WAKIF) + { + CAN1_BusWakeUpActivityHandler(); + C1INTHbits.WAKIF = 0; + } + + if (1 == C1INTHbits.CERRIF) + { + CAN1_BusErrorHandler(); + C1INTHbits.CERRIF = 0; + } + + if (1 == C1INTLbits.MODIF) + { + CAN1_ModeChangeHandler(); + C1INTLbits.MODIF = 0; + } + + if (1 == C1INTHbits.SERRIF) + { + CAN1_SystemErrorHandler(); + C1INTHbits.SERRIF = 0; + } + + if (1 == C1INTHbits.TXATIF) + { + CAN1_TxAttemptHandler(); + if (1 == C1TXQSTALbits.TXATIF) + { + C1TXQSTALbits.TXATIF = 0; + } + } + + if (1 == C1INTHbits.RXOVIF) + { + CAN1_RxBufferOverflowHandler(); + if (1 == C1FIFOSTA1Lbits.RXOVIF) + { + C1FIFOSTA1Lbits.RXOVIF = 0; + } + } + + PIR0bits.CANIF = 0; +} + +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)) +{ + CAN1_FIFO1NotEmptyHandler = handler; +} + + +void CAN1_RXI_ISR(void) +{ + if (1 == C1FIFOSTA1Lbits.TFNRFNIF) + { + CAN1_FIFO1NotEmptyHandler(); + + } + +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/can1.p1 b/ETC.X/build/default/debug/mcc_generated_files/can1.p1 new file mode 100644 index 0000000..f4b0117 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/can1.p1 @@ -0,0 +1,5761 @@ +Version 4.0 HI-TECH Software Intermediate Code +"69 mcc_generated_files/can_types.h +[; ;mcc_generated_files/can_types.h: 69: { +[s S3178 :1 `uc 1 :1 `uc 1 :4 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3178 . idType frameType dlc formatType brs ] +"66 +[; ;mcc_generated_files/can_types.h: 66: { +[u S3177 `uc 1 `S3178 1 ] +[n S3177 . msgfields . ] +"79 +[; ;mcc_generated_files/can_types.h: 79: { +[s S3179 `ul 1 `S3177 1 `*uc 1 ] +[n S3179 . msgId field data ] +"103 mcc_generated_files/can1.c +[; ;mcc_generated_files/can1.c: 103: static struct CAN1_RX_FIFO rxFifos[] = +[c E22386 1 .. ] +[n E22386 . FIFO1 ] +"95 +[; ;mcc_generated_files/can1.c: 95: { +[s S3183 `E22386 1 `Vuc 1 ] +[n S3183 CAN1_RX_FIFO channel fifoHead ] +"74 +[; ;mcc_generated_files/can1.c: 74: { +[s S3182 `uc 1 `uc 1 `uc 1 `uc 1 `uc 1 `uc 1 `uc 1 `uc 1 `ul 1 ] +[n S3182 CAN_FIFOREG CONL CONH CONU CONT STAL STAH STAU STAT UA ] +"13519 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13519: extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); +[v _C1TXQCONL `Vuc ~T0 @X0 0 e@336 ] +[v F23154 `(v ~T0 @X0 0 tf ] +[v F23156 `(v ~T0 @X0 0 tf ] +[v F23158 `(v ~T0 @X0 0 tf ] +[v F23160 `(v ~T0 @X0 0 tf ] +[v F23162 `(v ~T0 @X0 0 tf ] +[v F23164 `(v ~T0 @X0 0 tf ] +[v F23166 `(v ~T0 @X0 0 tf ] +[v F23168 `(v ~T0 @X0 0 tf ] +"99 mcc_generated_files/../MESSAGES.h +[; ;mcc_generated_files/../MESSAGES.h: 99: void CANReadMessage (void); +[v _CANReadMessage `(v ~T0 @X0 0 ef ] +"14150 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14150: extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); +[v _C1FIFOCON1L `Vuc ~T0 @X0 0 e@348 ] +"14212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14212: extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); +[v _C1FIFOCON1H `Vuc ~T0 @X0 0 e@349 ] +"14244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14244: extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); +[v _C1FIFOCON1U `Vuc ~T0 @X0 0 e@350 ] +"14314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14314: extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); +[v _C1FIFOCON1T `Vuc ~T0 @X0 0 e@351 ] +[v F22441 `(v ~T0 @X0 0 tf ] +"1324 mcc_generated_files/can1.h +[; ;mcc_generated_files/can1.h: 1324: void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +[v _CAN1_SetFIFO1NotEmptyHandler `(v ~T0 @X0 0 ef1`*F22441 ] +"10508 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10508: struct { +[s S499 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S499 . TXIE RXIE TBCIE MODIE TEFIE ] +"10507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10507: typedef union { +[u S498 `S499 1 ] +[n S498 . . ] +"10516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10516: extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +[v _C1INTUbits `VS498 ~T0 @X0 0 e@286 ] +"751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 751: extern volatile unsigned char NVMADRH __attribute__((address(0x044))); +[s S3037 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3037 . U1RXIF U1TXIF U1EIF U1IF CANRXIF CANTXIF PWM1PIF PWM1IF ] +"750 +[u S3036 `S3037 1 ] +[n S3036 . . ] +"762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 762: unsigned NVMADR9 :1; +[v _PIR4bits `VS3036 ~T0 @X0 0 e@1202 ] +"65302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65302: struct { +[s S3004 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3004 . U1RXIE U1TXIE U1EIE U1IE CANRXIE CANTXIE PWM1PIE PWM1IE ] +"65301 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65301: typedef union { +[u S3003 `S3004 1 ] +[n S3003 . . ] +"65313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65313: extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +[v _PIE4bits `VS3003 ~T0 @X0 0 e@1186 ] +"17439 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17439: extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); +[v _C1FLTOBJ1L `Vuc ~T0 @X0 0 e@404 ] +"17509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17509: extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); +[v _C1FLTOBJ1H `Vuc ~T0 @X0 0 e@405 ] +"17585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17585: extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); +[v _C1FLTOBJ1U `Vuc ~T0 @X0 0 e@406 ] +"17655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17655: extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); +[v _C1FLTOBJ1T `Vuc ~T0 @X0 0 e@407 ] +"17726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17726: extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); +[v _C1MASK1L `Vuc ~T0 @X0 0 e@408 ] +"17796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17796: extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); +[v _C1MASK1H `Vuc ~T0 @X0 0 e@409 ] +"17872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17872: extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); +[v _C1MASK1U `Vuc ~T0 @X0 0 e@410 ] +"17942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17942: extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); +[v _C1MASK1T `Vuc ~T0 @X0 0 e@411 ] +"16209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16209: extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); +[v _C1FLTCON0H `Vuc ~T0 @X0 0 e@385 ] +"13560 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13560: extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); +[v _C1TXQCONH `Vuc ~T0 @X0 0 e@337 ] +"13592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13592: extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); +[v _C1TXQCONU `Vuc ~T0 @X0 0 e@338 ] +"13662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13662: extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); +[v _C1TXQCONT `Vuc ~T0 @X0 0 e@339 ] +"9233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9233: extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); +[v _C1NBTCFGL `Vuc ~T0 @X0 0 e@260 ] +"9297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9297: extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); +[v _C1NBTCFGH `Vuc ~T0 @X0 0 e@261 ] +"9361 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9361: extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); +[v _C1NBTCFGU `Vuc ~T0 @X0 0 e@262 ] +"9431 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9431: extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); +[v _C1NBTCFGT `Vuc ~T0 @X0 0 e@263 ] +[v F22413 `(v ~T0 @X0 0 tf ] +"924 mcc_generated_files/can1.h +[; ;mcc_generated_files/can1.h: 924: void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +[v _CAN1_SetInvalidMessageInterruptHandler `(v ~T0 @X0 0 ef1`*F22413 ] +[v F22417 `(v ~T0 @X0 0 tf ] +"981 +[; ;mcc_generated_files/can1.h: 981: void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +[v _CAN1_SetBusWakeUpActivityInterruptHandler `(v ~T0 @X0 0 ef1`*F22417 ] +[v F22421 `(v ~T0 @X0 0 tf ] +"1049 +[; ;mcc_generated_files/can1.h: 1049: void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +[v _CAN1_SetBusErrorInterruptHandler `(v ~T0 @X0 0 ef1`*F22421 ] +[v F22425 `(v ~T0 @X0 0 tf ] +"1100 +[; ;mcc_generated_files/can1.h: 1100: void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +[v _CAN1_SetModeChangeInterruptHandler `(v ~T0 @X0 0 ef1`*F22425 ] +[v F22429 `(v ~T0 @X0 0 tf ] +"1169 +[; ;mcc_generated_files/can1.h: 1169: void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +[v _CAN1_SetSystemErrorInterruptHandler `(v ~T0 @X0 0 ef1`*F22429 ] +[v F22433 `(v ~T0 @X0 0 tf ] +"1237 +[; ;mcc_generated_files/can1.h: 1237: void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +[v _CAN1_SetTxAttemptInterruptHandler `(v ~T0 @X0 0 ef1`*F22433 ] +[v F22437 `(v ~T0 @X0 0 tf ] +"1289 +[; ;mcc_generated_files/can1.h: 1289: void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +[v _CAN1_SetRxBufferOverFlowInterruptHandler `(v ~T0 @X0 0 ef1`*F22437 ] +"495 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[s S3028 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3028 . SWIF HLVDIF OSFIF CSWIF TU16AIF CLC1IF CANIF IOCIF ] +"494 +[u S3027 `S3028 1 ] +[n S3027 . . ] +"506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 506: struct { +[v _PIR0bits `VS3027 ~T0 @X0 0 e@1198 ] +"10407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10407: extern volatile unsigned char C1INTL __attribute__((address(0x11C))); +[v _C1INTL `Vuc ~T0 @X0 0 e@284 ] +"10451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10451: extern volatile unsigned char C1INTH __attribute__((address(0x11D))); +[v _C1INTH `Vuc ~T0 @X0 0 e@285 ] +"10502 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10502: extern volatile unsigned char C1INTU __attribute__((address(0x11E))); +[v _C1INTU `Vuc ~T0 @X0 0 e@286 ] +"10546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10546: extern volatile unsigned char C1INTT __attribute__((address(0x11F))); +[v _C1INTT `Vuc ~T0 @X0 0 e@287 ] +"65046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65046: struct { +[s S2995 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2995 . SWIE HLVDIE OSFIE CSWIE TU16AIE CLC1IE CANIE IOCIE ] +"65045 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65045: typedef union { +[u S2994 `S2995 1 ] +[n S2994 . . ] +"65057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65057: extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +[v _PIE0bits `VS2994 ~T0 @X0 0 e@1182 ] +"9020 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9020: struct { +[s S423 :1 `uc 1 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S423 . WAKFIL WFT BUSY BRSDIS SIDL FRZ ON ] +"9029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9029: struct { +[s S424 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S424 . . WFT0 WFT1 ] +"9019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9019: typedef union { +[u S422 `S423 1 `S424 1 ] +[n S422 . . . ] +"9035 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9035: extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +[v _C1CONHbits `VS422 ~T0 @X0 0 e@257 ] +"274 mcc_generated_files/can1.c +[; ;mcc_generated_files/can1.c: 274: if (CAN_OP_MODE_REQUEST_SUCCESS == CAN1_OperationModeSet(CAN_CONFIGURATION_MODE)) +[c E22356 0 1 2 .. ] +[n E22356 . CAN_OP_MODE_REQUEST_SUCCESS CAN_OP_MODE_REQUEST_FAIL CAN_OP_MODE_SYS_ERROR_OCCURED ] +[c E22346 0 1 2 3 4 5 6 7 .. ] +[n E22346 . CAN_NORMAL_FD_MODE CAN_DISABLE_MODE CAN_INTERNAL_LOOPBACK_MODE CAN_LISTEN_ONLY_MODE CAN_CONFIGURATION_MODE CAN_EXTERNAL_LOOPBACK_MODE CAN_NORMAL_2_0_MODE CAN_RESTRICTED_OPERATION_MODE ] +"147 mcc_generated_files/can1.h +[; ;mcc_generated_files/can1.h: 147: CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +[v _CAN1_OperationModeSet `(E22356 ~T0 @X0 0 ef1`CE22346 ] +"13232 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13232: extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); +[v _C1FIFOBA `Vul ~T0 @X0 0 e@332 ] +"8944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8944: extern volatile unsigned char C1CONL __attribute__((address(0x100))); +[v _C1CONL `Vuc ~T0 @X0 0 e@256 ] +"9014 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9014: extern volatile unsigned char C1CONH __attribute__((address(0x101))); +[v _C1CONH `Vuc ~T0 @X0 0 e@257 ] +"9085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9085: extern volatile unsigned char C1CONU __attribute__((address(0x102))); +[v _C1CONU `Vuc ~T0 @X0 0 e@258 ] +"1728 +[s S3069 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3069 . TRISB0 TRISB1 TRISB2 TRISB3 TRISB4 TRISB5 TRISB6 TRISB7 ] +"1727 +[u S3068 `S3069 1 ] +[n S3068 . . ] +"1739 +[v _TRISBbits `VS3068 ~T0 @X0 0 e@1223 ] +"1542 +[s S3063 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3063 . LATB0 LATB1 LATB2 LATB3 LATB4 LATB5 LATB6 LATB7 ] +"1541 +[u S3062 `S3063 1 ] +[n S3062 . . ] +"1553 +[v _LATBbits `VS3062 ~T0 @X0 0 e@1215 ] +"185 mcc_generated_files/can1.h +[; ;mcc_generated_files/can1.h: 185: CAN_OP_MODES CAN1_OperationModeGet(void); +[v _CAN1_OperationModeGet `(E22346 ~T0 @X0 0 ef ] +"9162 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9162: struct { +[s S429 :3 `uc 1 :1 `uc 1 :4 `uc 1 ] +[n S429 . REQOP ABAT TXBWS ] +"9167 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9167: struct { +[s S430 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S430 . REQOP0 REQOP1 REQOP2 . TXBWS0 TXBWS1 TXBWS2 TXBWS3 ] +"9161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9161: typedef union { +[u S428 `S429 1 `S430 1 ] +[n S428 . . . ] +"9178 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9178: extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +[v _C1CONTbits `VS428 ~T0 @X0 0 e@259 ] +"10457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10457: struct { +[s S497 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S497 . . TXATIF RXOVIF SERRIF CERRIF WAKIF IVMIF ] +"10456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10456: typedef union { +[u S496 `S497 1 ] +[n S496 . . ] +"10467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10467: extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +[v _C1INTHbits `VS496 ~T0 @X0 0 e@285 ] +"9091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9091: struct { +[s S426 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :3 `uc 1 ] +[n S426 . RTXAT ESIGM SERR2LOM STEF TXQEN OPMOD ] +"9099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9099: struct { +[s S427 :5 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S427 . . OPMOD0 OPMOD1 OPMOD2 ] +"9090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9090: typedef union { +[u S425 `S426 1 `S427 1 ] +[n S425 . . . ] +"9106 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9106: extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +[v _C1CONUbits `VS425 ~T0 @X0 0 e@258 ] +"341 mcc_generated_files/can1.c +[; ;mcc_generated_files/can1.c: 341: static CAN_RX_FIFO_STATUS GetRxFifoStatus(uint8_t validChannel) +[c E23140 0 1 8 .. ] +[n E23140 . CAN_RX_MSG_NOT_AVAILABLE CAN_RX_MSG_AVAILABLE CAN_RX_MSG_OVERFLOW ] +"357 +[; ;mcc_generated_files/can1.c: 357: rxCanMsg->field.idType = (status & (1UL << (4U))) ? CAN_FRAME_EXT : CAN_FRAME_STD; +[c E22328 0 1 .. ] +[n E22328 . CAN_FRAME_STD CAN_FRAME_EXT ] +"358 +[; ;mcc_generated_files/can1.c: 358: rxCanMsg->field.frameType = (status & (1UL << (5U))) ? CAN_FRAME_RTR : CAN_FRAME_DATA; +[c E22332 0 1 .. ] +[n E22332 . CAN_FRAME_DATA CAN_FRAME_RTR ] +"359 +[; ;mcc_generated_files/can1.c: 359: rxCanMsg->field.brs = (status & (1UL << (6U))) ? CAN_BRS_MODE : CAN_NON_BRS_MODE; +[c E22324 0 1 .. ] +[n E22324 . CAN_NON_BRS_MODE CAN_BRS_MODE ] +"27 C:\Program Files\Microchip\xc8\v2.31\pic\include\c99\string.h +[; ;C:\Program Files\Microchip\xc8\v2.31\pic\include\c99\string.h: 27: void *memcpy (void *restrict, const void *restrict, size_t); +[v _memcpy `(*v ~T0 @X0 0 ef3`*v`*Cv`ui ] +"495 mcc_generated_files/can1.c +[; ;mcc_generated_files/can1.c: 495: static CAN_TX_FIFO_STATUS GetTxFifoStatus(uint8_t validChannel) +[c E22361 0 1 .. ] +[n E22361 . CAN_TX_FIFO_FULL CAN_TX_FIFO_AVAILABLE ] +"541 +[; ;mcc_generated_files/can1.c: 541: static CAN_TX_MSG_REQUEST_STATUS ValidateTransmission(uint8_t validChannel, CAN_MSG_OBJ *txCanMsg) +[c E22340 0 1 2 3 .. ] +[n E22340 . CAN_TX_MSG_REQUEST_SUCCESS CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR CAN_TX_MSG_REQUEST_BRS_ERROR CAN_TX_MSG_REQUEST_FIFO_FULL ] +"552 +[; ;mcc_generated_files/can1.c: 552: if (field.dlc > DLC_8 && (CAN_2_0_FORMAT == field.formatType || CAN_NORMAL_2_0_MODE == CAN1_OperationModeGet())) +[c E22365 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 .. ] +[n E22365 . DLC_0 DLC_1 DLC_2 DLC_3 DLC_4 DLC_5 DLC_6 DLC_7 DLC_8 DLC_12 DLC_16 DLC_20 DLC_24 DLC_32 DLC_48 DLC_64 ] +[c E22336 0 1 .. ] +[n E22336 . CAN_2_0_FORMAT CAN_FD_FORMAT ] +"570 +[; ;mcc_generated_files/can1.c: 570: CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg) +[c E22383 0 .. ] +[n E22383 . TXQ ] +"12170 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12170: struct { +[s S569 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S569 . EWARN RXWARN TXWARN RXBP TXBP TXBO ] +"12169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12169: typedef union { +[u S568 `S569 1 ] +[n S568 . . ] +"12179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12179: extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +[v _C1TRECUbits `VS568 ~T0 @X0 0 e@310 ] +"10552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10552: struct { +[s S501 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S501 . . TXATIE RXOVIE SERRIE CERRIE WAKIE IVMIE ] +"10551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10551: typedef union { +[u S500 `S501 1 ] +[n S500 . . ] +"10562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10562: extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +[v _C1INTTbits `VS500 ~T0 @X0 0 e@287 ] +[v F23266 `(v ~T0 @X0 0 tf ] +[v F23268 `(v ~T0 @X0 0 tf ] +[v F23271 `(v ~T0 @X0 0 tf ] +[v F23273 `(v ~T0 @X0 0 tf ] +[v F23276 `(v ~T0 @X0 0 tf ] +[v F23278 `(v ~T0 @X0 0 tf ] +[v F23281 `(v ~T0 @X0 0 tf ] +[v F23283 `(v ~T0 @X0 0 tf ] +[v F23286 `(v ~T0 @X0 0 tf ] +[v F23288 `(v ~T0 @X0 0 tf ] +[v F23291 `(v ~T0 @X0 0 tf ] +[v F23293 `(v ~T0 @X0 0 tf ] +[v F23296 `(v ~T0 @X0 0 tf ] +[v F23298 `(v ~T0 @X0 0 tf ] +"10413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10413: struct { +[s S495 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S495 . TXIF RXIF TBCIF MODIF TEFIF ] +"10412 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10412: typedef union { +[u S494 `S495 1 ] +[n S494 . . ] +"10421 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10421: extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +[v _C1INTLbits `VS494 ~T0 @X0 0 e@284 ] +"13744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13744: struct { +[s S636 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S636 . TXQNIF . TXQEIF . TXATIF TXERR TXLARB TXABT ] +"13743 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13743: typedef union { +[u S635 `S636 1 ] +[n S635 . . ] +"13755 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13755: extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +[v _C1TXQSTALbits `VS635 ~T0 @X0 0 e@340 ] +"14403 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14403: struct { +[s S663 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S663 . TFNRFNIF TFHRFHIF TFERFFIF RXOVIF TXATIF TXERR TXLARB TXABT ] +"14402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14402: typedef union { +[u S662 `S663 1 ] +[n S662 . . ] +"14414 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14414: extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +[v _C1FIFOSTA1Lbits `VS662 ~T0 @X0 0 e@352 ] +[v F23302 `(v ~T0 @X0 0 tf ] +[v F23304 `(v ~T0 @X0 0 tf ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"22 mcc_generated_files/../MESSAGES.h +[; ;mcc_generated_files/../MESSAGES.h: 22: CAN_MSG_OBJ msgTransmit; +[v _msgTransmit `S3179 ~T0 @X0 1 e ] +"23 +[; ;mcc_generated_files/../MESSAGES.h: 23: CAN_MSG_OBJ msgReceipt; +[v _msgReceipt `S3179 ~T0 @X0 1 e ] +"24 +[; ;mcc_generated_files/../MESSAGES.h: 24: uint8_t CANDATAdata[8]; +[v _CANDATAdata `uc ~T0 @X0 -> 8 `i e ] +"101 mcc_generated_files/can1.c +[; ;mcc_generated_files/can1.c: 101: static volatile uint8_t rxMsgData[(8U)]; +[v _rxMsgData `Vuc ~T0 @X0 -> 8 `i s ] +"103 +[; ;mcc_generated_files/can1.c: 103: static struct CAN1_RX_FIFO rxFifos[] = +[v _rxFifos `S3183 ~T0 @X0 -> -> 1 `i `ux s ] +[i _rxFifos +:U .. +:U .. +. `E22386 0 +-> -> 0 `ui `uc +.. +.. +] +[v F23151 `*VS3182 ~T0 @X0 1 t ] +"108 +[; ;mcc_generated_files/can1.c: 108: static volatile struct CAN_FIFOREG * const FIFO = (struct CAN_FIFOREG *)&C1TXQCONL; +[v _FIFO `C*VS3182 ~T0 @X0 1 s ] +[i _FIFO +-> -> &U _C1TXQCONL `*S3182 `*VS3182 +] +"109 +[; ;mcc_generated_files/can1.c: 109: static const uint8_t DLC_BYTES[] = {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U}; +[v _DLC_BYTES `Cuc ~T0 @X0 -> 9 `i s ] +[i _DLC_BYTES +:U .. +-> -> 0 `ui `uc +-> -> 1 `ui `uc +-> -> 2 `ui `uc +-> -> 3 `ui `uc +-> -> 4 `ui `uc +-> -> 5 `ui `uc +-> -> 6 `ui `uc +-> -> 7 `ui `uc +-> -> 8 `ui `uc +.. +] +"111 +[; ;mcc_generated_files/can1.c: 111: static void (*CAN1_FIFO1NotEmptyHandler)(void); +[v _CAN1_FIFO1NotEmptyHandler `*F23154 ~T0 @X0 1 s ] +"112 +[; ;mcc_generated_files/can1.c: 112: static void (*CAN1_InvalidMessageHandler)(void); +[v _CAN1_InvalidMessageHandler `*F23156 ~T0 @X0 1 s ] +"113 +[; ;mcc_generated_files/can1.c: 113: static void (*CAN1_BusWakeUpActivityHandler)(void); +[v _CAN1_BusWakeUpActivityHandler `*F23158 ~T0 @X0 1 s ] +"114 +[; ;mcc_generated_files/can1.c: 114: static void (*CAN1_BusErrorHandler)(void); +[v _CAN1_BusErrorHandler `*F23160 ~T0 @X0 1 s ] +"115 +[; ;mcc_generated_files/can1.c: 115: static void (*CAN1_ModeChangeHandler)(void); +[v _CAN1_ModeChangeHandler `*F23162 ~T0 @X0 1 s ] +"116 +[; ;mcc_generated_files/can1.c: 116: static void (*CAN1_SystemErrorHandler)(void); +[v _CAN1_SystemErrorHandler `*F23164 ~T0 @X0 1 s ] +"117 +[; ;mcc_generated_files/can1.c: 117: static void (*CAN1_TxAttemptHandler)(void); +[v _CAN1_TxAttemptHandler `*F23166 ~T0 @X0 1 s ] +"118 +[; ;mcc_generated_files/can1.c: 118: static void (*CAN1_RxBufferOverflowHandler)(void); +[v _CAN1_RxBufferOverflowHandler `*F23168 ~T0 @X0 1 s ] +"120 +[; ;mcc_generated_files/can1.c: 120: static void DefaultFIFO1NotEmptyHandler(void) +[v _DefaultFIFO1NotEmptyHandler `(v ~T0 @X0 1 sf ] +"121 +[; ;mcc_generated_files/can1.c: 121: { +{ +[e :U _DefaultFIFO1NotEmptyHandler ] +[f ] +"122 +[; ;mcc_generated_files/can1.c: 122: CANReadMessage(); +[e ( _CANReadMessage .. ] +"123 +[; ;mcc_generated_files/can1.c: 123: } +[e :UE 3184 ] +} +"125 +[; ;mcc_generated_files/can1.c: 125: static void DefaultInvalidMessageHandler(void) +[v _DefaultInvalidMessageHandler `(v ~T0 @X0 1 sf ] +"126 +[; ;mcc_generated_files/can1.c: 126: { +{ +[e :U _DefaultInvalidMessageHandler ] +[f ] +"127 +[; ;mcc_generated_files/can1.c: 127: } +[e :UE 3185 ] +} +"129 +[; ;mcc_generated_files/can1.c: 129: static void DefaultBusWakeUpActivityHandler(void) +[v _DefaultBusWakeUpActivityHandler `(v ~T0 @X0 1 sf ] +"130 +[; ;mcc_generated_files/can1.c: 130: { +{ +[e :U _DefaultBusWakeUpActivityHandler ] +[f ] +"131 +[; ;mcc_generated_files/can1.c: 131: } +[e :UE 3186 ] +} +"133 +[; ;mcc_generated_files/can1.c: 133: static void DefaultBusErrorHandler(void) +[v _DefaultBusErrorHandler `(v ~T0 @X0 1 sf ] +"134 +[; ;mcc_generated_files/can1.c: 134: { +{ +[e :U _DefaultBusErrorHandler ] +[f ] +"135 +[; ;mcc_generated_files/can1.c: 135: } +[e :UE 3187 ] +} +"137 +[; ;mcc_generated_files/can1.c: 137: static void DefaultModeChangeHandler(void) +[v _DefaultModeChangeHandler `(v ~T0 @X0 1 sf ] +"138 +[; ;mcc_generated_files/can1.c: 138: { +{ +[e :U _DefaultModeChangeHandler ] +[f ] +"139 +[; ;mcc_generated_files/can1.c: 139: } +[e :UE 3188 ] +} +"141 +[; ;mcc_generated_files/can1.c: 141: static void DefaultSystemErrorHandler(void) +[v _DefaultSystemErrorHandler `(v ~T0 @X0 1 sf ] +"142 +[; ;mcc_generated_files/can1.c: 142: { +{ +[e :U _DefaultSystemErrorHandler ] +[f ] +"143 +[; ;mcc_generated_files/can1.c: 143: } +[e :UE 3189 ] +} +"145 +[; ;mcc_generated_files/can1.c: 145: static void DefaultTxAttemptHandler(void) +[v _DefaultTxAttemptHandler `(v ~T0 @X0 1 sf ] +"146 +[; ;mcc_generated_files/can1.c: 146: { +{ +[e :U _DefaultTxAttemptHandler ] +[f ] +"147 +[; ;mcc_generated_files/can1.c: 147: } +[e :UE 3190 ] +} +"149 +[; ;mcc_generated_files/can1.c: 149: static void DefaultRxBufferOverflowHandler(void) +[v _DefaultRxBufferOverflowHandler `(v ~T0 @X0 1 sf ] +"150 +[; ;mcc_generated_files/can1.c: 150: { +{ +[e :U _DefaultRxBufferOverflowHandler ] +[f ] +"151 +[; ;mcc_generated_files/can1.c: 151: } +[e :UE 3191 ] +} +"153 +[; ;mcc_generated_files/can1.c: 153: void CAN1_RX_FIFO_ResetInfo(void) +[v _CAN1_RX_FIFO_ResetInfo `(v ~T0 @X0 1 ef ] +"154 +[; ;mcc_generated_files/can1.c: 154: { +{ +[e :U _CAN1_RX_FIFO_ResetInfo ] +[f ] +"155 +[; ;mcc_generated_files/can1.c: 155: uint8_t index; +[v _index `uc ~T0 @X0 1 a ] +"157 +[; ;mcc_generated_files/can1.c: 157: for (index = 0; index < (1U); index++) +{ +[e = _index -> -> 0 `i `uc ] +[e $ < -> _index `ui -> 1 `ui 3193 ] +[e $U 3194 ] +[e :U 3193 ] +"158 +[; ;mcc_generated_files/can1.c: 158: { +{ +"159 +[; ;mcc_generated_files/can1.c: 159: rxFifos[index].fifoHead = 0; +[e = . *U + &U _rxFifos * -> _index `ux -> -> # *U &U _rxFifos `ui `ux 1 -> -> 0 `i `uc ] +"160 +[; ;mcc_generated_files/can1.c: 160: } +} +[e ++ _index -> -> 1 `i `uc ] +[e $ < -> _index `ui -> 1 `ui 3193 ] +[e :U 3194 ] +} +"161 +[; ;mcc_generated_files/can1.c: 161: } +[e :UE 3192 ] +} +"163 +[; ;mcc_generated_files/can1.c: 163: static void CAN1_RX_FIFO_Configuration(void) +[v _CAN1_RX_FIFO_Configuration `(v ~T0 @X0 1 sf ] +"164 +[; ;mcc_generated_files/can1.c: 164: { +{ +[e :U _CAN1_RX_FIFO_Configuration ] +[f ] +"166 +[; ;mcc_generated_files/can1.c: 166: C1FIFOCON1L = 0x19; +[e = _C1FIFOCON1L -> -> 25 `i `uc ] +"169 +[; ;mcc_generated_files/can1.c: 169: C1FIFOCON1H = 0x04; +[e = _C1FIFOCON1H -> -> 4 `i `uc ] +"172 +[; ;mcc_generated_files/can1.c: 172: C1FIFOCON1U = 0x60; +[e = _C1FIFOCON1U -> -> 96 `i `uc ] +"175 +[; ;mcc_generated_files/can1.c: 175: C1FIFOCON1T = 0x05; +[e = _C1FIFOCON1T -> -> 5 `i `uc ] +"177 +[; ;mcc_generated_files/can1.c: 177: CAN1_SetFIFO1NotEmptyHandler(DefaultFIFO1NotEmptyHandler); +[e ( _CAN1_SetFIFO1NotEmptyHandler (1 &U _DefaultFIFO1NotEmptyHandler ] +"179 +[; ;mcc_generated_files/can1.c: 179: C1INTUbits.RXIE = 1; +[e = . . _C1INTUbits 0 1 -> -> 1 `i `uc ] +"181 +[; ;mcc_generated_files/can1.c: 181: PIR4bits.CANRXIF = 0; +[e = . . _PIR4bits 0 4 -> -> 0 `i `uc ] +"182 +[; ;mcc_generated_files/can1.c: 182: PIE4bits.CANRXIE = 1; +[e = . . _PIE4bits 0 4 -> -> 1 `i `uc ] +"183 +[; ;mcc_generated_files/can1.c: 183: } +[e :UE 3196 ] +} +"185 +[; ;mcc_generated_files/can1.c: 185: static void CAN1_RX_FIFO_FilterMaskConfiguration(void) +[v _CAN1_RX_FIFO_FilterMaskConfiguration `(v ~T0 @X0 1 sf ] +"186 +[; ;mcc_generated_files/can1.c: 186: { +{ +[e :U _CAN1_RX_FIFO_FilterMaskConfiguration ] +[f ] +"199 +[; ;mcc_generated_files/can1.c: 199: C1FLTOBJ1L = 0x5F; +[e = _C1FLTOBJ1L -> -> 95 `i `uc ] +"200 +[; ;mcc_generated_files/can1.c: 200: C1FLTOBJ1H = 0xFF; +[e = _C1FLTOBJ1H -> -> 255 `i `uc ] +"201 +[; ;mcc_generated_files/can1.c: 201: C1FLTOBJ1U = 0xFF; +[e = _C1FLTOBJ1U -> -> 255 `i `uc ] +"202 +[; ;mcc_generated_files/can1.c: 202: C1FLTOBJ1T = 0xFF; +[e = _C1FLTOBJ1T -> -> 255 `i `uc ] +"204 +[; ;mcc_generated_files/can1.c: 204: C1MASK1L = 0x00; +[e = _C1MASK1L -> -> 0 `i `uc ] +"205 +[; ;mcc_generated_files/can1.c: 205: C1MASK1H = 0x00; +[e = _C1MASK1H -> -> 0 `i `uc ] +"206 +[; ;mcc_generated_files/can1.c: 206: C1MASK1U = 0x00; +[e = _C1MASK1U -> -> 0 `i `uc ] +"207 +[; ;mcc_generated_files/can1.c: 207: C1MASK1T = 0x00; +[e = _C1MASK1T -> -> 0 `i `uc ] +"208 +[; ;mcc_generated_files/can1.c: 208: C1FLTCON0H = 0x81; +[e = _C1FLTCON0H -> -> 129 `i `uc ] +"209 +[; ;mcc_generated_files/can1.c: 209: } +[e :UE 3197 ] +} +"211 +[; ;mcc_generated_files/can1.c: 211: static void CAN1_TX_FIFO_Configuration(void) +[v _CAN1_TX_FIFO_Configuration `(v ~T0 @X0 1 sf ] +"212 +[; ;mcc_generated_files/can1.c: 212: { +{ +[e :U _CAN1_TX_FIFO_Configuration ] +[f ] +"214 +[; ;mcc_generated_files/can1.c: 214: C1TXQCONL = 0x10; +[e = _C1TXQCONL -> -> 16 `i `uc ] +"217 +[; ;mcc_generated_files/can1.c: 217: C1TXQCONH = 0x04; +[e = _C1TXQCONH -> -> 4 `i `uc ] +"220 +[; ;mcc_generated_files/can1.c: 220: C1TXQCONU = 0x61; +[e = _C1TXQCONU -> -> 97 `i `uc ] +"223 +[; ;mcc_generated_files/can1.c: 223: C1TXQCONT = 0x05; +[e = _C1TXQCONT -> -> 5 `i `uc ] +"225 +[; ;mcc_generated_files/can1.c: 225: } +[e :UE 3198 ] +} +"227 +[; ;mcc_generated_files/can1.c: 227: static void CAN1_BitRateConfiguration(void) +[v _CAN1_BitRateConfiguration `(v ~T0 @X0 1 sf ] +"228 +[; ;mcc_generated_files/can1.c: 228: { +{ +[e :U _CAN1_BitRateConfiguration ] +[f ] +"230 +[; ;mcc_generated_files/can1.c: 230: C1NBTCFGL = 0x01; +[e = _C1NBTCFGL -> -> 1 `i `uc ] +"233 +[; ;mcc_generated_files/can1.c: 233: C1NBTCFGH = 0x01; +[e = _C1NBTCFGH -> -> 1 `i `uc ] +"236 +[; ;mcc_generated_files/can1.c: 236: C1NBTCFGU = 0x06; +[e = _C1NBTCFGU -> -> 6 `i `uc ] +"239 +[; ;mcc_generated_files/can1.c: 239: C1NBTCFGT = 0x00; +[e = _C1NBTCFGT -> -> 0 `i `uc ] +"241 +[; ;mcc_generated_files/can1.c: 241: } +[e :UE 3199 ] +} +"243 +[; ;mcc_generated_files/can1.c: 243: static void CAN1_ErrorNotificationInterruptEnable(void) +[v _CAN1_ErrorNotificationInterruptEnable `(v ~T0 @X0 1 sf ] +"244 +[; ;mcc_generated_files/can1.c: 244: { +{ +[e :U _CAN1_ErrorNotificationInterruptEnable ] +[f ] +"245 +[; ;mcc_generated_files/can1.c: 245: CAN1_SetInvalidMessageInterruptHandler(DefaultInvalidMessageHandler); +[e ( _CAN1_SetInvalidMessageInterruptHandler (1 &U _DefaultInvalidMessageHandler ] +"246 +[; ;mcc_generated_files/can1.c: 246: CAN1_SetBusWakeUpActivityInterruptHandler(DefaultBusWakeUpActivityHandler); +[e ( _CAN1_SetBusWakeUpActivityInterruptHandler (1 &U _DefaultBusWakeUpActivityHandler ] +"247 +[; ;mcc_generated_files/can1.c: 247: CAN1_SetBusErrorInterruptHandler(DefaultBusErrorHandler); +[e ( _CAN1_SetBusErrorInterruptHandler (1 &U _DefaultBusErrorHandler ] +"248 +[; ;mcc_generated_files/can1.c: 248: CAN1_SetModeChangeInterruptHandler(DefaultModeChangeHandler); +[e ( _CAN1_SetModeChangeInterruptHandler (1 &U _DefaultModeChangeHandler ] +"249 +[; ;mcc_generated_files/can1.c: 249: CAN1_SetSystemErrorInterruptHandler(DefaultSystemErrorHandler); +[e ( _CAN1_SetSystemErrorInterruptHandler (1 &U _DefaultSystemErrorHandler ] +"250 +[; ;mcc_generated_files/can1.c: 250: CAN1_SetTxAttemptInterruptHandler(DefaultTxAttemptHandler); +[e ( _CAN1_SetTxAttemptInterruptHandler (1 &U _DefaultTxAttemptHandler ] +"251 +[; ;mcc_generated_files/can1.c: 251: CAN1_SetRxBufferOverFlowInterruptHandler(DefaultRxBufferOverflowHandler); +[e ( _CAN1_SetRxBufferOverFlowInterruptHandler (1 &U _DefaultRxBufferOverflowHandler ] +"252 +[; ;mcc_generated_files/can1.c: 252: PIR0bits.CANIF = 0; +[e = . . _PIR0bits 0 6 -> -> 0 `i `uc ] +"255 +[; ;mcc_generated_files/can1.c: 255: C1INTL = 0x00; +[e = _C1INTL -> -> 0 `i `uc ] +"258 +[; ;mcc_generated_files/can1.c: 258: C1INTH = 0x00; +[e = _C1INTH -> -> 0 `i `uc ] +"261 +[; ;mcc_generated_files/can1.c: 261: C1INTU = 0x0A; +[e = _C1INTU -> -> 10 `i `uc ] +"264 +[; ;mcc_generated_files/can1.c: 264: C1INTT = 0xFC; +[e = _C1INTT -> -> 252 `i `uc ] +"266 +[; ;mcc_generated_files/can1.c: 266: PIE0bits.CANIE = 1; +[e = . . _PIE0bits 0 6 -> -> 1 `i `uc ] +"267 +[; ;mcc_generated_files/can1.c: 267: } +[e :UE 3200 ] +} +"269 +[; ;mcc_generated_files/can1.c: 269: void CAN1_Initialize(void) +[v _CAN1_Initialize `(v ~T0 @X0 1 ef ] +"270 +[; ;mcc_generated_files/can1.c: 270: { +{ +[e :U _CAN1_Initialize ] +[f ] +"272 +[; ;mcc_generated_files/can1.c: 272: C1CONHbits.ON = 1; +[e = . . _C1CONHbits 0 6 -> -> 1 `i `uc ] +"274 +[; ;mcc_generated_files/can1.c: 274: if (CAN_OP_MODE_REQUEST_SUCCESS == CAN1_OperationModeSet(CAN_CONFIGURATION_MODE)) +[e $ ! == -> . `E22356 0 `ui -> ( _CAN1_OperationModeSet (1 . `E22346 4 `ui 3202 ] +"275 +[; ;mcc_generated_files/can1.c: 275: { +{ +"277 +[; ;mcc_generated_files/can1.c: 277: C1FIFOBA = 0x2600; +[e = _C1FIFOBA -> -> -> 9728 `i `l `ul ] +"280 +[; ;mcc_generated_files/can1.c: 280: C1CONL = 0x60; +[e = _C1CONL -> -> 96 `i `uc ] +"283 +[; ;mcc_generated_files/can1.c: 283: C1CONH = 0x97; +[e = _C1CONH -> -> 151 `i `uc ] +"286 +[; ;mcc_generated_files/can1.c: 286: C1CONU = 0x10; +[e = _C1CONU -> -> 16 `i `uc ] +"288 +[; ;mcc_generated_files/can1.c: 288: CAN1_BitRateConfiguration(); +[e ( _CAN1_BitRateConfiguration .. ] +"289 +[; ;mcc_generated_files/can1.c: 289: CAN1_TX_FIFO_Configuration(); +[e ( _CAN1_TX_FIFO_Configuration .. ] +"290 +[; ;mcc_generated_files/can1.c: 290: CAN1_RX_FIFO_Configuration(); +[e ( _CAN1_RX_FIFO_Configuration .. ] +"291 +[; ;mcc_generated_files/can1.c: 291: CAN1_RX_FIFO_FilterMaskConfiguration(); +[e ( _CAN1_RX_FIFO_FilterMaskConfiguration .. ] +"292 +[; ;mcc_generated_files/can1.c: 292: CAN1_RX_FIFO_ResetInfo(); +[e ( _CAN1_RX_FIFO_ResetInfo .. ] +"293 +[; ;mcc_generated_files/can1.c: 293: CAN1_ErrorNotificationInterruptEnable(); +[e ( _CAN1_ErrorNotificationInterruptEnable .. ] +"294 +[; ;mcc_generated_files/can1.c: 294: CAN1_OperationModeSet(CAN_NORMAL_2_0_MODE); +[e ( _CAN1_OperationModeSet (1 . `E22346 6 ] +"297 +[; ;mcc_generated_files/can1.c: 297: do { TRISBbits.TRISB5 = 0; } while(0); +[e :U 3205 ] +{ +[e = . . _TRISBbits 0 5 -> -> 0 `i `uc ] +} +[e :U 3204 ] +"298 +[; ;mcc_generated_files/can1.c: 298: do { LATBbits.LATB5 = 0; } while(0); +[e :U 3208 ] +{ +[e = . . _LATBbits 0 5 -> -> 0 `i `uc ] +} +[e :U 3207 ] +"299 +[; ;mcc_generated_files/can1.c: 299: } +} +[e :U 3202 ] +"300 +[; ;mcc_generated_files/can1.c: 300: } +[e :UE 3201 ] +} +"302 +[; ;mcc_generated_files/can1.c: 302: CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES requestMode) +[v _CAN1_OperationModeSet `(E22356 ~T0 @X0 1 ef1`CE22346 ] +"303 +[; ;mcc_generated_files/can1.c: 303: { +{ +[e :U _CAN1_OperationModeSet ] +"302 +[; ;mcc_generated_files/can1.c: 302: CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES requestMode) +[v _requestMode `CE22346 ~T0 @X0 1 r1 ] +"303 +[; ;mcc_generated_files/can1.c: 303: { +[f ] +"304 +[; ;mcc_generated_files/can1.c: 304: CAN_OP_MODE_STATUS status = CAN_OP_MODE_REQUEST_SUCCESS; +[v _status `E22356 ~T0 @X0 1 a ] +[e = _status . `E22356 0 ] +"305 +[; ;mcc_generated_files/can1.c: 305: CAN_OP_MODES opMode = CAN1_OperationModeGet(); +[v _opMode `E22346 ~T0 @X0 1 a ] +[e = _opMode ( _CAN1_OperationModeGet .. ] +"307 +[; ;mcc_generated_files/can1.c: 307: if (CAN_CONFIGURATION_MODE == opMode +[e $ ! || || == -> . `E22346 4 `ui -> _opMode `ui == -> . `E22346 1 `ui -> _requestMode `ui == -> . `E22346 4 `ui -> _requestMode `ui 3210 ] +"310 +[; ;mcc_generated_files/can1.c: 310: { +{ +"311 +[; ;mcc_generated_files/can1.c: 311: C1CONTbits.REQOP = requestMode; +[e = . . _C1CONTbits 0 0 -> _requestMode `uc ] +"313 +[; ;mcc_generated_files/can1.c: 313: while (C1CONUbits.OPMOD != requestMode) +[e $U 3211 ] +[e :U 3212 ] +"314 +[; ;mcc_generated_files/can1.c: 314: { +{ +"316 +[; ;mcc_generated_files/can1.c: 316: if (1 == C1INTHbits.SERRIF) +[e $ ! == -> 1 `i -> . . _C1INTHbits 0 3 `i 3214 ] +"317 +[; ;mcc_generated_files/can1.c: 317: { +{ +"318 +[; ;mcc_generated_files/can1.c: 318: status = CAN_OP_MODE_SYS_ERROR_OCCURED; +[e = _status . `E22356 2 ] +"319 +[; ;mcc_generated_files/can1.c: 319: break; +[e $U 3213 ] +"320 +[; ;mcc_generated_files/can1.c: 320: } +} +[e :U 3214 ] +"321 +[; ;mcc_generated_files/can1.c: 321: } +} +[e :U 3211 ] +"313 +[; ;mcc_generated_files/can1.c: 313: while (C1CONUbits.OPMOD != requestMode) +[e $ != -> . . _C1CONUbits 0 5 `ui -> _requestMode `ui 3212 ] +[e :U 3213 ] +"322 +[; ;mcc_generated_files/can1.c: 322: } +} +[e $U 3215 ] +"323 +[; ;mcc_generated_files/can1.c: 323: else +[e :U 3210 ] +"324 +[; ;mcc_generated_files/can1.c: 324: { +{ +"325 +[; ;mcc_generated_files/can1.c: 325: status = CAN_OP_MODE_REQUEST_FAIL; +[e = _status . `E22356 1 ] +"326 +[; ;mcc_generated_files/can1.c: 326: } +} +[e :U 3215 ] +"328 +[; ;mcc_generated_files/can1.c: 328: return status; +[e ) _status ] +[e $UE 3209 ] +"329 +[; ;mcc_generated_files/can1.c: 329: } +[e :UE 3209 ] +} +"331 +[; ;mcc_generated_files/can1.c: 331: CAN_OP_MODES CAN1_OperationModeGet(void) +[v _CAN1_OperationModeGet `(E22346 ~T0 @X0 1 ef ] +"332 +[; ;mcc_generated_files/can1.c: 332: { +{ +[e :U _CAN1_OperationModeGet ] +[f ] +"333 +[; ;mcc_generated_files/can1.c: 333: return C1CONUbits.OPMOD; +[e ) -> . . _C1CONUbits 0 5 `E22346 ] +[e $UE 3216 ] +"334 +[; ;mcc_generated_files/can1.c: 334: } +[e :UE 3216 ] +} +"336 +[; ;mcc_generated_files/can1.c: 336: static uint8_t GetRxFifoDepth(uint8_t validChannel) +[v _GetRxFifoDepth `(uc ~T0 @X0 1 sf1`uc ] +"337 +[; ;mcc_generated_files/can1.c: 337: { +{ +[e :U _GetRxFifoDepth ] +"336 +[; ;mcc_generated_files/can1.c: 336: static uint8_t GetRxFifoDepth(uint8_t validChannel) +[v _validChannel `uc ~T0 @X0 1 r1 ] +"337 +[; ;mcc_generated_files/can1.c: 337: { +[f ] +"338 +[; ;mcc_generated_files/can1.c: 338: return 1U + (FIFO[validChannel].CONT & 0x1F); +[e ) -> + -> 1 `ui -> & -> . *U + _FIFO * -> _validChannel `ux -> -> # *U _FIFO `ui `ux 3 `i -> 31 `i `ui `uc ] +[e $UE 3217 ] +"339 +[; ;mcc_generated_files/can1.c: 339: } +[e :UE 3217 ] +} +"341 +[; ;mcc_generated_files/can1.c: 341: static CAN_RX_FIFO_STATUS GetRxFifoStatus(uint8_t validChannel) +[v _GetRxFifoStatus `(E23140 ~T0 @X0 1 sf1`uc ] +"342 +[; ;mcc_generated_files/can1.c: 342: { +{ +[e :U _GetRxFifoStatus ] +"341 +[; ;mcc_generated_files/can1.c: 341: static CAN_RX_FIFO_STATUS GetRxFifoStatus(uint8_t validChannel) +[v _validChannel `uc ~T0 @X0 1 r1 ] +"342 +[; ;mcc_generated_files/can1.c: 342: { +[f ] +"343 +[; ;mcc_generated_files/can1.c: 343: return FIFO[validChannel].STAL & (CAN_RX_MSG_AVAILABLE | CAN_RX_MSG_OVERFLOW); +[e ) -> & -> . *U + _FIFO * -> _validChannel `ux -> -> # *U _FIFO `ui `ux 4 `i | -> . `E23140 1 `i -> . `E23140 2 `i `E23140 ] +[e $UE 3218 ] +"344 +[; ;mcc_generated_files/can1.c: 344: } +[e :UE 3218 ] +} +"346 +[; ;mcc_generated_files/can1.c: 346: static void ReadMessageFromFifo(uint8_t *rxFifoObj, CAN_MSG_OBJ *rxCanMsg) +[v _ReadMessageFromFifo `(v ~T0 @X0 1 sf2`*uc`*S3179 ] +"347 +[; ;mcc_generated_files/can1.c: 347: { +{ +[e :U _ReadMessageFromFifo ] +"346 +[; ;mcc_generated_files/can1.c: 346: static void ReadMessageFromFifo(uint8_t *rxFifoObj, CAN_MSG_OBJ *rxCanMsg) +[v _rxFifoObj `*uc ~T0 @X0 1 r1 ] +[v _rxCanMsg `*S3179 ~T0 @X0 1 r2 ] +"347 +[; ;mcc_generated_files/can1.c: 347: { +[f ] +"348 +[; ;mcc_generated_files/can1.c: 348: uint32_t msgId; +[v _msgId `ul ~T0 @X0 1 a ] +"349 +[; ;mcc_generated_files/can1.c: 349: uint8_t status = rxFifoObj[4]; +[v _status `uc ~T0 @X0 1 a ] +[e = _status *U + _rxFifoObj * -> -> 4 `i `x -> -> # *U _rxFifoObj `i `x ] +"350 +[; ;mcc_generated_files/can1.c: 350: const uint8_t payloadOffsetBytes = +[v _payloadOffsetBytes `Cuc ~T0 @X0 1 a ] +[e = _payloadOffsetBytes -> + + + -> 4 `ui -> 1 `ui -> 1 `ui -> 2 `ui `uc ] +"356 +[; ;mcc_generated_files/can1.c: 356: rxCanMsg->field.dlc = status; +[e = . . . *U _rxCanMsg 1 1 2 _status ] +"357 +[; ;mcc_generated_files/can1.c: 357: rxCanMsg->field.idType = (status & (1UL << (4U))) ? CAN_FRAME_EXT : CAN_FRAME_STD; +[e = . . . *U _rxCanMsg 1 1 0 -> ? != & -> _status `ul << -> 1 `ul -> 4 `ui -> -> -> 0 `i `l `ul : . `E22328 1 . `E22328 0 `uc ] +"358 +[; ;mcc_generated_files/can1.c: 358: rxCanMsg->field.frameType = (status & (1UL << (5U))) ? CAN_FRAME_RTR : CAN_FRAME_DATA; +[e = . . . *U _rxCanMsg 1 1 1 -> ? != & -> _status `ul << -> 1 `ul -> 5 `ui -> -> -> 0 `i `l `ul : . `E22332 1 . `E22332 0 `uc ] +"359 +[; ;mcc_generated_files/can1.c: 359: rxCanMsg->field.brs = (status & (1UL << (6U))) ? CAN_BRS_MODE : CAN_NON_BRS_MODE; +[e = . . . *U _rxCanMsg 1 1 4 -> ? != & -> _status `ul << -> 1 `ul -> 6 `ui -> -> -> 0 `i `l `ul : . `E22324 1 . `E22324 0 `uc ] +"360 +[; ;mcc_generated_files/can1.c: 360: rxCanMsg->field.formatType = (status & (1UL << (7U))) ? CAN_FRAME_EXT : CAN_FRAME_STD; +[e = . . . *U _rxCanMsg 1 1 3 -> ? != & -> _status `ul << -> 1 `ul -> 7 `ui -> -> -> 0 `i `l `ul : . `E22328 1 . `E22328 0 `uc ] +"362 +[; ;mcc_generated_files/can1.c: 362: msgId = rxFifoObj[1] & (0x07U); +[e = _msgId -> & -> *U + _rxFifoObj * -> -> 1 `i `x -> -> # *U _rxFifoObj `i `x `ui -> 7 `ui `ul ] +"363 +[; ;mcc_generated_files/can1.c: 363: msgId <<= (8U); +[e =<< _msgId -> -> 8 `ui `ul ] +"364 +[; ;mcc_generated_files/can1.c: 364: msgId |= rxFifoObj[0]; +[e =| _msgId -> *U + _rxFifoObj * -> -> 0 `i `x -> -> # *U _rxFifoObj `i `x `ul ] +"365 +[; ;mcc_generated_files/can1.c: 365: if (CAN_FRAME_EXT == rxCanMsg->field.idType) +[e $ ! == -> . `E22328 1 `i -> . . . *U _rxCanMsg 1 1 0 `i 3220 ] +"366 +[; ;mcc_generated_files/can1.c: 366: { +{ +"367 +[; ;mcc_generated_files/can1.c: 367: msgId <<= (5U); +[e =<< _msgId -> -> 5 `ui `ul ] +"368 +[; ;mcc_generated_files/can1.c: 368: msgId |= (rxFifoObj[3] & (0x1FU)); +[e =| _msgId -> & -> *U + _rxFifoObj * -> -> 3 `i `x -> -> # *U _rxFifoObj `i `x `ui -> 31 `ui `ul ] +"369 +[; ;mcc_generated_files/can1.c: 369: msgId <<= (8U); +[e =<< _msgId -> -> 8 `ui `ul ] +"370 +[; ;mcc_generated_files/can1.c: 370: msgId |= rxFifoObj[2]; +[e =| _msgId -> *U + _rxFifoObj * -> -> 2 `i `x -> -> # *U _rxFifoObj `i `x `ul ] +"371 +[; ;mcc_generated_files/can1.c: 371: msgId <<= (5U); +[e =<< _msgId -> -> 5 `ui `ul ] +"372 +[; ;mcc_generated_files/can1.c: 372: msgId |= (rxFifoObj[1] & (0xF8U)) >> (3U); +[e =| _msgId -> >> & -> *U + _rxFifoObj * -> -> 1 `i `x -> -> # *U _rxFifoObj `i `x `ui -> 248 `ui -> 3 `ui `ul ] +"373 +[; ;mcc_generated_files/can1.c: 373: } +} +[e :U 3220 ] +"374 +[; ;mcc_generated_files/can1.c: 374: rxCanMsg->msgId = msgId; +[e = . *U _rxCanMsg 0 _msgId ] +"376 +[; ;mcc_generated_files/can1.c: 376: memcpy(rxMsgData, rxFifoObj + payloadOffsetBytes, (DLC_BYTES[(rxCanMsg->field.dlc)])); +[e ( _memcpy (3 , , -> &U _rxMsgData `*v -> + _rxFifoObj * -> -> _payloadOffsetBytes `i `x -> -> # *U _rxFifoObj `i `x `*Cv -> *U + &U _DLC_BYTES * -> . . . *U _rxCanMsg 1 1 2 `ux -> -> # *U &U _DLC_BYTES `ui `ux `ui ] +"377 +[; ;mcc_generated_files/can1.c: 377: rxCanMsg->data = rxMsgData; +[e = . *U _rxCanMsg 2 -> &U _rxMsgData `*uc ] +"378 +[; ;mcc_generated_files/can1.c: 378: } +[e :UE 3219 ] +} +"380 +[; ;mcc_generated_files/can1.c: 380: static _Bool Receive(uint8_t index, CAN1_RX_FIFO_CHANNELS channel, CAN_MSG_OBJ *rxCanMsg) +[v _Receive `(a ~T0 @X0 1 sf3`uc`E22386`*S3179 ] +"381 +[; ;mcc_generated_files/can1.c: 381: { +{ +[e :U _Receive ] +"380 +[; ;mcc_generated_files/can1.c: 380: static _Bool Receive(uint8_t index, CAN1_RX_FIFO_CHANNELS channel, CAN_MSG_OBJ *rxCanMsg) +[v _index `uc ~T0 @X0 1 r1 ] +[v _channel `E22386 ~T0 @X0 1 r2 ] +[v _rxCanMsg `*S3179 ~T0 @X0 1 r3 ] +"381 +[; ;mcc_generated_files/can1.c: 381: { +[f ] +"382 +[; ;mcc_generated_files/can1.c: 382: _Bool status = 0; +[v _status `a ~T0 @X0 1 a ] +[e = _status -> -> 0 `i `a ] +"383 +[; ;mcc_generated_files/can1.c: 383: CAN_RX_FIFO_STATUS rxMsgStatus = GetRxFifoStatus(channel); +[v _rxMsgStatus `E23140 ~T0 @X0 1 a ] +[e = _rxMsgStatus ( _GetRxFifoStatus (1 -> _channel `uc ] +"385 +[; ;mcc_generated_files/can1.c: 385: if (CAN_RX_MSG_AVAILABLE == (rxMsgStatus & CAN_RX_MSG_AVAILABLE)) +[e $ ! == -> . `E23140 1 `ui & -> _rxMsgStatus `ui -> . `E23140 1 `ui 3222 ] +"386 +[; ;mcc_generated_files/can1.c: 386: { +{ +"387 +[; ;mcc_generated_files/can1.c: 387: uint8_t *rxFifoObj = (uint8_t *) FIFO[channel].UA; +[v _rxFifoObj `*uc ~T0 @X0 1 a ] +[e = _rxFifoObj -> . *U + _FIFO * -> _channel `x -> -> # *U _FIFO `i `x 8 `*uc ] +"389 +[; ;mcc_generated_files/can1.c: 389: if (rxFifoObj != ((void*)0)) +[e $ ! != _rxFifoObj -> -> -> 0 `i `*v `*uc 3223 ] +"390 +[; ;mcc_generated_files/can1.c: 390: { +{ +"391 +[; ;mcc_generated_files/can1.c: 391: ReadMessageFromFifo(rxFifoObj, rxCanMsg); +[e ( _ReadMessageFromFifo (2 , _rxFifoObj _rxCanMsg ] +"392 +[; ;mcc_generated_files/can1.c: 392: FIFO[channel].CONH |= 0x1; +[e =| . *U + _FIFO * -> _channel `x -> -> # *U _FIFO `i `x 1 -> -> 1 `i `Vuc ] +"394 +[; ;mcc_generated_files/can1.c: 394: rxFifos[index].fifoHead += 1; +[e =+ . *U + &U _rxFifos * -> _index `ux -> -> # *U &U _rxFifos `ui `ux 1 -> -> 1 `i `Vuc ] +"395 +[; ;mcc_generated_files/can1.c: 395: if (rxFifos[index].fifoHead >= GetRxFifoDepth(channel)) +[e $ ! >= -> . *U + &U _rxFifos * -> _index `ux -> -> # *U &U _rxFifos `ui `ux 1 `i -> ( _GetRxFifoDepth (1 -> _channel `uc `i 3224 ] +"396 +[; ;mcc_generated_files/can1.c: 396: { +{ +"397 +[; ;mcc_generated_files/can1.c: 397: rxFifos[index].fifoHead = 0; +[e = . *U + &U _rxFifos * -> _index `ux -> -> # *U &U _rxFifos `ui `ux 1 -> -> 0 `i `uc ] +"398 +[; ;mcc_generated_files/can1.c: 398: } +} +[e :U 3224 ] +"400 +[; ;mcc_generated_files/can1.c: 400: if (CAN_RX_MSG_OVERFLOW == (rxMsgStatus & CAN_RX_MSG_OVERFLOW)) +[e $ ! == -> . `E23140 2 `ui & -> _rxMsgStatus `ui -> . `E23140 2 `ui 3225 ] +"401 +[; ;mcc_generated_files/can1.c: 401: { +{ +"402 +[; ;mcc_generated_files/can1.c: 402: FIFO[channel].STAL &= ~0x8; +[e =& . *U + _FIFO * -> _channel `x -> -> # *U _FIFO `i `x 4 -> ~ -> 8 `i `Vuc ] +"403 +[; ;mcc_generated_files/can1.c: 403: } +} +[e :U 3225 ] +"405 +[; ;mcc_generated_files/can1.c: 405: status = 1; +[e = _status -> -> 1 `i `a ] +"406 +[; ;mcc_generated_files/can1.c: 406: } +} +[e :U 3223 ] +"407 +[; ;mcc_generated_files/can1.c: 407: } +} +[e :U 3222 ] +"409 +[; ;mcc_generated_files/can1.c: 409: return status; +[e ) _status ] +[e $UE 3221 ] +"410 +[; ;mcc_generated_files/can1.c: 410: } +[e :UE 3221 ] +} +"412 +[; ;mcc_generated_files/can1.c: 412: _Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg) +[v _CAN1_Receive `(a ~T0 @X0 1 ef1`*S3179 ] +"413 +[; ;mcc_generated_files/can1.c: 413: { +{ +[e :U _CAN1_Receive ] +"412 +[; ;mcc_generated_files/can1.c: 412: _Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg) +[v _rxCanMsg `*S3179 ~T0 @X0 1 r1 ] +"413 +[; ;mcc_generated_files/can1.c: 413: { +[f ] +"414 +[; ;mcc_generated_files/can1.c: 414: uint8_t index; +[v _index `uc ~T0 @X0 1 a ] +"415 +[; ;mcc_generated_files/can1.c: 415: _Bool status = 0; +[v _status `a ~T0 @X0 1 a ] +[e = _status -> -> 0 `i `a ] +"417 +[; ;mcc_generated_files/can1.c: 417: for (index = 0; index < (1U); index++) +{ +[e = _index -> -> 0 `i `uc ] +[e $ < -> _index `ui -> 1 `ui 3227 ] +[e $U 3228 ] +[e :U 3227 ] +"418 +[; ;mcc_generated_files/can1.c: 418: { +{ +"419 +[; ;mcc_generated_files/can1.c: 419: status = Receive(index, rxFifos[index].channel, rxCanMsg); +[e = _status ( _Receive (3 , , _index . *U + &U _rxFifos * -> _index `ux -> -> # *U &U _rxFifos `ui `ux 0 _rxCanMsg ] +"421 +[; ;mcc_generated_files/can1.c: 421: if (status) +[e $ ! != -> _status `i -> 0 `i 3230 ] +"422 +[; ;mcc_generated_files/can1.c: 422: { +{ +"423 +[; ;mcc_generated_files/can1.c: 423: break; +[e $U 3228 ] +"424 +[; ;mcc_generated_files/can1.c: 424: } +} +[e :U 3230 ] +"425 +[; ;mcc_generated_files/can1.c: 425: } +} +[e ++ _index -> -> 1 `i `uc ] +[e $ < -> _index `ui -> 1 `ui 3227 ] +[e :U 3228 ] +} +"427 +[; ;mcc_generated_files/can1.c: 427: return status; +[e ) _status ] +[e $UE 3226 ] +"428 +[; ;mcc_generated_files/can1.c: 428: } +[e :UE 3226 ] +} +"430 +[; ;mcc_generated_files/can1.c: 430: _Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS channel, CAN_MSG_OBJ *rxCanMsg) +[v _CAN1_ReceiveFrom `(a ~T0 @X0 1 ef2`CE22386`*S3179 ] +"431 +[; ;mcc_generated_files/can1.c: 431: { +{ +[e :U _CAN1_ReceiveFrom ] +"430 +[; ;mcc_generated_files/can1.c: 430: _Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS channel, CAN_MSG_OBJ *rxCanMsg) +[v _channel `CE22386 ~T0 @X0 1 r1 ] +[v _rxCanMsg `*S3179 ~T0 @X0 1 r2 ] +"431 +[; ;mcc_generated_files/can1.c: 431: { +[f ] +"432 +[; ;mcc_generated_files/can1.c: 432: uint8_t index; +[v _index `uc ~T0 @X0 1 a ] +"433 +[; ;mcc_generated_files/can1.c: 433: _Bool status = 0; +[v _status `a ~T0 @X0 1 a ] +[e = _status -> -> 0 `i `a ] +"435 +[; ;mcc_generated_files/can1.c: 435: for (index = 0; index < (1U); index++) +{ +[e = _index -> -> 0 `i `uc ] +[e $ < -> _index `ui -> 1 `ui 3232 ] +[e $U 3233 ] +[e :U 3232 ] +"436 +[; ;mcc_generated_files/can1.c: 436: { +{ +"437 +[; ;mcc_generated_files/can1.c: 437: if (channel == rxFifos[index].channel) +[e $ ! == -> _channel `ui -> . *U + &U _rxFifos * -> _index `ux -> -> # *U &U _rxFifos `ui `ux 0 `ui 3235 ] +"438 +[; ;mcc_generated_files/can1.c: 438: { +{ +"439 +[; ;mcc_generated_files/can1.c: 439: status = Receive(index, channel, rxCanMsg); +[e = _status ( _Receive (3 , , _index _channel _rxCanMsg ] +"440 +[; ;mcc_generated_files/can1.c: 440: break; +[e $U 3233 ] +"441 +[; ;mcc_generated_files/can1.c: 441: } +} +[e :U 3235 ] +"442 +[; ;mcc_generated_files/can1.c: 442: } +} +[e ++ _index -> -> 1 `i `uc ] +[e $ < -> _index `ui -> 1 `ui 3232 ] +[e :U 3233 ] +} +"444 +[; ;mcc_generated_files/can1.c: 444: return status; +[e ) _status ] +[e $UE 3231 ] +"445 +[; ;mcc_generated_files/can1.c: 445: } +[e :UE 3231 ] +} +"447 +[; ;mcc_generated_files/can1.c: 447: uint8_t CAN1_ReceivedMessageCountGet(void) +[v _CAN1_ReceivedMessageCountGet `(uc ~T0 @X0 1 ef ] +"448 +[; ;mcc_generated_files/can1.c: 448: { +{ +[e :U _CAN1_ReceivedMessageCountGet ] +[f ] +"449 +[; ;mcc_generated_files/can1.c: 449: uint8_t index, totalMsgObj = 0; +[v _index `uc ~T0 @X0 1 a ] +[v _totalMsgObj `uc ~T0 @X0 1 a ] +[e = _totalMsgObj -> -> 0 `i `uc ] +"451 +[; ;mcc_generated_files/can1.c: 451: for (index = 0; index < (1U); index++) +{ +[e = _index -> -> 0 `i `uc ] +[e $ < -> _index `ui -> 1 `ui 3237 ] +[e $U 3238 ] +[e :U 3237 ] +"452 +[; ;mcc_generated_files/can1.c: 452: { +{ +"453 +[; ;mcc_generated_files/can1.c: 453: CAN1_RX_FIFO_CHANNELS channel = rxFifos[index].channel; +[v _channel `E22386 ~T0 @X0 1 a ] +[e = _channel . *U + &U _rxFifos * -> _index `ux -> -> # *U &U _rxFifos `ui `ux 0 ] +"454 +[; ;mcc_generated_files/can1.c: 454: CAN_RX_FIFO_STATUS rxMsgStatus = GetRxFifoStatus(channel); +[v _rxMsgStatus `E23140 ~T0 @X0 1 a ] +[e = _rxMsgStatus ( _GetRxFifoStatus (1 -> _channel `uc ] +"456 +[; ;mcc_generated_files/can1.c: 456: if (CAN_RX_MSG_AVAILABLE == (rxMsgStatus & CAN_RX_MSG_AVAILABLE)) +[e $ ! == -> . `E23140 1 `ui & -> _rxMsgStatus `ui -> . `E23140 1 `ui 3240 ] +"457 +[; ;mcc_generated_files/can1.c: 457: { +{ +"458 +[; ;mcc_generated_files/can1.c: 458: uint8_t numOfMsg, fifoDepth = GetRxFifoDepth(channel); +[v _numOfMsg `uc ~T0 @X0 1 a ] +[v _fifoDepth `uc ~T0 @X0 1 a ] +[e = _fifoDepth ( _GetRxFifoDepth (1 -> _channel `uc ] +"460 +[; ;mcc_generated_files/can1.c: 460: if (CAN_RX_MSG_OVERFLOW == (rxMsgStatus & CAN_RX_MSG_OVERFLOW)) +[e $ ! == -> . `E23140 2 `ui & -> _rxMsgStatus `ui -> . `E23140 2 `ui 3241 ] +"461 +[; ;mcc_generated_files/can1.c: 461: { +{ +"462 +[; ;mcc_generated_files/can1.c: 462: numOfMsg = fifoDepth; +[e = _numOfMsg _fifoDepth ] +"463 +[; ;mcc_generated_files/can1.c: 463: } +} +[e $U 3242 ] +"464 +[; ;mcc_generated_files/can1.c: 464: else +[e :U 3241 ] +"465 +[; ;mcc_generated_files/can1.c: 465: { +{ +"466 +[; ;mcc_generated_files/can1.c: 466: uint8_t fifoTail = FIFO[channel].STAH & 0x1F; +[v _fifoTail `uc ~T0 @X0 1 a ] +[e = _fifoTail -> & -> . *U + _FIFO * -> _channel `x -> -> # *U _FIFO `i `x 5 `i -> 31 `i `uc ] +"467 +[; ;mcc_generated_files/can1.c: 467: uint8_t fifoHead = rxFifos[index].fifoHead; +[v _fifoHead `uc ~T0 @X0 1 a ] +[e = _fifoHead . *U + &U _rxFifos * -> _index `ux -> -> # *U &U _rxFifos `ui `ux 1 ] +"469 +[; ;mcc_generated_files/can1.c: 469: if (fifoTail < fifoHead) +[e $ ! < -> _fifoTail `i -> _fifoHead `i 3243 ] +"470 +[; ;mcc_generated_files/can1.c: 470: { +{ +"471 +[; ;mcc_generated_files/can1.c: 471: numOfMsg = ((fifoTail + fifoDepth) - fifoHead); +[e = _numOfMsg -> - + -> _fifoTail `i -> _fifoDepth `i -> _fifoHead `i `uc ] +"472 +[; ;mcc_generated_files/can1.c: 472: } +} +[e $U 3244 ] +"473 +[; ;mcc_generated_files/can1.c: 473: else if (fifoTail > fifoHead) +[e :U 3243 ] +[e $ ! > -> _fifoTail `i -> _fifoHead `i 3245 ] +"474 +[; ;mcc_generated_files/can1.c: 474: { +{ +"475 +[; ;mcc_generated_files/can1.c: 475: numOfMsg = fifoTail - fifoHead; +[e = _numOfMsg -> - -> _fifoTail `i -> _fifoHead `i `uc ] +"476 +[; ;mcc_generated_files/can1.c: 476: } +} +[e $U 3246 ] +"477 +[; ;mcc_generated_files/can1.c: 477: else +[e :U 3245 ] +"478 +[; ;mcc_generated_files/can1.c: 478: { +{ +"479 +[; ;mcc_generated_files/can1.c: 479: numOfMsg = fifoDepth; +[e = _numOfMsg _fifoDepth ] +"480 +[; ;mcc_generated_files/can1.c: 480: } +} +[e :U 3246 ] +[e :U 3244 ] +"481 +[; ;mcc_generated_files/can1.c: 481: } +} +[e :U 3242 ] +"483 +[; ;mcc_generated_files/can1.c: 483: totalMsgObj += numOfMsg; +[e =+ _totalMsgObj -> _numOfMsg `uc ] +"484 +[; ;mcc_generated_files/can1.c: 484: } +} +[e :U 3240 ] +"485 +[; ;mcc_generated_files/can1.c: 485: } +} +[e ++ _index -> -> 1 `i `uc ] +[e $ < -> _index `ui -> 1 `ui 3237 ] +[e :U 3238 ] +} +"487 +[; ;mcc_generated_files/can1.c: 487: return totalMsgObj; +[e ) _totalMsgObj ] +[e $UE 3236 ] +"488 +[; ;mcc_generated_files/can1.c: 488: } +[e :UE 3236 ] +} +"490 +[; ;mcc_generated_files/can1.c: 490: static _Bool isTxChannel(uint8_t channel) +[v _isTxChannel `(a ~T0 @X0 1 sf1`uc ] +"491 +[; ;mcc_generated_files/can1.c: 491: { +{ +[e :U _isTxChannel ] +"490 +[; ;mcc_generated_files/can1.c: 490: static _Bool isTxChannel(uint8_t channel) +[v _channel `uc ~T0 @X0 1 r1 ] +"491 +[; ;mcc_generated_files/can1.c: 491: { +[f ] +"492 +[; ;mcc_generated_files/can1.c: 492: return channel < 4u && (FIFO[channel].CONL & 0x80); +[e ) -> -> && < -> _channel `ui -> 4 `ui != & -> . *U + _FIFO * -> _channel `ux -> -> # *U _FIFO `ui `ux 0 `i -> 128 `i -> 0 `i `i `a ] +[e $UE 3247 ] +"493 +[; ;mcc_generated_files/can1.c: 493: } +[e :UE 3247 ] +} +"495 +[; ;mcc_generated_files/can1.c: 495: static CAN_TX_FIFO_STATUS GetTxFifoStatus(uint8_t validChannel) +[v _GetTxFifoStatus `(E22361 ~T0 @X0 1 sf1`uc ] +"496 +[; ;mcc_generated_files/can1.c: 496: { +{ +[e :U _GetTxFifoStatus ] +"495 +[; ;mcc_generated_files/can1.c: 495: static CAN_TX_FIFO_STATUS GetTxFifoStatus(uint8_t validChannel) +[v _validChannel `uc ~T0 @X0 1 r1 ] +"496 +[; ;mcc_generated_files/can1.c: 496: { +[f ] +"497 +[; ;mcc_generated_files/can1.c: 497: return (FIFO[validChannel].STAL & 0x1); +[e ) -> & -> . *U + _FIFO * -> _validChannel `ux -> -> # *U _FIFO `ui `ux 4 `i -> 1 `i `E22361 ] +[e $UE 3248 ] +"498 +[; ;mcc_generated_files/can1.c: 498: } +[e :UE 3248 ] +} +"500 +[; ;mcc_generated_files/can1.c: 500: static void WriteMessageToFifo(uint8_t *txFifoObj, CAN_MSG_OBJ *txCanMsg) +[v _WriteMessageToFifo `(v ~T0 @X0 1 sf2`*uc`*S3179 ] +"501 +[; ;mcc_generated_files/can1.c: 501: { +{ +[e :U _WriteMessageToFifo ] +"500 +[; ;mcc_generated_files/can1.c: 500: static void WriteMessageToFifo(uint8_t *txFifoObj, CAN_MSG_OBJ *txCanMsg) +[v _txFifoObj `*uc ~T0 @X0 1 r1 ] +[v _txCanMsg `*S3179 ~T0 @X0 1 r2 ] +"501 +[; ;mcc_generated_files/can1.c: 501: { +[f ] +"502 +[; ;mcc_generated_files/can1.c: 502: uint32_t msgId = txCanMsg->msgId; +[v _msgId `ul ~T0 @X0 1 a ] +[e = _msgId . *U _txCanMsg 0 ] +"503 +[; ;mcc_generated_files/can1.c: 503: uint8_t status; +[v _status `uc ~T0 @X0 1 a ] +"504 +[; ;mcc_generated_files/can1.c: 504: const uint8_t payloadOffsetBytes = +[v _payloadOffsetBytes `Cuc ~T0 @X0 1 a ] +[e = _payloadOffsetBytes -> + + + -> 4 `ui -> 1 `ui -> 1 `ui -> 2 `ui `uc ] +"510 +[; ;mcc_generated_files/can1.c: 510: if (CAN_FRAME_EXT == txCanMsg->field.idType) +[e $ ! == -> . `E22328 1 `i -> . . . *U _txCanMsg 1 1 0 `i 3250 ] +"511 +[; ;mcc_generated_files/can1.c: 511: { +{ +"512 +[; ;mcc_generated_files/can1.c: 512: txFifoObj[1] = (msgId << (3U)) & (0xF8U); +[e = *U + _txFifoObj * -> -> 1 `i `x -> -> # *U _txFifoObj `i `x -> & << _msgId -> 3 `ui -> -> 248 `ui `ul `uc ] +"513 +[; ;mcc_generated_files/can1.c: 513: msgId >>= (5U); +[e =>> _msgId -> -> 5 `ui `ul ] +"514 +[; ;mcc_generated_files/can1.c: 514: txFifoObj[2] = msgId; +[e = *U + _txFifoObj * -> -> 2 `i `x -> -> # *U _txFifoObj `i `x -> _msgId `uc ] +"515 +[; ;mcc_generated_files/can1.c: 515: msgId >>= (8U); +[e =>> _msgId -> -> 8 `ui `ul ] +"516 +[; ;mcc_generated_files/can1.c: 516: txFifoObj[3] = (msgId & (0x1FU)); +[e = *U + _txFifoObj * -> -> 3 `i `x -> -> # *U _txFifoObj `i `x -> & _msgId -> -> 31 `ui `ul `uc ] +"517 +[; ;mcc_generated_files/can1.c: 517: msgId >>= (5U); +[e =>> _msgId -> -> 5 `ui `ul ] +"518 +[; ;mcc_generated_files/can1.c: 518: } +} +[e $U 3251 ] +"519 +[; ;mcc_generated_files/can1.c: 519: else +[e :U 3250 ] +"520 +[; ;mcc_generated_files/can1.c: 520: { +{ +"521 +[; ;mcc_generated_files/can1.c: 521: txFifoObj[1] = txFifoObj[2] = txFifoObj[3] = 0; +[e = *U + _txFifoObj * -> -> 1 `i `x -> -> # *U _txFifoObj `i `x = *U + _txFifoObj * -> -> 2 `i `x -> -> # *U _txFifoObj `i `x = *U + _txFifoObj * -> -> 3 `i `x -> -> # *U _txFifoObj `i `x -> -> 0 `i `uc ] +"522 +[; ;mcc_generated_files/can1.c: 522: } +} +[e :U 3251 ] +"524 +[; ;mcc_generated_files/can1.c: 524: txFifoObj[0] = msgId; +[e = *U + _txFifoObj * -> -> 0 `i `x -> -> # *U _txFifoObj `i `x -> _msgId `uc ] +"525 +[; ;mcc_generated_files/can1.c: 525: msgId >>= (8U); +[e =>> _msgId -> -> 8 `ui `ul ] +"526 +[; ;mcc_generated_files/can1.c: 526: txFifoObj[1] |= (msgId & (0x07U)); +[e =| *U + _txFifoObj * -> -> 1 `i `x -> -> # *U _txFifoObj `i `x -> & _msgId -> -> 7 `ui `ul `uc ] +"528 +[; ;mcc_generated_files/can1.c: 528: status = txCanMsg->field.dlc; +[e = _status . . . *U _txCanMsg 1 1 2 ] +"529 +[; ;mcc_generated_files/can1.c: 529: status |= (txCanMsg->field.idType << (4U)); +[e =| _status -> << -> . . . *U _txCanMsg 1 1 0 `i -> 4 `ui `uc ] +"530 +[; ;mcc_generated_files/can1.c: 530: status |= (txCanMsg->field.frameType << (5U)); +[e =| _status -> << -> . . . *U _txCanMsg 1 1 1 `i -> 5 `ui `uc ] +"531 +[; ;mcc_generated_files/can1.c: 531: status |= (txCanMsg->field.brs << (6U)); +[e =| _status -> << -> . . . *U _txCanMsg 1 1 4 `i -> 6 `ui `uc ] +"532 +[; ;mcc_generated_files/can1.c: 532: status |= (txCanMsg->field.formatType << (7U)); +[e =| _status -> << -> . . . *U _txCanMsg 1 1 3 `i -> 7 `ui `uc ] +"533 +[; ;mcc_generated_files/can1.c: 533: txFifoObj[4] = status; +[e = *U + _txFifoObj * -> -> 4 `i `x -> -> # *U _txFifoObj `i `x _status ] +"535 +[; ;mcc_generated_files/can1.c: 535: if (CAN_FRAME_DATA == txCanMsg->field.frameType) +[e $ ! == -> . `E22332 0 `i -> . . . *U _txCanMsg 1 1 1 `i 3252 ] +"536 +[; ;mcc_generated_files/can1.c: 536: { +{ +"537 +[; ;mcc_generated_files/can1.c: 537: memcpy(txFifoObj + payloadOffsetBytes, txCanMsg->data, (DLC_BYTES[(txCanMsg->field.dlc)])); +[e ( _memcpy (3 , , -> + _txFifoObj * -> -> _payloadOffsetBytes `i `x -> -> # *U _txFifoObj `i `x `*v -> . *U _txCanMsg 2 `*Cv -> *U + &U _DLC_BYTES * -> . . . *U _txCanMsg 1 1 2 `ux -> -> # *U &U _DLC_BYTES `ui `ux `ui ] +"538 +[; ;mcc_generated_files/can1.c: 538: } +} +[e :U 3252 ] +"539 +[; ;mcc_generated_files/can1.c: 539: } +[e :UE 3249 ] +} +"541 +[; ;mcc_generated_files/can1.c: 541: static CAN_TX_MSG_REQUEST_STATUS ValidateTransmission(uint8_t validChannel, CAN_MSG_OBJ *txCanMsg) +[v _ValidateTransmission `(E22340 ~T0 @X0 1 sf2`uc`*S3179 ] +"542 +[; ;mcc_generated_files/can1.c: 542: { +{ +[e :U _ValidateTransmission ] +"541 +[; ;mcc_generated_files/can1.c: 541: static CAN_TX_MSG_REQUEST_STATUS ValidateTransmission(uint8_t validChannel, CAN_MSG_OBJ *txCanMsg) +[v _validChannel `uc ~T0 @X0 1 r1 ] +[v _txCanMsg `*S3179 ~T0 @X0 1 r2 ] +"542 +[; ;mcc_generated_files/can1.c: 542: { +[f ] +"543 +[; ;mcc_generated_files/can1.c: 543: CAN_TX_MSG_REQUEST_STATUS txMsgStatus = CAN_TX_MSG_REQUEST_SUCCESS; +[v _txMsgStatus `E22340 ~T0 @X0 1 a ] +[e = _txMsgStatus . `E22340 0 ] +"544 +[; ;mcc_generated_files/can1.c: 544: CAN_MSG_FIELD field = txCanMsg->field; +[v _field `S3177 ~T0 @X0 1 a ] +[e = _field . *U _txCanMsg 1 ] +"545 +[; ;mcc_generated_files/can1.c: 545: uint8_t plsize = 0; +[v _plsize `uc ~T0 @X0 1 a ] +[e = _plsize -> -> 0 `i `uc ] +"547 +[; ;mcc_generated_files/can1.c: 547: if (CAN_BRS_MODE == field.brs && (CAN_NORMAL_2_0_MODE == CAN1_OperationModeGet())) +[e $ ! && == -> . `E22324 1 `i -> . . _field 1 4 `i == -> . `E22346 6 `ui -> ( _CAN1_OperationModeGet .. `ui 3254 ] +"548 +[; ;mcc_generated_files/can1.c: 548: { +{ +"549 +[; ;mcc_generated_files/can1.c: 549: txMsgStatus |= CAN_TX_MSG_REQUEST_BRS_ERROR; +[e =| _txMsgStatus -> . `E22340 2 `E22340 ] +"550 +[; ;mcc_generated_files/can1.c: 550: } +} +[e :U 3254 ] +"552 +[; ;mcc_generated_files/can1.c: 552: if (field.dlc > DLC_8 && (CAN_2_0_FORMAT == field.formatType || CAN_NORMAL_2_0_MODE == CAN1_OperationModeGet())) +[e $ ! && > -> . . _field 1 2 `i -> . `E22365 8 `i || == -> . `E22336 0 `i -> . . _field 1 3 `i == -> . `E22346 6 `ui -> ( _CAN1_OperationModeGet .. `ui 3255 ] +"553 +[; ;mcc_generated_files/can1.c: 553: { +{ +"554 +[; ;mcc_generated_files/can1.c: 554: txMsgStatus |= CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR; +[e =| _txMsgStatus -> . `E22340 1 `E22340 ] +"555 +[; ;mcc_generated_files/can1.c: 555: } +} +[e :U 3255 ] +"557 +[; ;mcc_generated_files/can1.c: 557: if ((DLC_BYTES[(field.dlc)]) > ((DLC_BYTES[(8u + (plsize))]))) +[e $ ! > -> *U + &U _DLC_BYTES * -> . . _field 1 2 `ux -> -> # *U &U _DLC_BYTES `ui `ux `i -> *U + &U _DLC_BYTES * -> + -> 8 `ui -> _plsize `ui `ux -> -> # *U &U _DLC_BYTES `ui `ux `i 3256 ] +"558 +[; ;mcc_generated_files/can1.c: 558: { +{ +"559 +[; ;mcc_generated_files/can1.c: 559: txMsgStatus |= CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR; +[e =| _txMsgStatus -> . `E22340 1 `E22340 ] +"560 +[; ;mcc_generated_files/can1.c: 560: } +} +[e :U 3256 ] +"562 +[; ;mcc_generated_files/can1.c: 562: if (CAN_TX_FIFO_FULL == GetTxFifoStatus(validChannel)) +[e $ ! == -> . `E22361 0 `ui -> ( _GetTxFifoStatus (1 _validChannel `ui 3257 ] +"563 +[; ;mcc_generated_files/can1.c: 563: { +{ +"564 +[; ;mcc_generated_files/can1.c: 564: txMsgStatus |= CAN_TX_MSG_REQUEST_FIFO_FULL; +[e =| _txMsgStatus -> . `E22340 3 `E22340 ] +"565 +[; ;mcc_generated_files/can1.c: 565: } +} +[e :U 3257 ] +"567 +[; ;mcc_generated_files/can1.c: 567: return txMsgStatus; +[e ) _txMsgStatus ] +[e $UE 3253 ] +"568 +[; ;mcc_generated_files/can1.c: 568: } +[e :UE 3253 ] +} +"570 +[; ;mcc_generated_files/can1.c: 570: CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg) +[v _CAN1_Transmit `(E22340 ~T0 @X0 1 ef2`CE22383`*S3179 ] +"571 +[; ;mcc_generated_files/can1.c: 571: { +{ +[e :U _CAN1_Transmit ] +"570 +[; ;mcc_generated_files/can1.c: 570: CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg) +[v _fifoChannel `CE22383 ~T0 @X0 1 r1 ] +[v _txCanMsg `*S3179 ~T0 @X0 1 r2 ] +"571 +[; ;mcc_generated_files/can1.c: 571: { +[f ] +"572 +[; ;mcc_generated_files/can1.c: 572: CAN_TX_MSG_REQUEST_STATUS status = CAN_TX_MSG_REQUEST_FIFO_FULL; +[v _status `E22340 ~T0 @X0 1 a ] +[e = _status . `E22340 3 ] +"574 +[; ;mcc_generated_files/can1.c: 574: if (isTxChannel(fifoChannel)) +[e $ ! != -> ( _isTxChannel (1 -> _fifoChannel `uc `i -> 0 `i 3259 ] +"575 +[; ;mcc_generated_files/can1.c: 575: { +{ +"576 +[; ;mcc_generated_files/can1.c: 576: status = ValidateTransmission(fifoChannel, txCanMsg); +[e = _status ( _ValidateTransmission (2 , -> _fifoChannel `uc _txCanMsg ] +"577 +[; ;mcc_generated_files/can1.c: 577: if (CAN_TX_MSG_REQUEST_SUCCESS == status) +[e $ ! == -> . `E22340 0 `ui -> _status `ui 3260 ] +"578 +[; ;mcc_generated_files/can1.c: 578: { +{ +"579 +[; ;mcc_generated_files/can1.c: 579: uint8_t *txFifoObj = (uint8_t *) FIFO[fifoChannel].UA; +[v _txFifoObj `*uc ~T0 @X0 1 a ] +[e = _txFifoObj -> . *U + _FIFO * -> _fifoChannel `x -> -> # *U _FIFO `i `x 8 `*uc ] +"581 +[; ;mcc_generated_files/can1.c: 581: if (txFifoObj != ((void*)0)) +[e $ ! != _txFifoObj -> -> -> 0 `i `*v `*uc 3261 ] +"582 +[; ;mcc_generated_files/can1.c: 582: { +{ +"583 +[; ;mcc_generated_files/can1.c: 583: WriteMessageToFifo(txFifoObj, txCanMsg); +[e ( _WriteMessageToFifo (2 , _txFifoObj _txCanMsg ] +"584 +[; ;mcc_generated_files/can1.c: 584: FIFO[fifoChannel].CONH |= (0x2 | 0x1); +[e =| . *U + _FIFO * -> _fifoChannel `x -> -> # *U _FIFO `i `x 1 -> | -> 2 `i -> 1 `i `Vuc ] +"585 +[; ;mcc_generated_files/can1.c: 585: } +} +[e :U 3261 ] +"586 +[; ;mcc_generated_files/can1.c: 586: } +} +[e :U 3260 ] +"587 +[; ;mcc_generated_files/can1.c: 587: } +} +[e :U 3259 ] +"589 +[; ;mcc_generated_files/can1.c: 589: return status; +[e ) _status ] +[e $UE 3258 ] +"590 +[; ;mcc_generated_files/can1.c: 590: } +[e :UE 3258 ] +} +"592 +[; ;mcc_generated_files/can1.c: 592: CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel) +[v _CAN1_TransmitFIFOStatusGet `(E22361 ~T0 @X0 1 ef1`CE22383 ] +"593 +[; ;mcc_generated_files/can1.c: 593: { +{ +[e :U _CAN1_TransmitFIFOStatusGet ] +"592 +[; ;mcc_generated_files/can1.c: 592: CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel) +[v _fifoChannel `CE22383 ~T0 @X0 1 r1 ] +"593 +[; ;mcc_generated_files/can1.c: 593: { +[f ] +"594 +[; ;mcc_generated_files/can1.c: 594: CAN_TX_FIFO_STATUS status = CAN_TX_FIFO_FULL; +[v _status `E22361 ~T0 @X0 1 a ] +[e = _status . `E22361 0 ] +"596 +[; ;mcc_generated_files/can1.c: 596: if (isTxChannel(fifoChannel)) +[e $ ! != -> ( _isTxChannel (1 -> _fifoChannel `uc `i -> 0 `i 3263 ] +"597 +[; ;mcc_generated_files/can1.c: 597: { +{ +"598 +[; ;mcc_generated_files/can1.c: 598: status = GetTxFifoStatus(fifoChannel); +[e = _status ( _GetTxFifoStatus (1 -> _fifoChannel `uc ] +"599 +[; ;mcc_generated_files/can1.c: 599: } +} +[e :U 3263 ] +"601 +[; ;mcc_generated_files/can1.c: 601: return status; +[e ) _status ] +[e $UE 3262 ] +"602 +[; ;mcc_generated_files/can1.c: 602: } +[e :UE 3262 ] +} +"604 +[; ;mcc_generated_files/can1.c: 604: _Bool CAN1_IsBusOff(void) +[v _CAN1_IsBusOff `(a ~T0 @X0 1 ef ] +"605 +[; ;mcc_generated_files/can1.c: 605: { +{ +[e :U _CAN1_IsBusOff ] +[f ] +"606 +[; ;mcc_generated_files/can1.c: 606: return C1TRECUbits.TXBO; +[e ) -> . . _C1TRECUbits 0 5 `a ] +[e $UE 3264 ] +"607 +[; ;mcc_generated_files/can1.c: 607: } +[e :UE 3264 ] +} +"609 +[; ;mcc_generated_files/can1.c: 609: _Bool CAN1_IsRxErrorPassive(void) +[v _CAN1_IsRxErrorPassive `(a ~T0 @X0 1 ef ] +"610 +[; ;mcc_generated_files/can1.c: 610: { +{ +[e :U _CAN1_IsRxErrorPassive ] +[f ] +"611 +[; ;mcc_generated_files/can1.c: 611: return C1TRECUbits.RXBP; +[e ) -> . . _C1TRECUbits 0 3 `a ] +[e $UE 3265 ] +"612 +[; ;mcc_generated_files/can1.c: 612: } +[e :UE 3265 ] +} +"614 +[; ;mcc_generated_files/can1.c: 614: _Bool CAN1_IsRxErrorWarning(void) +[v _CAN1_IsRxErrorWarning `(a ~T0 @X0 1 ef ] +"615 +[; ;mcc_generated_files/can1.c: 615: { +{ +[e :U _CAN1_IsRxErrorWarning ] +[f ] +"616 +[; ;mcc_generated_files/can1.c: 616: return C1TRECUbits.RXWARN; +[e ) -> . . _C1TRECUbits 0 1 `a ] +[e $UE 3266 ] +"617 +[; ;mcc_generated_files/can1.c: 617: } +[e :UE 3266 ] +} +"619 +[; ;mcc_generated_files/can1.c: 619: _Bool CAN1_IsRxErrorActive(void) +[v _CAN1_IsRxErrorActive `(a ~T0 @X0 1 ef ] +"620 +[; ;mcc_generated_files/can1.c: 620: { +{ +[e :U _CAN1_IsRxErrorActive ] +[f ] +"621 +[; ;mcc_generated_files/can1.c: 621: return !CAN1_IsRxErrorPassive(); +[e ) -> -> ! != -> ( _CAN1_IsRxErrorPassive .. `i -> 0 `i `i `a ] +[e $UE 3267 ] +"622 +[; ;mcc_generated_files/can1.c: 622: } +[e :UE 3267 ] +} +"624 +[; ;mcc_generated_files/can1.c: 624: _Bool CAN1_IsTxErrorPassive(void) +[v _CAN1_IsTxErrorPassive `(a ~T0 @X0 1 ef ] +"625 +[; ;mcc_generated_files/can1.c: 625: { +{ +[e :U _CAN1_IsTxErrorPassive ] +[f ] +"626 +[; ;mcc_generated_files/can1.c: 626: return C1TRECUbits.TXBP; +[e ) -> . . _C1TRECUbits 0 4 `a ] +[e $UE 3268 ] +"627 +[; ;mcc_generated_files/can1.c: 627: } +[e :UE 3268 ] +} +"629 +[; ;mcc_generated_files/can1.c: 629: _Bool CAN1_IsTxErrorWarning(void) +[v _CAN1_IsTxErrorWarning `(a ~T0 @X0 1 ef ] +"630 +[; ;mcc_generated_files/can1.c: 630: { +{ +[e :U _CAN1_IsTxErrorWarning ] +[f ] +"631 +[; ;mcc_generated_files/can1.c: 631: return C1TRECUbits.TXWARN; +[e ) -> . . _C1TRECUbits 0 2 `a ] +[e $UE 3269 ] +"632 +[; ;mcc_generated_files/can1.c: 632: } +[e :UE 3269 ] +} +"634 +[; ;mcc_generated_files/can1.c: 634: _Bool CAN1_IsTxErrorActive(void) +[v _CAN1_IsTxErrorActive `(a ~T0 @X0 1 ef ] +"635 +[; ;mcc_generated_files/can1.c: 635: { +{ +[e :U _CAN1_IsTxErrorActive ] +[f ] +"636 +[; ;mcc_generated_files/can1.c: 636: return !CAN1_IsTxErrorPassive(); +[e ) -> -> ! != -> ( _CAN1_IsTxErrorPassive .. `i -> 0 `i `i `a ] +[e $UE 3270 ] +"637 +[; ;mcc_generated_files/can1.c: 637: } +[e :UE 3270 ] +} +"639 +[; ;mcc_generated_files/can1.c: 639: void CAN1_Sleep(void) +[v _CAN1_Sleep `(v ~T0 @X0 1 ef ] +"640 +[; ;mcc_generated_files/can1.c: 640: { +{ +[e :U _CAN1_Sleep ] +[f ] +"641 +[; ;mcc_generated_files/can1.c: 641: C1INTHbits.WAKIF = 0; +[e = . . _C1INTHbits 0 5 -> -> 0 `i `uc ] +"642 +[; ;mcc_generated_files/can1.c: 642: C1INTTbits.WAKIE = 1; +[e = . . _C1INTTbits 0 5 -> -> 1 `i `uc ] +"644 +[; ;mcc_generated_files/can1.c: 644: CAN1_OperationModeSet(CAN_DISABLE_MODE); +[e ( _CAN1_OperationModeSet (1 . `E22346 1 ] +"645 +[; ;mcc_generated_files/can1.c: 645: } +[e :UE 3271 ] +} +"647 +[; ;mcc_generated_files/can1.c: 647: void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)) +[v _CAN1_SetInvalidMessageInterruptHandler `(v ~T0 @X0 1 ef1`*F23266 ] +"648 +[; ;mcc_generated_files/can1.c: 648: { +{ +[e :U _CAN1_SetInvalidMessageInterruptHandler ] +"647 +[; ;mcc_generated_files/can1.c: 647: void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)) +[v _handler `*F23268 ~T0 @X0 1 r1 ] +"648 +[; ;mcc_generated_files/can1.c: 648: { +[f ] +"649 +[; ;mcc_generated_files/can1.c: 649: CAN1_InvalidMessageHandler = handler; +[e = _CAN1_InvalidMessageHandler _handler ] +"650 +[; ;mcc_generated_files/can1.c: 650: } +[e :UE 3272 ] +} +"652 +[; ;mcc_generated_files/can1.c: 652: void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)) +[v _CAN1_SetBusWakeUpActivityInterruptHandler `(v ~T0 @X0 1 ef1`*F23271 ] +"653 +[; ;mcc_generated_files/can1.c: 653: { +{ +[e :U _CAN1_SetBusWakeUpActivityInterruptHandler ] +"652 +[; ;mcc_generated_files/can1.c: 652: void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)) +[v _handler `*F23273 ~T0 @X0 1 r1 ] +"653 +[; ;mcc_generated_files/can1.c: 653: { +[f ] +"654 +[; ;mcc_generated_files/can1.c: 654: CAN1_BusWakeUpActivityHandler = handler; +[e = _CAN1_BusWakeUpActivityHandler _handler ] +"655 +[; ;mcc_generated_files/can1.c: 655: } +[e :UE 3273 ] +} +"657 +[; ;mcc_generated_files/can1.c: 657: void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)) +[v _CAN1_SetBusErrorInterruptHandler `(v ~T0 @X0 1 ef1`*F23276 ] +"658 +[; ;mcc_generated_files/can1.c: 658: { +{ +[e :U _CAN1_SetBusErrorInterruptHandler ] +"657 +[; ;mcc_generated_files/can1.c: 657: void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)) +[v _handler `*F23278 ~T0 @X0 1 r1 ] +"658 +[; ;mcc_generated_files/can1.c: 658: { +[f ] +"659 +[; ;mcc_generated_files/can1.c: 659: CAN1_BusErrorHandler = handler; +[e = _CAN1_BusErrorHandler _handler ] +"660 +[; ;mcc_generated_files/can1.c: 660: } +[e :UE 3274 ] +} +"662 +[; ;mcc_generated_files/can1.c: 662: void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)) +[v _CAN1_SetModeChangeInterruptHandler `(v ~T0 @X0 1 ef1`*F23281 ] +"663 +[; ;mcc_generated_files/can1.c: 663: { +{ +[e :U _CAN1_SetModeChangeInterruptHandler ] +"662 +[; ;mcc_generated_files/can1.c: 662: void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)) +[v _handler `*F23283 ~T0 @X0 1 r1 ] +"663 +[; ;mcc_generated_files/can1.c: 663: { +[f ] +"664 +[; ;mcc_generated_files/can1.c: 664: CAN1_ModeChangeHandler = handler; +[e = _CAN1_ModeChangeHandler _handler ] +"665 +[; ;mcc_generated_files/can1.c: 665: } +[e :UE 3275 ] +} +"667 +[; ;mcc_generated_files/can1.c: 667: void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)) +[v _CAN1_SetSystemErrorInterruptHandler `(v ~T0 @X0 1 ef1`*F23286 ] +"668 +[; ;mcc_generated_files/can1.c: 668: { +{ +[e :U _CAN1_SetSystemErrorInterruptHandler ] +"667 +[; ;mcc_generated_files/can1.c: 667: void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)) +[v _handler `*F23288 ~T0 @X0 1 r1 ] +"668 +[; ;mcc_generated_files/can1.c: 668: { +[f ] +"669 +[; ;mcc_generated_files/can1.c: 669: CAN1_SystemErrorHandler = handler; +[e = _CAN1_SystemErrorHandler _handler ] +"670 +[; ;mcc_generated_files/can1.c: 670: } +[e :UE 3276 ] +} +"672 +[; ;mcc_generated_files/can1.c: 672: void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)) +[v _CAN1_SetTxAttemptInterruptHandler `(v ~T0 @X0 1 ef1`*F23291 ] +"673 +[; ;mcc_generated_files/can1.c: 673: { +{ +[e :U _CAN1_SetTxAttemptInterruptHandler ] +"672 +[; ;mcc_generated_files/can1.c: 672: void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)) +[v _handler `*F23293 ~T0 @X0 1 r1 ] +"673 +[; ;mcc_generated_files/can1.c: 673: { +[f ] +"674 +[; ;mcc_generated_files/can1.c: 674: CAN1_TxAttemptHandler = handler; +[e = _CAN1_TxAttemptHandler _handler ] +"675 +[; ;mcc_generated_files/can1.c: 675: } +[e :UE 3277 ] +} +"677 +[; ;mcc_generated_files/can1.c: 677: void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)) +[v _CAN1_SetRxBufferOverFlowInterruptHandler `(v ~T0 @X0 1 ef1`*F23296 ] +"678 +[; ;mcc_generated_files/can1.c: 678: { +{ +[e :U _CAN1_SetRxBufferOverFlowInterruptHandler ] +"677 +[; ;mcc_generated_files/can1.c: 677: void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)) +[v _handler `*F23298 ~T0 @X0 1 r1 ] +"678 +[; ;mcc_generated_files/can1.c: 678: { +[f ] +"679 +[; ;mcc_generated_files/can1.c: 679: CAN1_RxBufferOverflowHandler = handler; +[e = _CAN1_RxBufferOverflowHandler _handler ] +"680 +[; ;mcc_generated_files/can1.c: 680: } +[e :UE 3278 ] +} +"682 +[; ;mcc_generated_files/can1.c: 682: void CAN1_ISR(void) +[v _CAN1_ISR `(v ~T0 @X0 1 ef ] +"683 +[; ;mcc_generated_files/can1.c: 683: { +{ +[e :U _CAN1_ISR ] +[f ] +"684 +[; ;mcc_generated_files/can1.c: 684: if (1 == C1INTHbits.IVMIF) +[e $ ! == -> 1 `i -> . . _C1INTHbits 0 6 `i 3280 ] +"685 +[; ;mcc_generated_files/can1.c: 685: { +{ +"686 +[; ;mcc_generated_files/can1.c: 686: CAN1_InvalidMessageHandler(); +[e ( *U _CAN1_InvalidMessageHandler .. ] +"687 +[; ;mcc_generated_files/can1.c: 687: C1INTHbits.IVMIF = 0; +[e = . . _C1INTHbits 0 6 -> -> 0 `i `uc ] +"688 +[; ;mcc_generated_files/can1.c: 688: } +} +[e :U 3280 ] +"690 +[; ;mcc_generated_files/can1.c: 690: if (1 == C1INTHbits.WAKIF) +[e $ ! == -> 1 `i -> . . _C1INTHbits 0 5 `i 3281 ] +"691 +[; ;mcc_generated_files/can1.c: 691: { +{ +"692 +[; ;mcc_generated_files/can1.c: 692: CAN1_BusWakeUpActivityHandler(); +[e ( *U _CAN1_BusWakeUpActivityHandler .. ] +"693 +[; ;mcc_generated_files/can1.c: 693: C1INTHbits.WAKIF = 0; +[e = . . _C1INTHbits 0 5 -> -> 0 `i `uc ] +"694 +[; ;mcc_generated_files/can1.c: 694: } +} +[e :U 3281 ] +"696 +[; ;mcc_generated_files/can1.c: 696: if (1 == C1INTHbits.CERRIF) +[e $ ! == -> 1 `i -> . . _C1INTHbits 0 4 `i 3282 ] +"697 +[; ;mcc_generated_files/can1.c: 697: { +{ +"698 +[; ;mcc_generated_files/can1.c: 698: CAN1_BusErrorHandler(); +[e ( *U _CAN1_BusErrorHandler .. ] +"699 +[; ;mcc_generated_files/can1.c: 699: C1INTHbits.CERRIF = 0; +[e = . . _C1INTHbits 0 4 -> -> 0 `i `uc ] +"700 +[; ;mcc_generated_files/can1.c: 700: } +} +[e :U 3282 ] +"702 +[; ;mcc_generated_files/can1.c: 702: if (1 == C1INTLbits.MODIF) +[e $ ! == -> 1 `i -> . . _C1INTLbits 0 3 `i 3283 ] +"703 +[; ;mcc_generated_files/can1.c: 703: { +{ +"704 +[; ;mcc_generated_files/can1.c: 704: CAN1_ModeChangeHandler(); +[e ( *U _CAN1_ModeChangeHandler .. ] +"705 +[; ;mcc_generated_files/can1.c: 705: C1INTLbits.MODIF = 0; +[e = . . _C1INTLbits 0 3 -> -> 0 `i `uc ] +"706 +[; ;mcc_generated_files/can1.c: 706: } +} +[e :U 3283 ] +"708 +[; ;mcc_generated_files/can1.c: 708: if (1 == C1INTHbits.SERRIF) +[e $ ! == -> 1 `i -> . . _C1INTHbits 0 3 `i 3284 ] +"709 +[; ;mcc_generated_files/can1.c: 709: { +{ +"710 +[; ;mcc_generated_files/can1.c: 710: CAN1_SystemErrorHandler(); +[e ( *U _CAN1_SystemErrorHandler .. ] +"711 +[; ;mcc_generated_files/can1.c: 711: C1INTHbits.SERRIF = 0; +[e = . . _C1INTHbits 0 3 -> -> 0 `i `uc ] +"712 +[; ;mcc_generated_files/can1.c: 712: } +} +[e :U 3284 ] +"714 +[; ;mcc_generated_files/can1.c: 714: if (1 == C1INTHbits.TXATIF) +[e $ ! == -> 1 `i -> . . _C1INTHbits 0 1 `i 3285 ] +"715 +[; ;mcc_generated_files/can1.c: 715: { +{ +"716 +[; ;mcc_generated_files/can1.c: 716: CAN1_TxAttemptHandler(); +[e ( *U _CAN1_TxAttemptHandler .. ] +"717 +[; ;mcc_generated_files/can1.c: 717: if (1 == C1TXQSTALbits.TXATIF) +[e $ ! == -> 1 `i -> . . _C1TXQSTALbits 0 4 `i 3286 ] +"718 +[; ;mcc_generated_files/can1.c: 718: { +{ +"719 +[; ;mcc_generated_files/can1.c: 719: C1TXQSTALbits.TXATIF = 0; +[e = . . _C1TXQSTALbits 0 4 -> -> 0 `i `uc ] +"720 +[; ;mcc_generated_files/can1.c: 720: } +} +[e :U 3286 ] +"721 +[; ;mcc_generated_files/can1.c: 721: } +} +[e :U 3285 ] +"723 +[; ;mcc_generated_files/can1.c: 723: if (1 == C1INTHbits.RXOVIF) +[e $ ! == -> 1 `i -> . . _C1INTHbits 0 2 `i 3287 ] +"724 +[; ;mcc_generated_files/can1.c: 724: { +{ +"725 +[; ;mcc_generated_files/can1.c: 725: CAN1_RxBufferOverflowHandler(); +[e ( *U _CAN1_RxBufferOverflowHandler .. ] +"726 +[; ;mcc_generated_files/can1.c: 726: if (1 == C1FIFOSTA1Lbits.RXOVIF) +[e $ ! == -> 1 `i -> . . _C1FIFOSTA1Lbits 0 3 `i 3288 ] +"727 +[; ;mcc_generated_files/can1.c: 727: { +{ +"728 +[; ;mcc_generated_files/can1.c: 728: C1FIFOSTA1Lbits.RXOVIF = 0; +[e = . . _C1FIFOSTA1Lbits 0 3 -> -> 0 `i `uc ] +"729 +[; ;mcc_generated_files/can1.c: 729: } +} +[e :U 3288 ] +"730 +[; ;mcc_generated_files/can1.c: 730: } +} +[e :U 3287 ] +"732 +[; ;mcc_generated_files/can1.c: 732: PIR0bits.CANIF = 0; +[e = . . _PIR0bits 0 6 -> -> 0 `i `uc ] +"733 +[; ;mcc_generated_files/can1.c: 733: } +[e :UE 3279 ] +} +"735 +[; ;mcc_generated_files/can1.c: 735: void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)) +[v _CAN1_SetFIFO1NotEmptyHandler `(v ~T0 @X0 1 ef1`*F23302 ] +"736 +[; ;mcc_generated_files/can1.c: 736: { +{ +[e :U _CAN1_SetFIFO1NotEmptyHandler ] +"735 +[; ;mcc_generated_files/can1.c: 735: void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)) +[v _handler `*F23304 ~T0 @X0 1 r1 ] +"736 +[; ;mcc_generated_files/can1.c: 736: { +[f ] +"737 +[; ;mcc_generated_files/can1.c: 737: CAN1_FIFO1NotEmptyHandler = handler; +[e = _CAN1_FIFO1NotEmptyHandler _handler ] +"738 +[; ;mcc_generated_files/can1.c: 738: } +[e :UE 3289 ] +} +"741 +[; ;mcc_generated_files/can1.c: 741: void CAN1_RXI_ISR(void) +[v _CAN1_RXI_ISR `(v ~T0 @X0 1 ef ] +"742 +[; ;mcc_generated_files/can1.c: 742: { +{ +[e :U _CAN1_RXI_ISR ] +[f ] +"743 +[; ;mcc_generated_files/can1.c: 743: if (1 == C1FIFOSTA1Lbits.TFNRFNIF) +[e $ ! == -> 1 `i -> . . _C1FIFOSTA1Lbits 0 0 `i 3291 ] +"744 +[; ;mcc_generated_files/can1.c: 744: { +{ +"745 +[; ;mcc_generated_files/can1.c: 745: CAN1_FIFO1NotEmptyHandler(); +[e ( *U _CAN1_FIFO1NotEmptyHandler .. ] +"747 +[; ;mcc_generated_files/can1.c: 747: } +} +[e :U 3291 ] +"749 +[; ;mcc_generated_files/can1.c: 749: } +[e :UE 3290 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/can1.p1.d b/ETC.X/build/default/debug/mcc_generated_files/can1.p1.d new file mode 100644 index 0000000..eec3f37 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/can1.p1.d @@ -0,0 +1,17 @@ +build/default/debug/mcc_generated_files/can1.p1: \ +mcc_generated_files/can1.c \ +mcc_generated_files/can1.h \ +mcc_generated_files/can_types.h \ +mcc_generated_files/../MESSAGES.h \ +mcc_generated_files/mcc.h \ +mcc_generated_files/device_config.h \ +mcc_generated_files/pin_manager.h \ +mcc_generated_files/interrupt_manager.h \ +mcc_generated_files/i2c1_master.h \ +mcc_generated_files/adc.h \ +mcc_generated_files/tmr1.h \ +mcc_generated_files/tmr0.h \ +mcc_generated_files/drivers/i2c_simple_master.h \ +mcc_generated_files/pwm2_16bit.h \ +mcc_generated_files/DAC3.h \ +mcc_generated_files/pwm1_16bit.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/device_config.i b/ETC.X/build/default/debug/mcc_generated_files/device_config.i new file mode 100644 index 0000000..eea58da --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/device_config.i @@ -0,0 +1,125 @@ +# 1 "mcc_generated_files/device_config.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/device_config.c" 2 +# 50 "mcc_generated_files/device_config.c" +#pragma config FEXTOSC = HS +#pragma config RSTOSC = EXTOSC + + +#pragma config CLKOUTEN = OFF +#pragma config PR1WAY = ON +#pragma config CSWEN = ON +#pragma config JTAGEN = OFF +#pragma config FCMEN = ON +#pragma config FCMENP = ON +#pragma config FCMENS = ON + + +#pragma config MCLRE = EXTMCLR +#pragma config PWRTS = PWRT_OFF +#pragma config MVECEN = OFF +#pragma config IVT1WAY = ON +#pragma config LPBOREN = OFF +#pragma config BOREN = SBORDIS + + +#pragma config BORV = VBOR_1P9 +#pragma config ZCD = OFF +#pragma config PPS1WAY = ON +#pragma config STVREN = ON +#pragma config LVP = OFF +#pragma config XINST = OFF + + +#pragma config WDTCPS = WDTCPS_31 +#pragma config WDTE = OFF + + +#pragma config WDTCWS = WDTCWS_7 +#pragma config WDTCCS = SC + + +#pragma config BBSIZE = BBSIZE_512 +#pragma config BBEN = OFF +#pragma config SAFEN = OFF + + +#pragma config WRTB = OFF +#pragma config WRTC = OFF +#pragma config WRTD = OFF +#pragma config WRTSAF = OFF +#pragma config WRTAPP = OFF + + +#pragma config BOOTPINSEL = RC5 +#pragma config BPEN = OFF +#pragma config ODCON = OFF + + +#pragma config CP = OFF + + +#pragma config BOOTSCEN = OFF +#pragma config BOOTCOE = HALT +#pragma config APPSCEN = OFF +#pragma config SAFSCEN = OFF +#pragma config DATASCEN = OFF +#pragma config CFGSCEN = OFF +#pragma config COE = HALT +#pragma config BOOTPOR = OFF + + +#pragma config BCRCPOLT = hFF + + +#pragma config BCRCPOLU = hFF + + +#pragma config BCRCPOLH = hFF + + +#pragma config BCRCPOLL = hFF + + +#pragma config BCRCSEEDT = hFF + + +#pragma config BCRCSEEDU = hFF + + +#pragma config BCRCSEEDH = hFF + + +#pragma config BCRCSEEDL = hFF + + +#pragma config CRCPOLT = hFF + + +#pragma config CRCPOLU = hFF + + +#pragma config CRCPOLH = hFF + + +#pragma config CRCPOLL = hFF + + +#pragma config CRCSEEDT = hFF + + +#pragma config CRCSEEDU = hFF + + +#pragma config CRCSEEDH = hFF + + +#pragma config CRCSEEDL = hFF +# 162 "mcc_generated_files/device_config.c" + diff --git a/ETC.X/build/default/debug/mcc_generated_files/device_config.p1 b/ETC.X/build/default/debug/mcc_generated_files/device_config.p1 new file mode 100644 index 0000000..69016ef --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/device_config.p1 @@ -0,0 +1,124 @@ +Version 4.0 HI-TECH Software Intermediate Code +"50 mcc_generated_files/device_config.c +[p x FEXTOSC = HS ] +"51 +[p x RSTOSC = EXTOSC ] +"54 +[p x CLKOUTEN = OFF ] +"55 +[p x PR1WAY = ON ] +"56 +[p x CSWEN = ON ] +"57 +[p x JTAGEN = OFF ] +"58 +[p x FCMEN = ON ] +"59 +[p x FCMENP = ON ] +"60 +[p x FCMENS = ON ] +"63 +[p x MCLRE = EXTMCLR ] +"64 +[p x PWRTS = PWRT_OFF ] +"65 +[p x MVECEN = OFF ] +"66 +[p x IVT1WAY = ON ] +"67 +[p x LPBOREN = OFF ] +"68 +[p x BOREN = SBORDIS ] +"71 +[p x BORV = VBOR_1P9 ] +"72 +[p x ZCD = OFF ] +"73 +[p x PPS1WAY = ON ] +"74 +[p x STVREN = ON ] +"75 +[p x LVP = OFF ] +"76 +[p x XINST = OFF ] +"79 +[p x WDTCPS = WDTCPS_31 ] +"80 +[p x WDTE = OFF ] +"83 +[p x WDTCWS = WDTCWS_7 ] +"84 +[p x WDTCCS = SC ] +"87 +[p x BBSIZE = BBSIZE_512 ] +"88 +[p x BBEN = OFF ] +"89 +[p x SAFEN = OFF ] +"92 +[p x WRTB = OFF ] +"93 +[p x WRTC = OFF ] +"94 +[p x WRTD = OFF ] +"95 +[p x WRTSAF = OFF ] +"96 +[p x WRTAPP = OFF ] +"99 +[p x BOOTPINSEL = RC5 ] +"100 +[p x BPEN = OFF ] +"101 +[p x ODCON = OFF ] +"104 +[p x CP = OFF ] +"107 +[p x BOOTSCEN = OFF ] +"108 +[p x BOOTCOE = HALT ] +"109 +[p x APPSCEN = OFF ] +"110 +[p x SAFSCEN = OFF ] +"111 +[p x DATASCEN = OFF ] +"112 +[p x CFGSCEN = OFF ] +"113 +[p x COE = HALT ] +"114 +[p x BOOTPOR = OFF ] +"117 +[p x BCRCPOLT = hFF ] +"120 +[p x BCRCPOLU = hFF ] +"123 +[p x BCRCPOLH = hFF ] +"126 +[p x BCRCPOLL = hFF ] +"129 +[p x BCRCSEEDT = hFF ] +"132 +[p x BCRCSEEDU = hFF ] +"135 +[p x BCRCSEEDH = hFF ] +"138 +[p x BCRCSEEDL = hFF ] +"141 +[p x CRCPOLT = hFF ] +"144 +[p x CRCPOLU = hFF ] +"147 +[p x CRCPOLH = hFF ] +"150 +[p x CRCPOLL = hFF ] +"153 +[p x CRCSEEDT = hFF ] +"156 +[p x CRCSEEDU = hFF ] +"159 +[p x CRCSEEDH = hFF ] +"162 +[; ;mcc_generated_files/device_config.c: 162: +[p x CRCSEEDL = hFF ] diff --git a/ETC.X/build/default/debug/mcc_generated_files/device_config.p1.d b/ETC.X/build/default/debug/mcc_generated_files/device_config.p1.d new file mode 100644 index 0000000..4a862c4 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/device_config.p1.d @@ -0,0 +1,2 @@ +build/default/debug/mcc_generated_files/device_config.p1: \ +mcc_generated_files/device_config.c diff --git a/ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.i b/ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.i new file mode 100644 index 0000000..eb9661c --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.i @@ -0,0 +1,472 @@ +# 1 "mcc_generated_files/drivers/i2c_simple_master.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/drivers/i2c_simple_master.c" 2 +# 30 "mcc_generated_files/drivers/i2c_simple_master.c" +# 1 "mcc_generated_files/drivers/.././i2c1_master.h" 1 +# 54 "mcc_generated_files/drivers/.././i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "mcc_generated_files/drivers/.././i2c1_master.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 55 "mcc_generated_files/drivers/.././i2c1_master.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 56 "mcc_generated_files/drivers/.././i2c1_master.h" 2 + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "mcc_generated_files/drivers/.././i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "mcc_generated_files/drivers/.././i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "mcc_generated_files/drivers/.././i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "mcc_generated_files/drivers/.././i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 30 "mcc_generated_files/drivers/i2c_simple_master.c" 2 + +# 1 "mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 37 "mcc_generated_files/drivers/i2c_simple_master.h" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 31 "mcc_generated_files/drivers/i2c_simple_master.c" 2 + + + +static i2c1_operations_t wr1RegCompleteHandler(void *p) +{ + I2C1_SetBuffer(p,1); + I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); + return I2C1_CONTINUE; +} +# 51 "mcc_generated_files/drivers/i2c_simple_master.c" +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data) +{ + while(!I2C1_Open(address)); + I2C1_SetDataCompleteCallback(wr1RegCompleteHandler,&data); + I2C1_SetBuffer(®,1); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); +} +# 71 "mcc_generated_files/drivers/i2c_simple_master.c" +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len) +{ + while(!I2C1_Open(address)); + I2C1_SetBuffer(data,len); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); +} + + +static i2c1_operations_t rd1RegCompleteHandler(void *p) +{ + I2C1_SetBuffer(p,1); + I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); + return I2C1_RESTART_READ; +} +# 97 "mcc_generated_files/drivers/i2c_simple_master.c" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg) +{ + uint8_t d2=42; + i2c1_error_t e; + int x; + + for(x = 2; x != 0; x--) + { + while(!I2C1_Open(address)); + I2C1_SetDataCompleteCallback(rd1RegCompleteHandler,&d2); + I2C1_SetBuffer(®,1); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == (e = I2C1_Close())); + if(e==I2C1_NOERR) break; + } + + + return d2; +} + + +static i2c1_operations_t rd2RegCompleteHandler(void *p) +{ + I2C1_SetBuffer(p,2); + I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); + return I2C1_RESTART_READ; +} +# 135 "mcc_generated_files/drivers/i2c_simple_master.c" +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg) +{ + + uint16_t result; + + while(!I2C1_Open(address)); + I2C1_SetDataCompleteCallback(rd2RegCompleteHandler,&result); + I2C1_SetBuffer(®,1); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); + + return (result << 8 | result >> 8); +} + + +static i2c1_operations_t wr2RegCompleteHandler(void *p) +{ + I2C1_SetBuffer(p,2); + I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); + return I2C1_CONTINUE; +} +# 168 "mcc_generated_files/drivers/i2c_simple_master.c" +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data) +{ + while(!I2C1_Open(address)); + I2C1_SetDataCompleteCallback(wr2RegCompleteHandler,&data); + I2C1_SetBuffer(®,1); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); +} + + +typedef struct +{ + size_t len; + char *data; +}buf_t; + +static i2c1_operations_t rdBlkRegCompleteHandler(void *p) +{ + I2C1_SetBuffer(((buf_t *)p)->data,((buf_t*)p)->len); + I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); + return I2C1_RESTART_READ; +} +# 203 "mcc_generated_files/drivers/i2c_simple_master.c" +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len) +{ + + buf_t d; + d.data = data; + d.len = len; + + while(!I2C1_Open(address)); + I2C1_SetDataCompleteCallback(rdBlkRegCompleteHandler,&d); + I2C1_SetBuffer(®,1); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); +} +# 228 "mcc_generated_files/drivers/i2c_simple_master.c" +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len) +{ + while(!I2C1_Open(address)); + I2C1_SetBuffer(data,len); + I2C1_MasterRead(); + while(I2C1_BUSY == I2C1_Close()); +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.p1 b/ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.p1 new file mode 100644 index 0000000..3da23d7 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.p1 @@ -0,0 +1,539 @@ +Version 4.0 HI-TECH Software Intermediate Code +"34 mcc_generated_files/drivers/i2c_simple_master.c +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 34: static i2c1_operations_t wr1RegCompleteHandler(void *p) +[c E360 1 2 3 4 5 .. ] +[n E360 . I2C1_STOP I2C1_RESTART_READ I2C1_RESTART_WRITE I2C1_CONTINUE I2C1_RESET_LINK ] +"152 mcc_generated_files/drivers/.././i2c1_master.h +[; ;mcc_generated_files/drivers/.././i2c1_master.h: 152: void I2C1_SetBuffer(void *buffer, size_t bufferSize); +[v _I2C1_SetBuffer `(v ~T0 @X0 0 ef2`*v`ui ] +[v F393 `(E360 ~T0 @X0 0 tf1`*v ] +"164 +[; ;mcc_generated_files/drivers/.././i2c1_master.h: 164: void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +[v _I2C1_SetDataCompleteCallback `(v ~T0 @X0 0 ef2`*F393`*v ] +[v F456 `(E360 ~T0 @X0 0 tf1`*v ] +"53 mcc_generated_files/drivers/i2c_simple_master.c +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 53: while(!I2C1_Open(address)); +[c E355 0 1 2 .. ] +[n E355 . I2C1_NOERR I2C1_BUSY I2C1_FAIL ] +"101 mcc_generated_files/drivers/.././i2c1_master.h +[; ;mcc_generated_files/drivers/.././i2c1_master.h: 101: i2c1_error_t I2C1_Open(i2c1_address_t address); +[v _I2C1_Open `(E355 ~T0 @X0 0 ef1`uc ] +[v F407 `(E360 ~T0 @X0 0 tf1`*v ] +"184 +[; ;mcc_generated_files/drivers/.././i2c1_master.h: 184: void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +[v _I2C1_SetAddressNackCallback `(v ~T0 @X0 0 ef2`*F407`*v ] +[v F464 `(E360 ~T0 @X0 0 tf1`*v ] +"128 +[; ;mcc_generated_files/drivers/.././i2c1_master.h: 128: i2c1_error_t I2C1_MasterWrite(void); +[v _I2C1_MasterWrite `(E355 ~T0 @X0 0 ef ] +"111 +[; ;mcc_generated_files/drivers/.././i2c1_master.h: 111: i2c1_error_t I2C1_Close(void); +[v _I2C1_Close `(E355 ~T0 @X0 0 ef ] +[v F470 `(E360 ~T0 @X0 0 tf1`*v ] +[v F474 `(E360 ~T0 @X0 0 tf1`*v ] +[v F484 `(E360 ~T0 @X0 0 tf1`*v ] +[v F488 `(E360 ~T0 @X0 0 tf1`*v ] +[v F496 `(E360 ~T0 @X0 0 tf1`*v ] +[v F500 `(E360 ~T0 @X0 0 tf1`*v ] +[v F508 `(E360 ~T0 @X0 0 tf1`*v ] +"180 mcc_generated_files/drivers/i2c_simple_master.c +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 180: { +[s S46 `ui 1 `*uc 1 ] +[n S46 . len data ] +[v F516 `(E360 ~T0 @X0 0 tf1`*v ] +[v F526 `(E360 ~T0 @X0 0 tf1`*v ] +"133 mcc_generated_files/drivers/.././i2c1_master.h +[; ;mcc_generated_files/drivers/.././i2c1_master.h: 133: i2c1_error_t I2C1_MasterRead(void); +[v _I2C1_MasterRead `(E355 ~T0 @X0 0 ef ] +"34 mcc_generated_files/drivers/i2c_simple_master.c +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 34: static i2c1_operations_t wr1RegCompleteHandler(void *p) +[v _wr1RegCompleteHandler `(E360 ~T0 @X0 1 sf1`*v ] +"35 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 35: { +{ +[e :U _wr1RegCompleteHandler ] +"34 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 34: static i2c1_operations_t wr1RegCompleteHandler(void *p) +[v _p `*v ~T0 @X0 1 r1 ] +"35 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 35: { +[f ] +"36 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 36: I2C1_SetBuffer(p,1); +[e ( _I2C1_SetBuffer (2 , _p -> -> 1 `i `ui ] +"37 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 37: I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetDataCompleteCallback (2 , -> -> -> 0 `i `*v `*F456 -> -> 0 `i `*v ] +"38 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 38: return I2C1_CONTINUE; +[e ) . `E360 3 ] +[e $UE 3 ] +"39 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 39: } +[e :UE 3 ] +} +"51 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 51: void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data) +[v _i2c_write1ByteRegister `(v ~T0 @X0 1 ef3`uc`uc`uc ] +"52 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 52: { +{ +[e :U _i2c_write1ByteRegister ] +"51 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 51: void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data) +[v _address `uc ~T0 @X0 1 r1 ] +[v _reg `uc ~T0 @X0 1 r2 ] +[v _data `uc ~T0 @X0 1 r3 ] +"52 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 52: { +[f ] +"53 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 53: while(!I2C1_Open(address)); +[e $U 5 ] +[e :U 6 ] +[e :U 5 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 6 ] +[e :U 7 ] +"54 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 54: I2C1_SetDataCompleteCallback(wr1RegCompleteHandler,&data); +[e ( _I2C1_SetDataCompleteCallback (2 , &U _wr1RegCompleteHandler -> &U _data `*v ] +"55 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 55: I2C1_SetBuffer(®,1); +[e ( _I2C1_SetBuffer (2 , -> &U _reg `*v -> -> 1 `i `ui ] +"56 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 56: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F464 -> -> 0 `i `*v ] +"57 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 57: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"58 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 58: while(I2C1_BUSY == I2C1_Close()); +[e $U 8 ] +[e :U 9 ] +[e :U 8 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 9 ] +[e :U 10 ] +"59 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 59: } +[e :UE 4 ] +} +"71 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 71: void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len) +[v _i2c_writeNBytes `(v ~T0 @X0 1 ef3`uc`*v`ui ] +"72 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 72: { +{ +[e :U _i2c_writeNBytes ] +"71 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 71: void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len) +[v _address `uc ~T0 @X0 1 r1 ] +[v _data `*v ~T0 @X0 1 r2 ] +[v _len `ui ~T0 @X0 1 r3 ] +"72 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 72: { +[f ] +"73 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 73: while(!I2C1_Open(address)); +[e $U 12 ] +[e :U 13 ] +[e :U 12 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 13 ] +[e :U 14 ] +"74 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 74: I2C1_SetBuffer(data,len); +[e ( _I2C1_SetBuffer (2 , _data _len ] +"75 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 75: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F470 -> -> 0 `i `*v ] +"76 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 76: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"77 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 77: while(I2C1_BUSY == I2C1_Close()); +[e $U 15 ] +[e :U 16 ] +[e :U 15 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 16 ] +[e :U 17 ] +"78 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 78: } +[e :UE 11 ] +} +"81 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 81: static i2c1_operations_t rd1RegCompleteHandler(void *p) +[v _rd1RegCompleteHandler `(E360 ~T0 @X0 1 sf1`*v ] +"82 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 82: { +{ +[e :U _rd1RegCompleteHandler ] +"81 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 81: static i2c1_operations_t rd1RegCompleteHandler(void *p) +[v _p `*v ~T0 @X0 1 r1 ] +"82 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 82: { +[f ] +"83 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 83: I2C1_SetBuffer(p,1); +[e ( _I2C1_SetBuffer (2 , _p -> -> 1 `i `ui ] +"84 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 84: I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetDataCompleteCallback (2 , -> -> -> 0 `i `*v `*F474 -> -> 0 `i `*v ] +"85 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 85: return I2C1_RESTART_READ; +[e ) . `E360 1 ] +[e $UE 18 ] +"86 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 86: } +[e :UE 18 ] +} +"97 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 97: uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg) +[v _i2c_read1ByteRegister `(uc ~T0 @X0 1 ef2`uc`uc ] +"98 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 98: { +{ +[e :U _i2c_read1ByteRegister ] +"97 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 97: uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg) +[v _address `uc ~T0 @X0 1 r1 ] +[v _reg `uc ~T0 @X0 1 r2 ] +"98 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 98: { +[f ] +"99 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 99: uint8_t d2=42; +[v _d2 `uc ~T0 @X0 1 a ] +[e = _d2 -> -> 42 `i `uc ] +"100 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 100: i2c1_error_t e; +[v _e `E355 ~T0 @X0 1 a ] +"101 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 101: int x; +[v _x `i ~T0 @X0 1 a ] +"103 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 103: for(x = 2; x != 0; x--) +{ +[e = _x -> 2 `i ] +[e $ != _x -> 0 `i 20 ] +[e $U 21 ] +[e :U 20 ] +"104 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 104: { +{ +"105 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 105: while(!I2C1_Open(address)); +[e $U 23 ] +[e :U 24 ] +[e :U 23 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 24 ] +[e :U 25 ] +"106 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 106: I2C1_SetDataCompleteCallback(rd1RegCompleteHandler,&d2); +[e ( _I2C1_SetDataCompleteCallback (2 , &U _rd1RegCompleteHandler -> &U _d2 `*v ] +"107 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 107: I2C1_SetBuffer(®,1); +[e ( _I2C1_SetBuffer (2 , -> &U _reg `*v -> -> 1 `i `ui ] +"108 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 108: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F484 -> -> 0 `i `*v ] +"109 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 109: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"110 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 110: while(I2C1_BUSY == (e = I2C1_Close())); +[e $U 26 ] +[e :U 27 ] +[e :U 26 ] +[e $ == -> . `E355 1 `ui -> = _e ( _I2C1_Close .. `ui 27 ] +[e :U 28 ] +"111 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 111: if(e==I2C1_NOERR) break; +[e $ ! == -> _e `ui -> . `E355 0 `ui 29 ] +[e $U 21 ] +[e :U 29 ] +"112 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 112: } +} +[e -- _x -> 1 `i ] +[e $ != _x -> 0 `i 20 ] +[e :U 21 ] +} +"115 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 115: return d2; +[e ) _d2 ] +[e $UE 19 ] +"116 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 116: } +[e :UE 19 ] +} +"119 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 119: static i2c1_operations_t rd2RegCompleteHandler(void *p) +[v _rd2RegCompleteHandler `(E360 ~T0 @X0 1 sf1`*v ] +"120 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 120: { +{ +[e :U _rd2RegCompleteHandler ] +"119 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 119: static i2c1_operations_t rd2RegCompleteHandler(void *p) +[v _p `*v ~T0 @X0 1 r1 ] +"120 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 120: { +[f ] +"121 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 121: I2C1_SetBuffer(p,2); +[e ( _I2C1_SetBuffer (2 , _p -> -> 2 `i `ui ] +"122 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 122: I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetDataCompleteCallback (2 , -> -> -> 0 `i `*v `*F488 -> -> 0 `i `*v ] +"123 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 123: return I2C1_RESTART_READ; +[e ) . `E360 1 ] +[e $UE 30 ] +"124 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 124: } +[e :UE 30 ] +} +"135 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 135: uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg) +[v _i2c_read2ByteRegister `(us ~T0 @X0 1 ef2`uc`uc ] +"136 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 136: { +{ +[e :U _i2c_read2ByteRegister ] +"135 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 135: uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg) +[v _address `uc ~T0 @X0 1 r1 ] +[v _reg `uc ~T0 @X0 1 r2 ] +"136 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 136: { +[f ] +"138 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 138: uint16_t result; +[v _result `us ~T0 @X0 1 a ] +"140 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 140: while(!I2C1_Open(address)); +[e $U 32 ] +[e :U 33 ] +[e :U 32 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 33 ] +[e :U 34 ] +"141 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 141: I2C1_SetDataCompleteCallback(rd2RegCompleteHandler,&result); +[e ( _I2C1_SetDataCompleteCallback (2 , &U _rd2RegCompleteHandler -> &U _result `*v ] +"142 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 142: I2C1_SetBuffer(®,1); +[e ( _I2C1_SetBuffer (2 , -> &U _reg `*v -> -> 1 `i `ui ] +"143 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 143: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F496 -> -> 0 `i `*v ] +"144 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 144: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"145 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 145: while(I2C1_BUSY == I2C1_Close()); +[e $U 35 ] +[e :U 36 ] +[e :U 35 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 36 ] +[e :U 37 ] +"147 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 147: return (result << 8 | result >> 8); +[e ) -> | << -> _result `ui -> 8 `i >> -> _result `ui -> 8 `i `us ] +[e $UE 31 ] +"148 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 148: } +[e :UE 31 ] +} +"151 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 151: static i2c1_operations_t wr2RegCompleteHandler(void *p) +[v _wr2RegCompleteHandler `(E360 ~T0 @X0 1 sf1`*v ] +"152 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 152: { +{ +[e :U _wr2RegCompleteHandler ] +"151 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 151: static i2c1_operations_t wr2RegCompleteHandler(void *p) +[v _p `*v ~T0 @X0 1 r1 ] +"152 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 152: { +[f ] +"153 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 153: I2C1_SetBuffer(p,2); +[e ( _I2C1_SetBuffer (2 , _p -> -> 2 `i `ui ] +"154 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 154: I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetDataCompleteCallback (2 , -> -> -> 0 `i `*v `*F500 -> -> 0 `i `*v ] +"155 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 155: return I2C1_CONTINUE; +[e ) . `E360 3 ] +[e $UE 38 ] +"156 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 156: } +[e :UE 38 ] +} +"168 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 168: void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data) +[v _i2c_write2ByteRegister `(v ~T0 @X0 1 ef3`uc`uc`us ] +"169 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 169: { +{ +[e :U _i2c_write2ByteRegister ] +"168 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 168: void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data) +[v _address `uc ~T0 @X0 1 r1 ] +[v _reg `uc ~T0 @X0 1 r2 ] +[v _data `us ~T0 @X0 1 r3 ] +"169 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 169: { +[f ] +"170 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 170: while(!I2C1_Open(address)); +[e $U 40 ] +[e :U 41 ] +[e :U 40 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 41 ] +[e :U 42 ] +"171 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 171: I2C1_SetDataCompleteCallback(wr2RegCompleteHandler,&data); +[e ( _I2C1_SetDataCompleteCallback (2 , &U _wr2RegCompleteHandler -> &U _data `*v ] +"172 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 172: I2C1_SetBuffer(®,1); +[e ( _I2C1_SetBuffer (2 , -> &U _reg `*v -> -> 1 `i `ui ] +"173 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 173: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F508 -> -> 0 `i `*v ] +"174 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 174: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"175 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 175: while(I2C1_BUSY == I2C1_Close()); +[e $U 43 ] +[e :U 44 ] +[e :U 43 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 44 ] +[e :U 45 ] +"176 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 176: } +[e :UE 39 ] +} +"185 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 185: static i2c1_operations_t rdBlkRegCompleteHandler(void *p) +[v _rdBlkRegCompleteHandler `(E360 ~T0 @X0 1 sf1`*v ] +"186 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 186: { +{ +[e :U _rdBlkRegCompleteHandler ] +"185 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 185: static i2c1_operations_t rdBlkRegCompleteHandler(void *p) +[v _p `*v ~T0 @X0 1 r1 ] +"186 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 186: { +[f ] +"187 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 187: I2C1_SetBuffer(((buf_t *)p)->data,((buf_t*)p)->len); +[e ( _I2C1_SetBuffer (2 , -> . *U -> _p `*S46 1 `*v . *U -> _p `*S46 0 ] +"188 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 188: I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetDataCompleteCallback (2 , -> -> -> 0 `i `*v `*F516 -> -> 0 `i `*v ] +"189 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 189: return I2C1_RESTART_READ; +[e ) . `E360 1 ] +[e $UE 47 ] +"190 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 190: } +[e :UE 47 ] +} +"203 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 203: void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len) +[v _i2c_readDataBlock `(v ~T0 @X0 1 ef4`uc`uc`*v`ui ] +"204 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 204: { +{ +[e :U _i2c_readDataBlock ] +"203 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 203: void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len) +[v _address `uc ~T0 @X0 1 r1 ] +[v _reg `uc ~T0 @X0 1 r2 ] +[v _data `*v ~T0 @X0 1 r3 ] +[v _len `ui ~T0 @X0 1 r4 ] +"204 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 204: { +[f ] +"206 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 206: buf_t d; +[v _d `S46 ~T0 @X0 1 a ] +"207 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 207: d.data = data; +[e = . _d 1 -> _data `*uc ] +"208 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 208: d.len = len; +[e = . _d 0 _len ] +"210 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 210: while(!I2C1_Open(address)); +[e $U 49 ] +[e :U 50 ] +[e :U 49 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 50 ] +[e :U 51 ] +"211 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 211: I2C1_SetDataCompleteCallback(rdBlkRegCompleteHandler,&d); +[e ( _I2C1_SetDataCompleteCallback (2 , &U _rdBlkRegCompleteHandler -> &U _d `*v ] +"212 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 212: I2C1_SetBuffer(®,1); +[e ( _I2C1_SetBuffer (2 , -> &U _reg `*v -> -> 1 `i `ui ] +"213 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 213: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F526 -> -> 0 `i `*v ] +"214 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 214: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"215 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 215: while(I2C1_BUSY == I2C1_Close()); +[e $U 52 ] +[e :U 53 ] +[e :U 52 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 53 ] +[e :U 54 ] +"216 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 216: } +[e :UE 48 ] +} +"228 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 228: void i2c_readNBytes(i2c1_address_t address, void *data, size_t len) +[v _i2c_readNBytes `(v ~T0 @X0 1 ef3`uc`*v`ui ] +"229 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 229: { +{ +[e :U _i2c_readNBytes ] +"228 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 228: void i2c_readNBytes(i2c1_address_t address, void *data, size_t len) +[v _address `uc ~T0 @X0 1 r1 ] +[v _data `*v ~T0 @X0 1 r2 ] +[v _len `ui ~T0 @X0 1 r3 ] +"229 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 229: { +[f ] +"230 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 230: while(!I2C1_Open(address)); +[e $U 56 ] +[e :U 57 ] +[e :U 56 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 57 ] +[e :U 58 ] +"231 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 231: I2C1_SetBuffer(data,len); +[e ( _I2C1_SetBuffer (2 , _data _len ] +"232 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 232: I2C1_MasterRead(); +[e ( _I2C1_MasterRead .. ] +"233 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 233: while(I2C1_BUSY == I2C1_Close()); +[e $U 59 ] +[e :U 60 ] +[e :U 59 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 60 ] +[e :U 61 ] +"234 +[; ;mcc_generated_files/drivers/i2c_simple_master.c: 234: } +[e :UE 55 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.p1.d b/ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.p1.d new file mode 100644 index 0000000..02666d5 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/drivers/i2c_simple_master.p1.d @@ -0,0 +1,4 @@ +build/default/debug/mcc_generated_files/drivers/i2c_simple_master.p1: \ +mcc_generated_files/drivers/i2c_simple_master.c \ +mcc_generated_files/drivers/.././i2c1_master.h \ +mcc_generated_files/drivers/i2c_simple_master.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.i b/ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.i new file mode 100644 index 0000000..df7ff6d --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.i @@ -0,0 +1,473 @@ +# 1 "mcc_generated_files/examples/i2c1_master_example.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/examples/i2c1_master_example.c" 2 +# 47 "mcc_generated_files/examples/i2c1_master_example.c" +# 1 "mcc_generated_files/examples/i2c1_master_example.h" 1 +# 50 "mcc_generated_files/examples/i2c1_master_example.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; + + + + +typedef __int24 int24_t; + + + + +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; + + + + +typedef __uint24 uint24_t; + + + + +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 50 "mcc_generated_files/examples/i2c1_master_example.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 51 "mcc_generated_files/examples/i2c1_master_example.h" 2 + +# 1 "mcc_generated_files/examples/../i2c1_master.h" 1 +# 56 "mcc_generated_files/examples/../i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 56 "mcc_generated_files/examples/../i2c1_master.h" 2 + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "mcc_generated_files/examples/../i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "mcc_generated_files/examples/../i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "mcc_generated_files/examples/../i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "mcc_generated_files/examples/../i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "mcc_generated_files/examples/../i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "mcc_generated_files/examples/../i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "mcc_generated_files/examples/../i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "mcc_generated_files/examples/../i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "mcc_generated_files/examples/../i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "mcc_generated_files/examples/../i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 52 "mcc_generated_files/examples/i2c1_master_example.h" 2 + + +uint8_t I2C1_Read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t I2C1_Read2ByteRegister(i2c1_address_t address, uint8_t reg); +void I2C1_Write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void I2C1_Write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); +void I2C1_WriteNBytes(i2c1_address_t address, uint8_t *data, size_t len); +void I2C1_ReadNBytes(i2c1_address_t address, uint8_t *data, size_t len); +void I2C1_ReadDataBlock(i2c1_address_t address, uint8_t reg, uint8_t *data, size_t len); +# 47 "mcc_generated_files/examples/i2c1_master_example.c" 2 + + + +typedef struct +{ + size_t len; + uint8_t *data; +}i2c1_buffer_t; + +static i2c1_operations_t rd1RegCompleteHandler(void *ptr); +static i2c1_operations_t rd2RegCompleteHandler(void *ptr); +static i2c1_operations_t wr1RegCompleteHandler(void *ptr); +static i2c1_operations_t wr2RegCompleteHandler(void *ptr); +static i2c1_operations_t rdBlkRegCompleteHandler(void *ptr); + + +uint8_t I2C1_Read1ByteRegister(i2c1_address_t address, uint8_t reg) +{ + uint8_t returnValue = 0x00; + + while(!I2C1_Open(address)); + I2C1_SetDataCompleteCallback(rd1RegCompleteHandler,&returnValue); + I2C1_SetBuffer(®,1); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); + + return returnValue; +} + +uint16_t I2C1_Read2ByteRegister(i2c1_address_t address, uint8_t reg) +{ + uint16_t returnValue =0x00; + + while(!I2C1_Open(address)); + I2C1_SetDataCompleteCallback(rd2RegCompleteHandler,&returnValue); + I2C1_SetBuffer(®,1); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); + + return (returnValue << 8 | returnValue >> 8); +} + +void I2C1_Write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data) +{ + while(!I2C1_Open(address)); + I2C1_SetDataCompleteCallback(wr1RegCompleteHandler,&data); + I2C1_SetBuffer(®,1); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); +} + +void I2C1_Write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data) +{ + while(!I2C1_Open(address)); + I2C1_SetDataCompleteCallback(wr2RegCompleteHandler,&data); + I2C1_SetBuffer(®,1); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); +} + +void I2C1_WriteNBytes(i2c1_address_t address, uint8_t* data, size_t len) +{ + while(!I2C1_Open(address)); + I2C1_SetBuffer(data,len); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); +} + +void I2C1_ReadNBytes(i2c1_address_t address, uint8_t *data, size_t len) +{ + while(!I2C1_Open(address)); + I2C1_SetBuffer(data,len); + I2C1_MasterRead(); + while(I2C1_BUSY == I2C1_Close()); +} + +void I2C1_ReadDataBlock(i2c1_address_t address, uint8_t reg, uint8_t *data, size_t len) +{ + i2c1_buffer_t bufferBlock; + bufferBlock.data = data; + bufferBlock.len = len; + + while(!I2C1_Open(address)); + I2C1_SetDataCompleteCallback(rdBlkRegCompleteHandler,&bufferBlock); + I2C1_SetBuffer(®,1); + I2C1_SetAddressNackCallback(((void*)0),((void*)0)); + I2C1_MasterWrite(); + while(I2C1_BUSY == I2C1_Close()); +} + +static i2c1_operations_t rd1RegCompleteHandler(void *ptr) +{ + I2C1_SetBuffer(ptr,1); + I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); + return I2C1_RESTART_READ; +} + +static i2c1_operations_t rd2RegCompleteHandler(void *ptr) +{ + I2C1_SetBuffer(ptr,2); + I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); + return I2C1_RESTART_READ; +} + +static i2c1_operations_t wr1RegCompleteHandler(void *ptr) +{ + I2C1_SetBuffer(ptr,1); + I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); + return I2C1_CONTINUE; +} + +static i2c1_operations_t wr2RegCompleteHandler(void *ptr) +{ + I2C1_SetBuffer(ptr,2); + I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); + return I2C1_CONTINUE; +} + +static i2c1_operations_t rdBlkRegCompleteHandler(void *ptr) +{ + I2C1_SetBuffer(((i2c1_buffer_t *)ptr)->data,((i2c1_buffer_t*)ptr)->len); + I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); + return I2C1_RESTART_READ; +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.p1 b/ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.p1 new file mode 100644 index 0000000..fdedd31 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.p1 @@ -0,0 +1,527 @@ +Version 4.0 HI-TECH Software Intermediate Code +"67 mcc_generated_files/examples/i2c1_master_example.c +[; ;mcc_generated_files/examples/i2c1_master_example.c: 67: while(!I2C1_Open(address)); +[c E355 0 1 2 .. ] +[n E355 . I2C1_NOERR I2C1_BUSY I2C1_FAIL ] +"101 mcc_generated_files/examples/../i2c1_master.h +[; ;mcc_generated_files/examples/../i2c1_master.h: 101: i2c1_error_t I2C1_Open(i2c1_address_t address); +[v _I2C1_Open `(E355 ~T0 @X0 0 ef1`uc ] +"68 mcc_generated_files/examples/i2c1_master_example.c +[; ;mcc_generated_files/examples/i2c1_master_example.c: 68: I2C1_SetDataCompleteCallback(rd1RegCompleteHandler,&returnValue); +[c E360 1 2 3 4 5 .. ] +[n E360 . I2C1_STOP I2C1_RESTART_READ I2C1_RESTART_WRITE I2C1_CONTINUE I2C1_RESET_LINK ] +[v F393 `(E360 ~T0 @X0 0 tf1`*v ] +"164 mcc_generated_files/examples/../i2c1_master.h +[; ;mcc_generated_files/examples/../i2c1_master.h: 164: void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +[v _I2C1_SetDataCompleteCallback `(v ~T0 @X0 0 ef2`*F393`*v ] +"56 mcc_generated_files/examples/i2c1_master_example.c +[; ;mcc_generated_files/examples/i2c1_master_example.c: 56: static i2c1_operations_t rd1RegCompleteHandler(void *ptr); +[v _rd1RegCompleteHandler `(E360 ~T0 @X0 0 sf1`*v ] +"152 mcc_generated_files/examples/../i2c1_master.h +[; ;mcc_generated_files/examples/../i2c1_master.h: 152: void I2C1_SetBuffer(void *buffer, size_t bufferSize); +[v _I2C1_SetBuffer `(v ~T0 @X0 0 ef2`*v`ui ] +[v F407 `(E360 ~T0 @X0 0 tf1`*v ] +"184 +[; ;mcc_generated_files/examples/../i2c1_master.h: 184: void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +[v _I2C1_SetAddressNackCallback `(v ~T0 @X0 0 ef2`*F407`*v ] +[v F474 `(E360 ~T0 @X0 0 tf1`*v ] +"128 +[; ;mcc_generated_files/examples/../i2c1_master.h: 128: i2c1_error_t I2C1_MasterWrite(void); +[v _I2C1_MasterWrite `(E355 ~T0 @X0 0 ef ] +"111 +[; ;mcc_generated_files/examples/../i2c1_master.h: 111: i2c1_error_t I2C1_Close(void); +[v _I2C1_Close `(E355 ~T0 @X0 0 ef ] +"57 mcc_generated_files/examples/i2c1_master_example.c +[; ;mcc_generated_files/examples/i2c1_master_example.c: 57: static i2c1_operations_t rd2RegCompleteHandler(void *ptr); +[v _rd2RegCompleteHandler `(E360 ~T0 @X0 0 sf1`*v ] +[v F482 `(E360 ~T0 @X0 0 tf1`*v ] +"58 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 58: static i2c1_operations_t wr1RegCompleteHandler(void *ptr); +[v _wr1RegCompleteHandler `(E360 ~T0 @X0 0 sf1`*v ] +[v F490 `(E360 ~T0 @X0 0 tf1`*v ] +"59 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 59: static i2c1_operations_t wr2RegCompleteHandler(void *ptr); +[v _wr2RegCompleteHandler `(E360 ~T0 @X0 0 sf1`*v ] +[v F498 `(E360 ~T0 @X0 0 tf1`*v ] +[v F504 `(E360 ~T0 @X0 0 tf1`*v ] +"133 mcc_generated_files/examples/../i2c1_master.h +[; ;mcc_generated_files/examples/../i2c1_master.h: 133: i2c1_error_t I2C1_MasterRead(void); +[v _I2C1_MasterRead `(E355 ~T0 @X0 0 ef ] +"51 mcc_generated_files/examples/i2c1_master_example.c +[; ;mcc_generated_files/examples/i2c1_master_example.c: 51: { +[s S3 `ui 1 `*uc 1 ] +[n S3 . len data ] +"60 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 60: static i2c1_operations_t rdBlkRegCompleteHandler(void *ptr); +[v _rdBlkRegCompleteHandler `(E360 ~T0 @X0 0 sf1`*v ] +[v F518 `(E360 ~T0 @X0 0 tf1`*v ] +[v F522 `(E360 ~T0 @X0 0 tf1`*v ] +[v F526 `(E360 ~T0 @X0 0 tf1`*v ] +[v F530 `(E360 ~T0 @X0 0 tf1`*v ] +[v F534 `(E360 ~T0 @X0 0 tf1`*v ] +[v F538 `(E360 ~T0 @X0 0 tf1`*v ] +"63 mcc_generated_files/examples/i2c1_master_example.c +[; ;mcc_generated_files/examples/i2c1_master_example.c: 63: uint8_t I2C1_Read1ByteRegister(i2c1_address_t address, uint8_t reg) +[v _I2C1_Read1ByteRegister `(uc ~T0 @X0 1 ef2`uc`uc ] +"64 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 64: { +{ +[e :U _I2C1_Read1ByteRegister ] +"63 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 63: uint8_t I2C1_Read1ByteRegister(i2c1_address_t address, uint8_t reg) +[v _address `uc ~T0 @X0 1 r1 ] +[v _reg `uc ~T0 @X0 1 r2 ] +"64 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 64: { +[f ] +"65 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 65: uint8_t returnValue = 0x00; +[v _returnValue `uc ~T0 @X0 1 a ] +[e = _returnValue -> -> 0 `i `uc ] +"67 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 67: while(!I2C1_Open(address)); +[e $U 5 ] +[e :U 6 ] +[e :U 5 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 6 ] +[e :U 7 ] +"68 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 68: I2C1_SetDataCompleteCallback(rd1RegCompleteHandler,&returnValue); +[e ( _I2C1_SetDataCompleteCallback (2 , &U _rd1RegCompleteHandler -> &U _returnValue `*v ] +"69 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 69: I2C1_SetBuffer(®,1); +[e ( _I2C1_SetBuffer (2 , -> &U _reg `*v -> -> 1 `i `ui ] +"70 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 70: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F474 -> -> 0 `i `*v ] +"71 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 71: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"72 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 72: while(I2C1_BUSY == I2C1_Close()); +[e $U 8 ] +[e :U 9 ] +[e :U 8 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 9 ] +[e :U 10 ] +"74 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 74: return returnValue; +[e ) _returnValue ] +[e $UE 4 ] +"75 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 75: } +[e :UE 4 ] +} +"77 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 77: uint16_t I2C1_Read2ByteRegister(i2c1_address_t address, uint8_t reg) +[v _I2C1_Read2ByteRegister `(us ~T0 @X0 1 ef2`uc`uc ] +"78 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 78: { +{ +[e :U _I2C1_Read2ByteRegister ] +"77 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 77: uint16_t I2C1_Read2ByteRegister(i2c1_address_t address, uint8_t reg) +[v _address `uc ~T0 @X0 1 r1 ] +[v _reg `uc ~T0 @X0 1 r2 ] +"78 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 78: { +[f ] +"79 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 79: uint16_t returnValue =0x00; +[v _returnValue `us ~T0 @X0 1 a ] +[e = _returnValue -> -> 0 `i `us ] +"81 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 81: while(!I2C1_Open(address)); +[e $U 12 ] +[e :U 13 ] +[e :U 12 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 13 ] +[e :U 14 ] +"82 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 82: I2C1_SetDataCompleteCallback(rd2RegCompleteHandler,&returnValue); +[e ( _I2C1_SetDataCompleteCallback (2 , &U _rd2RegCompleteHandler -> &U _returnValue `*v ] +"83 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 83: I2C1_SetBuffer(®,1); +[e ( _I2C1_SetBuffer (2 , -> &U _reg `*v -> -> 1 `i `ui ] +"84 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 84: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F482 -> -> 0 `i `*v ] +"85 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 85: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"86 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 86: while(I2C1_BUSY == I2C1_Close()); +[e $U 15 ] +[e :U 16 ] +[e :U 15 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 16 ] +[e :U 17 ] +"88 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 88: return (returnValue << 8 | returnValue >> 8); +[e ) -> | << -> _returnValue `ui -> 8 `i >> -> _returnValue `ui -> 8 `i `us ] +[e $UE 11 ] +"89 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 89: } +[e :UE 11 ] +} +"91 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 91: void I2C1_Write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data) +[v _I2C1_Write1ByteRegister `(v ~T0 @X0 1 ef3`uc`uc`uc ] +"92 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 92: { +{ +[e :U _I2C1_Write1ByteRegister ] +"91 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 91: void I2C1_Write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data) +[v _address `uc ~T0 @X0 1 r1 ] +[v _reg `uc ~T0 @X0 1 r2 ] +[v _data `uc ~T0 @X0 1 r3 ] +"92 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 92: { +[f ] +"93 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 93: while(!I2C1_Open(address)); +[e $U 19 ] +[e :U 20 ] +[e :U 19 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 20 ] +[e :U 21 ] +"94 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 94: I2C1_SetDataCompleteCallback(wr1RegCompleteHandler,&data); +[e ( _I2C1_SetDataCompleteCallback (2 , &U _wr1RegCompleteHandler -> &U _data `*v ] +"95 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 95: I2C1_SetBuffer(®,1); +[e ( _I2C1_SetBuffer (2 , -> &U _reg `*v -> -> 1 `i `ui ] +"96 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 96: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F490 -> -> 0 `i `*v ] +"97 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 97: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"98 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 98: while(I2C1_BUSY == I2C1_Close()); +[e $U 22 ] +[e :U 23 ] +[e :U 22 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 23 ] +[e :U 24 ] +"99 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 99: } +[e :UE 18 ] +} +"101 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 101: void I2C1_Write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data) +[v _I2C1_Write2ByteRegister `(v ~T0 @X0 1 ef3`uc`uc`us ] +"102 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 102: { +{ +[e :U _I2C1_Write2ByteRegister ] +"101 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 101: void I2C1_Write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data) +[v _address `uc ~T0 @X0 1 r1 ] +[v _reg `uc ~T0 @X0 1 r2 ] +[v _data `us ~T0 @X0 1 r3 ] +"102 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 102: { +[f ] +"103 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 103: while(!I2C1_Open(address)); +[e $U 26 ] +[e :U 27 ] +[e :U 26 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 27 ] +[e :U 28 ] +"104 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 104: I2C1_SetDataCompleteCallback(wr2RegCompleteHandler,&data); +[e ( _I2C1_SetDataCompleteCallback (2 , &U _wr2RegCompleteHandler -> &U _data `*v ] +"105 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 105: I2C1_SetBuffer(®,1); +[e ( _I2C1_SetBuffer (2 , -> &U _reg `*v -> -> 1 `i `ui ] +"106 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 106: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F498 -> -> 0 `i `*v ] +"107 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 107: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"108 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 108: while(I2C1_BUSY == I2C1_Close()); +[e $U 29 ] +[e :U 30 ] +[e :U 29 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 30 ] +[e :U 31 ] +"109 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 109: } +[e :UE 25 ] +} +"111 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 111: void I2C1_WriteNBytes(i2c1_address_t address, uint8_t* data, size_t len) +[v _I2C1_WriteNBytes `(v ~T0 @X0 1 ef3`uc`*uc`ui ] +"112 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 112: { +{ +[e :U _I2C1_WriteNBytes ] +"111 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 111: void I2C1_WriteNBytes(i2c1_address_t address, uint8_t* data, size_t len) +[v _address `uc ~T0 @X0 1 r1 ] +[v _data `*uc ~T0 @X0 1 r2 ] +[v _len `ui ~T0 @X0 1 r3 ] +"112 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 112: { +[f ] +"113 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 113: while(!I2C1_Open(address)); +[e $U 33 ] +[e :U 34 ] +[e :U 33 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 34 ] +[e :U 35 ] +"114 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 114: I2C1_SetBuffer(data,len); +[e ( _I2C1_SetBuffer (2 , -> _data `*v _len ] +"115 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 115: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F504 -> -> 0 `i `*v ] +"116 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 116: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"117 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 117: while(I2C1_BUSY == I2C1_Close()); +[e $U 36 ] +[e :U 37 ] +[e :U 36 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 37 ] +[e :U 38 ] +"118 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 118: } +[e :UE 32 ] +} +"120 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 120: void I2C1_ReadNBytes(i2c1_address_t address, uint8_t *data, size_t len) +[v _I2C1_ReadNBytes `(v ~T0 @X0 1 ef3`uc`*uc`ui ] +"121 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 121: { +{ +[e :U _I2C1_ReadNBytes ] +"120 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 120: void I2C1_ReadNBytes(i2c1_address_t address, uint8_t *data, size_t len) +[v _address `uc ~T0 @X0 1 r1 ] +[v _data `*uc ~T0 @X0 1 r2 ] +[v _len `ui ~T0 @X0 1 r3 ] +"121 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 121: { +[f ] +"122 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 122: while(!I2C1_Open(address)); +[e $U 40 ] +[e :U 41 ] +[e :U 40 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 41 ] +[e :U 42 ] +"123 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 123: I2C1_SetBuffer(data,len); +[e ( _I2C1_SetBuffer (2 , -> _data `*v _len ] +"124 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 124: I2C1_MasterRead(); +[e ( _I2C1_MasterRead .. ] +"125 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 125: while(I2C1_BUSY == I2C1_Close()); +[e $U 43 ] +[e :U 44 ] +[e :U 43 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 44 ] +[e :U 45 ] +"126 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 126: } +[e :UE 39 ] +} +"128 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 128: void I2C1_ReadDataBlock(i2c1_address_t address, uint8_t reg, uint8_t *data, size_t len) +[v _I2C1_ReadDataBlock `(v ~T0 @X0 1 ef4`uc`uc`*uc`ui ] +"129 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 129: { +{ +[e :U _I2C1_ReadDataBlock ] +"128 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 128: void I2C1_ReadDataBlock(i2c1_address_t address, uint8_t reg, uint8_t *data, size_t len) +[v _address `uc ~T0 @X0 1 r1 ] +[v _reg `uc ~T0 @X0 1 r2 ] +[v _data `*uc ~T0 @X0 1 r3 ] +[v _len `ui ~T0 @X0 1 r4 ] +"129 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 129: { +[f ] +"130 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 130: i2c1_buffer_t bufferBlock; +[v _bufferBlock `S3 ~T0 @X0 1 a ] +"131 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 131: bufferBlock.data = data; +[e = . _bufferBlock 1 _data ] +"132 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 132: bufferBlock.len = len; +[e = . _bufferBlock 0 _len ] +"134 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 134: while(!I2C1_Open(address)); +[e $U 47 ] +[e :U 48 ] +[e :U 47 ] +[e $ ! != -> ( _I2C1_Open (1 _address `ui -> -> 0 `i `ui 48 ] +[e :U 49 ] +"135 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 135: I2C1_SetDataCompleteCallback(rdBlkRegCompleteHandler,&bufferBlock); +[e ( _I2C1_SetDataCompleteCallback (2 , &U _rdBlkRegCompleteHandler -> &U _bufferBlock `*v ] +"136 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 136: I2C1_SetBuffer(®,1); +[e ( _I2C1_SetBuffer (2 , -> &U _reg `*v -> -> 1 `i `ui ] +"137 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 137: I2C1_SetAddressNackCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetAddressNackCallback (2 , -> -> -> 0 `i `*v `*F518 -> -> 0 `i `*v ] +"138 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 138: I2C1_MasterWrite(); +[e ( _I2C1_MasterWrite .. ] +"139 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 139: while(I2C1_BUSY == I2C1_Close()); +[e $U 50 ] +[e :U 51 ] +[e :U 50 ] +[e $ == -> . `E355 1 `ui -> ( _I2C1_Close .. `ui 51 ] +[e :U 52 ] +"140 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 140: } +[e :UE 46 ] +} +"142 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 142: static i2c1_operations_t rd1RegCompleteHandler(void *ptr) +[v _rd1RegCompleteHandler `(E360 ~T0 @X0 1 sf1`*v ] +"143 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 143: { +{ +[e :U _rd1RegCompleteHandler ] +"142 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 142: static i2c1_operations_t rd1RegCompleteHandler(void *ptr) +[v _ptr `*v ~T0 @X0 1 r1 ] +"143 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 143: { +[f ] +"144 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 144: I2C1_SetBuffer(ptr,1); +[e ( _I2C1_SetBuffer (2 , _ptr -> -> 1 `i `ui ] +"145 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 145: I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetDataCompleteCallback (2 , -> -> -> 0 `i `*v `*F522 -> -> 0 `i `*v ] +"146 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 146: return I2C1_RESTART_READ; +[e ) . `E360 1 ] +[e $UE 53 ] +"147 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 147: } +[e :UE 53 ] +} +"149 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 149: static i2c1_operations_t rd2RegCompleteHandler(void *ptr) +[v _rd2RegCompleteHandler `(E360 ~T0 @X0 1 sf1`*v ] +"150 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 150: { +{ +[e :U _rd2RegCompleteHandler ] +"149 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 149: static i2c1_operations_t rd2RegCompleteHandler(void *ptr) +[v _ptr `*v ~T0 @X0 1 r1 ] +"150 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 150: { +[f ] +"151 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 151: I2C1_SetBuffer(ptr,2); +[e ( _I2C1_SetBuffer (2 , _ptr -> -> 2 `i `ui ] +"152 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 152: I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetDataCompleteCallback (2 , -> -> -> 0 `i `*v `*F526 -> -> 0 `i `*v ] +"153 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 153: return I2C1_RESTART_READ; +[e ) . `E360 1 ] +[e $UE 54 ] +"154 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 154: } +[e :UE 54 ] +} +"156 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 156: static i2c1_operations_t wr1RegCompleteHandler(void *ptr) +[v _wr1RegCompleteHandler `(E360 ~T0 @X0 1 sf1`*v ] +"157 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 157: { +{ +[e :U _wr1RegCompleteHandler ] +"156 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 156: static i2c1_operations_t wr1RegCompleteHandler(void *ptr) +[v _ptr `*v ~T0 @X0 1 r1 ] +"157 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 157: { +[f ] +"158 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 158: I2C1_SetBuffer(ptr,1); +[e ( _I2C1_SetBuffer (2 , _ptr -> -> 1 `i `ui ] +"159 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 159: I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetDataCompleteCallback (2 , -> -> -> 0 `i `*v `*F530 -> -> 0 `i `*v ] +"160 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 160: return I2C1_CONTINUE; +[e ) . `E360 3 ] +[e $UE 55 ] +"161 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 161: } +[e :UE 55 ] +} +"163 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 163: static i2c1_operations_t wr2RegCompleteHandler(void *ptr) +[v _wr2RegCompleteHandler `(E360 ~T0 @X0 1 sf1`*v ] +"164 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 164: { +{ +[e :U _wr2RegCompleteHandler ] +"163 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 163: static i2c1_operations_t wr2RegCompleteHandler(void *ptr) +[v _ptr `*v ~T0 @X0 1 r1 ] +"164 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 164: { +[f ] +"165 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 165: I2C1_SetBuffer(ptr,2); +[e ( _I2C1_SetBuffer (2 , _ptr -> -> 2 `i `ui ] +"166 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 166: I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetDataCompleteCallback (2 , -> -> -> 0 `i `*v `*F534 -> -> 0 `i `*v ] +"167 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 167: return I2C1_CONTINUE; +[e ) . `E360 3 ] +[e $UE 56 ] +"168 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 168: } +[e :UE 56 ] +} +"170 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 170: static i2c1_operations_t rdBlkRegCompleteHandler(void *ptr) +[v _rdBlkRegCompleteHandler `(E360 ~T0 @X0 1 sf1`*v ] +"171 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 171: { +{ +[e :U _rdBlkRegCompleteHandler ] +"170 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 170: static i2c1_operations_t rdBlkRegCompleteHandler(void *ptr) +[v _ptr `*v ~T0 @X0 1 r1 ] +"171 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 171: { +[f ] +"172 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 172: I2C1_SetBuffer(((i2c1_buffer_t *)ptr)->data,((i2c1_buffer_t*)ptr)->len); +[e ( _I2C1_SetBuffer (2 , -> . *U -> _ptr `*S3 1 `*v . *U -> _ptr `*S3 0 ] +"173 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 173: I2C1_SetDataCompleteCallback(((void*)0),((void*)0)); +[e ( _I2C1_SetDataCompleteCallback (2 , -> -> -> 0 `i `*v `*F538 -> -> 0 `i `*v ] +"174 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 174: return I2C1_RESTART_READ; +[e ) . `E360 1 ] +[e $UE 57 ] +"175 +[; ;mcc_generated_files/examples/i2c1_master_example.c: 175: } +[e :UE 57 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.p1.d b/ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.p1.d new file mode 100644 index 0000000..5a30159 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/examples/i2c1_master_example.p1.d @@ -0,0 +1,4 @@ +build/default/debug/mcc_generated_files/examples/i2c1_master_example.p1: \ +mcc_generated_files/examples/i2c1_master_example.c \ +mcc_generated_files/examples/i2c1_master_example.h \ +mcc_generated_files/examples/../i2c1_master.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/i2c1_master.i b/ETC.X/build/default/debug/mcc_generated_files/i2c1_master.i new file mode 100644 index 0000000..a509c2c --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/i2c1_master.i @@ -0,0 +1,38490 @@ +# 1 "mcc_generated_files/i2c1_master.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/i2c1_master.c" 2 +# 47 "mcc_generated_files/i2c1_master.c" +# 1 "mcc_generated_files/i2c1_master.h" 1 +# 54 "mcc_generated_files/i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "mcc_generated_files/i2c1_master.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 55 "mcc_generated_files/i2c1_master.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 56 "mcc_generated_files/i2c1_master.h" 2 + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "mcc_generated_files/i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "mcc_generated_files/i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "mcc_generated_files/i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 47 "mcc_generated_files/i2c1_master.c" 2 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + + + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 48 "mcc_generated_files/i2c1_master.c" 2 + + + +typedef enum { + I2C1_IDLE = 0, + I2C1_SEND_ADR_READ, + I2C1_SEND_ADR_WRITE, + I2C1_TX, + I2C1_RX, + I2C1_TX_EMPTY, + I2C1_RX_EMPTY, + I2C1_SEND_RESTART_READ, + I2C1_SEND_RESTART_WRITE, + I2C1_SEND_RESTART, + I2C1_SEND_STOP, + I2C1_RX_ACK, + I2C1_TX_ACK, + I2C1_RX_NACK_STOP, + I2C1_RX_NACK_RESTART, + I2C1_RESET, + I2C1_ADDRESS_NACK, + I2C1_BUS_COLLISION, + I2C1_BUS_ERROR +} i2c1_fsm_states_t; + + +typedef enum { + I2C1_DATA_COMPLETE = 0, + I2C1_WRITE_COLLISION, + I2C1_ADDR_NACK, + I2C1_DATA_NACK, + I2C1_TIMEOUT, + I2C1_NULL +} i2c1_callbackIndex_t; + + +typedef struct +{ + i2c1_callback_t callbackTable[6]; + void *callbackPayload[6]; + uint16_t time_out; + uint16_t time_out_value; + i2c1_address_t address; + uint8_t *data_ptr; + size_t data_length; + i2c1_fsm_states_t state; + i2c1_error_t error; + unsigned addressNackCheck:2; + unsigned busy:1; + unsigned inUse:1; + unsigned bufferFree:1; + +} i2c1_status_t; + +static void I2C1_SetCallback(i2c1_callbackIndex_t idx, i2c1_callback_t cb, void *ptr); +static void I2C1_Poller(void); +static __attribute__((inline)) void I2C1_ClearInterruptFlags(void); +static __attribute__((inline)) void I2C1_MasterFsm(void); + + +static __attribute__((inline)) _Bool I2C1_MasterOpen(void); +static __attribute__((inline)) void I2C1_MasterClose(void); +static __attribute__((inline)) uint8_t I2C1_MasterGetRxData(void); +static __attribute__((inline)) void I2C1_MasterSendTxData(uint8_t data); +static __attribute__((inline)) void I2C1_MasterSetCounter(uint8_t counter); +static __attribute__((inline)) uint8_t I2C1_MasterGetCounter(); +static __attribute__((inline)) void I2C1_MasterResetBus(void); +static __attribute__((inline)) void I2C1_MasterEnableRestart(void); +static __attribute__((inline)) void I2C1_MasterDisableRestart(void); +static __attribute__((inline)) void I2C1_MasterStop(void); +static __attribute__((inline)) _Bool I2C1_MasterIsNack(void); +static __attribute__((inline)) void I2C1_MasterSendAck(void); +static __attribute__((inline)) void I2C1_MasterSendNack(void); +static __attribute__((inline)) void I2C1_MasterClearBusCollision(void); +static __attribute__((inline)) _Bool I2C1_MasterIsRxBufFull(void); +static __attribute__((inline)) _Bool I2C1_MasterIsTxBufEmpty(void); +static __attribute__((inline)) _Bool I2C1_MasterIsStopFlagSet(void); +static __attribute__((inline)) _Bool I2C1_MasterIsCountFlagSet(void); +static __attribute__((inline)) _Bool I2C1_MasterIsNackFlagSet(void); +static __attribute__((inline)) void I2C1_MasterClearStopFlag(void); +static __attribute__((inline)) void I2C1_MasterClearCountFlag(void); +static __attribute__((inline)) void I2C1_MasterClearNackFlag(void); + + +static __attribute__((inline)) void I2C1_MasterEnableIrq(void); +static __attribute__((inline)) _Bool I2C1_MasterIsIrqEnabled(void); +static __attribute__((inline)) void I2C1_MasterDisableIrq(void); +static __attribute__((inline)) void I2C1_MasterClearIrq(void); +static __attribute__((inline)) void I2C1_MasterWaitForEvent(void); + +static i2c1_fsm_states_t I2C1_DO_IDLE(void); +static i2c1_fsm_states_t I2C1_DO_SEND_ADR_READ(void); +static i2c1_fsm_states_t I2C1_DO_SEND_ADR_WRITE(void); +static i2c1_fsm_states_t I2C1_DO_TX(void); +static i2c1_fsm_states_t I2C1_DO_RX(void); +static i2c1_fsm_states_t I2C1_DO_TX_EMPTY(void); +static i2c1_fsm_states_t I2C1_DO_RX_EMPTY(void); +static i2c1_fsm_states_t I2C1_DO_SEND_RESTART_READ(void); +static i2c1_fsm_states_t I2C1_DO_SEND_RESTART_WRITE(void); +static i2c1_fsm_states_t I2C1_DO_SEND_RESTART(void); +static i2c1_fsm_states_t I2C1_DO_SEND_STOP(void); +static i2c1_fsm_states_t I2C1_DO_RX_ACK(void); +static i2c1_fsm_states_t I2C1_DO_TX_ACK(void); +static i2c1_fsm_states_t I2C1_DO_RX_NACK_STOP(void); +static i2c1_fsm_states_t I2C1_DO_RX_NACK_RESTART(void); +static i2c1_fsm_states_t I2C1_DO_RESET(void); +static i2c1_fsm_states_t I2C1_DO_ADDRESS_NACK(void); +static i2c1_fsm_states_t I2C1_DO_BUS_COLLISION(void); +static i2c1_fsm_states_t I2C1_DO_BUS_ERROR(void); + +typedef i2c1_fsm_states_t (*i2c1FsmHandler)(void); +const i2c1FsmHandler i2c1_fsmStateTable[] = { + I2C1_DO_IDLE, + I2C1_DO_SEND_ADR_READ, + I2C1_DO_SEND_ADR_WRITE, + I2C1_DO_TX, + I2C1_DO_RX, + I2C1_DO_TX_EMPTY, + I2C1_DO_RX_EMPTY, + I2C1_DO_SEND_RESTART_READ, + I2C1_DO_SEND_RESTART_WRITE, + I2C1_DO_SEND_RESTART, + I2C1_DO_SEND_STOP, + I2C1_DO_RX_ACK, + I2C1_DO_TX_ACK, + I2C1_DO_RX_NACK_STOP, + I2C1_DO_RX_NACK_RESTART, + I2C1_DO_RESET, + I2C1_DO_ADDRESS_NACK, + I2C1_DO_BUS_COLLISION, + I2C1_DO_BUS_ERROR +}; + +i2c1_status_t I2C1_Status = {0}; + +void I2C1_Initialize() +{ + + I2C1CON0 = 0x04; + + I2C1CON1 = 0x80; + + I2C1CON2 = 0x18; + + I2C1CLK = 0x03; + + I2C1PIR = 0x00; + + I2C1PIE = 0x00; + + I2C1ERR = 0x00; + + I2C1CNTL = 0x00; + I2C1CNTH = 0x00; + + I2C1BAUD = 0x00; + return; +} + +i2c1_error_t I2C1_Open(i2c1_address_t address) +{ + i2c1_error_t returnValue = I2C1_BUSY; + + if(!I2C1_Status.inUse) + { + I2C1_Status.address = address; + I2C1_Status.busy = 0; + I2C1_Status.inUse = 1; + I2C1_Status.addressNackCheck = 0; + I2C1_Status.state = I2C1_RESET; + I2C1_Status.time_out_value = 500; + I2C1_Status.bufferFree = 1; + + + I2C1_Status.callbackTable[I2C1_DATA_COMPLETE]=I2C1_CallbackReturnStop; + I2C1_Status.callbackPayload[I2C1_DATA_COMPLETE] = ((void*)0); + I2C1_Status.callbackTable[I2C1_WRITE_COLLISION]=I2C1_CallbackReturnStop; + I2C1_Status.callbackPayload[I2C1_WRITE_COLLISION] = ((void*)0); + I2C1_Status.callbackTable[I2C1_ADDR_NACK]=I2C1_CallbackReturnStop; + I2C1_Status.callbackPayload[I2C1_ADDR_NACK] = ((void*)0); + I2C1_Status.callbackTable[I2C1_DATA_NACK]=I2C1_CallbackReturnStop; + I2C1_Status.callbackPayload[I2C1_DATA_NACK] = ((void*)0); + I2C1_Status.callbackTable[I2C1_TIMEOUT]=I2C1_CallbackReturnReset; + I2C1_Status.callbackPayload[I2C1_TIMEOUT] = ((void*)0); + + I2C1_MasterClearIrq(); + I2C1_MasterOpen(); + returnValue = I2C1_NOERR; + } + return returnValue; +} + +i2c1_error_t I2C1_Close(void) +{ + i2c1_error_t returnValue = I2C1_BUSY; + if(!I2C1_Status.busy) + { + I2C1_Status.inUse = 0; + I2C1_Status.address = 0xff; + I2C1_MasterClearIrq(); + I2C1_MasterDisableIrq(); + I2C1_MasterClose(); + returnValue = I2C1_Status.error; + } + return returnValue; +} + +i2c1_error_t I2C1_MasterOperation(_Bool read) +{ + i2c1_error_t returnValue = I2C1_BUSY; + if(!I2C1_Status.busy) + { + I2C1_Status.busy = 1; + returnValue = I2C1_NOERR; + I2C1_MasterSetCounter((uint8_t) I2C1_Status.data_length); + + if(read) + { + I2C1_Status.state = I2C1_RX; + I2C1_DO_SEND_ADR_READ(); + } + else + { + I2C1_Status.state = I2C1_TX; + I2C1_DO_SEND_ADR_WRITE(); + } + I2C1_Poller(); + } + return returnValue; +} + +i2c1_error_t I2C1_MasterRead(void) +{ + return I2C1_MasterOperation(1); +} + +i2c1_error_t I2C1_MasterWrite(void) +{ + return I2C1_MasterOperation(0); +} + +void I2C1_SetTimeOut(uint8_t timeOutValue) +{ + I2C1_MasterDisableIrq(); + I2C1_Status.time_out_value = timeOutValue; + I2C1_MasterEnableIrq(); +} + +void I2C1_SetBuffer(void *buffer, size_t bufferSize) +{ + if(I2C1_Status.bufferFree) + { + I2C1_Status.data_ptr = buffer; + I2C1_Status.data_length = bufferSize; + I2C1_Status.bufferFree = 0; + } +} + +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr) +{ + I2C1_SetCallback(I2C1_DATA_COMPLETE, cb, ptr); +} + +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr) +{ + I2C1_SetCallback(I2C1_WRITE_COLLISION, cb, ptr); +} + +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr) +{ + I2C1_SetCallback(I2C1_ADDR_NACK, cb, ptr); +} + +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr) +{ + I2C1_SetCallback(I2C1_DATA_NACK, cb, ptr); +} + +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr) +{ + I2C1_SetCallback(I2C1_TIMEOUT, cb, ptr); +} + +static void I2C1_SetCallback(i2c1_callbackIndex_t idx, i2c1_callback_t cb, void *ptr) +{ + if(cb) + { + I2C1_Status.callbackTable[idx] = cb; + I2C1_Status.callbackPayload[idx] = ptr; + } + else + { + I2C1_Status.callbackTable[idx] = I2C1_CallbackReturnStop; + I2C1_Status.callbackPayload[idx] = ((void*)0); + } +} + +static void I2C1_Poller(void) +{ + while(I2C1_Status.busy) + { + I2C1_MasterWaitForEvent(); + I2C1_MasterFsm(); + } +} + +static __attribute__((inline)) void I2C1_MasterFsm(void) +{ + I2C1_ClearInterruptFlags(); + + if(I2C1_Status.addressNackCheck && I2C1_MasterIsNack()) + { + I2C1_Status.state = I2C1_ADDRESS_NACK; + } + I2C1_Status.state = i2c1_fsmStateTable[I2C1_Status.state](); +} + +static __attribute__((inline)) void I2C1_ClearInterruptFlags(void) +{ + if(I2C1_MasterIsCountFlagSet()) + { + I2C1_MasterClearCountFlag(); + } + else if(I2C1_MasterIsStopFlagSet()) + { + I2C1_MasterClearStopFlag(); + } + else if(I2C1_MasterIsNackFlagSet()) + { + I2C1_MasterClearNackFlag(); + } +} + +static i2c1_fsm_states_t I2C1_DO_IDLE(void) +{ + I2C1_Status.busy = 0; + I2C1_Status.error = I2C1_NOERR; + return I2C1_RESET; +} + +static i2c1_fsm_states_t I2C1_DO_SEND_ADR_READ(void) +{ + I2C1_Status.addressNackCheck = 2; + if(I2C1_Status.data_length == 1) + { + I2C1_DO_RX_EMPTY(); + } + I2C1_MasterSendTxData((uint8_t) (I2C1_Status.address << 1 | 1)); + return I2C1_RX; +} + +static i2c1_fsm_states_t I2C1_DO_SEND_ADR_WRITE(void) +{ + I2C1_Status.addressNackCheck = 2; + I2C1_MasterSendTxData((uint8_t) (I2C1_Status.address << 1)); + return I2C1_TX; +} + +static i2c1_fsm_states_t I2C1_DO_TX(void) +{ + if(I2C1_MasterIsNack()) + { + switch(I2C1_Status.callbackTable[I2C1_DATA_NACK](I2C1_Status.callbackPayload[I2C1_DATA_NACK])) + { + case I2C1_RESTART_READ: + return I2C1_DO_SEND_RESTART_READ(); + case I2C1_RESTART_WRITE: + return I2C1_DO_SEND_RESTART_WRITE(); + default: + case I2C1_CONTINUE: + case I2C1_STOP: + return I2C1_IDLE; + } + } + else if(I2C1_MasterIsTxBufEmpty()) + { + if(I2C1_Status.addressNackCheck) + { + I2C1_Status.addressNackCheck--; + } + uint8_t dataTx = *I2C1_Status.data_ptr++; + i2c1_fsm_states_t retFsmState = (--I2C1_Status.data_length)?I2C1_TX:I2C1_DO_TX_EMPTY(); + I2C1_MasterSendTxData(dataTx); + return retFsmState; + } + else + { + return I2C1_TX; + } +} + +static i2c1_fsm_states_t I2C1_DO_RX(void) +{ + if(!I2C1_MasterIsRxBufFull()) + { + return I2C1_RX; + } + if(I2C1_Status.addressNackCheck) + { + I2C1_Status.addressNackCheck--; + } + + if(--I2C1_Status.data_length) + { + *I2C1_Status.data_ptr++ = I2C1_MasterGetRxData(); + return I2C1_RX; + } + else + { + i2c1_fsm_states_t retFsmState = I2C1_DO_RX_EMPTY(); + *I2C1_Status.data_ptr++ = I2C1_MasterGetRxData(); + return retFsmState; + } +} + +static i2c1_fsm_states_t I2C1_DO_TX_EMPTY(void) +{ + I2C1_Status.bufferFree = 1; + switch(I2C1_Status.callbackTable[I2C1_DATA_COMPLETE](I2C1_Status.callbackPayload[I2C1_DATA_COMPLETE])) + { + case I2C1_RESTART_READ: + I2C1_MasterEnableRestart(); + return I2C1_SEND_RESTART_READ; + case I2C1_CONTINUE: + + I2C1_MasterSetCounter((uint8_t) I2C1_Status.data_length + 1); + return I2C1_TX; + default: + case I2C1_STOP: + I2C1_MasterDisableRestart(); + return I2C1_SEND_STOP; + } +} + +static i2c1_fsm_states_t I2C1_DO_RX_EMPTY(void) +{ + I2C1_Status.bufferFree = 1; + switch(I2C1_Status.callbackTable[I2C1_DATA_COMPLETE](I2C1_Status.callbackPayload[I2C1_DATA_COMPLETE])) + { + case I2C1_RESTART_WRITE: + I2C1_MasterEnableRestart(); + return I2C1_SEND_RESTART_WRITE; + case I2C1_RESTART_READ: + I2C1_MasterEnableRestart(); + return I2C1_SEND_RESTART_READ; + case I2C1_CONTINUE: + + I2C1_MasterSetCounter((uint8_t) (I2C1_Status.data_length + 1)); + return I2C1_RX; + default: + case I2C1_STOP: + if(I2C1_Status.state != I2C1_SEND_RESTART_READ) + { + I2C1_MasterDisableRestart(); + } + return I2C1_RESET; + } +} + +static i2c1_fsm_states_t I2C1_DO_SEND_RESTART_READ(void) +{ + I2C1_MasterSetCounter((uint8_t) I2C1_Status.data_length); + return I2C1_DO_SEND_ADR_READ(); +} + +static i2c1_fsm_states_t I2C1_DO_SEND_RESTART_WRITE(void) +{ + return I2C1_SEND_ADR_WRITE; +} + + +static i2c1_fsm_states_t I2C1_DO_SEND_RESTART(void) +{ + return I2C1_SEND_ADR_READ; +} + +static i2c1_fsm_states_t I2C1_DO_SEND_STOP(void) +{ + I2C1_MasterStop(); + if(I2C1_MasterGetCounter()) + { + I2C1_MasterSetCounter(0); + I2C1_MasterSendTxData(0); + } + return I2C1_IDLE; +} + +static i2c1_fsm_states_t I2C1_DO_RX_ACK(void) +{ + I2C1_MasterSendAck(); + return I2C1_RX; +} + +static i2c1_fsm_states_t I2C1_DO_TX_ACK(void) +{ + I2C1_MasterSendAck(); + return I2C1_TX; +} + +static i2c1_fsm_states_t I2C1_DO_RX_NACK_STOP(void) +{ + I2C1_MasterSendNack(); + I2C1_MasterStop(); + return I2C1_DO_IDLE(); +} + +static i2c1_fsm_states_t I2C1_DO_RX_NACK_RESTART(void) +{ + I2C1_MasterSendNack(); + return I2C1_SEND_RESTART; +} + +static i2c1_fsm_states_t I2C1_DO_RESET(void) +{ + I2C1_MasterResetBus(); + I2C1_Status.busy = 0; + I2C1_Status.error = I2C1_NOERR; + return I2C1_RESET; +} +static i2c1_fsm_states_t I2C1_DO_ADDRESS_NACK(void) +{ + I2C1_Status.addressNackCheck = 0; + I2C1_Status.error = I2C1_FAIL; + I2C1_Status.busy = 0; + switch(I2C1_Status.callbackTable[I2C1_ADDR_NACK](I2C1_Status.callbackPayload[I2C1_ADDR_NACK])) + { + case I2C1_RESTART_READ: + case I2C1_RESTART_WRITE: + return I2C1_DO_SEND_RESTART(); + default: + return I2C1_RESET; + } +} + +static i2c1_fsm_states_t I2C1_DO_BUS_COLLISION(void) +{ + + I2C1_MasterClearIrq(); + + I2C1_Status.error = I2C1_FAIL; + switch (I2C1_Status.callbackTable[I2C1_WRITE_COLLISION](I2C1_Status.callbackPayload[I2C1_WRITE_COLLISION])) { + case I2C1_RESTART_READ: + return I2C1_DO_SEND_RESTART_READ(); + case I2C1_RESTART_WRITE: + return I2C1_DO_SEND_RESTART_WRITE(); + default: + return I2C1_DO_RESET(); + } +} + +static i2c1_fsm_states_t I2C1_DO_BUS_ERROR(void) +{ + I2C1_MasterResetBus(); + I2C1_Status.busy = 0; + I2C1_Status.error = I2C1_FAIL; + return I2C1_RESET; +} + +void I2C1_BusCollisionIsr(void) +{ + I2C1_MasterClearBusCollision(); + I2C1_Status.state = I2C1_RESET; +} + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr) +{ + return I2C1_STOP; +} + +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr) +{ + return I2C1_RESET_LINK; +} + +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr) +{ + return I2C1_RESTART_WRITE; +} + +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr) +{ + return I2C1_RESTART_READ; +} + + + + +static __attribute__((inline)) _Bool I2C1_MasterOpen(void) +{ + if(!I2C1CON0bits.EN) + { + + I2C1PIR = 0x00; + + I2C1PIE = 0x00; + + I2C1ERR = 0x00; + + I2C1CNTL = 0x00; + I2C1CNTH = 0x00; + + I2C1BAUD = 0x00; + + I2C1CON0bits.EN = 1; + return 1; + } + return 0; +} + +static __attribute__((inline)) void I2C1_MasterClose(void) +{ + + I2C1CON0bits.EN = 0; + + I2C1PIR = 0x00; + + I2C1STAT1bits.CLRBF = 1; +} + +static __attribute__((inline)) uint8_t I2C1_MasterGetRxData(void) +{ + return I2C1RXB; +} + +static __attribute__((inline)) void I2C1_MasterSendTxData(uint8_t data) +{ + I2C1TXB = data; +} + +static __attribute__((inline)) uint8_t I2C1_MasterGetCounter() +{ + return I2C1CNTL; +} + +static __attribute__((inline)) void I2C1_MasterSetCounter(uint8_t counter) +{ + I2C1CNTL = counter; + I2C1CNTH = 0x00; +} + +static __attribute__((inline)) void I2C1_MasterResetBus(void) +{ + + I2C1CON0bits.EN = 0; + + I2C1STAT1bits.CLRBF = 1; + + I2C1CON0bits.EN = 1; +} + +static __attribute__((inline)) void I2C1_MasterEnableRestart(void) +{ + + I2C1CON0bits.RSEN = 1; +} + +static __attribute__((inline)) void I2C1_MasterDisableRestart(void) +{ + + I2C1CON0bits.RSEN = 0; +} + +static __attribute__((inline)) void I2C1_MasterStop(void) +{ + + I2C1CON0bits.S = 0; +} + +static __attribute__((inline)) _Bool I2C1_MasterIsNack(void) +{ + return I2C1CON1bits.ACKSTAT; +} + +static __attribute__((inline)) void I2C1_MasterSendAck(void) +{ + I2C1CON1bits.ACKDT = 0; +} + +static __attribute__((inline)) void I2C1_MasterSendNack(void) +{ + I2C1CON1bits.ACKDT = 1; +} + +static __attribute__((inline)) void I2C1_MasterClearBusCollision(void) +{ + I2C1ERRbits.BCLIF = 0; + I2C1ERRbits.BTOIF = 0; + I2C1ERRbits.NACKIF = 0; +} + +static __attribute__((inline)) _Bool I2C1_MasterIsRxBufFull(void) +{ + return I2C1STAT1bits.RXBF; +} + +static __attribute__((inline)) _Bool I2C1_MasterIsTxBufEmpty(void) +{ + return I2C1STAT1bits.TXBE; +} + +static __attribute__((inline)) _Bool I2C1_MasterIsStopFlagSet(void) +{ + return I2C1PIRbits.PCIF; +} + +static __attribute__((inline)) _Bool I2C1_MasterIsCountFlagSet(void) +{ + return I2C1PIRbits.CNTIF; +} + +static __attribute__((inline)) _Bool I2C1_MasterIsNackFlagSet(void) +{ + return I2C1ERRbits.NACKIF; +} + +static __attribute__((inline)) void I2C1_MasterClearStopFlag(void) +{ + I2C1PIRbits.PCIF = 0; +} + +static __attribute__((inline)) void I2C1_MasterClearCountFlag(void) +{ + I2C1PIRbits.CNTIF = 0; +} + +static __attribute__((inline)) void I2C1_MasterClearNackFlag(void) +{ + I2C1ERRbits.NACKIF = 0; +} + +static __attribute__((inline)) void I2C1_MasterEnableIrq(void) +{ + PIE7bits.I2C1IE = 1; + PIE7bits.I2C1EIE = 1; + PIE7bits.I2C1RXIE = 1; + PIE7bits.I2C1TXIE = 1; + + I2C1PIEbits.PCIE = 1; + I2C1PIEbits.CNTIE = 1; + I2C1ERRbits.NACKIE = 1; +} + +static __attribute__((inline)) _Bool I2C1_MasterIsIrqEnabled(void) +{ + return (PIE7bits.I2C1RXIE && PIE7bits.I2C1TXIE && PIE7bits.I2C1IE); +} + +static __attribute__((inline)) void I2C1_MasterDisableIrq(void) +{ + PIE7bits.I2C1IE = 0; + PIE7bits.I2C1EIE = 0; + PIE7bits.I2C1RXIE = 0; + PIE7bits.I2C1TXIE = 0; + I2C1PIEbits.SCIE = 0; + I2C1PIEbits.PCIE = 0; + I2C1PIEbits.CNTIE = 0; + I2C1PIEbits.ACKTIE = 0; + I2C1PIEbits.RSCIE = 0; + I2C1ERRbits.BCLIE = 0; + I2C1ERRbits.BTOIE = 0; + I2C1ERRbits.NACKIE = 0; +} + +static __attribute__((inline)) void I2C1_MasterClearIrq(void) +{ + I2C1PIR = 0x00; +} + +static __attribute__((inline)) void I2C1_MasterWaitForEvent(void) +{ + while(1) + { + if(PIR7bits.I2C1TXIF) + { + break; + } + if(PIR7bits.I2C1RXIF) + { + break; + } + if(I2C1PIRbits.PCIF) + { + break; + } + if(I2C1PIRbits.CNTIF) + { + break; + } + if(I2C1ERRbits.NACKIF) + { + break; + } + } +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/i2c1_master.p1 b/ETC.X/build/default/debug/mcc_generated_files/i2c1_master.p1 new file mode 100644 index 0000000..f63c1b3 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/i2c1_master.p1 @@ -0,0 +1,6028 @@ +Version 4.0 HI-TECH Software Intermediate Code +"159 mcc_generated_files/i2c1_master.c +[; ;mcc_generated_files/i2c1_master.c: 159: const i2c1FsmHandler i2c1_fsmStateTable[] = { +[c E22532 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 .. ] +[n E22532 . I2C1_IDLE I2C1_SEND_ADR_READ I2C1_SEND_ADR_WRITE I2C1_TX I2C1_RX I2C1_TX_EMPTY I2C1_RX_EMPTY I2C1_SEND_RESTART_READ I2C1_SEND_RESTART_WRITE I2C1_SEND_RESTART I2C1_SEND_STOP I2C1_RX_ACK I2C1_TX_ACK I2C1_RX_NACK_STOP I2C1_RX_NACK_RESTART I2C1_RESET I2C1_ADDRESS_NACK I2C1_BUS_COLLISION I2C1_BUS_ERROR ] +[v F22671 `(E22532 ~T0 @X0 0 tf ] +"138 +[; ;mcc_generated_files/i2c1_master.c: 138: static i2c1_fsm_states_t I2C1_DO_IDLE(void); +[v _I2C1_DO_IDLE `(E22532 ~T0 @X0 0 sf ] +"139 +[; ;mcc_generated_files/i2c1_master.c: 139: static i2c1_fsm_states_t I2C1_DO_SEND_ADR_READ(void); +[v _I2C1_DO_SEND_ADR_READ `(E22532 ~T0 @X0 0 sf ] +"140 +[; ;mcc_generated_files/i2c1_master.c: 140: static i2c1_fsm_states_t I2C1_DO_SEND_ADR_WRITE(void); +[v _I2C1_DO_SEND_ADR_WRITE `(E22532 ~T0 @X0 0 sf ] +"141 +[; ;mcc_generated_files/i2c1_master.c: 141: static i2c1_fsm_states_t I2C1_DO_TX(void); +[v _I2C1_DO_TX `(E22532 ~T0 @X0 0 sf ] +"142 +[; ;mcc_generated_files/i2c1_master.c: 142: static i2c1_fsm_states_t I2C1_DO_RX(void); +[v _I2C1_DO_RX `(E22532 ~T0 @X0 0 sf ] +"143 +[; ;mcc_generated_files/i2c1_master.c: 143: static i2c1_fsm_states_t I2C1_DO_TX_EMPTY(void); +[v _I2C1_DO_TX_EMPTY `(E22532 ~T0 @X0 0 sf ] +"144 +[; ;mcc_generated_files/i2c1_master.c: 144: static i2c1_fsm_states_t I2C1_DO_RX_EMPTY(void); +[v _I2C1_DO_RX_EMPTY `(E22532 ~T0 @X0 0 sf ] +"145 +[; ;mcc_generated_files/i2c1_master.c: 145: static i2c1_fsm_states_t I2C1_DO_SEND_RESTART_READ(void); +[v _I2C1_DO_SEND_RESTART_READ `(E22532 ~T0 @X0 0 sf ] +"146 +[; ;mcc_generated_files/i2c1_master.c: 146: static i2c1_fsm_states_t I2C1_DO_SEND_RESTART_WRITE(void); +[v _I2C1_DO_SEND_RESTART_WRITE `(E22532 ~T0 @X0 0 sf ] +"147 +[; ;mcc_generated_files/i2c1_master.c: 147: static i2c1_fsm_states_t I2C1_DO_SEND_RESTART(void); +[v _I2C1_DO_SEND_RESTART `(E22532 ~T0 @X0 0 sf ] +"148 +[; ;mcc_generated_files/i2c1_master.c: 148: static i2c1_fsm_states_t I2C1_DO_SEND_STOP(void); +[v _I2C1_DO_SEND_STOP `(E22532 ~T0 @X0 0 sf ] +"149 +[; ;mcc_generated_files/i2c1_master.c: 149: static i2c1_fsm_states_t I2C1_DO_RX_ACK(void); +[v _I2C1_DO_RX_ACK `(E22532 ~T0 @X0 0 sf ] +"150 +[; ;mcc_generated_files/i2c1_master.c: 150: static i2c1_fsm_states_t I2C1_DO_TX_ACK(void); +[v _I2C1_DO_TX_ACK `(E22532 ~T0 @X0 0 sf ] +"151 +[; ;mcc_generated_files/i2c1_master.c: 151: static i2c1_fsm_states_t I2C1_DO_RX_NACK_STOP(void); +[v _I2C1_DO_RX_NACK_STOP `(E22532 ~T0 @X0 0 sf ] +"152 +[; ;mcc_generated_files/i2c1_master.c: 152: static i2c1_fsm_states_t I2C1_DO_RX_NACK_RESTART(void); +[v _I2C1_DO_RX_NACK_RESTART `(E22532 ~T0 @X0 0 sf ] +"153 +[; ;mcc_generated_files/i2c1_master.c: 153: static i2c1_fsm_states_t I2C1_DO_RESET(void); +[v _I2C1_DO_RESET `(E22532 ~T0 @X0 0 sf ] +"154 +[; ;mcc_generated_files/i2c1_master.c: 154: static i2c1_fsm_states_t I2C1_DO_ADDRESS_NACK(void); +[v _I2C1_DO_ADDRESS_NACK `(E22532 ~T0 @X0 0 sf ] +"155 +[; ;mcc_generated_files/i2c1_master.c: 155: static i2c1_fsm_states_t I2C1_DO_BUS_COLLISION(void); +[v _I2C1_DO_BUS_COLLISION `(E22532 ~T0 @X0 0 sf ] +"156 +[; ;mcc_generated_files/i2c1_master.c: 156: static i2c1_fsm_states_t I2C1_DO_BUS_ERROR(void); +[v _I2C1_DO_BUS_ERROR `(E22532 ~T0 @X0 0 sf ] +"181 +[; ;mcc_generated_files/i2c1_master.c: 181: i2c1_status_t I2C1_Status = {0}; +[c E360 1 2 3 4 5 .. ] +[n E360 . I2C1_STOP I2C1_RESTART_READ I2C1_RESTART_WRITE I2C1_CONTINUE I2C1_RESET_LINK ] +[v F22563 `(E360 ~T0 @X0 0 tf1`*v ] +[c E355 0 1 2 .. ] +[n E355 . I2C1_NOERR I2C1_BUSY I2C1_FAIL ] +"85 +[; ;mcc_generated_files/i2c1_master.c: 85: { +[s S3178 `*F22563 -> 6 `i `*v -> 6 `i `us 1 `us 1 `uc 1 `*uc 1 `ui 1 `E22532 1 `E355 1 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3178 . callbackTable callbackPayload time_out time_out_value address data_ptr data_length state error addressNackCheck busy inUse bufferFree ] +[v F22692 `(E360 ~T0 @X0 0 tf1`*v ] +"30567 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30567: extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); +[v _I2C1CON0 `Vuc ~T0 @X0 0 e@660 ] +"30644 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30644: extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); +[v _I2C1CON1 `Vuc ~T0 @X0 0 e@661 ] +"30706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30706: extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); +[v _I2C1CON2 `Vuc ~T0 @X0 0 e@662 ] +"31303 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31303: extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); +[v _I2C1CLK `Vuc ~T0 @X0 0 e@670 ] +"31009 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31009: extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); +[v _I2C1PIR `Vuc ~T0 @X0 0 e@666 ] +"31111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31111: extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); +[v _I2C1PIE `Vuc ~T0 @X0 0 e@667 ] +"30782 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30782: extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); +[v _I2C1ERR `Vuc ~T0 @X0 0 e@663 ] +"30305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30305: extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); +[v _I2C1CNTL `Vuc ~T0 @X0 0 e@652 ] +"30375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30375: extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); +[v _I2C1CNTH `Vuc ~T0 @X0 0 e@653 ] +"31283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31283: extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); +[v _I2C1BAUD `Vuc ~T0 @X0 0 e@669 ] +"222 mcc_generated_files/i2c1_master.c +[; ;mcc_generated_files/i2c1_master.c: 222: I2C1_Status.callbackTable[I2C1_DATA_COMPLETE]=I2C1_CallbackReturnStop; +[c E22553 0 1 2 3 4 5 .. ] +[n E22553 . I2C1_DATA_COMPLETE I2C1_WRITE_COLLISION I2C1_ADDR_NACK I2C1_DATA_NACK I2C1_TIMEOUT I2C1_NULL ] +"79 mcc_generated_files/i2c1_master.h +[; ;mcc_generated_files/i2c1_master.h: 79: i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +[v _I2C1_CallbackReturnStop `(E360 ~T0 @X0 0 ef1`*v ] +"80 +[; ;mcc_generated_files/i2c1_master.h: 80: i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +[v _I2C1_CallbackReturnReset `(E360 ~T0 @X0 0 ef1`*v ] +[v F22644 `(v ~T0 @X0 1 tf ] +"135 mcc_generated_files/i2c1_master.c +[; ;mcc_generated_files/i2c1_master.c: 135: static __attribute__((inline)) void I2C1_MasterClearIrq(void); +[v _I2C1_MasterClearIrq `TF22644 ~T0 @X0 0 s ] +[v F22592 `(a ~T0 @X0 1 tf ] +"108 +[; ;mcc_generated_files/i2c1_master.c: 108: static __attribute__((inline)) _Bool I2C1_MasterOpen(void); +[v _I2C1_MasterOpen `TF22592 ~T0 @X0 0 s ] +[v F22642 `(v ~T0 @X0 1 tf ] +"134 +[; ;mcc_generated_files/i2c1_master.c: 134: static __attribute__((inline)) void I2C1_MasterDisableIrq(void); +[v _I2C1_MasterDisableIrq `TF22642 ~T0 @X0 0 s ] +[v F22594 `(v ~T0 @X0 1 tf ] +"109 +[; ;mcc_generated_files/i2c1_master.c: 109: static __attribute__((inline)) void I2C1_MasterClose(void); +[v _I2C1_MasterClose `TF22594 ~T0 @X0 0 s ] +[v F22601 `(v ~T0 @X0 1 tf1`uc ] +"112 +[; ;mcc_generated_files/i2c1_master.c: 112: static __attribute__((inline)) void I2C1_MasterSetCounter(uint8_t counter); +[v _I2C1_MasterSetCounter `TF22601 ~T0 @X0 0 s ] +"103 +[; ;mcc_generated_files/i2c1_master.c: 103: static void I2C1_Poller(void); +[v _I2C1_Poller `(v ~T0 @X0 0 sf ] +[v F22638 `(v ~T0 @X0 1 tf ] +"132 +[; ;mcc_generated_files/i2c1_master.c: 132: static __attribute__((inline)) void I2C1_MasterEnableIrq(void); +[v _I2C1_MasterEnableIrq `TF22638 ~T0 @X0 0 s ] +[v F22771 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22774 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22579 `(E360 ~T0 @X0 0 tf1`*v ] +"102 +[; ;mcc_generated_files/i2c1_master.c: 102: static void I2C1_SetCallback(i2c1_callbackIndex_t idx, i2c1_callback_t cb, void *ptr); +[v _I2C1_SetCallback `(v ~T0 @X0 0 sf3`E22553`*F22579`*v ] +[v F22778 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22781 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22785 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22788 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22792 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22795 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22799 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22802 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22806 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22810 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22813 `(E360 ~T0 @X0 0 tf1`*v ] +[v F22646 `(v ~T0 @X0 1 tf ] +"136 +[; ;mcc_generated_files/i2c1_master.c: 136: static __attribute__((inline)) void I2C1_MasterWaitForEvent(void); +[v _I2C1_MasterWaitForEvent `TF22646 ~T0 @X0 0 s ] +[v F22590 `(v ~T0 @X0 1 tf ] +"105 +[; ;mcc_generated_files/i2c1_master.c: 105: static __attribute__((inline)) void I2C1_MasterFsm(void); +[v _I2C1_MasterFsm `TF22590 ~T0 @X0 0 s ] +[v F22588 `(v ~T0 @X0 1 tf ] +"104 +[; ;mcc_generated_files/i2c1_master.c: 104: static __attribute__((inline)) void I2C1_ClearInterruptFlags(void); +[v _I2C1_ClearInterruptFlags `TF22588 ~T0 @X0 0 s ] +[v F22614 `(a ~T0 @X0 1 tf ] +"118 +[; ;mcc_generated_files/i2c1_master.c: 118: static __attribute__((inline)) _Bool I2C1_MasterIsNack(void); +[v _I2C1_MasterIsNack `TF22614 ~T0 @X0 0 s ] +[v F22628 `(a ~T0 @X0 1 tf ] +"125 +[; ;mcc_generated_files/i2c1_master.c: 125: static __attribute__((inline)) _Bool I2C1_MasterIsCountFlagSet(void); +[v _I2C1_MasterIsCountFlagSet `TF22628 ~T0 @X0 0 s ] +[v F22634 `(v ~T0 @X0 1 tf ] +"128 +[; ;mcc_generated_files/i2c1_master.c: 128: static __attribute__((inline)) void I2C1_MasterClearCountFlag(void); +[v _I2C1_MasterClearCountFlag `TF22634 ~T0 @X0 0 s ] +[v F22626 `(a ~T0 @X0 1 tf ] +"124 +[; ;mcc_generated_files/i2c1_master.c: 124: static __attribute__((inline)) _Bool I2C1_MasterIsStopFlagSet(void); +[v _I2C1_MasterIsStopFlagSet `TF22626 ~T0 @X0 0 s ] +[v F22632 `(v ~T0 @X0 1 tf ] +"127 +[; ;mcc_generated_files/i2c1_master.c: 127: static __attribute__((inline)) void I2C1_MasterClearStopFlag(void); +[v _I2C1_MasterClearStopFlag `TF22632 ~T0 @X0 0 s ] +[v F22630 `(a ~T0 @X0 1 tf ] +"126 +[; ;mcc_generated_files/i2c1_master.c: 126: static __attribute__((inline)) _Bool I2C1_MasterIsNackFlagSet(void); +[v _I2C1_MasterIsNackFlagSet `TF22630 ~T0 @X0 0 s ] +[v F22636 `(v ~T0 @X0 1 tf ] +"129 +[; ;mcc_generated_files/i2c1_master.c: 129: static __attribute__((inline)) void I2C1_MasterClearNackFlag(void); +[v _I2C1_MasterClearNackFlag `TF22636 ~T0 @X0 0 s ] +[v F22598 `(v ~T0 @X0 1 tf1`uc ] +"111 +[; ;mcc_generated_files/i2c1_master.c: 111: static __attribute__((inline)) void I2C1_MasterSendTxData(uint8_t data); +[v _I2C1_MasterSendTxData `TF22598 ~T0 @X0 0 s ] +[v F22624 `(a ~T0 @X0 1 tf ] +"123 +[; ;mcc_generated_files/i2c1_master.c: 123: static __attribute__((inline)) _Bool I2C1_MasterIsTxBufEmpty(void); +[v _I2C1_MasterIsTxBufEmpty `TF22624 ~T0 @X0 0 s ] +[v F22622 `(a ~T0 @X0 1 tf ] +"122 +[; ;mcc_generated_files/i2c1_master.c: 122: static __attribute__((inline)) _Bool I2C1_MasterIsRxBufFull(void); +[v _I2C1_MasterIsRxBufFull `TF22622 ~T0 @X0 0 s ] +[v F22596 `(uc ~T0 @X0 1 tf ] +"110 +[; ;mcc_generated_files/i2c1_master.c: 110: static __attribute__((inline)) uint8_t I2C1_MasterGetRxData(void); +[v _I2C1_MasterGetRxData `TF22596 ~T0 @X0 0 s ] +[v F22608 `(v ~T0 @X0 1 tf ] +"115 +[; ;mcc_generated_files/i2c1_master.c: 115: static __attribute__((inline)) void I2C1_MasterEnableRestart(void); +[v _I2C1_MasterEnableRestart `TF22608 ~T0 @X0 0 s ] +[v F22610 `(v ~T0 @X0 1 tf ] +"116 +[; ;mcc_generated_files/i2c1_master.c: 116: static __attribute__((inline)) void I2C1_MasterDisableRestart(void); +[v _I2C1_MasterDisableRestart `TF22610 ~T0 @X0 0 s ] +[v F22612 `(v ~T0 @X0 1 tf ] +"117 +[; ;mcc_generated_files/i2c1_master.c: 117: static __attribute__((inline)) void I2C1_MasterStop(void); +[v _I2C1_MasterStop `TF22612 ~T0 @X0 0 s ] +[v F22604 `(uc ~T0 @X0 1 tf ] +"113 +[; ;mcc_generated_files/i2c1_master.c: 113: static __attribute__((inline)) uint8_t I2C1_MasterGetCounter(); +[v _I2C1_MasterGetCounter `TF22604 ~T0 @X0 0 s ] +[v F22616 `(v ~T0 @X0 1 tf ] +"119 +[; ;mcc_generated_files/i2c1_master.c: 119: static __attribute__((inline)) void I2C1_MasterSendAck(void); +[v _I2C1_MasterSendAck `TF22616 ~T0 @X0 0 s ] +[v F22618 `(v ~T0 @X0 1 tf ] +"120 +[; ;mcc_generated_files/i2c1_master.c: 120: static __attribute__((inline)) void I2C1_MasterSendNack(void); +[v _I2C1_MasterSendNack `TF22618 ~T0 @X0 0 s ] +[v F22606 `(v ~T0 @X0 1 tf ] +"114 +[; ;mcc_generated_files/i2c1_master.c: 114: static __attribute__((inline)) void I2C1_MasterResetBus(void); +[v _I2C1_MasterResetBus `TF22606 ~T0 @X0 0 s ] +[v F22620 `(v ~T0 @X0 1 tf ] +"121 +[; ;mcc_generated_files/i2c1_master.c: 121: static __attribute__((inline)) void I2C1_MasterClearBusCollision(void); +[v _I2C1_MasterClearBusCollision `TF22620 ~T0 @X0 0 s ] +"30573 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30573: struct { +[s S1432 :3 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1432 . MODE MDR CSTR S RSEN EN ] +"30581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30581: struct { +[s S1433 :1 `uc 1 :1 `uc 1 :1 `uc 1 :4 `uc 1 :1 `uc 1 ] +[n S1433 . MODE0 MODE1 MODE2 . I2CEN ] +"30572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30572: typedef union { +[u S1431 `S1432 1 `S1433 1 ] +[n S1431 . . . ] +"30589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30589: extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +[v _I2C1CON0bits `VS1431 ~T0 @X0 0 e@660 ] +"30968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30968: struct { +[s S1448 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1448 . RXBF . CLRBF RXRE . TXBE . TXWE ] +"30967 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30967: typedef union { +[u S1447 `S1448 1 ] +[n S1447 . . ] +"30979 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30979: extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +[v _I2C1STAT1bits `VS1447 ~T0 @X0 0 e@665 ] +"30265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30265: extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); +[v _I2C1RXB `Vuc ~T0 @X0 0 e@650 ] +"30285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30285: extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); +[v _I2C1TXB `Vuc ~T0 @X0 0 e@651 ] +"30650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30650: struct { +[s S1435 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1435 . CSD TXU RXO P ACKT ACKSTAT ACKDT ACKCNT ] +"30649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30649: typedef union { +[u S1434 `S1435 1 ] +[n S1434 . . ] +"30661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30661: extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +[v _I2C1CON1bits `VS1434 ~T0 @X0 0 e@661 ] +"30788 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30788: struct { +[s S1440 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1440 . NACKIE BCLIE BTOIE . NACKIF BCLIF BTOIF ] +"30797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30797: struct { +[s S1441 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1441 . NACK1IE BCL1IE BTO1IE . NACK1IF BCL1IF BTO1IF ] +"30787 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30787: typedef union { +[u S1439 `S1440 1 `S1441 1 ] +[n S1439 . . . ] +"30807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30807: extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +[v _I2C1ERRbits `VS1439 ~T0 @X0 0 e@663 ] +"31015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31015: struct { +[s S1450 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1450 . SCIF RSCIF PCIF ADRIF WRIF . ACKTIF CNTIF ] +"31025 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31025: struct { +[s S1451 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1451 . SC1IF RSC1IF PC1IF ADR1IF WR1IF . ACKT1IF CNT1IF ] +"31014 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31014: typedef union { +[u S1449 `S1450 1 `S1451 1 ] +[n S1449 . . . ] +"31036 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31036: extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +[v _I2C1PIRbits `VS1449 ~T0 @X0 0 e@666 ] +"65488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65488: struct { +[s S3012 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3012 . I2C1RXIE I2C1TXIE I2C1IE I2C1EIE . CLC3IE PWM3PIE PWM3IE ] +"65487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65487: typedef union { +[u S3011 `S3012 1 ] +[n S3011 . . ] +"65499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65499: extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +[v _PIE7bits `VS3011 ~T0 @X0 0 e@1189 ] +"31117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31117: struct { +[s S1453 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1453 . SCIE RSCIE PCIE ADRIE WRIE . ACKTIE CNTIE ] +"31127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31127: struct { +[s S1454 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1454 . SC1IE RSC1IE PC1IE ADR1IE WR1IE . ACKT1IE CNT1IE ] +"31116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31116: typedef union { +[u S1452 `S1453 1 `S1454 1 ] +[n S1452 . . . ] +"31138 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31138: extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +[v _I2C1PIEbits `VS1452 ~T0 @X0 0 e@667 ] +"937 +[s S3045 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3045 . I2C1RXIF I2C1TXIF I2C1IF I2C1EIF . CLC3IF PWM3PIF PWM3IF ] +"936 +[u S3044 `S3045 1 ] +[n S3044 . . ] +"948 +[v _PIR7bits `VS3044 ~T0 @X0 0 e@1205 ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +[v F22670 `*F22671 ~T0 @X0 1 t ] +"159 mcc_generated_files/i2c1_master.c +[; ;mcc_generated_files/i2c1_master.c: 159: const i2c1FsmHandler i2c1_fsmStateTable[] = { +[v _i2c1_fsmStateTable `C*F22671 ~T0 @X0 -> 19 `i e ] +[i _i2c1_fsmStateTable +:U .. +&U _I2C1_DO_IDLE +&U _I2C1_DO_SEND_ADR_READ +&U _I2C1_DO_SEND_ADR_WRITE +&U _I2C1_DO_TX +&U _I2C1_DO_RX +&U _I2C1_DO_TX_EMPTY +&U _I2C1_DO_RX_EMPTY +&U _I2C1_DO_SEND_RESTART_READ +&U _I2C1_DO_SEND_RESTART_WRITE +&U _I2C1_DO_SEND_RESTART +&U _I2C1_DO_SEND_STOP +&U _I2C1_DO_RX_ACK +&U _I2C1_DO_TX_ACK +&U _I2C1_DO_RX_NACK_STOP +&U _I2C1_DO_RX_NACK_RESTART +&U _I2C1_DO_RESET +&U _I2C1_DO_ADDRESS_NACK +&U _I2C1_DO_BUS_COLLISION +&U _I2C1_DO_BUS_ERROR +.. +] +"181 +[; ;mcc_generated_files/i2c1_master.c: 181: i2c1_status_t I2C1_Status = {0}; +[v _I2C1_Status `S3178 ~T0 @X0 1 e ] +[i _I2C1_Status +:U .. +:U .. +:U .. +-> -> 0 `i `*F22692 +.. +.. +.. +] +"183 +[; ;mcc_generated_files/i2c1_master.c: 183: void I2C1_Initialize() +[v _I2C1_Initialize `(v ~T0 @X0 1 ef ] +"184 +[; ;mcc_generated_files/i2c1_master.c: 184: { +{ +[e :U _I2C1_Initialize ] +[f ] +"186 +[; ;mcc_generated_files/i2c1_master.c: 186: I2C1CON0 = 0x04; +[e = _I2C1CON0 -> -> 4 `i `uc ] +"188 +[; ;mcc_generated_files/i2c1_master.c: 188: I2C1CON1 = 0x80; +[e = _I2C1CON1 -> -> 128 `i `uc ] +"190 +[; ;mcc_generated_files/i2c1_master.c: 190: I2C1CON2 = 0x18; +[e = _I2C1CON2 -> -> 24 `i `uc ] +"192 +[; ;mcc_generated_files/i2c1_master.c: 192: I2C1CLK = 0x03; +[e = _I2C1CLK -> -> 3 `i `uc ] +"194 +[; ;mcc_generated_files/i2c1_master.c: 194: I2C1PIR = 0x00; +[e = _I2C1PIR -> -> 0 `i `uc ] +"196 +[; ;mcc_generated_files/i2c1_master.c: 196: I2C1PIE = 0x00; +[e = _I2C1PIE -> -> 0 `i `uc ] +"198 +[; ;mcc_generated_files/i2c1_master.c: 198: I2C1ERR = 0x00; +[e = _I2C1ERR -> -> 0 `i `uc ] +"200 +[; ;mcc_generated_files/i2c1_master.c: 200: I2C1CNTL = 0x00; +[e = _I2C1CNTL -> -> 0 `i `uc ] +"201 +[; ;mcc_generated_files/i2c1_master.c: 201: I2C1CNTH = 0x00; +[e = _I2C1CNTH -> -> 0 `i `uc ] +"203 +[; ;mcc_generated_files/i2c1_master.c: 203: I2C1BAUD = 0x00; +[e = _I2C1BAUD -> -> 0 `i `uc ] +"204 +[; ;mcc_generated_files/i2c1_master.c: 204: return; +[e $UE 3179 ] +"205 +[; ;mcc_generated_files/i2c1_master.c: 205: } +[e :UE 3179 ] +} +"207 +[; ;mcc_generated_files/i2c1_master.c: 207: i2c1_error_t I2C1_Open(i2c1_address_t address) +[v _I2C1_Open `(E355 ~T0 @X0 1 ef1`uc ] +"208 +[; ;mcc_generated_files/i2c1_master.c: 208: { +{ +[e :U _I2C1_Open ] +"207 +[; ;mcc_generated_files/i2c1_master.c: 207: i2c1_error_t I2C1_Open(i2c1_address_t address) +[v _address `uc ~T0 @X0 1 r1 ] +"208 +[; ;mcc_generated_files/i2c1_master.c: 208: { +[f ] +"209 +[; ;mcc_generated_files/i2c1_master.c: 209: i2c1_error_t returnValue = I2C1_BUSY; +[v _returnValue `E355 ~T0 @X0 1 a ] +[e = _returnValue . `E355 1 ] +"211 +[; ;mcc_generated_files/i2c1_master.c: 211: if(!I2C1_Status.inUse) +[e $ ! ! != -> . _I2C1_Status 11 `i -> 0 `i 3181 ] +"212 +[; ;mcc_generated_files/i2c1_master.c: 212: { +{ +"213 +[; ;mcc_generated_files/i2c1_master.c: 213: I2C1_Status.address = address; +[e = . _I2C1_Status 4 _address ] +"214 +[; ;mcc_generated_files/i2c1_master.c: 214: I2C1_Status.busy = 0; +[e = . _I2C1_Status 10 -> -> 0 `i `uc ] +"215 +[; ;mcc_generated_files/i2c1_master.c: 215: I2C1_Status.inUse = 1; +[e = . _I2C1_Status 11 -> -> 1 `i `uc ] +"216 +[; ;mcc_generated_files/i2c1_master.c: 216: I2C1_Status.addressNackCheck = 0; +[e = . _I2C1_Status 9 -> -> 0 `i `uc ] +"217 +[; ;mcc_generated_files/i2c1_master.c: 217: I2C1_Status.state = I2C1_RESET; +[e = . _I2C1_Status 7 . `E22532 15 ] +"218 +[; ;mcc_generated_files/i2c1_master.c: 218: I2C1_Status.time_out_value = 500; +[e = . _I2C1_Status 3 -> -> 500 `i `us ] +"219 +[; ;mcc_generated_files/i2c1_master.c: 219: I2C1_Status.bufferFree = 1; +[e = . _I2C1_Status 12 -> -> 1 `i `uc ] +"222 +[; ;mcc_generated_files/i2c1_master.c: 222: I2C1_Status.callbackTable[I2C1_DATA_COMPLETE]=I2C1_CallbackReturnStop; +[e = *U + &U . _I2C1_Status 0 * -> . `E22553 0 `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux &U _I2C1_CallbackReturnStop ] +"223 +[; ;mcc_generated_files/i2c1_master.c: 223: I2C1_Status.callbackPayload[I2C1_DATA_COMPLETE] = ((void*)0); +[e = *U + &U . _I2C1_Status 1 * -> . `E22553 0 `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux -> -> 0 `i `*v ] +"224 +[; ;mcc_generated_files/i2c1_master.c: 224: I2C1_Status.callbackTable[I2C1_WRITE_COLLISION]=I2C1_CallbackReturnStop; +[e = *U + &U . _I2C1_Status 0 * -> . `E22553 1 `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux &U _I2C1_CallbackReturnStop ] +"225 +[; ;mcc_generated_files/i2c1_master.c: 225: I2C1_Status.callbackPayload[I2C1_WRITE_COLLISION] = ((void*)0); +[e = *U + &U . _I2C1_Status 1 * -> . `E22553 1 `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux -> -> 0 `i `*v ] +"226 +[; ;mcc_generated_files/i2c1_master.c: 226: I2C1_Status.callbackTable[I2C1_ADDR_NACK]=I2C1_CallbackReturnStop; +[e = *U + &U . _I2C1_Status 0 * -> . `E22553 2 `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux &U _I2C1_CallbackReturnStop ] +"227 +[; ;mcc_generated_files/i2c1_master.c: 227: I2C1_Status.callbackPayload[I2C1_ADDR_NACK] = ((void*)0); +[e = *U + &U . _I2C1_Status 1 * -> . `E22553 2 `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux -> -> 0 `i `*v ] +"228 +[; ;mcc_generated_files/i2c1_master.c: 228: I2C1_Status.callbackTable[I2C1_DATA_NACK]=I2C1_CallbackReturnStop; +[e = *U + &U . _I2C1_Status 0 * -> . `E22553 3 `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux &U _I2C1_CallbackReturnStop ] +"229 +[; ;mcc_generated_files/i2c1_master.c: 229: I2C1_Status.callbackPayload[I2C1_DATA_NACK] = ((void*)0); +[e = *U + &U . _I2C1_Status 1 * -> . `E22553 3 `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux -> -> 0 `i `*v ] +"230 +[; ;mcc_generated_files/i2c1_master.c: 230: I2C1_Status.callbackTable[I2C1_TIMEOUT]=I2C1_CallbackReturnReset; +[e = *U + &U . _I2C1_Status 0 * -> . `E22553 4 `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux &U _I2C1_CallbackReturnReset ] +"231 +[; ;mcc_generated_files/i2c1_master.c: 231: I2C1_Status.callbackPayload[I2C1_TIMEOUT] = ((void*)0); +[e = *U + &U . _I2C1_Status 1 * -> . `E22553 4 `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux -> -> 0 `i `*v ] +"233 +[; ;mcc_generated_files/i2c1_master.c: 233: I2C1_MasterClearIrq(); +[e ( _I2C1_MasterClearIrq .. ] +"234 +[; ;mcc_generated_files/i2c1_master.c: 234: I2C1_MasterOpen(); +[e ( _I2C1_MasterOpen .. ] +"235 +[; ;mcc_generated_files/i2c1_master.c: 235: returnValue = I2C1_NOERR; +[e = _returnValue . `E355 0 ] +"236 +[; ;mcc_generated_files/i2c1_master.c: 236: } +} +[e :U 3181 ] +"237 +[; ;mcc_generated_files/i2c1_master.c: 237: return returnValue; +[e ) _returnValue ] +[e $UE 3180 ] +"238 +[; ;mcc_generated_files/i2c1_master.c: 238: } +[e :UE 3180 ] +} +"240 +[; ;mcc_generated_files/i2c1_master.c: 240: i2c1_error_t I2C1_Close(void) +[v _I2C1_Close `(E355 ~T0 @X0 1 ef ] +"241 +[; ;mcc_generated_files/i2c1_master.c: 241: { +{ +[e :U _I2C1_Close ] +[f ] +"242 +[; ;mcc_generated_files/i2c1_master.c: 242: i2c1_error_t returnValue = I2C1_BUSY; +[v _returnValue `E355 ~T0 @X0 1 a ] +[e = _returnValue . `E355 1 ] +"243 +[; ;mcc_generated_files/i2c1_master.c: 243: if(!I2C1_Status.busy) +[e $ ! ! != -> . _I2C1_Status 10 `i -> 0 `i 3183 ] +"244 +[; ;mcc_generated_files/i2c1_master.c: 244: { +{ +"245 +[; ;mcc_generated_files/i2c1_master.c: 245: I2C1_Status.inUse = 0; +[e = . _I2C1_Status 11 -> -> 0 `i `uc ] +"246 +[; ;mcc_generated_files/i2c1_master.c: 246: I2C1_Status.address = 0xff; +[e = . _I2C1_Status 4 -> -> 255 `i `uc ] +"247 +[; ;mcc_generated_files/i2c1_master.c: 247: I2C1_MasterClearIrq(); +[e ( _I2C1_MasterClearIrq .. ] +"248 +[; ;mcc_generated_files/i2c1_master.c: 248: I2C1_MasterDisableIrq(); +[e ( _I2C1_MasterDisableIrq .. ] +"249 +[; ;mcc_generated_files/i2c1_master.c: 249: I2C1_MasterClose(); +[e ( _I2C1_MasterClose .. ] +"250 +[; ;mcc_generated_files/i2c1_master.c: 250: returnValue = I2C1_Status.error; +[e = _returnValue . _I2C1_Status 8 ] +"251 +[; ;mcc_generated_files/i2c1_master.c: 251: } +} +[e :U 3183 ] +"252 +[; ;mcc_generated_files/i2c1_master.c: 252: return returnValue; +[e ) _returnValue ] +[e $UE 3182 ] +"253 +[; ;mcc_generated_files/i2c1_master.c: 253: } +[e :UE 3182 ] +} +"255 +[; ;mcc_generated_files/i2c1_master.c: 255: i2c1_error_t I2C1_MasterOperation(_Bool read) +[v _I2C1_MasterOperation `(E355 ~T0 @X0 1 ef1`a ] +"256 +[; ;mcc_generated_files/i2c1_master.c: 256: { +{ +[e :U _I2C1_MasterOperation ] +"255 +[; ;mcc_generated_files/i2c1_master.c: 255: i2c1_error_t I2C1_MasterOperation(_Bool read) +[v _read `a ~T0 @X0 1 r1 ] +"256 +[; ;mcc_generated_files/i2c1_master.c: 256: { +[f ] +"257 +[; ;mcc_generated_files/i2c1_master.c: 257: i2c1_error_t returnValue = I2C1_BUSY; +[v _returnValue `E355 ~T0 @X0 1 a ] +[e = _returnValue . `E355 1 ] +"258 +[; ;mcc_generated_files/i2c1_master.c: 258: if(!I2C1_Status.busy) +[e $ ! ! != -> . _I2C1_Status 10 `i -> 0 `i 3185 ] +"259 +[; ;mcc_generated_files/i2c1_master.c: 259: { +{ +"260 +[; ;mcc_generated_files/i2c1_master.c: 260: I2C1_Status.busy = 1; +[e = . _I2C1_Status 10 -> -> 1 `i `uc ] +"261 +[; ;mcc_generated_files/i2c1_master.c: 261: returnValue = I2C1_NOERR; +[e = _returnValue . `E355 0 ] +"262 +[; ;mcc_generated_files/i2c1_master.c: 262: I2C1_MasterSetCounter((uint8_t) I2C1_Status.data_length); +[e ( _I2C1_MasterSetCounter (1 -> . _I2C1_Status 6 `uc ] +"264 +[; ;mcc_generated_files/i2c1_master.c: 264: if(read) +[e $ ! != -> _read `i -> 0 `i 3186 ] +"265 +[; ;mcc_generated_files/i2c1_master.c: 265: { +{ +"266 +[; ;mcc_generated_files/i2c1_master.c: 266: I2C1_Status.state = I2C1_RX; +[e = . _I2C1_Status 7 . `E22532 4 ] +"267 +[; ;mcc_generated_files/i2c1_master.c: 267: I2C1_DO_SEND_ADR_READ(); +[e ( _I2C1_DO_SEND_ADR_READ .. ] +"268 +[; ;mcc_generated_files/i2c1_master.c: 268: } +} +[e $U 3187 ] +"269 +[; ;mcc_generated_files/i2c1_master.c: 269: else +[e :U 3186 ] +"270 +[; ;mcc_generated_files/i2c1_master.c: 270: { +{ +"271 +[; ;mcc_generated_files/i2c1_master.c: 271: I2C1_Status.state = I2C1_TX; +[e = . _I2C1_Status 7 . `E22532 3 ] +"272 +[; ;mcc_generated_files/i2c1_master.c: 272: I2C1_DO_SEND_ADR_WRITE(); +[e ( _I2C1_DO_SEND_ADR_WRITE .. ] +"273 +[; ;mcc_generated_files/i2c1_master.c: 273: } +} +[e :U 3187 ] +"274 +[; ;mcc_generated_files/i2c1_master.c: 274: I2C1_Poller(); +[e ( _I2C1_Poller .. ] +"275 +[; ;mcc_generated_files/i2c1_master.c: 275: } +} +[e :U 3185 ] +"276 +[; ;mcc_generated_files/i2c1_master.c: 276: return returnValue; +[e ) _returnValue ] +[e $UE 3184 ] +"277 +[; ;mcc_generated_files/i2c1_master.c: 277: } +[e :UE 3184 ] +} +"279 +[; ;mcc_generated_files/i2c1_master.c: 279: i2c1_error_t I2C1_MasterRead(void) +[v _I2C1_MasterRead `(E355 ~T0 @X0 1 ef ] +"280 +[; ;mcc_generated_files/i2c1_master.c: 280: { +{ +[e :U _I2C1_MasterRead ] +[f ] +"281 +[; ;mcc_generated_files/i2c1_master.c: 281: return I2C1_MasterOperation(1); +[e ) ( _I2C1_MasterOperation (1 -> -> 1 `i `a ] +[e $UE 3188 ] +"282 +[; ;mcc_generated_files/i2c1_master.c: 282: } +[e :UE 3188 ] +} +"284 +[; ;mcc_generated_files/i2c1_master.c: 284: i2c1_error_t I2C1_MasterWrite(void) +[v _I2C1_MasterWrite `(E355 ~T0 @X0 1 ef ] +"285 +[; ;mcc_generated_files/i2c1_master.c: 285: { +{ +[e :U _I2C1_MasterWrite ] +[f ] +"286 +[; ;mcc_generated_files/i2c1_master.c: 286: return I2C1_MasterOperation(0); +[e ) ( _I2C1_MasterOperation (1 -> -> 0 `i `a ] +[e $UE 3189 ] +"287 +[; ;mcc_generated_files/i2c1_master.c: 287: } +[e :UE 3189 ] +} +"289 +[; ;mcc_generated_files/i2c1_master.c: 289: void I2C1_SetTimeOut(uint8_t timeOutValue) +[v _I2C1_SetTimeOut `(v ~T0 @X0 1 ef1`uc ] +"290 +[; ;mcc_generated_files/i2c1_master.c: 290: { +{ +[e :U _I2C1_SetTimeOut ] +"289 +[; ;mcc_generated_files/i2c1_master.c: 289: void I2C1_SetTimeOut(uint8_t timeOutValue) +[v _timeOutValue `uc ~T0 @X0 1 r1 ] +"290 +[; ;mcc_generated_files/i2c1_master.c: 290: { +[f ] +"291 +[; ;mcc_generated_files/i2c1_master.c: 291: I2C1_MasterDisableIrq(); +[e ( _I2C1_MasterDisableIrq .. ] +"292 +[; ;mcc_generated_files/i2c1_master.c: 292: I2C1_Status.time_out_value = timeOutValue; +[e = . _I2C1_Status 3 -> _timeOutValue `us ] +"293 +[; ;mcc_generated_files/i2c1_master.c: 293: I2C1_MasterEnableIrq(); +[e ( _I2C1_MasterEnableIrq .. ] +"294 +[; ;mcc_generated_files/i2c1_master.c: 294: } +[e :UE 3190 ] +} +"296 +[; ;mcc_generated_files/i2c1_master.c: 296: void I2C1_SetBuffer(void *buffer, size_t bufferSize) +[v _I2C1_SetBuffer `(v ~T0 @X0 1 ef2`*v`ui ] +"297 +[; ;mcc_generated_files/i2c1_master.c: 297: { +{ +[e :U _I2C1_SetBuffer ] +"296 +[; ;mcc_generated_files/i2c1_master.c: 296: void I2C1_SetBuffer(void *buffer, size_t bufferSize) +[v _buffer `*v ~T0 @X0 1 r1 ] +[v _bufferSize `ui ~T0 @X0 1 r2 ] +"297 +[; ;mcc_generated_files/i2c1_master.c: 297: { +[f ] +"298 +[; ;mcc_generated_files/i2c1_master.c: 298: if(I2C1_Status.bufferFree) +[e $ ! != -> . _I2C1_Status 12 `i -> 0 `i 3192 ] +"299 +[; ;mcc_generated_files/i2c1_master.c: 299: { +{ +"300 +[; ;mcc_generated_files/i2c1_master.c: 300: I2C1_Status.data_ptr = buffer; +[e = . _I2C1_Status 5 -> _buffer `*uc ] +"301 +[; ;mcc_generated_files/i2c1_master.c: 301: I2C1_Status.data_length = bufferSize; +[e = . _I2C1_Status 6 _bufferSize ] +"302 +[; ;mcc_generated_files/i2c1_master.c: 302: I2C1_Status.bufferFree = 0; +[e = . _I2C1_Status 12 -> -> 0 `i `uc ] +"303 +[; ;mcc_generated_files/i2c1_master.c: 303: } +} +[e :U 3192 ] +"304 +[; ;mcc_generated_files/i2c1_master.c: 304: } +[e :UE 3191 ] +} +"306 +[; ;mcc_generated_files/i2c1_master.c: 306: void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr) +[v _I2C1_SetDataCompleteCallback `(v ~T0 @X0 1 ef2`*F22771`*v ] +"307 +[; ;mcc_generated_files/i2c1_master.c: 307: { +{ +[e :U _I2C1_SetDataCompleteCallback ] +"306 +[; ;mcc_generated_files/i2c1_master.c: 306: void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr) +[v _cb `*F22774 ~T0 @X0 1 r1 ] +[v _ptr `*v ~T0 @X0 1 r2 ] +"307 +[; ;mcc_generated_files/i2c1_master.c: 307: { +[f ] +"308 +[; ;mcc_generated_files/i2c1_master.c: 308: I2C1_SetCallback(I2C1_DATA_COMPLETE, cb, ptr); +[e ( _I2C1_SetCallback (3 , , . `E22553 0 _cb _ptr ] +"309 +[; ;mcc_generated_files/i2c1_master.c: 309: } +[e :UE 3193 ] +} +"311 +[; ;mcc_generated_files/i2c1_master.c: 311: void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr) +[v _I2C1_SetWriteCollisionCallback `(v ~T0 @X0 1 ef2`*F22778`*v ] +"312 +[; ;mcc_generated_files/i2c1_master.c: 312: { +{ +[e :U _I2C1_SetWriteCollisionCallback ] +"311 +[; ;mcc_generated_files/i2c1_master.c: 311: void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr) +[v _cb `*F22781 ~T0 @X0 1 r1 ] +[v _ptr `*v ~T0 @X0 1 r2 ] +"312 +[; ;mcc_generated_files/i2c1_master.c: 312: { +[f ] +"313 +[; ;mcc_generated_files/i2c1_master.c: 313: I2C1_SetCallback(I2C1_WRITE_COLLISION, cb, ptr); +[e ( _I2C1_SetCallback (3 , , . `E22553 1 _cb _ptr ] +"314 +[; ;mcc_generated_files/i2c1_master.c: 314: } +[e :UE 3194 ] +} +"316 +[; ;mcc_generated_files/i2c1_master.c: 316: void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr) +[v _I2C1_SetAddressNackCallback `(v ~T0 @X0 1 ef2`*F22785`*v ] +"317 +[; ;mcc_generated_files/i2c1_master.c: 317: { +{ +[e :U _I2C1_SetAddressNackCallback ] +"316 +[; ;mcc_generated_files/i2c1_master.c: 316: void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr) +[v _cb `*F22788 ~T0 @X0 1 r1 ] +[v _ptr `*v ~T0 @X0 1 r2 ] +"317 +[; ;mcc_generated_files/i2c1_master.c: 317: { +[f ] +"318 +[; ;mcc_generated_files/i2c1_master.c: 318: I2C1_SetCallback(I2C1_ADDR_NACK, cb, ptr); +[e ( _I2C1_SetCallback (3 , , . `E22553 2 _cb _ptr ] +"319 +[; ;mcc_generated_files/i2c1_master.c: 319: } +[e :UE 3195 ] +} +"321 +[; ;mcc_generated_files/i2c1_master.c: 321: void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr) +[v _I2C1_SetDataNackCallback `(v ~T0 @X0 1 ef2`*F22792`*v ] +"322 +[; ;mcc_generated_files/i2c1_master.c: 322: { +{ +[e :U _I2C1_SetDataNackCallback ] +"321 +[; ;mcc_generated_files/i2c1_master.c: 321: void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr) +[v _cb `*F22795 ~T0 @X0 1 r1 ] +[v _ptr `*v ~T0 @X0 1 r2 ] +"322 +[; ;mcc_generated_files/i2c1_master.c: 322: { +[f ] +"323 +[; ;mcc_generated_files/i2c1_master.c: 323: I2C1_SetCallback(I2C1_DATA_NACK, cb, ptr); +[e ( _I2C1_SetCallback (3 , , . `E22553 3 _cb _ptr ] +"324 +[; ;mcc_generated_files/i2c1_master.c: 324: } +[e :UE 3196 ] +} +"326 +[; ;mcc_generated_files/i2c1_master.c: 326: void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr) +[v _I2C1_SetTimeoutCallback `(v ~T0 @X0 1 ef2`*F22799`*v ] +"327 +[; ;mcc_generated_files/i2c1_master.c: 327: { +{ +[e :U _I2C1_SetTimeoutCallback ] +"326 +[; ;mcc_generated_files/i2c1_master.c: 326: void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr) +[v _cb `*F22802 ~T0 @X0 1 r1 ] +[v _ptr `*v ~T0 @X0 1 r2 ] +"327 +[; ;mcc_generated_files/i2c1_master.c: 327: { +[f ] +"328 +[; ;mcc_generated_files/i2c1_master.c: 328: I2C1_SetCallback(I2C1_TIMEOUT, cb, ptr); +[e ( _I2C1_SetCallback (3 , , . `E22553 4 _cb _ptr ] +"329 +[; ;mcc_generated_files/i2c1_master.c: 329: } +[e :UE 3197 ] +} +"331 +[; ;mcc_generated_files/i2c1_master.c: 331: static void I2C1_SetCallback(i2c1_callbackIndex_t idx, i2c1_callback_t cb, void *ptr) +[v _I2C1_SetCallback `(v ~T0 @X0 1 sf3`E22553`*F22806`*v ] +"332 +[; ;mcc_generated_files/i2c1_master.c: 332: { +{ +[e :U _I2C1_SetCallback ] +"331 +[; ;mcc_generated_files/i2c1_master.c: 331: static void I2C1_SetCallback(i2c1_callbackIndex_t idx, i2c1_callback_t cb, void *ptr) +[v _idx `E22553 ~T0 @X0 1 r1 ] +[v _cb `*F22810 ~T0 @X0 1 r2 ] +[v _ptr `*v ~T0 @X0 1 r3 ] +"332 +[; ;mcc_generated_files/i2c1_master.c: 332: { +[f ] +"333 +[; ;mcc_generated_files/i2c1_master.c: 333: if(cb) +[e $ ! != _cb -> -> 0 `i `*F22813 3199 ] +"334 +[; ;mcc_generated_files/i2c1_master.c: 334: { +{ +"335 +[; ;mcc_generated_files/i2c1_master.c: 335: I2C1_Status.callbackTable[idx] = cb; +[e = *U + &U . _I2C1_Status 0 * -> _idx `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux _cb ] +"336 +[; ;mcc_generated_files/i2c1_master.c: 336: I2C1_Status.callbackPayload[idx] = ptr; +[e = *U + &U . _I2C1_Status 1 * -> _idx `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux _ptr ] +"337 +[; ;mcc_generated_files/i2c1_master.c: 337: } +} +[e $U 3200 ] +"338 +[; ;mcc_generated_files/i2c1_master.c: 338: else +[e :U 3199 ] +"339 +[; ;mcc_generated_files/i2c1_master.c: 339: { +{ +"340 +[; ;mcc_generated_files/i2c1_master.c: 340: I2C1_Status.callbackTable[idx] = I2C1_CallbackReturnStop; +[e = *U + &U . _I2C1_Status 0 * -> _idx `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux &U _I2C1_CallbackReturnStop ] +"341 +[; ;mcc_generated_files/i2c1_master.c: 341: I2C1_Status.callbackPayload[idx] = ((void*)0); +[e = *U + &U . _I2C1_Status 1 * -> _idx `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux -> -> 0 `i `*v ] +"342 +[; ;mcc_generated_files/i2c1_master.c: 342: } +} +[e :U 3200 ] +"343 +[; ;mcc_generated_files/i2c1_master.c: 343: } +[e :UE 3198 ] +} +"345 +[; ;mcc_generated_files/i2c1_master.c: 345: static void I2C1_Poller(void) +[v _I2C1_Poller `(v ~T0 @X0 1 sf ] +"346 +[; ;mcc_generated_files/i2c1_master.c: 346: { +{ +[e :U _I2C1_Poller ] +[f ] +"347 +[; ;mcc_generated_files/i2c1_master.c: 347: while(I2C1_Status.busy) +[e $U 3202 ] +[e :U 3203 ] +"348 +[; ;mcc_generated_files/i2c1_master.c: 348: { +{ +"349 +[; ;mcc_generated_files/i2c1_master.c: 349: I2C1_MasterWaitForEvent(); +[e ( _I2C1_MasterWaitForEvent .. ] +"350 +[; ;mcc_generated_files/i2c1_master.c: 350: I2C1_MasterFsm(); +[e ( _I2C1_MasterFsm .. ] +"351 +[; ;mcc_generated_files/i2c1_master.c: 351: } +} +[e :U 3202 ] +"347 +[; ;mcc_generated_files/i2c1_master.c: 347: while(I2C1_Status.busy) +[e $ != -> . _I2C1_Status 10 `i -> 0 `i 3203 ] +[e :U 3204 ] +"352 +[; ;mcc_generated_files/i2c1_master.c: 352: } +[e :UE 3201 ] +} +[v F22839 `(v ~T0 @X0 1 tf ] +"354 +[; ;mcc_generated_files/i2c1_master.c: 354: static __attribute__((inline)) void I2C1_MasterFsm(void) +[v _I2C1_MasterFsm `TF22839 ~T0 @X0 1 s ] +"355 +[; ;mcc_generated_files/i2c1_master.c: 355: { +{ +[e :U _I2C1_MasterFsm ] +[f ] +"356 +[; ;mcc_generated_files/i2c1_master.c: 356: I2C1_ClearInterruptFlags(); +[e ( _I2C1_ClearInterruptFlags .. ] +"358 +[; ;mcc_generated_files/i2c1_master.c: 358: if(I2C1_Status.addressNackCheck && I2C1_MasterIsNack()) +[e $ ! && != -> . _I2C1_Status 9 `i -> 0 `i != -> ( _I2C1_MasterIsNack .. `i -> 0 `i 3206 ] +"359 +[; ;mcc_generated_files/i2c1_master.c: 359: { +{ +"360 +[; ;mcc_generated_files/i2c1_master.c: 360: I2C1_Status.state = I2C1_ADDRESS_NACK; +[e = . _I2C1_Status 7 . `E22532 16 ] +"361 +[; ;mcc_generated_files/i2c1_master.c: 361: } +} +[e :U 3206 ] +"362 +[; ;mcc_generated_files/i2c1_master.c: 362: I2C1_Status.state = i2c1_fsmStateTable[I2C1_Status.state](); +[e = . _I2C1_Status 7 ( *U *U + &U _i2c1_fsmStateTable * -> . _I2C1_Status 7 `ux -> -> # *U &U _i2c1_fsmStateTable `ui `ux .. ] +"363 +[; ;mcc_generated_files/i2c1_master.c: 363: } +[e :UE 3205 ] +} +[v F22847 `(v ~T0 @X0 1 tf ] +"365 +[; ;mcc_generated_files/i2c1_master.c: 365: static __attribute__((inline)) void I2C1_ClearInterruptFlags(void) +[v _I2C1_ClearInterruptFlags `TF22847 ~T0 @X0 1 s ] +"366 +[; ;mcc_generated_files/i2c1_master.c: 366: { +{ +[e :U _I2C1_ClearInterruptFlags ] +[f ] +"367 +[; ;mcc_generated_files/i2c1_master.c: 367: if(I2C1_MasterIsCountFlagSet()) +[e $ ! != -> ( _I2C1_MasterIsCountFlagSet .. `i -> 0 `i 3208 ] +"368 +[; ;mcc_generated_files/i2c1_master.c: 368: { +{ +"369 +[; ;mcc_generated_files/i2c1_master.c: 369: I2C1_MasterClearCountFlag(); +[e ( _I2C1_MasterClearCountFlag .. ] +"370 +[; ;mcc_generated_files/i2c1_master.c: 370: } +} +[e $U 3209 ] +"371 +[; ;mcc_generated_files/i2c1_master.c: 371: else if(I2C1_MasterIsStopFlagSet()) +[e :U 3208 ] +[e $ ! != -> ( _I2C1_MasterIsStopFlagSet .. `i -> 0 `i 3210 ] +"372 +[; ;mcc_generated_files/i2c1_master.c: 372: { +{ +"373 +[; ;mcc_generated_files/i2c1_master.c: 373: I2C1_MasterClearStopFlag(); +[e ( _I2C1_MasterClearStopFlag .. ] +"374 +[; ;mcc_generated_files/i2c1_master.c: 374: } +} +[e $U 3211 ] +"375 +[; ;mcc_generated_files/i2c1_master.c: 375: else if(I2C1_MasterIsNackFlagSet()) +[e :U 3210 ] +[e $ ! != -> ( _I2C1_MasterIsNackFlagSet .. `i -> 0 `i 3212 ] +"376 +[; ;mcc_generated_files/i2c1_master.c: 376: { +{ +"377 +[; ;mcc_generated_files/i2c1_master.c: 377: I2C1_MasterClearNackFlag(); +[e ( _I2C1_MasterClearNackFlag .. ] +"378 +[; ;mcc_generated_files/i2c1_master.c: 378: } +} +[e :U 3212 ] +[e :U 3211 ] +[e :U 3209 ] +"379 +[; ;mcc_generated_files/i2c1_master.c: 379: } +[e :UE 3207 ] +} +"381 +[; ;mcc_generated_files/i2c1_master.c: 381: static i2c1_fsm_states_t I2C1_DO_IDLE(void) +[v _I2C1_DO_IDLE `(E22532 ~T0 @X0 1 sf ] +"382 +[; ;mcc_generated_files/i2c1_master.c: 382: { +{ +[e :U _I2C1_DO_IDLE ] +[f ] +"383 +[; ;mcc_generated_files/i2c1_master.c: 383: I2C1_Status.busy = 0; +[e = . _I2C1_Status 10 -> -> 0 `i `uc ] +"384 +[; ;mcc_generated_files/i2c1_master.c: 384: I2C1_Status.error = I2C1_NOERR; +[e = . _I2C1_Status 8 . `E355 0 ] +"385 +[; ;mcc_generated_files/i2c1_master.c: 385: return I2C1_RESET; +[e ) . `E22532 15 ] +[e $UE 3213 ] +"386 +[; ;mcc_generated_files/i2c1_master.c: 386: } +[e :UE 3213 ] +} +"388 +[; ;mcc_generated_files/i2c1_master.c: 388: static i2c1_fsm_states_t I2C1_DO_SEND_ADR_READ(void) +[v _I2C1_DO_SEND_ADR_READ `(E22532 ~T0 @X0 1 sf ] +"389 +[; ;mcc_generated_files/i2c1_master.c: 389: { +{ +[e :U _I2C1_DO_SEND_ADR_READ ] +[f ] +"390 +[; ;mcc_generated_files/i2c1_master.c: 390: I2C1_Status.addressNackCheck = 2; +[e = . _I2C1_Status 9 -> -> 2 `i `uc ] +"391 +[; ;mcc_generated_files/i2c1_master.c: 391: if(I2C1_Status.data_length == 1) +[e $ ! == . _I2C1_Status 6 -> -> 1 `i `ui 3215 ] +"392 +[; ;mcc_generated_files/i2c1_master.c: 392: { +{ +"393 +[; ;mcc_generated_files/i2c1_master.c: 393: I2C1_DO_RX_EMPTY(); +[e ( _I2C1_DO_RX_EMPTY .. ] +"394 +[; ;mcc_generated_files/i2c1_master.c: 394: } +} +[e :U 3215 ] +"395 +[; ;mcc_generated_files/i2c1_master.c: 395: I2C1_MasterSendTxData((uint8_t) (I2C1_Status.address << 1 | 1)); +[e ( _I2C1_MasterSendTxData (1 -> | << -> . _I2C1_Status 4 `i -> 1 `i -> 1 `i `uc ] +"396 +[; ;mcc_generated_files/i2c1_master.c: 396: return I2C1_RX; +[e ) . `E22532 4 ] +[e $UE 3214 ] +"397 +[; ;mcc_generated_files/i2c1_master.c: 397: } +[e :UE 3214 ] +} +"399 +[; ;mcc_generated_files/i2c1_master.c: 399: static i2c1_fsm_states_t I2C1_DO_SEND_ADR_WRITE(void) +[v _I2C1_DO_SEND_ADR_WRITE `(E22532 ~T0 @X0 1 sf ] +"400 +[; ;mcc_generated_files/i2c1_master.c: 400: { +{ +[e :U _I2C1_DO_SEND_ADR_WRITE ] +[f ] +"401 +[; ;mcc_generated_files/i2c1_master.c: 401: I2C1_Status.addressNackCheck = 2; +[e = . _I2C1_Status 9 -> -> 2 `i `uc ] +"402 +[; ;mcc_generated_files/i2c1_master.c: 402: I2C1_MasterSendTxData((uint8_t) (I2C1_Status.address << 1)); +[e ( _I2C1_MasterSendTxData (1 -> << -> . _I2C1_Status 4 `i -> 1 `i `uc ] +"403 +[; ;mcc_generated_files/i2c1_master.c: 403: return I2C1_TX; +[e ) . `E22532 3 ] +[e $UE 3216 ] +"404 +[; ;mcc_generated_files/i2c1_master.c: 404: } +[e :UE 3216 ] +} +"406 +[; ;mcc_generated_files/i2c1_master.c: 406: static i2c1_fsm_states_t I2C1_DO_TX(void) +[v _I2C1_DO_TX `(E22532 ~T0 @X0 1 sf ] +"407 +[; ;mcc_generated_files/i2c1_master.c: 407: { +{ +[e :U _I2C1_DO_TX ] +[f ] +"408 +[; ;mcc_generated_files/i2c1_master.c: 408: if(I2C1_MasterIsNack()) +[e $ ! != -> ( _I2C1_MasterIsNack .. `i -> 0 `i 3218 ] +"409 +[; ;mcc_generated_files/i2c1_master.c: 409: { +{ +"410 +[; ;mcc_generated_files/i2c1_master.c: 410: switch(I2C1_Status.callbackTable[I2C1_DATA_NACK](I2C1_Status.callbackPayload[I2C1_DATA_NACK])) +[e $U 3220 ] +"411 +[; ;mcc_generated_files/i2c1_master.c: 411: { +{ +"412 +[; ;mcc_generated_files/i2c1_master.c: 412: case I2C1_RESTART_READ: +[e :U 3221 ] +"413 +[; ;mcc_generated_files/i2c1_master.c: 413: return I2C1_DO_SEND_RESTART_READ(); +[e ) ( _I2C1_DO_SEND_RESTART_READ .. ] +[e $UE 3217 ] +"414 +[; ;mcc_generated_files/i2c1_master.c: 414: case I2C1_RESTART_WRITE: +[e :U 3222 ] +"415 +[; ;mcc_generated_files/i2c1_master.c: 415: return I2C1_DO_SEND_RESTART_WRITE(); +[e ) ( _I2C1_DO_SEND_RESTART_WRITE .. ] +[e $UE 3217 ] +"416 +[; ;mcc_generated_files/i2c1_master.c: 416: default: +[e :U 3223 ] +"417 +[; ;mcc_generated_files/i2c1_master.c: 417: case I2C1_CONTINUE: +[e :U 3224 ] +"418 +[; ;mcc_generated_files/i2c1_master.c: 418: case I2C1_STOP: +[e :U 3225 ] +"419 +[; ;mcc_generated_files/i2c1_master.c: 419: return I2C1_IDLE; +[e ) . `E22532 0 ] +[e $UE 3217 ] +"420 +[; ;mcc_generated_files/i2c1_master.c: 420: } +} +[e $U 3219 ] +[e :U 3220 ] +[e [\ -> ( *U *U + &U . _I2C1_Status 0 * -> . `E22553 3 `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux (1 *U + &U . _I2C1_Status 1 * -> . `E22553 3 `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux `ui , $ -> . `E360 1 `ui 3221 + , $ -> . `E360 2 `ui 3222 + , $ -> . `E360 3 `ui 3224 + , $ -> . `E360 0 `ui 3225 + 3223 ] +[e :U 3219 ] +"421 +[; ;mcc_generated_files/i2c1_master.c: 421: } +} +[e $U 3226 ] +"422 +[; ;mcc_generated_files/i2c1_master.c: 422: else if(I2C1_MasterIsTxBufEmpty()) +[e :U 3218 ] +[e $ ! != -> ( _I2C1_MasterIsTxBufEmpty .. `i -> 0 `i 3227 ] +"423 +[; ;mcc_generated_files/i2c1_master.c: 423: { +{ +"424 +[; ;mcc_generated_files/i2c1_master.c: 424: if(I2C1_Status.addressNackCheck) +[e $ ! != -> . _I2C1_Status 9 `i -> 0 `i 3228 ] +"425 +[; ;mcc_generated_files/i2c1_master.c: 425: { +{ +"426 +[; ;mcc_generated_files/i2c1_master.c: 426: I2C1_Status.addressNackCheck--; +[e -- . _I2C1_Status 9 -> -> 1 `i `uc ] +"427 +[; ;mcc_generated_files/i2c1_master.c: 427: } +} +[e :U 3228 ] +"428 +[; ;mcc_generated_files/i2c1_master.c: 428: uint8_t dataTx = *I2C1_Status.data_ptr++; +[v _dataTx `uc ~T0 @X0 1 a ] +[e = _dataTx *U ++ . _I2C1_Status 5 * -> -> 1 `i `x -> -> # *U . _I2C1_Status 5 `i `x ] +"429 +[; ;mcc_generated_files/i2c1_master.c: 429: i2c1_fsm_states_t retFsmState = (--I2C1_Status.data_length)?I2C1_TX:I2C1_DO_TX_EMPTY(); +[v _retFsmState `E22532 ~T0 @X0 1 a ] +[e = _retFsmState -> ? != =- . _I2C1_Status 6 -> -> 1 `i `ui -> -> 0 `i `ui : -> . `E22532 3 `ui -> ( _I2C1_DO_TX_EMPTY .. `ui `E22532 ] +"430 +[; ;mcc_generated_files/i2c1_master.c: 430: I2C1_MasterSendTxData(dataTx); +[e ( _I2C1_MasterSendTxData (1 _dataTx ] +"431 +[; ;mcc_generated_files/i2c1_master.c: 431: return retFsmState; +[e ) _retFsmState ] +[e $UE 3217 ] +"432 +[; ;mcc_generated_files/i2c1_master.c: 432: } +} +[e $U 3229 ] +"433 +[; ;mcc_generated_files/i2c1_master.c: 433: else +[e :U 3227 ] +"434 +[; ;mcc_generated_files/i2c1_master.c: 434: { +{ +"435 +[; ;mcc_generated_files/i2c1_master.c: 435: return I2C1_TX; +[e ) . `E22532 3 ] +[e $UE 3217 ] +"436 +[; ;mcc_generated_files/i2c1_master.c: 436: } +} +[e :U 3229 ] +[e :U 3226 ] +"437 +[; ;mcc_generated_files/i2c1_master.c: 437: } +[e :UE 3217 ] +} +"439 +[; ;mcc_generated_files/i2c1_master.c: 439: static i2c1_fsm_states_t I2C1_DO_RX(void) +[v _I2C1_DO_RX `(E22532 ~T0 @X0 1 sf ] +"440 +[; ;mcc_generated_files/i2c1_master.c: 440: { +{ +[e :U _I2C1_DO_RX ] +[f ] +"441 +[; ;mcc_generated_files/i2c1_master.c: 441: if(!I2C1_MasterIsRxBufFull()) +[e $ ! ! != -> ( _I2C1_MasterIsRxBufFull .. `i -> 0 `i 3231 ] +"442 +[; ;mcc_generated_files/i2c1_master.c: 442: { +{ +"443 +[; ;mcc_generated_files/i2c1_master.c: 443: return I2C1_RX; +[e ) . `E22532 4 ] +[e $UE 3230 ] +"444 +[; ;mcc_generated_files/i2c1_master.c: 444: } +} +[e :U 3231 ] +"445 +[; ;mcc_generated_files/i2c1_master.c: 445: if(I2C1_Status.addressNackCheck) +[e $ ! != -> . _I2C1_Status 9 `i -> 0 `i 3232 ] +"446 +[; ;mcc_generated_files/i2c1_master.c: 446: { +{ +"447 +[; ;mcc_generated_files/i2c1_master.c: 447: I2C1_Status.addressNackCheck--; +[e -- . _I2C1_Status 9 -> -> 1 `i `uc ] +"448 +[; ;mcc_generated_files/i2c1_master.c: 448: } +} +[e :U 3232 ] +"450 +[; ;mcc_generated_files/i2c1_master.c: 450: if(--I2C1_Status.data_length) +[e $ ! != =- . _I2C1_Status 6 -> -> 1 `i `ui -> -> 0 `i `ui 3233 ] +"451 +[; ;mcc_generated_files/i2c1_master.c: 451: { +{ +"452 +[; ;mcc_generated_files/i2c1_master.c: 452: *I2C1_Status.data_ptr++ = I2C1_MasterGetRxData(); +[e = *U ++ . _I2C1_Status 5 * -> -> 1 `i `x -> -> # *U . _I2C1_Status 5 `i `x ( _I2C1_MasterGetRxData .. ] +"453 +[; ;mcc_generated_files/i2c1_master.c: 453: return I2C1_RX; +[e ) . `E22532 4 ] +[e $UE 3230 ] +"454 +[; ;mcc_generated_files/i2c1_master.c: 454: } +} +[e $U 3234 ] +"455 +[; ;mcc_generated_files/i2c1_master.c: 455: else +[e :U 3233 ] +"456 +[; ;mcc_generated_files/i2c1_master.c: 456: { +{ +"457 +[; ;mcc_generated_files/i2c1_master.c: 457: i2c1_fsm_states_t retFsmState = I2C1_DO_RX_EMPTY(); +[v _retFsmState `E22532 ~T0 @X0 1 a ] +[e = _retFsmState ( _I2C1_DO_RX_EMPTY .. ] +"458 +[; ;mcc_generated_files/i2c1_master.c: 458: *I2C1_Status.data_ptr++ = I2C1_MasterGetRxData(); +[e = *U ++ . _I2C1_Status 5 * -> -> 1 `i `x -> -> # *U . _I2C1_Status 5 `i `x ( _I2C1_MasterGetRxData .. ] +"459 +[; ;mcc_generated_files/i2c1_master.c: 459: return retFsmState; +[e ) _retFsmState ] +[e $UE 3230 ] +"460 +[; ;mcc_generated_files/i2c1_master.c: 460: } +} +[e :U 3234 ] +"461 +[; ;mcc_generated_files/i2c1_master.c: 461: } +[e :UE 3230 ] +} +"463 +[; ;mcc_generated_files/i2c1_master.c: 463: static i2c1_fsm_states_t I2C1_DO_TX_EMPTY(void) +[v _I2C1_DO_TX_EMPTY `(E22532 ~T0 @X0 1 sf ] +"464 +[; ;mcc_generated_files/i2c1_master.c: 464: { +{ +[e :U _I2C1_DO_TX_EMPTY ] +[f ] +"465 +[; ;mcc_generated_files/i2c1_master.c: 465: I2C1_Status.bufferFree = 1; +[e = . _I2C1_Status 12 -> -> 1 `i `uc ] +"466 +[; ;mcc_generated_files/i2c1_master.c: 466: switch(I2C1_Status.callbackTable[I2C1_DATA_COMPLETE](I2C1_Status.callbackPayload[I2C1_DATA_COMPLETE])) +[e $U 3237 ] +"467 +[; ;mcc_generated_files/i2c1_master.c: 467: { +{ +"468 +[; ;mcc_generated_files/i2c1_master.c: 468: case I2C1_RESTART_READ: +[e :U 3238 ] +"469 +[; ;mcc_generated_files/i2c1_master.c: 469: I2C1_MasterEnableRestart(); +[e ( _I2C1_MasterEnableRestart .. ] +"470 +[; ;mcc_generated_files/i2c1_master.c: 470: return I2C1_SEND_RESTART_READ; +[e ) . `E22532 7 ] +[e $UE 3235 ] +"471 +[; ;mcc_generated_files/i2c1_master.c: 471: case I2C1_CONTINUE: +[e :U 3239 ] +"473 +[; ;mcc_generated_files/i2c1_master.c: 473: I2C1_MasterSetCounter((uint8_t) I2C1_Status.data_length + 1); +[e ( _I2C1_MasterSetCounter (1 -> + -> -> . _I2C1_Status 6 `uc `i -> 1 `i `uc ] +"474 +[; ;mcc_generated_files/i2c1_master.c: 474: return I2C1_TX; +[e ) . `E22532 3 ] +[e $UE 3235 ] +"475 +[; ;mcc_generated_files/i2c1_master.c: 475: default: +[e :U 3240 ] +"476 +[; ;mcc_generated_files/i2c1_master.c: 476: case I2C1_STOP: +[e :U 3241 ] +"477 +[; ;mcc_generated_files/i2c1_master.c: 477: I2C1_MasterDisableRestart(); +[e ( _I2C1_MasterDisableRestart .. ] +"478 +[; ;mcc_generated_files/i2c1_master.c: 478: return I2C1_SEND_STOP; +[e ) . `E22532 10 ] +[e $UE 3235 ] +"479 +[; ;mcc_generated_files/i2c1_master.c: 479: } +} +[e $U 3236 ] +[e :U 3237 ] +[e [\ -> ( *U *U + &U . _I2C1_Status 0 * -> . `E22553 0 `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux (1 *U + &U . _I2C1_Status 1 * -> . `E22553 0 `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux `ui , $ -> . `E360 1 `ui 3238 + , $ -> . `E360 3 `ui 3239 + , $ -> . `E360 0 `ui 3241 + 3240 ] +[e :U 3236 ] +"480 +[; ;mcc_generated_files/i2c1_master.c: 480: } +[e :UE 3235 ] +} +"482 +[; ;mcc_generated_files/i2c1_master.c: 482: static i2c1_fsm_states_t I2C1_DO_RX_EMPTY(void) +[v _I2C1_DO_RX_EMPTY `(E22532 ~T0 @X0 1 sf ] +"483 +[; ;mcc_generated_files/i2c1_master.c: 483: { +{ +[e :U _I2C1_DO_RX_EMPTY ] +[f ] +"484 +[; ;mcc_generated_files/i2c1_master.c: 484: I2C1_Status.bufferFree = 1; +[e = . _I2C1_Status 12 -> -> 1 `i `uc ] +"485 +[; ;mcc_generated_files/i2c1_master.c: 485: switch(I2C1_Status.callbackTable[I2C1_DATA_COMPLETE](I2C1_Status.callbackPayload[I2C1_DATA_COMPLETE])) +[e $U 3244 ] +"486 +[; ;mcc_generated_files/i2c1_master.c: 486: { +{ +"487 +[; ;mcc_generated_files/i2c1_master.c: 487: case I2C1_RESTART_WRITE: +[e :U 3245 ] +"488 +[; ;mcc_generated_files/i2c1_master.c: 488: I2C1_MasterEnableRestart(); +[e ( _I2C1_MasterEnableRestart .. ] +"489 +[; ;mcc_generated_files/i2c1_master.c: 489: return I2C1_SEND_RESTART_WRITE; +[e ) . `E22532 8 ] +[e $UE 3242 ] +"490 +[; ;mcc_generated_files/i2c1_master.c: 490: case I2C1_RESTART_READ: +[e :U 3246 ] +"491 +[; ;mcc_generated_files/i2c1_master.c: 491: I2C1_MasterEnableRestart(); +[e ( _I2C1_MasterEnableRestart .. ] +"492 +[; ;mcc_generated_files/i2c1_master.c: 492: return I2C1_SEND_RESTART_READ; +[e ) . `E22532 7 ] +[e $UE 3242 ] +"493 +[; ;mcc_generated_files/i2c1_master.c: 493: case I2C1_CONTINUE: +[e :U 3247 ] +"495 +[; ;mcc_generated_files/i2c1_master.c: 495: I2C1_MasterSetCounter((uint8_t) (I2C1_Status.data_length + 1)); +[e ( _I2C1_MasterSetCounter (1 -> + . _I2C1_Status 6 -> -> 1 `i `ui `uc ] +"496 +[; ;mcc_generated_files/i2c1_master.c: 496: return I2C1_RX; +[e ) . `E22532 4 ] +[e $UE 3242 ] +"497 +[; ;mcc_generated_files/i2c1_master.c: 497: default: +[e :U 3248 ] +"498 +[; ;mcc_generated_files/i2c1_master.c: 498: case I2C1_STOP: +[e :U 3249 ] +"499 +[; ;mcc_generated_files/i2c1_master.c: 499: if(I2C1_Status.state != I2C1_SEND_RESTART_READ) +[e $ ! != -> . _I2C1_Status 7 `ui -> . `E22532 7 `ui 3250 ] +"500 +[; ;mcc_generated_files/i2c1_master.c: 500: { +{ +"501 +[; ;mcc_generated_files/i2c1_master.c: 501: I2C1_MasterDisableRestart(); +[e ( _I2C1_MasterDisableRestart .. ] +"502 +[; ;mcc_generated_files/i2c1_master.c: 502: } +} +[e :U 3250 ] +"503 +[; ;mcc_generated_files/i2c1_master.c: 503: return I2C1_RESET; +[e ) . `E22532 15 ] +[e $UE 3242 ] +"504 +[; ;mcc_generated_files/i2c1_master.c: 504: } +} +[e $U 3243 ] +[e :U 3244 ] +[e [\ -> ( *U *U + &U . _I2C1_Status 0 * -> . `E22553 0 `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux (1 *U + &U . _I2C1_Status 1 * -> . `E22553 0 `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux `ui , $ -> . `E360 2 `ui 3245 + , $ -> . `E360 1 `ui 3246 + , $ -> . `E360 3 `ui 3247 + , $ -> . `E360 0 `ui 3249 + 3248 ] +[e :U 3243 ] +"505 +[; ;mcc_generated_files/i2c1_master.c: 505: } +[e :UE 3242 ] +} +"507 +[; ;mcc_generated_files/i2c1_master.c: 507: static i2c1_fsm_states_t I2C1_DO_SEND_RESTART_READ(void) +[v _I2C1_DO_SEND_RESTART_READ `(E22532 ~T0 @X0 1 sf ] +"508 +[; ;mcc_generated_files/i2c1_master.c: 508: { +{ +[e :U _I2C1_DO_SEND_RESTART_READ ] +[f ] +"509 +[; ;mcc_generated_files/i2c1_master.c: 509: I2C1_MasterSetCounter((uint8_t) I2C1_Status.data_length); +[e ( _I2C1_MasterSetCounter (1 -> . _I2C1_Status 6 `uc ] +"510 +[; ;mcc_generated_files/i2c1_master.c: 510: return I2C1_DO_SEND_ADR_READ(); +[e ) ( _I2C1_DO_SEND_ADR_READ .. ] +[e $UE 3251 ] +"511 +[; ;mcc_generated_files/i2c1_master.c: 511: } +[e :UE 3251 ] +} +"513 +[; ;mcc_generated_files/i2c1_master.c: 513: static i2c1_fsm_states_t I2C1_DO_SEND_RESTART_WRITE(void) +[v _I2C1_DO_SEND_RESTART_WRITE `(E22532 ~T0 @X0 1 sf ] +"514 +[; ;mcc_generated_files/i2c1_master.c: 514: { +{ +[e :U _I2C1_DO_SEND_RESTART_WRITE ] +[f ] +"515 +[; ;mcc_generated_files/i2c1_master.c: 515: return I2C1_SEND_ADR_WRITE; +[e ) . `E22532 2 ] +[e $UE 3252 ] +"516 +[; ;mcc_generated_files/i2c1_master.c: 516: } +[e :UE 3252 ] +} +"519 +[; ;mcc_generated_files/i2c1_master.c: 519: static i2c1_fsm_states_t I2C1_DO_SEND_RESTART(void) +[v _I2C1_DO_SEND_RESTART `(E22532 ~T0 @X0 1 sf ] +"520 +[; ;mcc_generated_files/i2c1_master.c: 520: { +{ +[e :U _I2C1_DO_SEND_RESTART ] +[f ] +"521 +[; ;mcc_generated_files/i2c1_master.c: 521: return I2C1_SEND_ADR_READ; +[e ) . `E22532 1 ] +[e $UE 3253 ] +"522 +[; ;mcc_generated_files/i2c1_master.c: 522: } +[e :UE 3253 ] +} +"524 +[; ;mcc_generated_files/i2c1_master.c: 524: static i2c1_fsm_states_t I2C1_DO_SEND_STOP(void) +[v _I2C1_DO_SEND_STOP `(E22532 ~T0 @X0 1 sf ] +"525 +[; ;mcc_generated_files/i2c1_master.c: 525: { +{ +[e :U _I2C1_DO_SEND_STOP ] +[f ] +"526 +[; ;mcc_generated_files/i2c1_master.c: 526: I2C1_MasterStop(); +[e ( _I2C1_MasterStop .. ] +"527 +[; ;mcc_generated_files/i2c1_master.c: 527: if(I2C1_MasterGetCounter()) +[e $ ! != -> ( _I2C1_MasterGetCounter .. `i -> 0 `i 3255 ] +"528 +[; ;mcc_generated_files/i2c1_master.c: 528: { +{ +"529 +[; ;mcc_generated_files/i2c1_master.c: 529: I2C1_MasterSetCounter(0); +[e ( _I2C1_MasterSetCounter (1 -> -> 0 `i `uc ] +"530 +[; ;mcc_generated_files/i2c1_master.c: 530: I2C1_MasterSendTxData(0); +[e ( _I2C1_MasterSendTxData (1 -> -> 0 `i `uc ] +"531 +[; ;mcc_generated_files/i2c1_master.c: 531: } +} +[e :U 3255 ] +"532 +[; ;mcc_generated_files/i2c1_master.c: 532: return I2C1_IDLE; +[e ) . `E22532 0 ] +[e $UE 3254 ] +"533 +[; ;mcc_generated_files/i2c1_master.c: 533: } +[e :UE 3254 ] +} +"535 +[; ;mcc_generated_files/i2c1_master.c: 535: static i2c1_fsm_states_t I2C1_DO_RX_ACK(void) +[v _I2C1_DO_RX_ACK `(E22532 ~T0 @X0 1 sf ] +"536 +[; ;mcc_generated_files/i2c1_master.c: 536: { +{ +[e :U _I2C1_DO_RX_ACK ] +[f ] +"537 +[; ;mcc_generated_files/i2c1_master.c: 537: I2C1_MasterSendAck(); +[e ( _I2C1_MasterSendAck .. ] +"538 +[; ;mcc_generated_files/i2c1_master.c: 538: return I2C1_RX; +[e ) . `E22532 4 ] +[e $UE 3256 ] +"539 +[; ;mcc_generated_files/i2c1_master.c: 539: } +[e :UE 3256 ] +} +"541 +[; ;mcc_generated_files/i2c1_master.c: 541: static i2c1_fsm_states_t I2C1_DO_TX_ACK(void) +[v _I2C1_DO_TX_ACK `(E22532 ~T0 @X0 1 sf ] +"542 +[; ;mcc_generated_files/i2c1_master.c: 542: { +{ +[e :U _I2C1_DO_TX_ACK ] +[f ] +"543 +[; ;mcc_generated_files/i2c1_master.c: 543: I2C1_MasterSendAck(); +[e ( _I2C1_MasterSendAck .. ] +"544 +[; ;mcc_generated_files/i2c1_master.c: 544: return I2C1_TX; +[e ) . `E22532 3 ] +[e $UE 3257 ] +"545 +[; ;mcc_generated_files/i2c1_master.c: 545: } +[e :UE 3257 ] +} +"547 +[; ;mcc_generated_files/i2c1_master.c: 547: static i2c1_fsm_states_t I2C1_DO_RX_NACK_STOP(void) +[v _I2C1_DO_RX_NACK_STOP `(E22532 ~T0 @X0 1 sf ] +"548 +[; ;mcc_generated_files/i2c1_master.c: 548: { +{ +[e :U _I2C1_DO_RX_NACK_STOP ] +[f ] +"549 +[; ;mcc_generated_files/i2c1_master.c: 549: I2C1_MasterSendNack(); +[e ( _I2C1_MasterSendNack .. ] +"550 +[; ;mcc_generated_files/i2c1_master.c: 550: I2C1_MasterStop(); +[e ( _I2C1_MasterStop .. ] +"551 +[; ;mcc_generated_files/i2c1_master.c: 551: return I2C1_DO_IDLE(); +[e ) ( _I2C1_DO_IDLE .. ] +[e $UE 3258 ] +"552 +[; ;mcc_generated_files/i2c1_master.c: 552: } +[e :UE 3258 ] +} +"554 +[; ;mcc_generated_files/i2c1_master.c: 554: static i2c1_fsm_states_t I2C1_DO_RX_NACK_RESTART(void) +[v _I2C1_DO_RX_NACK_RESTART `(E22532 ~T0 @X0 1 sf ] +"555 +[; ;mcc_generated_files/i2c1_master.c: 555: { +{ +[e :U _I2C1_DO_RX_NACK_RESTART ] +[f ] +"556 +[; ;mcc_generated_files/i2c1_master.c: 556: I2C1_MasterSendNack(); +[e ( _I2C1_MasterSendNack .. ] +"557 +[; ;mcc_generated_files/i2c1_master.c: 557: return I2C1_SEND_RESTART; +[e ) . `E22532 9 ] +[e $UE 3259 ] +"558 +[; ;mcc_generated_files/i2c1_master.c: 558: } +[e :UE 3259 ] +} +"560 +[; ;mcc_generated_files/i2c1_master.c: 560: static i2c1_fsm_states_t I2C1_DO_RESET(void) +[v _I2C1_DO_RESET `(E22532 ~T0 @X0 1 sf ] +"561 +[; ;mcc_generated_files/i2c1_master.c: 561: { +{ +[e :U _I2C1_DO_RESET ] +[f ] +"562 +[; ;mcc_generated_files/i2c1_master.c: 562: I2C1_MasterResetBus(); +[e ( _I2C1_MasterResetBus .. ] +"563 +[; ;mcc_generated_files/i2c1_master.c: 563: I2C1_Status.busy = 0; +[e = . _I2C1_Status 10 -> -> 0 `i `uc ] +"564 +[; ;mcc_generated_files/i2c1_master.c: 564: I2C1_Status.error = I2C1_NOERR; +[e = . _I2C1_Status 8 . `E355 0 ] +"565 +[; ;mcc_generated_files/i2c1_master.c: 565: return I2C1_RESET; +[e ) . `E22532 15 ] +[e $UE 3260 ] +"566 +[; ;mcc_generated_files/i2c1_master.c: 566: } +[e :UE 3260 ] +} +"567 +[; ;mcc_generated_files/i2c1_master.c: 567: static i2c1_fsm_states_t I2C1_DO_ADDRESS_NACK(void) +[v _I2C1_DO_ADDRESS_NACK `(E22532 ~T0 @X0 1 sf ] +"568 +[; ;mcc_generated_files/i2c1_master.c: 568: { +{ +[e :U _I2C1_DO_ADDRESS_NACK ] +[f ] +"569 +[; ;mcc_generated_files/i2c1_master.c: 569: I2C1_Status.addressNackCheck = 0; +[e = . _I2C1_Status 9 -> -> 0 `i `uc ] +"570 +[; ;mcc_generated_files/i2c1_master.c: 570: I2C1_Status.error = I2C1_FAIL; +[e = . _I2C1_Status 8 . `E355 2 ] +"571 +[; ;mcc_generated_files/i2c1_master.c: 571: I2C1_Status.busy = 0; +[e = . _I2C1_Status 10 -> -> 0 `i `uc ] +"572 +[; ;mcc_generated_files/i2c1_master.c: 572: switch(I2C1_Status.callbackTable[I2C1_ADDR_NACK](I2C1_Status.callbackPayload[I2C1_ADDR_NACK])) +[e $U 3263 ] +"573 +[; ;mcc_generated_files/i2c1_master.c: 573: { +{ +"574 +[; ;mcc_generated_files/i2c1_master.c: 574: case I2C1_RESTART_READ: +[e :U 3264 ] +"575 +[; ;mcc_generated_files/i2c1_master.c: 575: case I2C1_RESTART_WRITE: +[e :U 3265 ] +"576 +[; ;mcc_generated_files/i2c1_master.c: 576: return I2C1_DO_SEND_RESTART(); +[e ) ( _I2C1_DO_SEND_RESTART .. ] +[e $UE 3261 ] +"577 +[; ;mcc_generated_files/i2c1_master.c: 577: default: +[e :U 3266 ] +"578 +[; ;mcc_generated_files/i2c1_master.c: 578: return I2C1_RESET; +[e ) . `E22532 15 ] +[e $UE 3261 ] +"579 +[; ;mcc_generated_files/i2c1_master.c: 579: } +} +[e $U 3262 ] +[e :U 3263 ] +[e [\ -> ( *U *U + &U . _I2C1_Status 0 * -> . `E22553 2 `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux (1 *U + &U . _I2C1_Status 1 * -> . `E22553 2 `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux `ui , $ -> . `E360 1 `ui 3264 + , $ -> . `E360 2 `ui 3265 + 3266 ] +[e :U 3262 ] +"580 +[; ;mcc_generated_files/i2c1_master.c: 580: } +[e :UE 3261 ] +} +"582 +[; ;mcc_generated_files/i2c1_master.c: 582: static i2c1_fsm_states_t I2C1_DO_BUS_COLLISION(void) +[v _I2C1_DO_BUS_COLLISION `(E22532 ~T0 @X0 1 sf ] +"583 +[; ;mcc_generated_files/i2c1_master.c: 583: { +{ +[e :U _I2C1_DO_BUS_COLLISION ] +[f ] +"585 +[; ;mcc_generated_files/i2c1_master.c: 585: I2C1_MasterClearIrq(); +[e ( _I2C1_MasterClearIrq .. ] +"587 +[; ;mcc_generated_files/i2c1_master.c: 587: I2C1_Status.error = I2C1_FAIL; +[e = . _I2C1_Status 8 . `E355 2 ] +"588 +[; ;mcc_generated_files/i2c1_master.c: 588: switch (I2C1_Status.callbackTable[I2C1_WRITE_COLLISION](I2C1_Status.callbackPayload[I2C1_WRITE_COLLISION])) { +[e $U 3269 ] +{ +"589 +[; ;mcc_generated_files/i2c1_master.c: 589: case I2C1_RESTART_READ: +[e :U 3270 ] +"590 +[; ;mcc_generated_files/i2c1_master.c: 590: return I2C1_DO_SEND_RESTART_READ(); +[e ) ( _I2C1_DO_SEND_RESTART_READ .. ] +[e $UE 3267 ] +"591 +[; ;mcc_generated_files/i2c1_master.c: 591: case I2C1_RESTART_WRITE: +[e :U 3271 ] +"592 +[; ;mcc_generated_files/i2c1_master.c: 592: return I2C1_DO_SEND_RESTART_WRITE(); +[e ) ( _I2C1_DO_SEND_RESTART_WRITE .. ] +[e $UE 3267 ] +"593 +[; ;mcc_generated_files/i2c1_master.c: 593: default: +[e :U 3272 ] +"594 +[; ;mcc_generated_files/i2c1_master.c: 594: return I2C1_DO_RESET(); +[e ) ( _I2C1_DO_RESET .. ] +[e $UE 3267 ] +"595 +[; ;mcc_generated_files/i2c1_master.c: 595: } +} +[e $U 3268 ] +[e :U 3269 ] +[e [\ -> ( *U *U + &U . _I2C1_Status 0 * -> . `E22553 1 `ux -> -> # *U &U . _I2C1_Status 0 `ui `ux (1 *U + &U . _I2C1_Status 1 * -> . `E22553 1 `ux -> -> # *U &U . _I2C1_Status 1 `ui `ux `ui , $ -> . `E360 1 `ui 3270 + , $ -> . `E360 2 `ui 3271 + 3272 ] +[e :U 3268 ] +"596 +[; ;mcc_generated_files/i2c1_master.c: 596: } +[e :UE 3267 ] +} +"598 +[; ;mcc_generated_files/i2c1_master.c: 598: static i2c1_fsm_states_t I2C1_DO_BUS_ERROR(void) +[v _I2C1_DO_BUS_ERROR `(E22532 ~T0 @X0 1 sf ] +"599 +[; ;mcc_generated_files/i2c1_master.c: 599: { +{ +[e :U _I2C1_DO_BUS_ERROR ] +[f ] +"600 +[; ;mcc_generated_files/i2c1_master.c: 600: I2C1_MasterResetBus(); +[e ( _I2C1_MasterResetBus .. ] +"601 +[; ;mcc_generated_files/i2c1_master.c: 601: I2C1_Status.busy = 0; +[e = . _I2C1_Status 10 -> -> 0 `i `uc ] +"602 +[; ;mcc_generated_files/i2c1_master.c: 602: I2C1_Status.error = I2C1_FAIL; +[e = . _I2C1_Status 8 . `E355 2 ] +"603 +[; ;mcc_generated_files/i2c1_master.c: 603: return I2C1_RESET; +[e ) . `E22532 15 ] +[e $UE 3273 ] +"604 +[; ;mcc_generated_files/i2c1_master.c: 604: } +[e :UE 3273 ] +} +"606 +[; ;mcc_generated_files/i2c1_master.c: 606: void I2C1_BusCollisionIsr(void) +[v _I2C1_BusCollisionIsr `(v ~T0 @X0 1 ef ] +"607 +[; ;mcc_generated_files/i2c1_master.c: 607: { +{ +[e :U _I2C1_BusCollisionIsr ] +[f ] +"608 +[; ;mcc_generated_files/i2c1_master.c: 608: I2C1_MasterClearBusCollision(); +[e ( _I2C1_MasterClearBusCollision .. ] +"609 +[; ;mcc_generated_files/i2c1_master.c: 609: I2C1_Status.state = I2C1_RESET; +[e = . _I2C1_Status 7 . `E22532 15 ] +"610 +[; ;mcc_generated_files/i2c1_master.c: 610: } +[e :UE 3274 ] +} +"612 +[; ;mcc_generated_files/i2c1_master.c: 612: i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr) +[v _I2C1_CallbackReturnStop `(E360 ~T0 @X0 1 ef1`*v ] +"613 +[; ;mcc_generated_files/i2c1_master.c: 613: { +{ +[e :U _I2C1_CallbackReturnStop ] +"612 +[; ;mcc_generated_files/i2c1_master.c: 612: i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr) +[v _funPtr `*v ~T0 @X0 1 r1 ] +"613 +[; ;mcc_generated_files/i2c1_master.c: 613: { +[f ] +"614 +[; ;mcc_generated_files/i2c1_master.c: 614: return I2C1_STOP; +[e ) . `E360 0 ] +[e $UE 3275 ] +"615 +[; ;mcc_generated_files/i2c1_master.c: 615: } +[e :UE 3275 ] +} +"617 +[; ;mcc_generated_files/i2c1_master.c: 617: i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr) +[v _I2C1_CallbackReturnReset `(E360 ~T0 @X0 1 ef1`*v ] +"618 +[; ;mcc_generated_files/i2c1_master.c: 618: { +{ +[e :U _I2C1_CallbackReturnReset ] +"617 +[; ;mcc_generated_files/i2c1_master.c: 617: i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr) +[v _funPtr `*v ~T0 @X0 1 r1 ] +"618 +[; ;mcc_generated_files/i2c1_master.c: 618: { +[f ] +"619 +[; ;mcc_generated_files/i2c1_master.c: 619: return I2C1_RESET_LINK; +[e ) . `E360 4 ] +[e $UE 3276 ] +"620 +[; ;mcc_generated_files/i2c1_master.c: 620: } +[e :UE 3276 ] +} +"622 +[; ;mcc_generated_files/i2c1_master.c: 622: i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr) +[v _I2C1_CallbackRestartWrite `(E360 ~T0 @X0 1 ef1`*v ] +"623 +[; ;mcc_generated_files/i2c1_master.c: 623: { +{ +[e :U _I2C1_CallbackRestartWrite ] +"622 +[; ;mcc_generated_files/i2c1_master.c: 622: i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr) +[v _funPtr `*v ~T0 @X0 1 r1 ] +"623 +[; ;mcc_generated_files/i2c1_master.c: 623: { +[f ] +"624 +[; ;mcc_generated_files/i2c1_master.c: 624: return I2C1_RESTART_WRITE; +[e ) . `E360 2 ] +[e $UE 3277 ] +"625 +[; ;mcc_generated_files/i2c1_master.c: 625: } +[e :UE 3277 ] +} +"627 +[; ;mcc_generated_files/i2c1_master.c: 627: i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr) +[v _I2C1_CallbackRestartRead `(E360 ~T0 @X0 1 ef1`*v ] +"628 +[; ;mcc_generated_files/i2c1_master.c: 628: { +{ +[e :U _I2C1_CallbackRestartRead ] +"627 +[; ;mcc_generated_files/i2c1_master.c: 627: i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr) +[v _funPtr `*v ~T0 @X0 1 r1 ] +"628 +[; ;mcc_generated_files/i2c1_master.c: 628: { +[f ] +"629 +[; ;mcc_generated_files/i2c1_master.c: 629: return I2C1_RESTART_READ; +[e ) . `E360 1 ] +[e $UE 3278 ] +"630 +[; ;mcc_generated_files/i2c1_master.c: 630: } +[e :UE 3278 ] +} +[v F22920 `(a ~T0 @X0 1 tf ] +"635 +[; ;mcc_generated_files/i2c1_master.c: 635: static __attribute__((inline)) _Bool I2C1_MasterOpen(void) +[v _I2C1_MasterOpen `TF22920 ~T0 @X0 1 s ] +"636 +[; ;mcc_generated_files/i2c1_master.c: 636: { +{ +[e :U _I2C1_MasterOpen ] +[f ] +"637 +[; ;mcc_generated_files/i2c1_master.c: 637: if(!I2C1CON0bits.EN) +[e $ ! ! != -> . . _I2C1CON0bits 0 5 `i -> 0 `i 3280 ] +"638 +[; ;mcc_generated_files/i2c1_master.c: 638: { +{ +"640 +[; ;mcc_generated_files/i2c1_master.c: 640: I2C1PIR = 0x00; +[e = _I2C1PIR -> -> 0 `i `uc ] +"642 +[; ;mcc_generated_files/i2c1_master.c: 642: I2C1PIE = 0x00; +[e = _I2C1PIE -> -> 0 `i `uc ] +"644 +[; ;mcc_generated_files/i2c1_master.c: 644: I2C1ERR = 0x00; +[e = _I2C1ERR -> -> 0 `i `uc ] +"646 +[; ;mcc_generated_files/i2c1_master.c: 646: I2C1CNTL = 0x00; +[e = _I2C1CNTL -> -> 0 `i `uc ] +"647 +[; ;mcc_generated_files/i2c1_master.c: 647: I2C1CNTH = 0x00; +[e = _I2C1CNTH -> -> 0 `i `uc ] +"649 +[; ;mcc_generated_files/i2c1_master.c: 649: I2C1BAUD = 0x00; +[e = _I2C1BAUD -> -> 0 `i `uc ] +"651 +[; ;mcc_generated_files/i2c1_master.c: 651: I2C1CON0bits.EN = 1; +[e = . . _I2C1CON0bits 0 5 -> -> 1 `i `uc ] +"652 +[; ;mcc_generated_files/i2c1_master.c: 652: return 1; +[e ) -> -> 1 `i `a ] +[e $UE 3279 ] +"653 +[; ;mcc_generated_files/i2c1_master.c: 653: } +} +[e :U 3280 ] +"654 +[; ;mcc_generated_files/i2c1_master.c: 654: return 0; +[e ) -> -> 0 `i `a ] +[e $UE 3279 ] +"655 +[; ;mcc_generated_files/i2c1_master.c: 655: } +[e :UE 3279 ] +} +[v F22922 `(v ~T0 @X0 1 tf ] +"657 +[; ;mcc_generated_files/i2c1_master.c: 657: static __attribute__((inline)) void I2C1_MasterClose(void) +[v _I2C1_MasterClose `TF22922 ~T0 @X0 1 s ] +"658 +[; ;mcc_generated_files/i2c1_master.c: 658: { +{ +[e :U _I2C1_MasterClose ] +[f ] +"660 +[; ;mcc_generated_files/i2c1_master.c: 660: I2C1CON0bits.EN = 0; +[e = . . _I2C1CON0bits 0 5 -> -> 0 `i `uc ] +"662 +[; ;mcc_generated_files/i2c1_master.c: 662: I2C1PIR = 0x00; +[e = _I2C1PIR -> -> 0 `i `uc ] +"664 +[; ;mcc_generated_files/i2c1_master.c: 664: I2C1STAT1bits.CLRBF = 1; +[e = . . _I2C1STAT1bits 0 2 -> -> 1 `i `uc ] +"665 +[; ;mcc_generated_files/i2c1_master.c: 665: } +[e :UE 3281 ] +} +[v F22924 `(uc ~T0 @X0 1 tf ] +"667 +[; ;mcc_generated_files/i2c1_master.c: 667: static __attribute__((inline)) uint8_t I2C1_MasterGetRxData(void) +[v _I2C1_MasterGetRxData `TF22924 ~T0 @X0 1 s ] +"668 +[; ;mcc_generated_files/i2c1_master.c: 668: { +{ +[e :U _I2C1_MasterGetRxData ] +[f ] +"669 +[; ;mcc_generated_files/i2c1_master.c: 669: return I2C1RXB; +[e ) _I2C1RXB ] +[e $UE 3282 ] +"670 +[; ;mcc_generated_files/i2c1_master.c: 670: } +[e :UE 3282 ] +} +[v F22926 `(v ~T0 @X0 1 tf1`uc ] +"672 +[; ;mcc_generated_files/i2c1_master.c: 672: static __attribute__((inline)) void I2C1_MasterSendTxData(uint8_t data) +[v _I2C1_MasterSendTxData `TF22926 ~T0 @X0 1 s ] +"673 +[; ;mcc_generated_files/i2c1_master.c: 673: { +{ +[e :U _I2C1_MasterSendTxData ] +"672 +[; ;mcc_generated_files/i2c1_master.c: 672: static __attribute__((inline)) void I2C1_MasterSendTxData(uint8_t data) +[v _data `uc ~T0 @X0 1 r1 ] +"673 +[; ;mcc_generated_files/i2c1_master.c: 673: { +[f ] +"674 +[; ;mcc_generated_files/i2c1_master.c: 674: I2C1TXB = data; +[e = _I2C1TXB _data ] +"675 +[; ;mcc_generated_files/i2c1_master.c: 675: } +[e :UE 3283 ] +} +[v F22929 `(uc ~T0 @X0 1 tf ] +"677 +[; ;mcc_generated_files/i2c1_master.c: 677: static __attribute__((inline)) uint8_t I2C1_MasterGetCounter() +[v _I2C1_MasterGetCounter `TF22929 ~T0 @X0 1 s ] +"678 +[; ;mcc_generated_files/i2c1_master.c: 678: { +{ +[e :U _I2C1_MasterGetCounter ] +[f ] +"679 +[; ;mcc_generated_files/i2c1_master.c: 679: return I2C1CNTL; +[e ) _I2C1CNTL ] +[e $UE 3284 ] +"680 +[; ;mcc_generated_files/i2c1_master.c: 680: } +[e :UE 3284 ] +} +[v F22931 `(v ~T0 @X0 1 tf1`uc ] +"682 +[; ;mcc_generated_files/i2c1_master.c: 682: static __attribute__((inline)) void I2C1_MasterSetCounter(uint8_t counter) +[v _I2C1_MasterSetCounter `TF22931 ~T0 @X0 1 s ] +"683 +[; ;mcc_generated_files/i2c1_master.c: 683: { +{ +[e :U _I2C1_MasterSetCounter ] +"682 +[; ;mcc_generated_files/i2c1_master.c: 682: static __attribute__((inline)) void I2C1_MasterSetCounter(uint8_t counter) +[v _counter `uc ~T0 @X0 1 r1 ] +"683 +[; ;mcc_generated_files/i2c1_master.c: 683: { +[f ] +"684 +[; ;mcc_generated_files/i2c1_master.c: 684: I2C1CNTL = counter; +[e = _I2C1CNTL _counter ] +"685 +[; ;mcc_generated_files/i2c1_master.c: 685: I2C1CNTH = 0x00; +[e = _I2C1CNTH -> -> 0 `i `uc ] +"686 +[; ;mcc_generated_files/i2c1_master.c: 686: } +[e :UE 3285 ] +} +[v F22934 `(v ~T0 @X0 1 tf ] +"688 +[; ;mcc_generated_files/i2c1_master.c: 688: static __attribute__((inline)) void I2C1_MasterResetBus(void) +[v _I2C1_MasterResetBus `TF22934 ~T0 @X0 1 s ] +"689 +[; ;mcc_generated_files/i2c1_master.c: 689: { +{ +[e :U _I2C1_MasterResetBus ] +[f ] +"691 +[; ;mcc_generated_files/i2c1_master.c: 691: I2C1CON0bits.EN = 0; +[e = . . _I2C1CON0bits 0 5 -> -> 0 `i `uc ] +"693 +[; ;mcc_generated_files/i2c1_master.c: 693: I2C1STAT1bits.CLRBF = 1; +[e = . . _I2C1STAT1bits 0 2 -> -> 1 `i `uc ] +"695 +[; ;mcc_generated_files/i2c1_master.c: 695: I2C1CON0bits.EN = 1; +[e = . . _I2C1CON0bits 0 5 -> -> 1 `i `uc ] +"696 +[; ;mcc_generated_files/i2c1_master.c: 696: } +[e :UE 3286 ] +} +[v F22936 `(v ~T0 @X0 1 tf ] +"698 +[; ;mcc_generated_files/i2c1_master.c: 698: static __attribute__((inline)) void I2C1_MasterEnableRestart(void) +[v _I2C1_MasterEnableRestart `TF22936 ~T0 @X0 1 s ] +"699 +[; ;mcc_generated_files/i2c1_master.c: 699: { +{ +[e :U _I2C1_MasterEnableRestart ] +[f ] +"701 +[; ;mcc_generated_files/i2c1_master.c: 701: I2C1CON0bits.RSEN = 1; +[e = . . _I2C1CON0bits 0 4 -> -> 1 `i `uc ] +"702 +[; ;mcc_generated_files/i2c1_master.c: 702: } +[e :UE 3287 ] +} +[v F22938 `(v ~T0 @X0 1 tf ] +"704 +[; ;mcc_generated_files/i2c1_master.c: 704: static __attribute__((inline)) void I2C1_MasterDisableRestart(void) +[v _I2C1_MasterDisableRestart `TF22938 ~T0 @X0 1 s ] +"705 +[; ;mcc_generated_files/i2c1_master.c: 705: { +{ +[e :U _I2C1_MasterDisableRestart ] +[f ] +"707 +[; ;mcc_generated_files/i2c1_master.c: 707: I2C1CON0bits.RSEN = 0; +[e = . . _I2C1CON0bits 0 4 -> -> 0 `i `uc ] +"708 +[; ;mcc_generated_files/i2c1_master.c: 708: } +[e :UE 3288 ] +} +[v F22940 `(v ~T0 @X0 1 tf ] +"710 +[; ;mcc_generated_files/i2c1_master.c: 710: static __attribute__((inline)) void I2C1_MasterStop(void) +[v _I2C1_MasterStop `TF22940 ~T0 @X0 1 s ] +"711 +[; ;mcc_generated_files/i2c1_master.c: 711: { +{ +[e :U _I2C1_MasterStop ] +[f ] +"713 +[; ;mcc_generated_files/i2c1_master.c: 713: I2C1CON0bits.S = 0; +[e = . . _I2C1CON0bits 0 3 -> -> 0 `i `uc ] +"714 +[; ;mcc_generated_files/i2c1_master.c: 714: } +[e :UE 3289 ] +} +[v F22942 `(a ~T0 @X0 1 tf ] +"716 +[; ;mcc_generated_files/i2c1_master.c: 716: static __attribute__((inline)) _Bool I2C1_MasterIsNack(void) +[v _I2C1_MasterIsNack `TF22942 ~T0 @X0 1 s ] +"717 +[; ;mcc_generated_files/i2c1_master.c: 717: { +{ +[e :U _I2C1_MasterIsNack ] +[f ] +"718 +[; ;mcc_generated_files/i2c1_master.c: 718: return I2C1CON1bits.ACKSTAT; +[e ) -> . . _I2C1CON1bits 0 5 `a ] +[e $UE 3290 ] +"719 +[; ;mcc_generated_files/i2c1_master.c: 719: } +[e :UE 3290 ] +} +[v F22944 `(v ~T0 @X0 1 tf ] +"721 +[; ;mcc_generated_files/i2c1_master.c: 721: static __attribute__((inline)) void I2C1_MasterSendAck(void) +[v _I2C1_MasterSendAck `TF22944 ~T0 @X0 1 s ] +"722 +[; ;mcc_generated_files/i2c1_master.c: 722: { +{ +[e :U _I2C1_MasterSendAck ] +[f ] +"723 +[; ;mcc_generated_files/i2c1_master.c: 723: I2C1CON1bits.ACKDT = 0; +[e = . . _I2C1CON1bits 0 6 -> -> 0 `i `uc ] +"724 +[; ;mcc_generated_files/i2c1_master.c: 724: } +[e :UE 3291 ] +} +[v F22946 `(v ~T0 @X0 1 tf ] +"726 +[; ;mcc_generated_files/i2c1_master.c: 726: static __attribute__((inline)) void I2C1_MasterSendNack(void) +[v _I2C1_MasterSendNack `TF22946 ~T0 @X0 1 s ] +"727 +[; ;mcc_generated_files/i2c1_master.c: 727: { +{ +[e :U _I2C1_MasterSendNack ] +[f ] +"728 +[; ;mcc_generated_files/i2c1_master.c: 728: I2C1CON1bits.ACKDT = 1; +[e = . . _I2C1CON1bits 0 6 -> -> 1 `i `uc ] +"729 +[; ;mcc_generated_files/i2c1_master.c: 729: } +[e :UE 3292 ] +} +[v F22948 `(v ~T0 @X0 1 tf ] +"731 +[; ;mcc_generated_files/i2c1_master.c: 731: static __attribute__((inline)) void I2C1_MasterClearBusCollision(void) +[v _I2C1_MasterClearBusCollision `TF22948 ~T0 @X0 1 s ] +"732 +[; ;mcc_generated_files/i2c1_master.c: 732: { +{ +[e :U _I2C1_MasterClearBusCollision ] +[f ] +"733 +[; ;mcc_generated_files/i2c1_master.c: 733: I2C1ERRbits.BCLIF = 0; +[e = . . _I2C1ERRbits 0 5 -> -> 0 `i `uc ] +"734 +[; ;mcc_generated_files/i2c1_master.c: 734: I2C1ERRbits.BTOIF = 0; +[e = . . _I2C1ERRbits 0 6 -> -> 0 `i `uc ] +"735 +[; ;mcc_generated_files/i2c1_master.c: 735: I2C1ERRbits.NACKIF = 0; +[e = . . _I2C1ERRbits 0 4 -> -> 0 `i `uc ] +"736 +[; ;mcc_generated_files/i2c1_master.c: 736: } +[e :UE 3293 ] +} +[v F22950 `(a ~T0 @X0 1 tf ] +"738 +[; ;mcc_generated_files/i2c1_master.c: 738: static __attribute__((inline)) _Bool I2C1_MasterIsRxBufFull(void) +[v _I2C1_MasterIsRxBufFull `TF22950 ~T0 @X0 1 s ] +"739 +[; ;mcc_generated_files/i2c1_master.c: 739: { +{ +[e :U _I2C1_MasterIsRxBufFull ] +[f ] +"740 +[; ;mcc_generated_files/i2c1_master.c: 740: return I2C1STAT1bits.RXBF; +[e ) -> . . _I2C1STAT1bits 0 0 `a ] +[e $UE 3294 ] +"741 +[; ;mcc_generated_files/i2c1_master.c: 741: } +[e :UE 3294 ] +} +[v F22952 `(a ~T0 @X0 1 tf ] +"743 +[; ;mcc_generated_files/i2c1_master.c: 743: static __attribute__((inline)) _Bool I2C1_MasterIsTxBufEmpty(void) +[v _I2C1_MasterIsTxBufEmpty `TF22952 ~T0 @X0 1 s ] +"744 +[; ;mcc_generated_files/i2c1_master.c: 744: { +{ +[e :U _I2C1_MasterIsTxBufEmpty ] +[f ] +"745 +[; ;mcc_generated_files/i2c1_master.c: 745: return I2C1STAT1bits.TXBE; +[e ) -> . . _I2C1STAT1bits 0 5 `a ] +[e $UE 3295 ] +"746 +[; ;mcc_generated_files/i2c1_master.c: 746: } +[e :UE 3295 ] +} +[v F22954 `(a ~T0 @X0 1 tf ] +"748 +[; ;mcc_generated_files/i2c1_master.c: 748: static __attribute__((inline)) _Bool I2C1_MasterIsStopFlagSet(void) +[v _I2C1_MasterIsStopFlagSet `TF22954 ~T0 @X0 1 s ] +"749 +[; ;mcc_generated_files/i2c1_master.c: 749: { +{ +[e :U _I2C1_MasterIsStopFlagSet ] +[f ] +"750 +[; ;mcc_generated_files/i2c1_master.c: 750: return I2C1PIRbits.PCIF; +[e ) -> . . _I2C1PIRbits 0 2 `a ] +[e $UE 3296 ] +"751 +[; ;mcc_generated_files/i2c1_master.c: 751: } +[e :UE 3296 ] +} +[v F22956 `(a ~T0 @X0 1 tf ] +"753 +[; ;mcc_generated_files/i2c1_master.c: 753: static __attribute__((inline)) _Bool I2C1_MasterIsCountFlagSet(void) +[v _I2C1_MasterIsCountFlagSet `TF22956 ~T0 @X0 1 s ] +"754 +[; ;mcc_generated_files/i2c1_master.c: 754: { +{ +[e :U _I2C1_MasterIsCountFlagSet ] +[f ] +"755 +[; ;mcc_generated_files/i2c1_master.c: 755: return I2C1PIRbits.CNTIF; +[e ) -> . . _I2C1PIRbits 0 7 `a ] +[e $UE 3297 ] +"756 +[; ;mcc_generated_files/i2c1_master.c: 756: } +[e :UE 3297 ] +} +[v F22958 `(a ~T0 @X0 1 tf ] +"758 +[; ;mcc_generated_files/i2c1_master.c: 758: static __attribute__((inline)) _Bool I2C1_MasterIsNackFlagSet(void) +[v _I2C1_MasterIsNackFlagSet `TF22958 ~T0 @X0 1 s ] +"759 +[; ;mcc_generated_files/i2c1_master.c: 759: { +{ +[e :U _I2C1_MasterIsNackFlagSet ] +[f ] +"760 +[; ;mcc_generated_files/i2c1_master.c: 760: return I2C1ERRbits.NACKIF; +[e ) -> . . _I2C1ERRbits 0 4 `a ] +[e $UE 3298 ] +"761 +[; ;mcc_generated_files/i2c1_master.c: 761: } +[e :UE 3298 ] +} +[v F22960 `(v ~T0 @X0 1 tf ] +"763 +[; ;mcc_generated_files/i2c1_master.c: 763: static __attribute__((inline)) void I2C1_MasterClearStopFlag(void) +[v _I2C1_MasterClearStopFlag `TF22960 ~T0 @X0 1 s ] +"764 +[; ;mcc_generated_files/i2c1_master.c: 764: { +{ +[e :U _I2C1_MasterClearStopFlag ] +[f ] +"765 +[; ;mcc_generated_files/i2c1_master.c: 765: I2C1PIRbits.PCIF = 0; +[e = . . _I2C1PIRbits 0 2 -> -> 0 `i `uc ] +"766 +[; ;mcc_generated_files/i2c1_master.c: 766: } +[e :UE 3299 ] +} +[v F22962 `(v ~T0 @X0 1 tf ] +"768 +[; ;mcc_generated_files/i2c1_master.c: 768: static __attribute__((inline)) void I2C1_MasterClearCountFlag(void) +[v _I2C1_MasterClearCountFlag `TF22962 ~T0 @X0 1 s ] +"769 +[; ;mcc_generated_files/i2c1_master.c: 769: { +{ +[e :U _I2C1_MasterClearCountFlag ] +[f ] +"770 +[; ;mcc_generated_files/i2c1_master.c: 770: I2C1PIRbits.CNTIF = 0; +[e = . . _I2C1PIRbits 0 7 -> -> 0 `i `uc ] +"771 +[; ;mcc_generated_files/i2c1_master.c: 771: } +[e :UE 3300 ] +} +[v F22964 `(v ~T0 @X0 1 tf ] +"773 +[; ;mcc_generated_files/i2c1_master.c: 773: static __attribute__((inline)) void I2C1_MasterClearNackFlag(void) +[v _I2C1_MasterClearNackFlag `TF22964 ~T0 @X0 1 s ] +"774 +[; ;mcc_generated_files/i2c1_master.c: 774: { +{ +[e :U _I2C1_MasterClearNackFlag ] +[f ] +"775 +[; ;mcc_generated_files/i2c1_master.c: 775: I2C1ERRbits.NACKIF = 0; +[e = . . _I2C1ERRbits 0 4 -> -> 0 `i `uc ] +"776 +[; ;mcc_generated_files/i2c1_master.c: 776: } +[e :UE 3301 ] +} +[v F22966 `(v ~T0 @X0 1 tf ] +"778 +[; ;mcc_generated_files/i2c1_master.c: 778: static __attribute__((inline)) void I2C1_MasterEnableIrq(void) +[v _I2C1_MasterEnableIrq `TF22966 ~T0 @X0 1 s ] +"779 +[; ;mcc_generated_files/i2c1_master.c: 779: { +{ +[e :U _I2C1_MasterEnableIrq ] +[f ] +"780 +[; ;mcc_generated_files/i2c1_master.c: 780: PIE7bits.I2C1IE = 1; +[e = . . _PIE7bits 0 2 -> -> 1 `i `uc ] +"781 +[; ;mcc_generated_files/i2c1_master.c: 781: PIE7bits.I2C1EIE = 1; +[e = . . _PIE7bits 0 3 -> -> 1 `i `uc ] +"782 +[; ;mcc_generated_files/i2c1_master.c: 782: PIE7bits.I2C1RXIE = 1; +[e = . . _PIE7bits 0 0 -> -> 1 `i `uc ] +"783 +[; ;mcc_generated_files/i2c1_master.c: 783: PIE7bits.I2C1TXIE = 1; +[e = . . _PIE7bits 0 1 -> -> 1 `i `uc ] +"785 +[; ;mcc_generated_files/i2c1_master.c: 785: I2C1PIEbits.PCIE = 1; +[e = . . _I2C1PIEbits 0 2 -> -> 1 `i `uc ] +"786 +[; ;mcc_generated_files/i2c1_master.c: 786: I2C1PIEbits.CNTIE = 1; +[e = . . _I2C1PIEbits 0 7 -> -> 1 `i `uc ] +"787 +[; ;mcc_generated_files/i2c1_master.c: 787: I2C1ERRbits.NACKIE = 1; +[e = . . _I2C1ERRbits 0 0 -> -> 1 `i `uc ] +"788 +[; ;mcc_generated_files/i2c1_master.c: 788: } +[e :UE 3302 ] +} +[v F22968 `(a ~T0 @X0 1 tf ] +"790 +[; ;mcc_generated_files/i2c1_master.c: 790: static __attribute__((inline)) _Bool I2C1_MasterIsIrqEnabled(void) +[v _I2C1_MasterIsIrqEnabled `TF22968 ~T0 @X0 1 s ] +"791 +[; ;mcc_generated_files/i2c1_master.c: 791: { +{ +[e :U _I2C1_MasterIsIrqEnabled ] +[f ] +"792 +[; ;mcc_generated_files/i2c1_master.c: 792: return (PIE7bits.I2C1RXIE && PIE7bits.I2C1TXIE && PIE7bits.I2C1IE); +[e ) -> -> && && != -> . . _PIE7bits 0 0 `i -> 0 `i != -> . . _PIE7bits 0 1 `i -> 0 `i != -> . . _PIE7bits 0 2 `i -> 0 `i `i `a ] +[e $UE 3303 ] +"793 +[; ;mcc_generated_files/i2c1_master.c: 793: } +[e :UE 3303 ] +} +[v F22970 `(v ~T0 @X0 1 tf ] +"795 +[; ;mcc_generated_files/i2c1_master.c: 795: static __attribute__((inline)) void I2C1_MasterDisableIrq(void) +[v _I2C1_MasterDisableIrq `TF22970 ~T0 @X0 1 s ] +"796 +[; ;mcc_generated_files/i2c1_master.c: 796: { +{ +[e :U _I2C1_MasterDisableIrq ] +[f ] +"797 +[; ;mcc_generated_files/i2c1_master.c: 797: PIE7bits.I2C1IE = 0; +[e = . . _PIE7bits 0 2 -> -> 0 `i `uc ] +"798 +[; ;mcc_generated_files/i2c1_master.c: 798: PIE7bits.I2C1EIE = 0; +[e = . . _PIE7bits 0 3 -> -> 0 `i `uc ] +"799 +[; ;mcc_generated_files/i2c1_master.c: 799: PIE7bits.I2C1RXIE = 0; +[e = . . _PIE7bits 0 0 -> -> 0 `i `uc ] +"800 +[; ;mcc_generated_files/i2c1_master.c: 800: PIE7bits.I2C1TXIE = 0; +[e = . . _PIE7bits 0 1 -> -> 0 `i `uc ] +"801 +[; ;mcc_generated_files/i2c1_master.c: 801: I2C1PIEbits.SCIE = 0; +[e = . . _I2C1PIEbits 0 0 -> -> 0 `i `uc ] +"802 +[; ;mcc_generated_files/i2c1_master.c: 802: I2C1PIEbits.PCIE = 0; +[e = . . _I2C1PIEbits 0 2 -> -> 0 `i `uc ] +"803 +[; ;mcc_generated_files/i2c1_master.c: 803: I2C1PIEbits.CNTIE = 0; +[e = . . _I2C1PIEbits 0 7 -> -> 0 `i `uc ] +"804 +[; ;mcc_generated_files/i2c1_master.c: 804: I2C1PIEbits.ACKTIE = 0; +[e = . . _I2C1PIEbits 0 6 -> -> 0 `i `uc ] +"805 +[; ;mcc_generated_files/i2c1_master.c: 805: I2C1PIEbits.RSCIE = 0; +[e = . . _I2C1PIEbits 0 1 -> -> 0 `i `uc ] +"806 +[; ;mcc_generated_files/i2c1_master.c: 806: I2C1ERRbits.BCLIE = 0; +[e = . . _I2C1ERRbits 0 1 -> -> 0 `i `uc ] +"807 +[; ;mcc_generated_files/i2c1_master.c: 807: I2C1ERRbits.BTOIE = 0; +[e = . . _I2C1ERRbits 0 2 -> -> 0 `i `uc ] +"808 +[; ;mcc_generated_files/i2c1_master.c: 808: I2C1ERRbits.NACKIE = 0; +[e = . . _I2C1ERRbits 0 0 -> -> 0 `i `uc ] +"809 +[; ;mcc_generated_files/i2c1_master.c: 809: } +[e :UE 3304 ] +} +[v F22972 `(v ~T0 @X0 1 tf ] +"811 +[; ;mcc_generated_files/i2c1_master.c: 811: static __attribute__((inline)) void I2C1_MasterClearIrq(void) +[v _I2C1_MasterClearIrq `TF22972 ~T0 @X0 1 s ] +"812 +[; ;mcc_generated_files/i2c1_master.c: 812: { +{ +[e :U _I2C1_MasterClearIrq ] +[f ] +"813 +[; ;mcc_generated_files/i2c1_master.c: 813: I2C1PIR = 0x00; +[e = _I2C1PIR -> -> 0 `i `uc ] +"814 +[; ;mcc_generated_files/i2c1_master.c: 814: } +[e :UE 3305 ] +} +[v F22974 `(v ~T0 @X0 1 tf ] +"816 +[; ;mcc_generated_files/i2c1_master.c: 816: static __attribute__((inline)) void I2C1_MasterWaitForEvent(void) +[v _I2C1_MasterWaitForEvent `TF22974 ~T0 @X0 1 s ] +"817 +[; ;mcc_generated_files/i2c1_master.c: 817: { +{ +[e :U _I2C1_MasterWaitForEvent ] +[f ] +"818 +[; ;mcc_generated_files/i2c1_master.c: 818: while(1) +[e :U 3308 ] +"819 +[; ;mcc_generated_files/i2c1_master.c: 819: { +{ +"820 +[; ;mcc_generated_files/i2c1_master.c: 820: if(PIR7bits.I2C1TXIF) +[e $ ! != -> . . _PIR7bits 0 1 `i -> 0 `i 3310 ] +"821 +[; ;mcc_generated_files/i2c1_master.c: 821: { +{ +"822 +[; ;mcc_generated_files/i2c1_master.c: 822: break; +[e $U 3309 ] +"823 +[; ;mcc_generated_files/i2c1_master.c: 823: } +} +[e :U 3310 ] +"824 +[; ;mcc_generated_files/i2c1_master.c: 824: if(PIR7bits.I2C1RXIF) +[e $ ! != -> . . _PIR7bits 0 0 `i -> 0 `i 3311 ] +"825 +[; ;mcc_generated_files/i2c1_master.c: 825: { +{ +"826 +[; ;mcc_generated_files/i2c1_master.c: 826: break; +[e $U 3309 ] +"827 +[; ;mcc_generated_files/i2c1_master.c: 827: } +} +[e :U 3311 ] +"828 +[; ;mcc_generated_files/i2c1_master.c: 828: if(I2C1PIRbits.PCIF) +[e $ ! != -> . . _I2C1PIRbits 0 2 `i -> 0 `i 3312 ] +"829 +[; ;mcc_generated_files/i2c1_master.c: 829: { +{ +"830 +[; ;mcc_generated_files/i2c1_master.c: 830: break; +[e $U 3309 ] +"831 +[; ;mcc_generated_files/i2c1_master.c: 831: } +} +[e :U 3312 ] +"832 +[; ;mcc_generated_files/i2c1_master.c: 832: if(I2C1PIRbits.CNTIF) +[e $ ! != -> . . _I2C1PIRbits 0 7 `i -> 0 `i 3313 ] +"833 +[; ;mcc_generated_files/i2c1_master.c: 833: { +{ +"834 +[; ;mcc_generated_files/i2c1_master.c: 834: break; +[e $U 3309 ] +"835 +[; ;mcc_generated_files/i2c1_master.c: 835: } +} +[e :U 3313 ] +"836 +[; ;mcc_generated_files/i2c1_master.c: 836: if(I2C1ERRbits.NACKIF) +[e $ ! != -> . . _I2C1ERRbits 0 4 `i -> 0 `i 3314 ] +"837 +[; ;mcc_generated_files/i2c1_master.c: 837: { +{ +"838 +[; ;mcc_generated_files/i2c1_master.c: 838: break; +[e $U 3309 ] +"839 +[; ;mcc_generated_files/i2c1_master.c: 839: } +} +[e :U 3314 ] +"840 +[; ;mcc_generated_files/i2c1_master.c: 840: } +} +[e :U 3307 ] +[e $U 3308 ] +[e :U 3309 ] +"841 +[; ;mcc_generated_files/i2c1_master.c: 841: } +[e :UE 3306 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/i2c1_master.p1.d b/ETC.X/build/default/debug/mcc_generated_files/i2c1_master.p1.d new file mode 100644 index 0000000..8c295b0 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/i2c1_master.p1.d @@ -0,0 +1,3 @@ +build/default/debug/mcc_generated_files/i2c1_master.p1: \ +mcc_generated_files/i2c1_master.c \ +mcc_generated_files/i2c1_master.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.i b/ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.i new file mode 100644 index 0000000..1b72b6a --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.i @@ -0,0 +1,38288 @@ +# 1 "mcc_generated_files/interrupt_manager.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/interrupt_manager.c" 2 +# 49 "mcc_generated_files/interrupt_manager.c" +# 1 "mcc_generated_files/interrupt_manager.h" 1 +# 87 "mcc_generated_files/interrupt_manager.h" +void INTERRUPT_Initialize (void); +# 49 "mcc_generated_files/interrupt_manager.c" 2 + +# 1 "mcc_generated_files/mcc.h" 1 +# 49 "mcc_generated_files/mcc.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 49 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/device_config.h" 1 +# 50 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pin_manager.h" 1 +# 402 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 51 "mcc_generated_files/mcc.h" 2 + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 53 "mcc_generated_files/mcc.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 1 3 + + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 1 3 +# 12 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 3 +extern int errno; +# 8 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__null.h" 1 3 +# 9 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + + + +extern void init_uart(void); + +extern char getch(void); +extern char getche(void); +extern void putch(char); +extern void ungetch(char); + +extern __bit kbhit(void); + + + +extern char * cgets(char *); +extern void cputs(const char *); +# 54 "mcc_generated_files/mcc.h" 2 + + +# 1 "mcc_generated_files/i2c1_master.h" 1 +# 54 "mcc_generated_files/i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "mcc_generated_files/i2c1_master.h" 2 + + + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "mcc_generated_files/i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "mcc_generated_files/i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "mcc_generated_files/i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 56 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/adc.h" 1 +# 65 "mcc_generated_files/adc.h" +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 57 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/tmr1.h" 1 +# 101 "mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 58 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/tmr0.h" 1 +# 106 "mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 59 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/can1.h" 1 +# 56 "mcc_generated_files/can1.h" +# 1 "mcc_generated_files/can_types.h" 1 +# 65 "mcc_generated_files/can_types.h" +typedef union +{ + uint8_t msgfields; + struct + { + uint8_t idType:1; + uint8_t frameType:1; + uint8_t dlc:4; + uint8_t formatType:1; + uint8_t brs:1; + }; +} CAN_MSG_FIELD; + +typedef struct +{ + uint32_t msgId; + CAN_MSG_FIELD field; + uint8_t *data; +} CAN_MSG_OBJ; +# 94 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NON_BRS_MODE = 0, + CAN_BRS_MODE = 1 +} CAN_MSG_OBJ_BRS_MODE; +# 109 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_STD = 0, + CAN_FRAME_EXT = 1, +} CAN_MSG_OBJ_ID_TYPE; +# 124 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_DATA = 0, + CAN_FRAME_RTR = 1, +} CAN_MSG_OBJ_FRAME_TYPE; +# 139 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_2_0_FORMAT = 0, + CAN_FD_FORMAT = 1 +} CAN_MSG_OBJ_TYPE; +# 154 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_MSG_REQUEST_SUCCESS = 0, + CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR = 1, + CAN_TX_MSG_REQUEST_BRS_ERROR = 2, + CAN_TX_MSG_REQUEST_FIFO_FULL = 3, +} CAN_TX_MSG_REQUEST_STATUS; +# 171 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NORMAL_FD_MODE = 0, + CAN_DISABLE_MODE = 1, + CAN_INTERNAL_LOOPBACK_MODE = 2, + CAN_LISTEN_ONLY_MODE = 3, + CAN_CONFIGURATION_MODE = 4, + CAN_EXTERNAL_LOOPBACK_MODE = 5, + CAN_NORMAL_2_0_MODE = 6, + CAN_RESTRICTED_OPERATION_MODE =7, +} CAN_OP_MODES; +# 192 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_OP_MODE_REQUEST_SUCCESS, + CAN_OP_MODE_REQUEST_FAIL, + CAN_OP_MODE_SYS_ERROR_OCCURED +} CAN_OP_MODE_STATUS; +# 208 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_FIFO_FULL, + CAN_TX_FIFO_AVAILABLE, +} CAN_TX_FIFO_STATUS; +# 223 "mcc_generated_files/can_types.h" +typedef enum +{ + + DLC_0, + DLC_1, + DLC_2, + DLC_3, + DLC_4, + DLC_5, + DLC_6, + DLC_7, + DLC_8, + + + + DLC_12, + DLC_16, + DLC_20, + DLC_24, + DLC_32, + DLC_48, + DLC_64, +} CAN_DLC; +# 56 "mcc_generated_files/can1.h" 2 + + + + + +typedef enum +{ + TXQ = 0 +} CAN1_TX_FIFO_CHANNELS; + +typedef enum +{ + FIFO1 = 1 +} CAN1_RX_FIFO_CHANNELS; +# 106 "mcc_generated_files/can1.h" +void CAN1_Initialize(void); +# 147 "mcc_generated_files/can1.h" +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +# 185 "mcc_generated_files/can1.h" +CAN_OP_MODES CAN1_OperationModeGet(void); +# 235 "mcc_generated_files/can1.h" +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +# 275 "mcc_generated_files/can1.h" +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *rxCanMsg); +# 334 "mcc_generated_files/can1.h" +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +# 390 "mcc_generated_files/can1.h" +_Bool CAN1_IsBusOff(void); +# 448 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorPassive(void); +# 507 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorWarning(void); +# 566 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorActive(void); +# 614 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorPassive(void); +# 662 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorWarning(void); +# 710 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorActive(void); +# 761 "mcc_generated_files/can1.h" +void CAN1_Sleep(void); +# 815 "mcc_generated_files/can1.h" +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +# 857 "mcc_generated_files/can1.h" +uint8_t CAN1_ReceivedMessageCountGet(void); +# 924 "mcc_generated_files/can1.h" +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +# 981 "mcc_generated_files/can1.h" +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +# 1049 "mcc_generated_files/can1.h" +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +# 1100 "mcc_generated_files/can1.h" +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +# 1169 "mcc_generated_files/can1.h" +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +# 1237 "mcc_generated_files/can1.h" +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +# 1289 "mcc_generated_files/can1.h" +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +# 1324 "mcc_generated_files/can1.h" +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +# 1368 "mcc_generated_files/can1.h" +void CAN1_SetTXQnullHandler(void (*handler)(void)); + + +void CAN1_ISR(void); +void CAN1_RXI_ISR(void); +# 60 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 37 "mcc_generated_files/drivers/i2c_simple_master.h" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 61 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pwm2_16bit.h" 1 +# 63 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 62 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/DAC3.h" 1 +# 29 "mcc_generated_files/DAC3.h" +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 63 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pwm1_16bit.h" 1 +# 63 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 64 "mcc_generated_files/mcc.h" 2 +# 79 "mcc_generated_files/mcc.h" +void SYSTEM_Initialize(void); +# 92 "mcc_generated_files/mcc.h" +void OSCILLATOR_Initialize(void); +# 105 "mcc_generated_files/mcc.h" +void PMD_Initialize(void); +# 50 "mcc_generated_files/interrupt_manager.c" 2 + + +void INTERRUPT_Initialize (void) +{ + + INTCON0bits.IPEN = 0; +} + +void __attribute__((picinterrupt(("")))) INTERRUPT_InterruptManager (void) +{ + + if(PIE3bits.TMR0IE == 1 && PIR3bits.TMR0IF == 1) + { + TMR0_ISR(); + } + else if(PIE3bits.TMR1IE == 1 && PIR3bits.TMR1IF == 1) + { + TMR1_ISR(); + } + else if(PIE0bits.CANIE == 1 && PIR0bits.CANIF == 1) + { + CAN1_ISR(); + } + else if(PIE4bits.CANRXIE == 1 && PIR4bits.CANRXIF == 1) + { + CAN1_RXI_ISR(); + } + else + { + + } +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.p1 b/ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.p1 new file mode 100644 index 0000000..236fac0 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.p1 @@ -0,0 +1,3701 @@ +Version 4.0 HI-TECH Software Intermediate Code +"2080 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[s S3083 :1 `uc 1 :1 `uc 1 :1 `uc 1 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3083 . INT0EDG INT1EDG INT2EDG . IPEN GIEL GIE ] +"2089 +[s S3084 :7 `uc 1 :1 `uc 1 ] +[n S3084 . . GIEH ] +"2079 +[u S3082 `S3083 1 `S3084 1 ] +[n S3082 . . . ] +"2094 +[v _INTCON0bits `VS3082 ~T0 @X0 0 e@1238 ] +[t ~ __interrupt . k ] +[t T1 __interrupt ] +"65240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65240: struct { +[s S3002 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3002 . SPI1RXIE SPI1TXIE SPI1IE TMR2IE TMR1IE TMR1GIE CCP1IE TMR0IE ] +"65239 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65239: typedef union { +[u S3001 `S3002 1 ] +[n S3001 . . ] +"65251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65251: extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +[v _PIE3bits `VS3001 ~T0 @X0 0 e@1185 ] +"689 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 689: }; +[s S3035 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3035 . SPI1RXIF SPI1TXIF SPI1IF TMR2IF TMR1IF TMR1GIF CCP1IF TMR0IF ] +"688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 688: unsigned NVMADRL :8; +[u S3034 `S3035 1 ] +[n S3034 . . ] +"700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 700: } NVMADRLbits_t; +[v _PIR3bits `VS3034 ~T0 @X0 0 e@1201 ] +"297 mcc_generated_files/tmr0.h +[; ;mcc_generated_files/tmr0.h: 297: void TMR0_ISR(void); +[v _TMR0_ISR `(v ~T0 @X0 0 ef ] +"368 mcc_generated_files/tmr1.h +[; ;mcc_generated_files/tmr1.h: 368: void TMR1_ISR(void); +[v _TMR1_ISR `(v ~T0 @X0 0 ef ] +"65046 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65046: struct { +[s S2995 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S2995 . SWIE HLVDIE OSFIE CSWIE TU16AIE CLC1IE CANIE IOCIE ] +"65045 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65045: typedef union { +[u S2994 `S2995 1 ] +[n S2994 . . ] +"65057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65057: extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +[v _PIE0bits `VS2994 ~T0 @X0 0 e@1182 ] +"495 +[s S3028 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3028 . SWIF HLVDIF OSFIF CSWIF TU16AIF CLC1IF CANIF IOCIF ] +"494 +[u S3027 `S3028 1 ] +[n S3027 . . ] +"506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 506: struct { +[v _PIR0bits `VS3027 ~T0 @X0 0 e@1198 ] +"1371 mcc_generated_files/can1.h +[; ;mcc_generated_files/can1.h: 1371: void CAN1_ISR(void); +[v _CAN1_ISR `(v ~T0 @X0 0 ef ] +"65302 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65302: struct { +[s S3004 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3004 . U1RXIE U1TXIE U1EIE U1IE CANRXIE CANTXIE PWM1PIE PWM1IE ] +"65301 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65301: typedef union { +[u S3003 `S3004 1 ] +[n S3003 . . ] +"65313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65313: extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +[v _PIE4bits `VS3003 ~T0 @X0 0 e@1186 ] +"751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 751: extern volatile unsigned char NVMADRH __attribute__((address(0x044))); +[s S3037 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3037 . U1RXIF U1TXIF U1EIF U1IF CANRXIF CANTXIF PWM1PIF PWM1IF ] +"750 +[u S3036 `S3037 1 ] +[n S3036 . . ] +"762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 762: unsigned NVMADR9 :1; +[v _PIR4bits `VS3036 ~T0 @X0 0 e@1202 ] +"1372 mcc_generated_files/can1.h +[; ;mcc_generated_files/can1.h: 1372: void CAN1_RXI_ISR(void); +[v _CAN1_RXI_ISR `(v ~T0 @X0 0 ef ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"52 mcc_generated_files/interrupt_manager.c +[; ;mcc_generated_files/interrupt_manager.c: 52: void INTERRUPT_Initialize (void) +[v _INTERRUPT_Initialize `(v ~T0 @X0 1 ef ] +"53 +[; ;mcc_generated_files/interrupt_manager.c: 53: { +{ +[e :U _INTERRUPT_Initialize ] +[f ] +"55 +[; ;mcc_generated_files/interrupt_manager.c: 55: INTCON0bits.IPEN = 0; +[e = . . _INTCON0bits 0 4 -> -> 0 `i `uc ] +"56 +[; ;mcc_generated_files/interrupt_manager.c: 56: } +[e :UE 3181 ] +} +[v $root$_INTERRUPT_InterruptManager `(v ~T0 @X0 0 e ] +"58 +[; ;mcc_generated_files/interrupt_manager.c: 58: void __attribute__((picinterrupt(("")))) INTERRUPT_InterruptManager (void) +[v _INTERRUPT_InterruptManager `(v ~T1 @X0 1 ef ] +"59 +[; ;mcc_generated_files/interrupt_manager.c: 59: { +{ +[e :U _INTERRUPT_InterruptManager ] +[f ] +"61 +[; ;mcc_generated_files/interrupt_manager.c: 61: if(PIE3bits.TMR0IE == 1 && PIR3bits.TMR0IF == 1) +[e $ ! && == -> . . _PIE3bits 0 7 `i -> 1 `i == -> . . _PIR3bits 0 7 `i -> 1 `i 3183 ] +"62 +[; ;mcc_generated_files/interrupt_manager.c: 62: { +{ +"63 +[; ;mcc_generated_files/interrupt_manager.c: 63: TMR0_ISR(); +[e ( _TMR0_ISR .. ] +"64 +[; ;mcc_generated_files/interrupt_manager.c: 64: } +} +[e $U 3184 ] +"65 +[; ;mcc_generated_files/interrupt_manager.c: 65: else if(PIE3bits.TMR1IE == 1 && PIR3bits.TMR1IF == 1) +[e :U 3183 ] +[e $ ! && == -> . . _PIE3bits 0 4 `i -> 1 `i == -> . . _PIR3bits 0 4 `i -> 1 `i 3185 ] +"66 +[; ;mcc_generated_files/interrupt_manager.c: 66: { +{ +"67 +[; ;mcc_generated_files/interrupt_manager.c: 67: TMR1_ISR(); +[e ( _TMR1_ISR .. ] +"68 +[; ;mcc_generated_files/interrupt_manager.c: 68: } +} +[e $U 3186 ] +"69 +[; ;mcc_generated_files/interrupt_manager.c: 69: else if(PIE0bits.CANIE == 1 && PIR0bits.CANIF == 1) +[e :U 3185 ] +[e $ ! && == -> . . _PIE0bits 0 6 `i -> 1 `i == -> . . _PIR0bits 0 6 `i -> 1 `i 3187 ] +"70 +[; ;mcc_generated_files/interrupt_manager.c: 70: { +{ +"71 +[; ;mcc_generated_files/interrupt_manager.c: 71: CAN1_ISR(); +[e ( _CAN1_ISR .. ] +"72 +[; ;mcc_generated_files/interrupt_manager.c: 72: } +} +[e $U 3188 ] +"73 +[; ;mcc_generated_files/interrupt_manager.c: 73: else if(PIE4bits.CANRXIE == 1 && PIR4bits.CANRXIF == 1) +[e :U 3187 ] +[e $ ! && == -> . . _PIE4bits 0 4 `i -> 1 `i == -> . . _PIR4bits 0 4 `i -> 1 `i 3189 ] +"74 +[; ;mcc_generated_files/interrupt_manager.c: 74: { +{ +"75 +[; ;mcc_generated_files/interrupt_manager.c: 75: CAN1_RXI_ISR(); +[e ( _CAN1_RXI_ISR .. ] +"76 +[; ;mcc_generated_files/interrupt_manager.c: 76: } +} +[e $U 3190 ] +"77 +[; ;mcc_generated_files/interrupt_manager.c: 77: else +[e :U 3189 ] +"78 +[; ;mcc_generated_files/interrupt_manager.c: 78: { +{ +"80 +[; ;mcc_generated_files/interrupt_manager.c: 80: } +} +[e :U 3190 ] +[e :U 3188 ] +[e :U 3186 ] +[e :U 3184 ] +"81 +[; ;mcc_generated_files/interrupt_manager.c: 81: } +[e :UE 3182 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.p1.d b/ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.p1.d new file mode 100644 index 0000000..2892df3 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/interrupt_manager.p1.d @@ -0,0 +1,16 @@ +build/default/debug/mcc_generated_files/interrupt_manager.p1: \ +mcc_generated_files/interrupt_manager.c \ +mcc_generated_files/interrupt_manager.h \ +mcc_generated_files/mcc.h \ +mcc_generated_files/device_config.h \ +mcc_generated_files/pin_manager.h \ +mcc_generated_files/i2c1_master.h \ +mcc_generated_files/adc.h \ +mcc_generated_files/tmr1.h \ +mcc_generated_files/tmr0.h \ +mcc_generated_files/can1.h \ +mcc_generated_files/can_types.h \ +mcc_generated_files/drivers/i2c_simple_master.h \ +mcc_generated_files/pwm2_16bit.h \ +mcc_generated_files/DAC3.h \ +mcc_generated_files/pwm1_16bit.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/mcc.i b/ETC.X/build/default/debug/mcc_generated_files/mcc.i new file mode 100644 index 0000000..bc53e3e --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/mcc.i @@ -0,0 +1,38308 @@ +# 1 "mcc_generated_files/mcc.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/mcc.c" 2 +# 47 "mcc_generated_files/mcc.c" +# 1 "mcc_generated_files/mcc.h" 1 +# 49 "mcc_generated_files/mcc.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 49 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/device_config.h" 1 +# 50 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pin_manager.h" 1 +# 402 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 51 "mcc_generated_files/mcc.h" 2 + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 53 "mcc_generated_files/mcc.h" 2 + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 1 3 + + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 1 3 +# 12 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\errno.h" 3 +extern int errno; +# 8 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__null.h" 1 3 +# 9 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\conio.h" 2 3 + + + +extern void init_uart(void); + +extern char getch(void); +extern char getche(void); +extern void putch(char); +extern void ungetch(char); + +extern __bit kbhit(void); + + + +extern char * cgets(char *); +extern void cputs(const char *); +# 54 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/interrupt_manager.h" 1 +# 87 "mcc_generated_files/interrupt_manager.h" +void INTERRUPT_Initialize (void); +# 55 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/i2c1_master.h" 1 +# 54 "mcc_generated_files/i2c1_master.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 1 3 +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 + + + + + +typedef void * va_list[1]; + + + + +typedef void * __isoc_va_list[1]; +# 137 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long ssize_t; +# 246 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long off_t; +# 399 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef struct _IO_FILE FILE; +# 24 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 2 3 +# 52 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdio.h" 3 +typedef union _G_fpos64_t { + char __opaque[16]; + double __align; +} fpos_t; + +extern FILE *const stdin; +extern FILE *const stdout; +extern FILE *const stderr; + + + + + +FILE *fopen(const char *restrict, const char *restrict); +FILE *freopen(const char *restrict, const char *restrict, FILE *restrict); +int fclose(FILE *); + +int remove(const char *); +int rename(const char *, const char *); + +int feof(FILE *); +int ferror(FILE *); +int fflush(FILE *); +void clearerr(FILE *); + +int fseek(FILE *, long, int); +long ftell(FILE *); +void rewind(FILE *); + +int fgetpos(FILE *restrict, fpos_t *restrict); +int fsetpos(FILE *, const fpos_t *); + +size_t fread(void *restrict, size_t, size_t, FILE *restrict); +size_t fwrite(const void *restrict, size_t, size_t, FILE *restrict); + +int fgetc(FILE *); +int getc(FILE *); +int getchar(void); +int ungetc(int, FILE *); + +int fputc(int, FILE *); +int putc(int, FILE *); +int putchar(int); + +char *fgets(char *restrict, int, FILE *restrict); + +char *gets(char *); + + +int fputs(const char *restrict, FILE *restrict); +int puts(const char *); + +#pragma printf_check(printf) const +#pragma printf_check(vprintf) const +#pragma printf_check(sprintf) const +#pragma printf_check(snprintf) const +#pragma printf_check(vsprintf) const +#pragma printf_check(vsnprintf) const + +int printf(const char *restrict, ...); +int fprintf(FILE *restrict, const char *restrict, ...); +int sprintf(char *restrict, const char *restrict, ...); +int snprintf(char *restrict, size_t, const char *restrict, ...); + +int vprintf(const char *restrict, __isoc_va_list); +int vfprintf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsprintf(char *restrict, const char *restrict, __isoc_va_list); +int vsnprintf(char *restrict, size_t, const char *restrict, __isoc_va_list); + +int scanf(const char *restrict, ...); +int fscanf(FILE *restrict, const char *restrict, ...); +int sscanf(const char *restrict, const char *restrict, ...); +int vscanf(const char *restrict, __isoc_va_list); +int vfscanf(FILE *restrict, const char *restrict, __isoc_va_list); +int vsscanf(const char *restrict, const char *restrict, __isoc_va_list); + +void perror(const char *); + +int setvbuf(FILE *restrict, char *restrict, int, size_t); +void setbuf(FILE *restrict, char *restrict); + +char *tmpnam(char *); +FILE *tmpfile(void); + + + + +FILE *fmemopen(void *restrict, size_t, const char *restrict); +FILE *open_memstream(char **, size_t *); +FILE *fdopen(int, const char *); +FILE *popen(const char *, const char *); +int pclose(FILE *); +int fileno(FILE *); +int fseeko(FILE *, off_t, int); +off_t ftello(FILE *); +int dprintf(int, const char *restrict, ...); +int vdprintf(int, const char *restrict, __isoc_va_list); +void flockfile(FILE *); +int ftrylockfile(FILE *); +void funlockfile(FILE *); +int getc_unlocked(FILE *); +int getchar_unlocked(void); +int putc_unlocked(int, FILE *); +int putchar_unlocked(int); +ssize_t getdelim(char **restrict, size_t *restrict, int, FILE *restrict); +ssize_t getline(char **restrict, size_t *restrict, FILE *restrict); +int renameat(int, const char *, int, const char *); +char *ctermid(char *); + + + + + + + +char *tempnam(const char *, const char *); +# 54 "mcc_generated_files/i2c1_master.h" 2 + + + + +typedef enum { + I2C1_NOERR, + I2C1_BUSY, + I2C1_FAIL + + +} i2c1_error_t; + +typedef enum +{ + I2C1_STOP=1, + I2C1_RESTART_READ, + I2C1_RESTART_WRITE, + I2C1_CONTINUE, + I2C1_RESET_LINK +} i2c1_operations_t; + +typedef uint8_t i2c1_address_t; +typedef i2c1_operations_t (*i2c1_callback_t)(void *funPtr); + + +i2c1_operations_t I2C1_CallbackReturnStop(void *funPtr); +i2c1_operations_t I2C1_CallbackReturnReset(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartWrite(void *funPtr); +i2c1_operations_t I2C1_CallbackRestartRead(void *funPtr); + + + + + + +void I2C1_Initialize(void); +# 101 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Open(i2c1_address_t address); +# 111 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_Close(void); +# 123 "mcc_generated_files/i2c1_master.h" +i2c1_error_t I2C1_MasterOperation(_Bool read); + + + + +i2c1_error_t I2C1_MasterWrite(void); + + + + +i2c1_error_t I2C1_MasterRead(void); +# 142 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeout(uint8_t timeOut); +# 152 "mcc_generated_files/i2c1_master.h" +void I2C1_SetBuffer(void *buffer, size_t bufferSize); +# 164 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataCompleteCallback(i2c1_callback_t cb, void *ptr); +# 174 "mcc_generated_files/i2c1_master.h" +void I2C1_SetWriteCollisionCallback(i2c1_callback_t cb, void *ptr); +# 184 "mcc_generated_files/i2c1_master.h" +void I2C1_SetAddressNackCallback(i2c1_callback_t cb, void *ptr); +# 194 "mcc_generated_files/i2c1_master.h" +void I2C1_SetDataNackCallback(i2c1_callback_t cb, void *ptr); +# 204 "mcc_generated_files/i2c1_master.h" +void I2C1_SetTimeoutCallback(i2c1_callback_t cb, void *ptr); +# 56 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/adc.h" 1 +# 65 "mcc_generated_files/adc.h" +typedef uint16_t adc_result_t; + + + + + + +typedef enum +{ + TPS2 = 0x4, + TPS1 = 0x10, + APPS2 = 0x11, + APPS1 = 0x12, + channel_VSS = 0x3B, + channel_Temp = 0x3C, + channel_DAC1 = 0x3D, + channel_FVR_Buffer1 = 0x3E, + channel_FVR_Buffer2 = 0x3F +} ADC_channel_t; + + + + + + +typedef enum +{ + CONTEXT_TPS1, + CONTEXT_TPS2, + CONTEXT_APPS1, + CONTEXT_APPS2, +} ADC_context_t; +# 119 "mcc_generated_files/adc.h" +void ADC_Initialize(void); +# 150 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChannelSequencer(void); +# 172 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChannelSequencer(void); +# 204 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StartChannelSequencer(void); +# 227 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SelectContext(ADC_context_t context); +# 249 "mcc_generated_files/adc.h" +void ADC_EnableChannelScan(ADC_context_t context); +# 273 "mcc_generated_files/adc.h" +void ADC_DisableChannelScan(ADC_context_t context); +# 300 "mcc_generated_files/adc.h" +void ADC_StartConversion(ADC_channel_t channel); +# 326 "mcc_generated_files/adc.h" +_Bool ADC_IsConversionDone(void); +# 352 "mcc_generated_files/adc.h" +adc_result_t ADC_GetConversionResult(void); +# 378 "mcc_generated_files/adc.h" +adc_result_t ADC_GetSingleConversion(ADC_channel_t channel); +# 403 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_StopConversion(void); +# 427 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetStopOnInterrupt(void); +# 455 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DischargeSampleCapacitor(void); +# 479 "mcc_generated_files/adc.h" +void ADC_LoadAcquisitionRegister(uint16_t acquisitionValue); +# 503 "mcc_generated_files/adc.h" +void ADC_SetPrechargeTime(uint16_t prechargeTime); +# 527 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_SetRepeatCount(uint8_t repeatCount); +# 551 "mcc_generated_files/adc.h" +uint8_t ADC_GetCurrentCountofConversions(void); +# 574 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_ClearAccumulator(void); +# 598 "mcc_generated_files/adc.h" +uint24_t ADC_GetAccumulatorValue(void); +# 625 "mcc_generated_files/adc.h" +_Bool ADC_HasAccumulatorOverflowed(void); +# 649 "mcc_generated_files/adc.h" +uint16_t ADC_GetFilterValue(void); +# 673 "mcc_generated_files/adc.h" +uint16_t ADC_GetPreviousResult(void); +# 697 "mcc_generated_files/adc.h" +void ADC_DefineSetPoint(uint16_t setPoint); +# 721 "mcc_generated_files/adc.h" +void ADC_SetUpperThreshold(uint16_t upperThreshold); +# 745 "mcc_generated_files/adc.h" +void ADC_SetLowerThreshold(uint16_t lowerThreshold); +# 770 "mcc_generated_files/adc.h" +uint16_t ADC_GetErrorCalculation(void); +# 794 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableDoubleSampling(void); +# 818 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableContinuousConversion(void); +# 842 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableContinuousConversion(void); +# 869 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedUpperThreshold(void); +# 896 "mcc_generated_files/adc.h" +_Bool ADC_HasErrorCrossedLowerThreshold(void); +# 921 "mcc_generated_files/adc.h" +uint8_t ADC_GetConversionStageStatus(void); +# 942 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_EnableChargePump(void); +# 963 "mcc_generated_files/adc.h" +__attribute__((inline)) void ADC_DisableChargePump(void); + + + + + + + +void ADC_ADI_ISR(void); +# 999 "mcc_generated_files/adc.h" +void ADC_SetADIInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ACTI_ISR(void); +# 1035 "mcc_generated_files/adc.h" +void ADC_SetActiveClockTuningInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH1_ISR(void); +# 1071 "mcc_generated_files/adc.h" +void ADC_SetContext1ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH2_ISR(void); +# 1107 "mcc_generated_files/adc.h" +void ADC_SetContext2ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH3_ISR(void); +# 1143 "mcc_generated_files/adc.h" +void ADC_SetContext3ThresholdInterruptHandler(void (* InterruptHandler)(void)); + + + + + + + +void ADC_ADCH4_ISR(void); +# 1179 "mcc_generated_files/adc.h" +void ADC_SetContext4ThresholdInterruptHandler(void (* InterruptHandler)(void)); +# 57 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/tmr1.h" 1 +# 101 "mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 58 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/tmr0.h" 1 +# 106 "mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 59 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/can1.h" 1 +# 56 "mcc_generated_files/can1.h" +# 1 "mcc_generated_files/can_types.h" 1 +# 65 "mcc_generated_files/can_types.h" +typedef union +{ + uint8_t msgfields; + struct + { + uint8_t idType:1; + uint8_t frameType:1; + uint8_t dlc:4; + uint8_t formatType:1; + uint8_t brs:1; + }; +} CAN_MSG_FIELD; + +typedef struct +{ + uint32_t msgId; + CAN_MSG_FIELD field; + uint8_t *data; +} CAN_MSG_OBJ; +# 94 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NON_BRS_MODE = 0, + CAN_BRS_MODE = 1 +} CAN_MSG_OBJ_BRS_MODE; +# 109 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_STD = 0, + CAN_FRAME_EXT = 1, +} CAN_MSG_OBJ_ID_TYPE; +# 124 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_FRAME_DATA = 0, + CAN_FRAME_RTR = 1, +} CAN_MSG_OBJ_FRAME_TYPE; +# 139 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_2_0_FORMAT = 0, + CAN_FD_FORMAT = 1 +} CAN_MSG_OBJ_TYPE; +# 154 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_MSG_REQUEST_SUCCESS = 0, + CAN_TX_MSG_REQUEST_DLC_EXCEED_ERROR = 1, + CAN_TX_MSG_REQUEST_BRS_ERROR = 2, + CAN_TX_MSG_REQUEST_FIFO_FULL = 3, +} CAN_TX_MSG_REQUEST_STATUS; +# 171 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_NORMAL_FD_MODE = 0, + CAN_DISABLE_MODE = 1, + CAN_INTERNAL_LOOPBACK_MODE = 2, + CAN_LISTEN_ONLY_MODE = 3, + CAN_CONFIGURATION_MODE = 4, + CAN_EXTERNAL_LOOPBACK_MODE = 5, + CAN_NORMAL_2_0_MODE = 6, + CAN_RESTRICTED_OPERATION_MODE =7, +} CAN_OP_MODES; +# 192 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_OP_MODE_REQUEST_SUCCESS, + CAN_OP_MODE_REQUEST_FAIL, + CAN_OP_MODE_SYS_ERROR_OCCURED +} CAN_OP_MODE_STATUS; +# 208 "mcc_generated_files/can_types.h" +typedef enum +{ + CAN_TX_FIFO_FULL, + CAN_TX_FIFO_AVAILABLE, +} CAN_TX_FIFO_STATUS; +# 223 "mcc_generated_files/can_types.h" +typedef enum +{ + + DLC_0, + DLC_1, + DLC_2, + DLC_3, + DLC_4, + DLC_5, + DLC_6, + DLC_7, + DLC_8, + + + + DLC_12, + DLC_16, + DLC_20, + DLC_24, + DLC_32, + DLC_48, + DLC_64, +} CAN_DLC; +# 56 "mcc_generated_files/can1.h" 2 + + + + + +typedef enum +{ + TXQ = 0 +} CAN1_TX_FIFO_CHANNELS; + +typedef enum +{ + FIFO1 = 1 +} CAN1_RX_FIFO_CHANNELS; +# 106 "mcc_generated_files/can1.h" +void CAN1_Initialize(void); +# 147 "mcc_generated_files/can1.h" +CAN_OP_MODE_STATUS CAN1_OperationModeSet(const CAN_OP_MODES reqestMode); +# 185 "mcc_generated_files/can1.h" +CAN_OP_MODES CAN1_OperationModeGet(void); +# 235 "mcc_generated_files/can1.h" +_Bool CAN1_Receive(CAN_MSG_OBJ *rxCanMsg); +# 275 "mcc_generated_files/can1.h" +_Bool CAN1_ReceiveFrom(const CAN1_RX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *rxCanMsg); +# 334 "mcc_generated_files/can1.h" +CAN_TX_MSG_REQUEST_STATUS CAN1_Transmit(const CAN1_TX_FIFO_CHANNELS fifoChannel, CAN_MSG_OBJ *txCanMsg); +# 390 "mcc_generated_files/can1.h" +_Bool CAN1_IsBusOff(void); +# 448 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorPassive(void); +# 507 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorWarning(void); +# 566 "mcc_generated_files/can1.h" +_Bool CAN1_IsTxErrorActive(void); +# 614 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorPassive(void); +# 662 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorWarning(void); +# 710 "mcc_generated_files/can1.h" +_Bool CAN1_IsRxErrorActive(void); +# 761 "mcc_generated_files/can1.h" +void CAN1_Sleep(void); +# 815 "mcc_generated_files/can1.h" +CAN_TX_FIFO_STATUS CAN1_TransmitFIFOStatusGet(const CAN1_TX_FIFO_CHANNELS fifoChannel); +# 857 "mcc_generated_files/can1.h" +uint8_t CAN1_ReceivedMessageCountGet(void); +# 924 "mcc_generated_files/can1.h" +void CAN1_SetInvalidMessageInterruptHandler(void (*handler)(void)); +# 981 "mcc_generated_files/can1.h" +void CAN1_SetBusWakeUpActivityInterruptHandler(void (*handler)(void)); +# 1049 "mcc_generated_files/can1.h" +void CAN1_SetBusErrorInterruptHandler(void (*handler)(void)); +# 1100 "mcc_generated_files/can1.h" +void CAN1_SetModeChangeInterruptHandler(void (*handler)(void)); +# 1169 "mcc_generated_files/can1.h" +void CAN1_SetSystemErrorInterruptHandler(void (*handler)(void)); +# 1237 "mcc_generated_files/can1.h" +void CAN1_SetTxAttemptInterruptHandler(void (*handler)(void)); +# 1289 "mcc_generated_files/can1.h" +void CAN1_SetRxBufferOverFlowInterruptHandler(void (*handler)(void)); +# 1324 "mcc_generated_files/can1.h" +void CAN1_SetFIFO1NotEmptyHandler(void (*handler)(void)); +# 1368 "mcc_generated_files/can1.h" +void CAN1_SetTXQnullHandler(void (*handler)(void)); + + +void CAN1_ISR(void); +void CAN1_RXI_ISR(void); +# 60 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/drivers/i2c_simple_master.h" 1 +# 37 "mcc_generated_files/drivers/i2c_simple_master.h" +uint8_t i2c_read1ByteRegister(i2c1_address_t address, uint8_t reg); +uint16_t i2c_read2ByteRegister(i2c1_address_t address, uint8_t reg); +void i2c_write1ByteRegister(i2c1_address_t address, uint8_t reg, uint8_t data); +void i2c_write2ByteRegister(i2c1_address_t address, uint8_t reg, uint16_t data); + +void i2c_writeNBytes(i2c1_address_t address, void* data, size_t len); +void i2c_readDataBlock(i2c1_address_t address, uint8_t reg, void *data, size_t len); +void i2c_readNBytes(i2c1_address_t address, void *data, size_t len); +# 61 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pwm2_16bit.h" 1 +# 63 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 62 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/DAC3.h" 1 +# 29 "mcc_generated_files/DAC3.h" +void DAC3_SetNonvolatile(uint16_t dacValue); + + +void DAC3_Set(uint16_t dacValue); + +uint16_t DAC3_Read(uint16_t *dacNonvolatile); +# 63 "mcc_generated_files/mcc.h" 2 + +# 1 "mcc_generated_files/pwm1_16bit.h" 1 +# 63 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 64 "mcc_generated_files/mcc.h" 2 +# 79 "mcc_generated_files/mcc.h" +void SYSTEM_Initialize(void); +# 92 "mcc_generated_files/mcc.h" +void OSCILLATOR_Initialize(void); +# 105 "mcc_generated_files/mcc.h" +void PMD_Initialize(void); +# 47 "mcc_generated_files/mcc.c" 2 + + + +void SYSTEM_Initialize(void) +{ + INTERRUPT_Initialize(); + PMD_Initialize(); + I2C1_Initialize(); + ADC_Initialize(); + PIN_MANAGER_Initialize(); + OSCILLATOR_Initialize(); + TMR1_Initialize(); + TMR0_Initialize(); + PWM2_16BIT_Initialize(); + CAN1_Initialize(); + PWM1_16BIT_Initialize(); +} + +void OSCILLATOR_Initialize(void) +{ + + OSCCON1 = 0x70; + + OSCCON3 = 0x00; + + OSCEN = 0x00; + + OSCFRQ = 0x02; + + OSCTUNE = 0x00; +} + +void PMD_Initialize(void) +{ + + PMD0 = 0x00; + + PMD1 = 0x00; + + PMD2 = 0x00; + + PMD3 = 0x00; + + PMD4 = 0x00; + + PMD5 = 0x00; + + PMD6 = 0x00; + + PMD7 = 0x00; + + PMD8 = 0x00; +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/mcc.p1 b/ETC.X/build/default/debug/mcc_generated_files/mcc.p1 new file mode 100644 index 0000000..733374a --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/mcc.p1 @@ -0,0 +1,3702 @@ +Version 4.0 HI-TECH Software Intermediate Code +"87 mcc_generated_files/interrupt_manager.h +[; ;mcc_generated_files/interrupt_manager.h: 87: void INTERRUPT_Initialize (void); +[v _INTERRUPT_Initialize `(v ~T0 @X0 0 ef ] +"105 mcc_generated_files/mcc.h +[; ;mcc_generated_files/mcc.h: 105: void PMD_Initialize(void); +[v _PMD_Initialize `(v ~T0 @X0 0 ef ] +"89 mcc_generated_files/drivers/.././i2c1_master.h +[v _I2C1_Initialize `(v ~T0 @X0 0 ef ] +"119 mcc_generated_files/adc.h +[; ;mcc_generated_files/adc.h: 119: void ADC_Initialize(void); +[v _ADC_Initialize `(v ~T0 @X0 0 ef ] +"402 mcc_generated_files/pin_manager.h +[; ;mcc_generated_files/pin_manager.h: 402: void PIN_MANAGER_Initialize (void); +[v _PIN_MANAGER_Initialize `(v ~T0 @X0 0 ef ] +"92 mcc_generated_files/mcc.h +[; ;mcc_generated_files/mcc.h: 92: void OSCILLATOR_Initialize(void); +[v _OSCILLATOR_Initialize `(v ~T0 @X0 0 ef ] +"101 mcc_generated_files/tmr1.h +[; ;mcc_generated_files/tmr1.h: 101: void TMR1_Initialize(void); +[v _TMR1_Initialize `(v ~T0 @X0 0 ef ] +"106 mcc_generated_files/tmr0.h +[; ;mcc_generated_files/tmr0.h: 106: void TMR0_Initialize(void); +[v _TMR0_Initialize `(v ~T0 @X0 0 ef ] +"63 mcc_generated_files/pwm2_16bit.h +[; ;mcc_generated_files/pwm2_16bit.h: 63: void PWM2_16BIT_Initialize(void); +[v _PWM2_16BIT_Initialize `(v ~T0 @X0 0 ef ] +"106 mcc_generated_files/can1.h +[; ;mcc_generated_files/can1.h: 106: void CAN1_Initialize(void); +[v _CAN1_Initialize `(v ~T0 @X0 0 ef ] +"63 mcc_generated_files/pwm1_16bit.h +[; ;mcc_generated_files/pwm1_16bit.h: 63: void PWM1_16BIT_Initialize(void); +[v _PWM1_16BIT_Initialize `(v ~T0 @X0 0 ef ] +"5336 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5336: extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); +[v _OSCCON1 `Vuc ~T0 @X0 0 e@173 ] +"5476 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5476: extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); +[v _OSCCON3 `Vuc ~T0 @X0 0 e@175 ] +"5776 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5776: extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); +[v _OSCEN `Vuc ~T0 @X0 0 e@179 ] +"5574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5574: extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); +[v _OSCFRQ `Vuc ~T0 @X0 0 e@177 ] +"5516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5516: extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); +[v _OSCTUNE `Vuc ~T0 @X0 0 e@176 ] +"1339 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1339: extern volatile unsigned char PMD0 __attribute__((address(0x060))); +[v _PMD0 `Vuc ~T0 @X0 0 e@96 ] +"1405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1405: extern volatile unsigned char PMD1 __attribute__((address(0x061))); +[v _PMD1 `Vuc ~T0 @X0 0 e@97 ] +"1467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1467: extern volatile unsigned char PMD2 __attribute__((address(0x062))); +[v _PMD2 `Vuc ~T0 @X0 0 e@98 ] +"1514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1514: extern volatile unsigned char PMD3 __attribute__((address(0x063))); +[v _PMD3 `Vuc ~T0 @X0 0 e@99 ] +"1565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1565: extern volatile unsigned char PMD4 __attribute__((address(0x064))); +[v _PMD4 `Vuc ~T0 @X0 0 e@100 ] +"1621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1621: extern volatile unsigned char PMD5 __attribute__((address(0x065))); +[v _PMD5 `Vuc ~T0 @X0 0 e@101 ] +"1678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1678: extern volatile unsigned char PMD6 __attribute__((address(0x066))); +[v _PMD6 `Vuc ~T0 @X0 0 e@102 ] +"1740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1740: extern volatile unsigned char PMD7 __attribute__((address(0x067))); +[v _PMD7 `Vuc ~T0 @X0 0 e@103 ] +"1802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1802: extern volatile unsigned char PMD8 __attribute__((address(0x068))); +[v _PMD8 `Vuc ~T0 @X0 0 e@104 ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"50 mcc_generated_files/mcc.c +[; ;mcc_generated_files/mcc.c: 50: void SYSTEM_Initialize(void) +[v _SYSTEM_Initialize `(v ~T0 @X0 1 ef ] +"51 +[; ;mcc_generated_files/mcc.c: 51: { +{ +[e :U _SYSTEM_Initialize ] +[f ] +"52 +[; ;mcc_generated_files/mcc.c: 52: INTERRUPT_Initialize(); +[e ( _INTERRUPT_Initialize .. ] +"53 +[; ;mcc_generated_files/mcc.c: 53: PMD_Initialize(); +[e ( _PMD_Initialize .. ] +"54 +[; ;mcc_generated_files/mcc.c: 54: I2C1_Initialize(); +[e ( _I2C1_Initialize .. ] +"55 +[; ;mcc_generated_files/mcc.c: 55: ADC_Initialize(); +[e ( _ADC_Initialize .. ] +"56 +[; ;mcc_generated_files/mcc.c: 56: PIN_MANAGER_Initialize(); +[e ( _PIN_MANAGER_Initialize .. ] +"57 +[; ;mcc_generated_files/mcc.c: 57: OSCILLATOR_Initialize(); +[e ( _OSCILLATOR_Initialize .. ] +"58 +[; ;mcc_generated_files/mcc.c: 58: TMR1_Initialize(); +[e ( _TMR1_Initialize .. ] +"59 +[; ;mcc_generated_files/mcc.c: 59: TMR0_Initialize(); +[e ( _TMR0_Initialize .. ] +"60 +[; ;mcc_generated_files/mcc.c: 60: PWM2_16BIT_Initialize(); +[e ( _PWM2_16BIT_Initialize .. ] +"61 +[; ;mcc_generated_files/mcc.c: 61: CAN1_Initialize(); +[e ( _CAN1_Initialize .. ] +"62 +[; ;mcc_generated_files/mcc.c: 62: PWM1_16BIT_Initialize(); +[e ( _PWM1_16BIT_Initialize .. ] +"63 +[; ;mcc_generated_files/mcc.c: 63: } +[e :UE 3181 ] +} +"65 +[; ;mcc_generated_files/mcc.c: 65: void OSCILLATOR_Initialize(void) +[v _OSCILLATOR_Initialize `(v ~T0 @X0 1 ef ] +"66 +[; ;mcc_generated_files/mcc.c: 66: { +{ +[e :U _OSCILLATOR_Initialize ] +[f ] +"68 +[; ;mcc_generated_files/mcc.c: 68: OSCCON1 = 0x70; +[e = _OSCCON1 -> -> 112 `i `uc ] +"70 +[; ;mcc_generated_files/mcc.c: 70: OSCCON3 = 0x00; +[e = _OSCCON3 -> -> 0 `i `uc ] +"72 +[; ;mcc_generated_files/mcc.c: 72: OSCEN = 0x00; +[e = _OSCEN -> -> 0 `i `uc ] +"74 +[; ;mcc_generated_files/mcc.c: 74: OSCFRQ = 0x02; +[e = _OSCFRQ -> -> 2 `i `uc ] +"76 +[; ;mcc_generated_files/mcc.c: 76: OSCTUNE = 0x00; +[e = _OSCTUNE -> -> 0 `i `uc ] +"77 +[; ;mcc_generated_files/mcc.c: 77: } +[e :UE 3182 ] +} +"79 +[; ;mcc_generated_files/mcc.c: 79: void PMD_Initialize(void) +[v _PMD_Initialize `(v ~T0 @X0 1 ef ] +"80 +[; ;mcc_generated_files/mcc.c: 80: { +{ +[e :U _PMD_Initialize ] +[f ] +"82 +[; ;mcc_generated_files/mcc.c: 82: PMD0 = 0x00; +[e = _PMD0 -> -> 0 `i `uc ] +"84 +[; ;mcc_generated_files/mcc.c: 84: PMD1 = 0x00; +[e = _PMD1 -> -> 0 `i `uc ] +"86 +[; ;mcc_generated_files/mcc.c: 86: PMD2 = 0x00; +[e = _PMD2 -> -> 0 `i `uc ] +"88 +[; ;mcc_generated_files/mcc.c: 88: PMD3 = 0x00; +[e = _PMD3 -> -> 0 `i `uc ] +"90 +[; ;mcc_generated_files/mcc.c: 90: PMD4 = 0x00; +[e = _PMD4 -> -> 0 `i `uc ] +"92 +[; ;mcc_generated_files/mcc.c: 92: PMD5 = 0x00; +[e = _PMD5 -> -> 0 `i `uc ] +"94 +[; ;mcc_generated_files/mcc.c: 94: PMD6 = 0x00; +[e = _PMD6 -> -> 0 `i `uc ] +"96 +[; ;mcc_generated_files/mcc.c: 96: PMD7 = 0x00; +[e = _PMD7 -> -> 0 `i `uc ] +"98 +[; ;mcc_generated_files/mcc.c: 98: PMD8 = 0x00; +[e = _PMD8 -> -> 0 `i `uc ] +"99 +[; ;mcc_generated_files/mcc.c: 99: } +[e :UE 3183 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/mcc.p1.d b/ETC.X/build/default/debug/mcc_generated_files/mcc.p1.d new file mode 100644 index 0000000..0dcfca3 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/mcc.p1.d @@ -0,0 +1,16 @@ +build/default/debug/mcc_generated_files/mcc.p1: \ +mcc_generated_files/mcc.c \ +mcc_generated_files/mcc.h \ +mcc_generated_files/device_config.h \ +mcc_generated_files/pin_manager.h \ +mcc_generated_files/interrupt_manager.h \ +mcc_generated_files/i2c1_master.h \ +mcc_generated_files/adc.h \ +mcc_generated_files/tmr1.h \ +mcc_generated_files/tmr0.h \ +mcc_generated_files/can1.h \ +mcc_generated_files/can_types.h \ +mcc_generated_files/drivers/i2c_simple_master.h \ +mcc_generated_files/pwm2_16bit.h \ +mcc_generated_files/DAC3.h \ +mcc_generated_files/pwm1_16bit.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/pin_manager.i b/ETC.X/build/default/debug/mcc_generated_files/pin_manager.i new file mode 100644 index 0000000..e75ccbe --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/pin_manager.i @@ -0,0 +1,37565 @@ +# 1 "mcc_generated_files/pin_manager.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/pin_manager.c" 2 +# 49 "mcc_generated_files/pin_manager.c" +# 1 "mcc_generated_files/pin_manager.h" 1 +# 54 "mcc_generated_files/pin_manager.h" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 54 "mcc_generated_files/pin_manager.h" 2 +# 402 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_Initialize (void); +# 414 "mcc_generated_files/pin_manager.h" +void PIN_MANAGER_IOC(void); +# 49 "mcc_generated_files/pin_manager.c" 2 + + + + + + +void PIN_MANAGER_Initialize(void) +{ + + + + LATA = 0x00; + LATB = 0x00; + LATC = 0x00; + + + + + TRISE = 0x08; + TRISA = 0xDE; + TRISB = 0xCC; + TRISC = 0x07; + + + + + ANSELC = 0xE7; + ANSELB = 0x73; + ANSELA = 0xFD; + + + + + WPUE = 0x00; + WPUB = 0x00; + WPUA = 0x00; + WPUC = 0x00; + + + + + ODCONA = 0x00; + ODCONB = 0x00; + ODCONC = 0x18; + + + + + SLRCONA = 0xFF; + SLRCONB = 0xFF; + SLRCONC = 0xFF; + + + + + INLVLA = 0xFF; + INLVLB = 0xFF; + INLVLC = 0xFF; + INLVLE = 0x08; +# 116 "mcc_generated_files/pin_manager.c" + ADACTPPS = 0x0F; + I2C1SDAPPS = 0x14; + RB1PPS = 0x1A; + RC3PPS = 0x37; + RB0PPS = 0x18; + RC4PPS = 0x38; + CANRXPPS = 0x0B; + RB4PPS = 0x46; + I2C1SCLPPS = 0x13; +} + +void PIN_MANAGER_IOC(void) +{ +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/pin_manager.p1 b/ETC.X/build/default/debug/mcc_generated_files/pin_manager.p1 new file mode 100644 index 0000000..2b8e520 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/pin_manager.p1 @@ -0,0 +1,3733 @@ +Version 4.0 HI-TECH Software Intermediate Code +"1474 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1474: unsigned TU16AMD :1; +[v _LATA `Vuc ~T0 @X0 0 e@1214 ] +"1536 +[v _LATB `Vuc ~T0 @X0 0 e@1215 ] +"1598 +[v _LATC `Vuc ~T0 @X0 0 e@1216 ] +"1846 +[v _TRISE `Vuc ~T0 @X0 0 e@1226 ] +"1660 +[v _TRISA `Vuc ~T0 @X0 0 e@1222 ] +"1722 +[v _TRISB `Vuc ~T0 @X0 0 e@1223 ] +"1784 +[v _TRISC `Vuc ~T0 @X0 0 e@1224 ] +"59417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59417: extern volatile unsigned char ANSELC __attribute__((address(0x410))); +[v _ANSELC `Vuc ~T0 @X0 0 e@1040 ] +"58921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58921: extern volatile unsigned char ANSELB __attribute__((address(0x408))); +[v _ANSELB `Vuc ~T0 @X0 0 e@1032 ] +"58425 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58425: extern volatile unsigned char ANSELA __attribute__((address(0x400))); +[v _ANSELA `Vuc ~T0 @X0 0 e@1024 ] +"59913 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59913: extern volatile unsigned char WPUE __attribute__((address(0x421))); +[v _WPUE `Vuc ~T0 @X0 0 e@1057 ] +"58983 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58983: extern volatile unsigned char WPUB __attribute__((address(0x409))); +[v _WPUB `Vuc ~T0 @X0 0 e@1033 ] +"58487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58487: extern volatile unsigned char WPUA __attribute__((address(0x401))); +[v _WPUA `Vuc ~T0 @X0 0 e@1025 ] +"59479 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59479: extern volatile unsigned char WPUC __attribute__((address(0x411))); +[v _WPUC `Vuc ~T0 @X0 0 e@1041 ] +"58549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58549: extern volatile unsigned char ODCONA __attribute__((address(0x402))); +[v _ODCONA `Vuc ~T0 @X0 0 e@1026 ] +"59045 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59045: extern volatile unsigned char ODCONB __attribute__((address(0x40A))); +[v _ODCONB `Vuc ~T0 @X0 0 e@1034 ] +"59541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59541: extern volatile unsigned char ODCONC __attribute__((address(0x412))); +[v _ODCONC `Vuc ~T0 @X0 0 e@1042 ] +"58611 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58611: extern volatile unsigned char SLRCONA __attribute__((address(0x403))); +[v _SLRCONA `Vuc ~T0 @X0 0 e@1027 ] +"59107 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59107: extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); +[v _SLRCONB `Vuc ~T0 @X0 0 e@1035 ] +"59603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59603: extern volatile unsigned char SLRCONC __attribute__((address(0x413))); +[v _SLRCONC `Vuc ~T0 @X0 0 e@1043 ] +"58673 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58673: extern volatile unsigned char INLVLA __attribute__((address(0x404))); +[v _INLVLA `Vuc ~T0 @X0 0 e@1028 ] +"59169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59169: extern volatile unsigned char INLVLB __attribute__((address(0x40C))); +[v _INLVLB `Vuc ~T0 @X0 0 e@1036 ] +"59665 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59665: extern volatile unsigned char INLVLC __attribute__((address(0x414))); +[v _INLVLC `Vuc ~T0 @X0 0 e@1044 ] +"59934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59934: extern volatile unsigned char INLVLE __attribute__((address(0x424))); +[v _INLVLE `Vuc ~T0 @X0 0 e@1060 ] +"28447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28447: extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); +[v _ADACTPPS `Vuc ~T0 @X0 0 e@617 ] +"28909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28909: extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); +[v _I2C1SDAPPS `Vuc ~T0 @X0 0 e@624 ] +"24216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24216: extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); +[v _RB1PPS `Vuc ~T0 @X0 0 e@522 ] +"24716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24716: extern volatile unsigned char RC3PPS __attribute__((address(0x214))); +[v _RC3PPS `Vuc ~T0 @X0 0 e@532 ] +"24166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24166: extern volatile unsigned char RB0PPS __attribute__((address(0x209))); +[v _RB0PPS `Vuc ~T0 @X0 0 e@521 ] +"24766 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24766: extern volatile unsigned char RC4PPS __attribute__((address(0x215))); +[v _RC4PPS `Vuc ~T0 @X0 0 e@533 ] +"24966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24966: extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); +[v _CANRXPPS `Vuc ~T0 @X0 0 e@573 ] +"24366 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24366: extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); +[v _RB4PPS `Vuc ~T0 @X0 0 e@525 ] +"28975 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28975: extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); +[v _I2C1SCLPPS `Vuc ~T0 @X0 0 e@625 ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"55 mcc_generated_files/pin_manager.c +[; ;mcc_generated_files/pin_manager.c: 55: void PIN_MANAGER_Initialize(void) +[v _PIN_MANAGER_Initialize `(v ~T0 @X0 1 ef ] +"56 +[; ;mcc_generated_files/pin_manager.c: 56: { +{ +[e :U _PIN_MANAGER_Initialize ] +[f ] +"60 +[; ;mcc_generated_files/pin_manager.c: 60: LATA = 0x00; +[e = _LATA -> -> 0 `i `uc ] +"61 +[; ;mcc_generated_files/pin_manager.c: 61: LATB = 0x00; +[e = _LATB -> -> 0 `i `uc ] +"62 +[; ;mcc_generated_files/pin_manager.c: 62: LATC = 0x00; +[e = _LATC -> -> 0 `i `uc ] +"67 +[; ;mcc_generated_files/pin_manager.c: 67: TRISE = 0x08; +[e = _TRISE -> -> 8 `i `uc ] +"68 +[; ;mcc_generated_files/pin_manager.c: 68: TRISA = 0xDE; +[e = _TRISA -> -> 222 `i `uc ] +"69 +[; ;mcc_generated_files/pin_manager.c: 69: TRISB = 0xCC; +[e = _TRISB -> -> 204 `i `uc ] +"70 +[; ;mcc_generated_files/pin_manager.c: 70: TRISC = 0x07; +[e = _TRISC -> -> 7 `i `uc ] +"75 +[; ;mcc_generated_files/pin_manager.c: 75: ANSELC = 0xE7; +[e = _ANSELC -> -> 231 `i `uc ] +"76 +[; ;mcc_generated_files/pin_manager.c: 76: ANSELB = 0x73; +[e = _ANSELB -> -> 115 `i `uc ] +"77 +[; ;mcc_generated_files/pin_manager.c: 77: ANSELA = 0xFD; +[e = _ANSELA -> -> 253 `i `uc ] +"82 +[; ;mcc_generated_files/pin_manager.c: 82: WPUE = 0x00; +[e = _WPUE -> -> 0 `i `uc ] +"83 +[; ;mcc_generated_files/pin_manager.c: 83: WPUB = 0x00; +[e = _WPUB -> -> 0 `i `uc ] +"84 +[; ;mcc_generated_files/pin_manager.c: 84: WPUA = 0x00; +[e = _WPUA -> -> 0 `i `uc ] +"85 +[; ;mcc_generated_files/pin_manager.c: 85: WPUC = 0x00; +[e = _WPUC -> -> 0 `i `uc ] +"90 +[; ;mcc_generated_files/pin_manager.c: 90: ODCONA = 0x00; +[e = _ODCONA -> -> 0 `i `uc ] +"91 +[; ;mcc_generated_files/pin_manager.c: 91: ODCONB = 0x00; +[e = _ODCONB -> -> 0 `i `uc ] +"92 +[; ;mcc_generated_files/pin_manager.c: 92: ODCONC = 0x18; +[e = _ODCONC -> -> 24 `i `uc ] +"97 +[; ;mcc_generated_files/pin_manager.c: 97: SLRCONA = 0xFF; +[e = _SLRCONA -> -> 255 `i `uc ] +"98 +[; ;mcc_generated_files/pin_manager.c: 98: SLRCONB = 0xFF; +[e = _SLRCONB -> -> 255 `i `uc ] +"99 +[; ;mcc_generated_files/pin_manager.c: 99: SLRCONC = 0xFF; +[e = _SLRCONC -> -> 255 `i `uc ] +"104 +[; ;mcc_generated_files/pin_manager.c: 104: INLVLA = 0xFF; +[e = _INLVLA -> -> 255 `i `uc ] +"105 +[; ;mcc_generated_files/pin_manager.c: 105: INLVLB = 0xFF; +[e = _INLVLB -> -> 255 `i `uc ] +"106 +[; ;mcc_generated_files/pin_manager.c: 106: INLVLC = 0xFF; +[e = _INLVLC -> -> 255 `i `uc ] +"107 +[; ;mcc_generated_files/pin_manager.c: 107: INLVLE = 0x08; +[e = _INLVLE -> -> 8 `i `uc ] +"116 +[; ;mcc_generated_files/pin_manager.c: 116: ADACTPPS = 0x0F; +[e = _ADACTPPS -> -> 15 `i `uc ] +"117 +[; ;mcc_generated_files/pin_manager.c: 117: I2C1SDAPPS = 0x14; +[e = _I2C1SDAPPS -> -> 20 `i `uc ] +"118 +[; ;mcc_generated_files/pin_manager.c: 118: RB1PPS = 0x1A; +[e = _RB1PPS -> -> 26 `i `uc ] +"119 +[; ;mcc_generated_files/pin_manager.c: 119: RC3PPS = 0x37; +[e = _RC3PPS -> -> 55 `i `uc ] +"120 +[; ;mcc_generated_files/pin_manager.c: 120: RB0PPS = 0x18; +[e = _RB0PPS -> -> 24 `i `uc ] +"121 +[; ;mcc_generated_files/pin_manager.c: 121: RC4PPS = 0x38; +[e = _RC4PPS -> -> 56 `i `uc ] +"122 +[; ;mcc_generated_files/pin_manager.c: 122: CANRXPPS = 0x0B; +[e = _CANRXPPS -> -> 11 `i `uc ] +"123 +[; ;mcc_generated_files/pin_manager.c: 123: RB4PPS = 0x46; +[e = _RB4PPS -> -> 70 `i `uc ] +"124 +[; ;mcc_generated_files/pin_manager.c: 124: I2C1SCLPPS = 0x13; +[e = _I2C1SCLPPS -> -> 19 `i `uc ] +"125 +[; ;mcc_generated_files/pin_manager.c: 125: } +[e :UE 3176 ] +} +"127 +[; ;mcc_generated_files/pin_manager.c: 127: void PIN_MANAGER_IOC(void) +[v _PIN_MANAGER_IOC `(v ~T0 @X0 1 ef ] +"128 +[; ;mcc_generated_files/pin_manager.c: 128: { +{ +[e :U _PIN_MANAGER_IOC ] +[f ] +"129 +[; ;mcc_generated_files/pin_manager.c: 129: } +[e :UE 3177 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/pin_manager.p1.d b/ETC.X/build/default/debug/mcc_generated_files/pin_manager.p1.d new file mode 100644 index 0000000..93caf3d --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/pin_manager.p1.d @@ -0,0 +1,3 @@ +build/default/debug/mcc_generated_files/pin_manager.p1: \ +mcc_generated_files/pin_manager.c \ +mcc_generated_files/pin_manager.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.i b/ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.i new file mode 100644 index 0000000..0f67e6d --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.i @@ -0,0 +1,37708 @@ +# 1 "mcc_generated_files/pwm1_16bit.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/pwm1_16bit.c" 2 +# 51 "mcc_generated_files/pwm1_16bit.c" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 51 "mcc_generated_files/pwm1_16bit.c" 2 + +# 1 "mcc_generated_files/pwm1_16bit.h" 1 +# 55 "mcc_generated_files/pwm1_16bit.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 55 "mcc_generated_files/pwm1_16bit.h" 2 + + + + + + + + +void PWM1_16BIT_Initialize(void); + + + + + + +void PWM1_16BIT_Enable(); +# 79 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Disable(); +# 96 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM1_16BIT_PWMI_ISR(void); + + + + + + +void PWM1_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm1_16bit.h" +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 52 "mcc_generated_files/pwm1_16bit.c" 2 + + + + +static void (*PWM1_16BIT_Slice1Output1_InterruptHandler)(void); +static void (*PWM1_16BIT_Slice1Output2_InterruptHandler)(void); +static void (*PWM1_16BIT_Period_InterruptHandler)(void); +static void PWM1_16BIT_Slice1Output1_DefaultInterruptHandler(void); +static void PWM1_16BIT_Slice1Output2_DefaultInterruptHandler(void); +static void PWM1_16BIT_Period_DefaultInterruptHandler(void); + +void PWM1_16BIT_Initialize(void) +{ + + PWM1ERS = 0x00; + + + PWM1CLK = 0x02; + + + PWM1LDS = 0x00; + + + PWM1PRL = 0x3D; + + + PWM1PRH = 0x00; + + + PWM1CPRE = 0xFE; + + + PWM1PIPOS = 0x00; + + + PWM1GIR = 0x00; + + + PWM1GIE = 0x00; + + + PWM1S1CFG = 0x00; + + + PWM1S1P1L = 0x1F; + + + PWM1S1P1H = 0x00; + + + PWM1S1P2L = 0x1F; + + + PWM1S1P2H = 0x00; + + + PIR4bits.PWM1PIF = 0; + + + PIR4bits.PWM1IF = 0; + + + PWM1GIRbits.S1P1IF = 0; + + + PWM1GIRbits.S1P2IF = 0; + + + PIE4bits.PWM1IE = 0; + + + PIE4bits.PWM1PIE = 0; + + + PWM1_16BIT_Slice1Output1_SetInterruptHandler(PWM1_16BIT_Slice1Output1_DefaultInterruptHandler); + PWM1_16BIT_Slice1Output2_SetInterruptHandler(PWM1_16BIT_Slice1Output2_DefaultInterruptHandler); + PWM1_16BIT_Period_SetInterruptHandler(PWM1_16BIT_Period_DefaultInterruptHandler); + + + PWM1CON = 0x80; +} + +void PWM1_16BIT_Enable() +{ + PWM1CON |= 0x80; +} + +void PWM1_16BIT_Disable() +{ + PWM1CON &= (~0x80); +} + +void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount) +{ + PWM1PRL = (uint8_t)periodCount; + PWM1PRH = (uint8_t)(periodCount >> 8); +} + +void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t registerValue) +{ + PWM1S1P1L = (uint8_t)(registerValue); + PWM1S1P1H = (uint8_t)(registerValue >> 8); +} + +void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t registerValue) +{ + PWM1S1P2L = (uint8_t)(registerValue); + PWM1S1P2H = (uint8_t)(registerValue >> 8); +} + +void PWM1_16BIT_LoadBufferRegisters(void) +{ + + PWM1CONbits.LD = 1; +} + +void PWM1_16BIT_PWMI_ISR(void) +{ + PIR4bits.PWM1IF = 0; + if((PWM1GIEbits.S1P1IE == 1) && (PWM1GIRbits.S1P1IF == 1)) + { + PWM1GIRbits.S1P1IF = 0; + if(PWM1_16BIT_Slice1Output1_InterruptHandler != ((void*)0)) + PWM1_16BIT_Slice1Output1_InterruptHandler(); + } + else if((PWM1GIEbits.S1P2IE == 1) && (PWM1GIRbits.S1P2IF == 1)) + { + PWM1GIRbits.S1P2IF = 0; + if(PWM1_16BIT_Slice1Output2_InterruptHandler != ((void*)0)) + PWM1_16BIT_Slice1Output2_InterruptHandler(); + } +} + +void PWM1_16BIT_PWMPI_ISR(void) +{ + PIR4bits.PWM1PIF = 0; + if(PWM1_16BIT_Period_InterruptHandler != ((void*)0)) + PWM1_16BIT_Period_InterruptHandler(); +} + +void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)) +{ + PWM1_16BIT_Slice1Output1_InterruptHandler = InterruptHandler; +} + +void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)) +{ + PWM1_16BIT_Slice1Output2_InterruptHandler = InterruptHandler; +} + +void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)) +{ + PWM1_16BIT_Period_InterruptHandler = InterruptHandler; +} + +static void PWM1_16BIT_Slice1Output1_DefaultInterruptHandler(void) +{ + + +} + +static void PWM1_16BIT_Slice1Output2_DefaultInterruptHandler(void) +{ + + +} + +static void PWM1_16BIT_Period_DefaultInterruptHandler(void) +{ + + +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.p1 b/ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.p1 new file mode 100644 index 0000000..643fa6c --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.p1 @@ -0,0 +1,4031 @@ +Version 4.0 HI-TECH Software Intermediate Code +[v F22167 `(v ~T0 @X0 0 tf ] +[v F22169 `(v ~T0 @X0 0 tf ] +[v F22171 `(v ~T0 @X0 0 tf ] +"63400 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63400: extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); +[v _PWM1ERS `Vuc ~T0 @X0 0 e@1120 ] +"63420 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63420: extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); +[v _PWM1CLK `Vuc ~T0 @X0 0 e@1121 ] +"63440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63440: extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); +[v _PWM1LDS `Vuc ~T0 @X0 0 e@1122 ] +"63467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63467: extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); +[v _PWM1PRL `Vuc ~T0 @X0 0 e@1123 ] +"63487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63487: extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); +[v _PWM1PRH `Vuc ~T0 @X0 0 e@1124 ] +"63507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63507: extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); +[v _PWM1CPRE `Vuc ~T0 @X0 0 e@1125 ] +"63527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63527: extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); +[v _PWM1PIPOS `Vuc ~T0 @X0 0 e@1126 ] +"63547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63547: extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); +[v _PWM1GIR `Vuc ~T0 @X0 0 e@1127 ] +"63573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63573: extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); +[v _PWM1GIE `Vuc ~T0 @X0 0 e@1128 ] +"63638 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63638: extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); +[v _PWM1S1CFG `Vuc ~T0 @X0 0 e@1130 ] +"63704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63704: extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); +[v _PWM1S1P1L `Vuc ~T0 @X0 0 e@1131 ] +"63724 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63724: extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); +[v _PWM1S1P1H `Vuc ~T0 @X0 0 e@1132 ] +"63751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63751: extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); +[v _PWM1S1P2L `Vuc ~T0 @X0 0 e@1133 ] +"63771 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63771: extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); +[v _PWM1S1P2H `Vuc ~T0 @X0 0 e@1134 ] +"751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 751: extern volatile unsigned char NVMADRH __attribute__((address(0x044))); +[s S3037 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3037 . U1RXIF U1TXIF U1EIF U1IF CANRXIF CANTXIF PWM1PIF PWM1IF ] +"750 +[u S3036 `S3037 1 ] +[n S3036 . . ] +"762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 762: unsigned NVMADR9 :1; +[v _PIR4bits `VS3036 ~T0 @X0 0 e@1202 ] +"63553 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63553: struct { +[s S2881 :1 `uc 1 :1 `uc 1 ] +[n S2881 . S1P1IF S1P2IF ] +"63552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63552: typedef union { +[u S2880 `S2881 1 ] +[n S2880 . . ] +"63558 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63558: extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +[v _PWM1GIRbits `VS2880 ~T0 @X0 0 e@1127 ] +"65302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65302: struct { +[s S3004 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3004 . U1RXIE U1TXIE U1EIE U1IE CANRXIE CANTXIE PWM1PIE PWM1IE ] +"65301 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65301: typedef union { +[u S3003 `S3004 1 ] +[n S3003 . . ] +"65313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65313: extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +[v _PIE4bits `VS3003 ~T0 @X0 0 e@1186 ] +[v F22155 `(v ~T0 @X0 0 tf ] +"182 mcc_generated_files/pwm1_16bit.h +[; ;mcc_generated_files/pwm1_16bit.h: 182: void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +[v _PWM1_16BIT_Slice1Output1_SetInterruptHandler `(v ~T0 @X0 0 ef1`*F22155 ] +"59 mcc_generated_files/pwm1_16bit.c +[; ;mcc_generated_files/pwm1_16bit.c: 59: static void PWM1_16BIT_Slice1Output1_DefaultInterruptHandler(void); +[v _PWM1_16BIT_Slice1Output1_DefaultInterruptHandler `(v ~T0 @X0 0 sf ] +[v F22159 `(v ~T0 @X0 0 tf ] +"202 mcc_generated_files/pwm1_16bit.h +[; ;mcc_generated_files/pwm1_16bit.h: 202: void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +[v _PWM1_16BIT_Slice1Output2_SetInterruptHandler `(v ~T0 @X0 0 ef1`*F22159 ] +"60 mcc_generated_files/pwm1_16bit.c +[; ;mcc_generated_files/pwm1_16bit.c: 60: static void PWM1_16BIT_Slice1Output2_DefaultInterruptHandler(void); +[v _PWM1_16BIT_Slice1Output2_DefaultInterruptHandler `(v ~T0 @X0 0 sf ] +[v F22163 `(v ~T0 @X0 0 tf ] +"222 mcc_generated_files/pwm1_16bit.h +[; ;mcc_generated_files/pwm1_16bit.h: 222: void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +[v _PWM1_16BIT_Period_SetInterruptHandler `(v ~T0 @X0 0 ef1`*F22163 ] +"61 mcc_generated_files/pwm1_16bit.c +[; ;mcc_generated_files/pwm1_16bit.c: 61: static void PWM1_16BIT_Period_DefaultInterruptHandler(void); +[v _PWM1_16BIT_Period_DefaultInterruptHandler `(v ~T0 @X0 0 sf ] +"63599 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63599: extern volatile unsigned char PWM1CON __attribute__((address(0x469))); +[v _PWM1CON `Vuc ~T0 @X0 0 e@1129 ] +"63605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63605: struct { +[s S2885 :1 `uc 1 :1 `uc 1 :1 `uc 1 :4 `uc 1 :1 `uc 1 ] +[n S2885 . ERSNOW ERSPOL LD . EN ] +"63604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63604: typedef union { +[u S2884 `S2885 1 ] +[n S2884 . . ] +"63613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63613: extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +[v _PWM1CONbits `VS2884 ~T0 @X0 0 e@1129 ] +"63579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63579: struct { +[s S2883 :1 `uc 1 :1 `uc 1 ] +[n S2883 . S1P1IE S1P2IE ] +"63578 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63578: typedef union { +[u S2882 `S2883 1 ] +[n S2882 . . ] +"63584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63584: extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +[v _PWM1GIEbits `VS2882 ~T0 @X0 0 e@1128 ] +[v F22189 `(v ~T0 @X0 0 tf ] +[v F22190 `(v ~T0 @X0 0 tf ] +[v F22192 `(v ~T0 @X0 0 tf ] +[v F22194 `(v ~T0 @X0 0 tf ] +[v F22196 `(v ~T0 @X0 0 tf ] +[v F22199 `(v ~T0 @X0 0 tf ] +[v F22201 `(v ~T0 @X0 0 tf ] +[v F22204 `(v ~T0 @X0 0 tf ] +[v F22206 `(v ~T0 @X0 0 tf ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"56 mcc_generated_files/pwm1_16bit.c +[; ;mcc_generated_files/pwm1_16bit.c: 56: static void (*PWM1_16BIT_Slice1Output1_InterruptHandler)(void); +[v _PWM1_16BIT_Slice1Output1_InterruptHandler `*F22167 ~T0 @X0 1 s ] +"57 +[; ;mcc_generated_files/pwm1_16bit.c: 57: static void (*PWM1_16BIT_Slice1Output2_InterruptHandler)(void); +[v _PWM1_16BIT_Slice1Output2_InterruptHandler `*F22169 ~T0 @X0 1 s ] +"58 +[; ;mcc_generated_files/pwm1_16bit.c: 58: static void (*PWM1_16BIT_Period_InterruptHandler)(void); +[v _PWM1_16BIT_Period_InterruptHandler `*F22171 ~T0 @X0 1 s ] +"63 +[; ;mcc_generated_files/pwm1_16bit.c: 63: void PWM1_16BIT_Initialize(void) +[v _PWM1_16BIT_Initialize `(v ~T0 @X0 1 ef ] +"64 +[; ;mcc_generated_files/pwm1_16bit.c: 64: { +{ +[e :U _PWM1_16BIT_Initialize ] +[f ] +"66 +[; ;mcc_generated_files/pwm1_16bit.c: 66: PWM1ERS = 0x00; +[e = _PWM1ERS -> -> 0 `i `uc ] +"69 +[; ;mcc_generated_files/pwm1_16bit.c: 69: PWM1CLK = 0x02; +[e = _PWM1CLK -> -> 2 `i `uc ] +"72 +[; ;mcc_generated_files/pwm1_16bit.c: 72: PWM1LDS = 0x00; +[e = _PWM1LDS -> -> 0 `i `uc ] +"75 +[; ;mcc_generated_files/pwm1_16bit.c: 75: PWM1PRL = 0x3D; +[e = _PWM1PRL -> -> 61 `i `uc ] +"78 +[; ;mcc_generated_files/pwm1_16bit.c: 78: PWM1PRH = 0x00; +[e = _PWM1PRH -> -> 0 `i `uc ] +"81 +[; ;mcc_generated_files/pwm1_16bit.c: 81: PWM1CPRE = 0xFE; +[e = _PWM1CPRE -> -> 254 `i `uc ] +"84 +[; ;mcc_generated_files/pwm1_16bit.c: 84: PWM1PIPOS = 0x00; +[e = _PWM1PIPOS -> -> 0 `i `uc ] +"87 +[; ;mcc_generated_files/pwm1_16bit.c: 87: PWM1GIR = 0x00; +[e = _PWM1GIR -> -> 0 `i `uc ] +"90 +[; ;mcc_generated_files/pwm1_16bit.c: 90: PWM1GIE = 0x00; +[e = _PWM1GIE -> -> 0 `i `uc ] +"93 +[; ;mcc_generated_files/pwm1_16bit.c: 93: PWM1S1CFG = 0x00; +[e = _PWM1S1CFG -> -> 0 `i `uc ] +"96 +[; ;mcc_generated_files/pwm1_16bit.c: 96: PWM1S1P1L = 0x1F; +[e = _PWM1S1P1L -> -> 31 `i `uc ] +"99 +[; ;mcc_generated_files/pwm1_16bit.c: 99: PWM1S1P1H = 0x00; +[e = _PWM1S1P1H -> -> 0 `i `uc ] +"102 +[; ;mcc_generated_files/pwm1_16bit.c: 102: PWM1S1P2L = 0x1F; +[e = _PWM1S1P2L -> -> 31 `i `uc ] +"105 +[; ;mcc_generated_files/pwm1_16bit.c: 105: PWM1S1P2H = 0x00; +[e = _PWM1S1P2H -> -> 0 `i `uc ] +"108 +[; ;mcc_generated_files/pwm1_16bit.c: 108: PIR4bits.PWM1PIF = 0; +[e = . . _PIR4bits 0 6 -> -> 0 `i `uc ] +"111 +[; ;mcc_generated_files/pwm1_16bit.c: 111: PIR4bits.PWM1IF = 0; +[e = . . _PIR4bits 0 7 -> -> 0 `i `uc ] +"114 +[; ;mcc_generated_files/pwm1_16bit.c: 114: PWM1GIRbits.S1P1IF = 0; +[e = . . _PWM1GIRbits 0 0 -> -> 0 `i `uc ] +"117 +[; ;mcc_generated_files/pwm1_16bit.c: 117: PWM1GIRbits.S1P2IF = 0; +[e = . . _PWM1GIRbits 0 1 -> -> 0 `i `uc ] +"120 +[; ;mcc_generated_files/pwm1_16bit.c: 120: PIE4bits.PWM1IE = 0; +[e = . . _PIE4bits 0 7 -> -> 0 `i `uc ] +"123 +[; ;mcc_generated_files/pwm1_16bit.c: 123: PIE4bits.PWM1PIE = 0; +[e = . . _PIE4bits 0 6 -> -> 0 `i `uc ] +"126 +[; ;mcc_generated_files/pwm1_16bit.c: 126: PWM1_16BIT_Slice1Output1_SetInterruptHandler(PWM1_16BIT_Slice1Output1_DefaultInterruptHandler); +[e ( _PWM1_16BIT_Slice1Output1_SetInterruptHandler (1 &U _PWM1_16BIT_Slice1Output1_DefaultInterruptHandler ] +"127 +[; ;mcc_generated_files/pwm1_16bit.c: 127: PWM1_16BIT_Slice1Output2_SetInterruptHandler(PWM1_16BIT_Slice1Output2_DefaultInterruptHandler); +[e ( _PWM1_16BIT_Slice1Output2_SetInterruptHandler (1 &U _PWM1_16BIT_Slice1Output2_DefaultInterruptHandler ] +"128 +[; ;mcc_generated_files/pwm1_16bit.c: 128: PWM1_16BIT_Period_SetInterruptHandler(PWM1_16BIT_Period_DefaultInterruptHandler); +[e ( _PWM1_16BIT_Period_SetInterruptHandler (1 &U _PWM1_16BIT_Period_DefaultInterruptHandler ] +"131 +[; ;mcc_generated_files/pwm1_16bit.c: 131: PWM1CON = 0x80; +[e = _PWM1CON -> -> 128 `i `uc ] +"132 +[; ;mcc_generated_files/pwm1_16bit.c: 132: } +[e :UE 3176 ] +} +"134 +[; ;mcc_generated_files/pwm1_16bit.c: 134: void PWM1_16BIT_Enable() +[v _PWM1_16BIT_Enable `(v ~T0 @X0 1 ef ] +"135 +[; ;mcc_generated_files/pwm1_16bit.c: 135: { +{ +[e :U _PWM1_16BIT_Enable ] +[f ] +"136 +[; ;mcc_generated_files/pwm1_16bit.c: 136: PWM1CON |= 0x80; +[e =| _PWM1CON -> -> 128 `i `Vuc ] +"137 +[; ;mcc_generated_files/pwm1_16bit.c: 137: } +[e :UE 3177 ] +} +"139 +[; ;mcc_generated_files/pwm1_16bit.c: 139: void PWM1_16BIT_Disable() +[v _PWM1_16BIT_Disable `(v ~T0 @X0 1 ef ] +"140 +[; ;mcc_generated_files/pwm1_16bit.c: 140: { +{ +[e :U _PWM1_16BIT_Disable ] +[f ] +"141 +[; ;mcc_generated_files/pwm1_16bit.c: 141: PWM1CON &= (~0x80); +[e =& _PWM1CON -> ~ -> 128 `i `Vuc ] +"142 +[; ;mcc_generated_files/pwm1_16bit.c: 142: } +[e :UE 3178 ] +} +"144 +[; ;mcc_generated_files/pwm1_16bit.c: 144: void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount) +[v _PWM1_16BIT_WritePeriodRegister `(v ~T0 @X0 1 ef1`us ] +"145 +[; ;mcc_generated_files/pwm1_16bit.c: 145: { +{ +[e :U _PWM1_16BIT_WritePeriodRegister ] +"144 +[; ;mcc_generated_files/pwm1_16bit.c: 144: void PWM1_16BIT_WritePeriodRegister(uint16_t periodCount) +[v _periodCount `us ~T0 @X0 1 r1 ] +"145 +[; ;mcc_generated_files/pwm1_16bit.c: 145: { +[f ] +"146 +[; ;mcc_generated_files/pwm1_16bit.c: 146: PWM1PRL = (uint8_t)periodCount; +[e = _PWM1PRL -> _periodCount `uc ] +"147 +[; ;mcc_generated_files/pwm1_16bit.c: 147: PWM1PRH = (uint8_t)(periodCount >> 8); +[e = _PWM1PRH -> >> -> _periodCount `ui -> 8 `i `uc ] +"148 +[; ;mcc_generated_files/pwm1_16bit.c: 148: } +[e :UE 3179 ] +} +"150 +[; ;mcc_generated_files/pwm1_16bit.c: 150: void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t registerValue) +[v _PWM1_16BIT_SetSlice1Output1DutyCycleRegister `(v ~T0 @X0 1 ef1`us ] +"151 +[; ;mcc_generated_files/pwm1_16bit.c: 151: { +{ +[e :U _PWM1_16BIT_SetSlice1Output1DutyCycleRegister ] +"150 +[; ;mcc_generated_files/pwm1_16bit.c: 150: void PWM1_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t registerValue) +[v _registerValue `us ~T0 @X0 1 r1 ] +"151 +[; ;mcc_generated_files/pwm1_16bit.c: 151: { +[f ] +"152 +[; ;mcc_generated_files/pwm1_16bit.c: 152: PWM1S1P1L = (uint8_t)(registerValue); +[e = _PWM1S1P1L -> _registerValue `uc ] +"153 +[; ;mcc_generated_files/pwm1_16bit.c: 153: PWM1S1P1H = (uint8_t)(registerValue >> 8); +[e = _PWM1S1P1H -> >> -> _registerValue `ui -> 8 `i `uc ] +"154 +[; ;mcc_generated_files/pwm1_16bit.c: 154: } +[e :UE 3180 ] +} +"156 +[; ;mcc_generated_files/pwm1_16bit.c: 156: void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t registerValue) +[v _PWM1_16BIT_SetSlice1Output2DutyCycleRegister `(v ~T0 @X0 1 ef1`us ] +"157 +[; ;mcc_generated_files/pwm1_16bit.c: 157: { +{ +[e :U _PWM1_16BIT_SetSlice1Output2DutyCycleRegister ] +"156 +[; ;mcc_generated_files/pwm1_16bit.c: 156: void PWM1_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t registerValue) +[v _registerValue `us ~T0 @X0 1 r1 ] +"157 +[; ;mcc_generated_files/pwm1_16bit.c: 157: { +[f ] +"158 +[; ;mcc_generated_files/pwm1_16bit.c: 158: PWM1S1P2L = (uint8_t)(registerValue); +[e = _PWM1S1P2L -> _registerValue `uc ] +"159 +[; ;mcc_generated_files/pwm1_16bit.c: 159: PWM1S1P2H = (uint8_t)(registerValue >> 8); +[e = _PWM1S1P2H -> >> -> _registerValue `ui -> 8 `i `uc ] +"160 +[; ;mcc_generated_files/pwm1_16bit.c: 160: } +[e :UE 3181 ] +} +"162 +[; ;mcc_generated_files/pwm1_16bit.c: 162: void PWM1_16BIT_LoadBufferRegisters(void) +[v _PWM1_16BIT_LoadBufferRegisters `(v ~T0 @X0 1 ef ] +"163 +[; ;mcc_generated_files/pwm1_16bit.c: 163: { +{ +[e :U _PWM1_16BIT_LoadBufferRegisters ] +[f ] +"165 +[; ;mcc_generated_files/pwm1_16bit.c: 165: PWM1CONbits.LD = 1; +[e = . . _PWM1CONbits 0 2 -> -> 1 `i `uc ] +"166 +[; ;mcc_generated_files/pwm1_16bit.c: 166: } +[e :UE 3182 ] +} +"168 +[; ;mcc_generated_files/pwm1_16bit.c: 168: void PWM1_16BIT_PWMI_ISR(void) +[v _PWM1_16BIT_PWMI_ISR `(v ~T0 @X0 1 ef ] +"169 +[; ;mcc_generated_files/pwm1_16bit.c: 169: { +{ +[e :U _PWM1_16BIT_PWMI_ISR ] +[f ] +"170 +[; ;mcc_generated_files/pwm1_16bit.c: 170: PIR4bits.PWM1IF = 0; +[e = . . _PIR4bits 0 7 -> -> 0 `i `uc ] +"171 +[; ;mcc_generated_files/pwm1_16bit.c: 171: if((PWM1GIEbits.S1P1IE == 1) && (PWM1GIRbits.S1P1IF == 1)) +[e $ ! && == -> . . _PWM1GIEbits 0 0 `i -> 1 `i == -> . . _PWM1GIRbits 0 0 `i -> 1 `i 3184 ] +"172 +[; ;mcc_generated_files/pwm1_16bit.c: 172: { +{ +"173 +[; ;mcc_generated_files/pwm1_16bit.c: 173: PWM1GIRbits.S1P1IF = 0; +[e = . . _PWM1GIRbits 0 0 -> -> 0 `i `uc ] +"174 +[; ;mcc_generated_files/pwm1_16bit.c: 174: if(PWM1_16BIT_Slice1Output1_InterruptHandler != ((void*)0)) +[e $ ! != _PWM1_16BIT_Slice1Output1_InterruptHandler -> -> -> 0 `i `*v `*F22189 3185 ] +"175 +[; ;mcc_generated_files/pwm1_16bit.c: 175: PWM1_16BIT_Slice1Output1_InterruptHandler(); +[e ( *U _PWM1_16BIT_Slice1Output1_InterruptHandler .. ] +[e :U 3185 ] +"176 +[; ;mcc_generated_files/pwm1_16bit.c: 176: } +} +[e $U 3186 ] +"177 +[; ;mcc_generated_files/pwm1_16bit.c: 177: else if((PWM1GIEbits.S1P2IE == 1) && (PWM1GIRbits.S1P2IF == 1)) +[e :U 3184 ] +[e $ ! && == -> . . _PWM1GIEbits 0 1 `i -> 1 `i == -> . . _PWM1GIRbits 0 1 `i -> 1 `i 3187 ] +"178 +[; ;mcc_generated_files/pwm1_16bit.c: 178: { +{ +"179 +[; ;mcc_generated_files/pwm1_16bit.c: 179: PWM1GIRbits.S1P2IF = 0; +[e = . . _PWM1GIRbits 0 1 -> -> 0 `i `uc ] +"180 +[; ;mcc_generated_files/pwm1_16bit.c: 180: if(PWM1_16BIT_Slice1Output2_InterruptHandler != ((void*)0)) +[e $ ! != _PWM1_16BIT_Slice1Output2_InterruptHandler -> -> -> 0 `i `*v `*F22190 3188 ] +"181 +[; ;mcc_generated_files/pwm1_16bit.c: 181: PWM1_16BIT_Slice1Output2_InterruptHandler(); +[e ( *U _PWM1_16BIT_Slice1Output2_InterruptHandler .. ] +[e :U 3188 ] +"182 +[; ;mcc_generated_files/pwm1_16bit.c: 182: } +} +[e :U 3187 ] +[e :U 3186 ] +"183 +[; ;mcc_generated_files/pwm1_16bit.c: 183: } +[e :UE 3183 ] +} +"185 +[; ;mcc_generated_files/pwm1_16bit.c: 185: void PWM1_16BIT_PWMPI_ISR(void) +[v _PWM1_16BIT_PWMPI_ISR `(v ~T0 @X0 1 ef ] +"186 +[; ;mcc_generated_files/pwm1_16bit.c: 186: { +{ +[e :U _PWM1_16BIT_PWMPI_ISR ] +[f ] +"187 +[; ;mcc_generated_files/pwm1_16bit.c: 187: PIR4bits.PWM1PIF = 0; +[e = . . _PIR4bits 0 6 -> -> 0 `i `uc ] +"188 +[; ;mcc_generated_files/pwm1_16bit.c: 188: if(PWM1_16BIT_Period_InterruptHandler != ((void*)0)) +[e $ ! != _PWM1_16BIT_Period_InterruptHandler -> -> -> 0 `i `*v `*F22192 3190 ] +"189 +[; ;mcc_generated_files/pwm1_16bit.c: 189: PWM1_16BIT_Period_InterruptHandler(); +[e ( *U _PWM1_16BIT_Period_InterruptHandler .. ] +[e :U 3190 ] +"190 +[; ;mcc_generated_files/pwm1_16bit.c: 190: } +[e :UE 3189 ] +} +"192 +[; ;mcc_generated_files/pwm1_16bit.c: 192: void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _PWM1_16BIT_Slice1Output1_SetInterruptHandler `(v ~T0 @X0 1 ef1`*F22194 ] +"193 +[; ;mcc_generated_files/pwm1_16bit.c: 193: { +{ +[e :U _PWM1_16BIT_Slice1Output1_SetInterruptHandler ] +"192 +[; ;mcc_generated_files/pwm1_16bit.c: 192: void PWM1_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22196 ~T0 @X0 1 r1 ] +"193 +[; ;mcc_generated_files/pwm1_16bit.c: 193: { +[f ] +"194 +[; ;mcc_generated_files/pwm1_16bit.c: 194: PWM1_16BIT_Slice1Output1_InterruptHandler = InterruptHandler; +[e = _PWM1_16BIT_Slice1Output1_InterruptHandler _InterruptHandler ] +"195 +[; ;mcc_generated_files/pwm1_16bit.c: 195: } +[e :UE 3191 ] +} +"197 +[; ;mcc_generated_files/pwm1_16bit.c: 197: void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _PWM1_16BIT_Slice1Output2_SetInterruptHandler `(v ~T0 @X0 1 ef1`*F22199 ] +"198 +[; ;mcc_generated_files/pwm1_16bit.c: 198: { +{ +[e :U _PWM1_16BIT_Slice1Output2_SetInterruptHandler ] +"197 +[; ;mcc_generated_files/pwm1_16bit.c: 197: void PWM1_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22201 ~T0 @X0 1 r1 ] +"198 +[; ;mcc_generated_files/pwm1_16bit.c: 198: { +[f ] +"199 +[; ;mcc_generated_files/pwm1_16bit.c: 199: PWM1_16BIT_Slice1Output2_InterruptHandler = InterruptHandler; +[e = _PWM1_16BIT_Slice1Output2_InterruptHandler _InterruptHandler ] +"200 +[; ;mcc_generated_files/pwm1_16bit.c: 200: } +[e :UE 3192 ] +} +"202 +[; ;mcc_generated_files/pwm1_16bit.c: 202: void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _PWM1_16BIT_Period_SetInterruptHandler `(v ~T0 @X0 1 ef1`*F22204 ] +"203 +[; ;mcc_generated_files/pwm1_16bit.c: 203: { +{ +[e :U _PWM1_16BIT_Period_SetInterruptHandler ] +"202 +[; ;mcc_generated_files/pwm1_16bit.c: 202: void PWM1_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22206 ~T0 @X0 1 r1 ] +"203 +[; ;mcc_generated_files/pwm1_16bit.c: 203: { +[f ] +"204 +[; ;mcc_generated_files/pwm1_16bit.c: 204: PWM1_16BIT_Period_InterruptHandler = InterruptHandler; +[e = _PWM1_16BIT_Period_InterruptHandler _InterruptHandler ] +"205 +[; ;mcc_generated_files/pwm1_16bit.c: 205: } +[e :UE 3193 ] +} +"207 +[; ;mcc_generated_files/pwm1_16bit.c: 207: static void PWM1_16BIT_Slice1Output1_DefaultInterruptHandler(void) +[v _PWM1_16BIT_Slice1Output1_DefaultInterruptHandler `(v ~T0 @X0 1 sf ] +"208 +[; ;mcc_generated_files/pwm1_16bit.c: 208: { +{ +[e :U _PWM1_16BIT_Slice1Output1_DefaultInterruptHandler ] +[f ] +"211 +[; ;mcc_generated_files/pwm1_16bit.c: 211: } +[e :UE 3194 ] +} +"213 +[; ;mcc_generated_files/pwm1_16bit.c: 213: static void PWM1_16BIT_Slice1Output2_DefaultInterruptHandler(void) +[v _PWM1_16BIT_Slice1Output2_DefaultInterruptHandler `(v ~T0 @X0 1 sf ] +"214 +[; ;mcc_generated_files/pwm1_16bit.c: 214: { +{ +[e :U _PWM1_16BIT_Slice1Output2_DefaultInterruptHandler ] +[f ] +"217 +[; ;mcc_generated_files/pwm1_16bit.c: 217: } +[e :UE 3195 ] +} +"219 +[; ;mcc_generated_files/pwm1_16bit.c: 219: static void PWM1_16BIT_Period_DefaultInterruptHandler(void) +[v _PWM1_16BIT_Period_DefaultInterruptHandler `(v ~T0 @X0 1 sf ] +"220 +[; ;mcc_generated_files/pwm1_16bit.c: 220: { +{ +[e :U _PWM1_16BIT_Period_DefaultInterruptHandler ] +[f ] +"223 +[; ;mcc_generated_files/pwm1_16bit.c: 223: } +[e :UE 3196 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.p1.d b/ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.p1.d new file mode 100644 index 0000000..eb628ef --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/pwm1_16bit.p1.d @@ -0,0 +1,3 @@ +build/default/debug/mcc_generated_files/pwm1_16bit.p1: \ +mcc_generated_files/pwm1_16bit.c \ +mcc_generated_files/pwm1_16bit.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.i b/ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.i new file mode 100644 index 0000000..ec7c7e8 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.i @@ -0,0 +1,37708 @@ +# 1 "mcc_generated_files/pwm2_16bit.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/pwm2_16bit.c" 2 +# 51 "mcc_generated_files/pwm2_16bit.c" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 51 "mcc_generated_files/pwm2_16bit.c" 2 + +# 1 "mcc_generated_files/pwm2_16bit.h" 1 +# 55 "mcc_generated_files/pwm2_16bit.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 55 "mcc_generated_files/pwm2_16bit.h" 2 + + + + + + + + +void PWM2_16BIT_Initialize(void); + + + + + + +void PWM2_16BIT_Enable(); +# 79 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Disable(); +# 96 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount); +# 114 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t value); +# 131 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t value); +# 148 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_LoadBufferRegisters(void); + + + + + + +void PWM2_16BIT_PWMI_ISR(void); + + + + + + +void PWM2_16BIT_PWMPI_ISR(void); +# 182 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 202 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +# 222 "mcc_generated_files/pwm2_16bit.h" +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +# 52 "mcc_generated_files/pwm2_16bit.c" 2 + + + + +static void (*PWM2_16BIT_Slice1Output1_InterruptHandler)(void); +static void (*PWM2_16BIT_Slice1Output2_InterruptHandler)(void); +static void (*PWM2_16BIT_Period_InterruptHandler)(void); +static void PWM2_16BIT_Slice1Output1_DefaultInterruptHandler(void); +static void PWM2_16BIT_Slice1Output2_DefaultInterruptHandler(void); +static void PWM2_16BIT_Period_DefaultInterruptHandler(void); + +void PWM2_16BIT_Initialize(void) +{ + + PWM2ERS = 0x00; + + + PWM2CLK = 0x02; + + + PWM2LDS = 0x00; + + + PWM2PRL = 0x3D; + + + PWM2PRH = 0x00; + + + PWM2CPRE = 0xFE; + + + PWM2PIPOS = 0x00; + + + PWM2GIR = 0x00; + + + PWM2GIE = 0x00; + + + PWM2S1CFG = 0x00; + + + PWM2S1P1L = 0x1F; + + + PWM2S1P1H = 0x00; + + + PWM2S1P2L = 0x1F; + + + PWM2S1P2H = 0x00; + + + PIR5bits.PWM2PIF = 0; + + + PIR5bits.PWM2IF = 0; + + + PWM2GIRbits.S1P1IF = 0; + + + PWM2GIRbits.S1P2IF = 0; + + + PIE5bits.PWM2IE = 0; + + + PIE5bits.PWM2PIE = 0; + + + PWM2_16BIT_Slice1Output1_SetInterruptHandler(PWM2_16BIT_Slice1Output1_DefaultInterruptHandler); + PWM2_16BIT_Slice1Output2_SetInterruptHandler(PWM2_16BIT_Slice1Output2_DefaultInterruptHandler); + PWM2_16BIT_Period_SetInterruptHandler(PWM2_16BIT_Period_DefaultInterruptHandler); + + + PWM2CON = 0x80; +} + +void PWM2_16BIT_Enable() +{ + PWM2CON |= 0x80; +} + +void PWM2_16BIT_Disable() +{ + PWM2CON &= (~0x80); +} + +void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount) +{ + PWM2PRL = (uint8_t)periodCount; + PWM2PRH = (uint8_t)(periodCount >> 8); +} + +void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t registerValue) +{ + PWM2S1P1L = (uint8_t)(registerValue); + PWM2S1P1H = (uint8_t)(registerValue >> 8); +} + +void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t registerValue) +{ + PWM2S1P2L = (uint8_t)(registerValue); + PWM2S1P2H = (uint8_t)(registerValue >> 8); +} + +void PWM2_16BIT_LoadBufferRegisters(void) +{ + + PWM2CONbits.LD = 1; +} + +void PWM2_16BIT_PWMI_ISR(void) +{ + PIR5bits.PWM2IF = 0; + if((PWM2GIEbits.S1P1IE == 1) && (PWM2GIRbits.S1P1IF == 1)) + { + PWM2GIRbits.S1P1IF = 0; + if(PWM2_16BIT_Slice1Output1_InterruptHandler != ((void*)0)) + PWM2_16BIT_Slice1Output1_InterruptHandler(); + } + else if((PWM2GIEbits.S1P2IE == 1) && (PWM2GIRbits.S1P2IF == 1)) + { + PWM2GIRbits.S1P2IF = 0; + if(PWM2_16BIT_Slice1Output2_InterruptHandler != ((void*)0)) + PWM2_16BIT_Slice1Output2_InterruptHandler(); + } +} + +void PWM2_16BIT_PWMPI_ISR(void) +{ + PIR5bits.PWM2PIF = 0; + if(PWM2_16BIT_Period_InterruptHandler != ((void*)0)) + PWM2_16BIT_Period_InterruptHandler(); +} + +void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)) +{ + PWM2_16BIT_Slice1Output1_InterruptHandler = InterruptHandler; +} + +void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)) +{ + PWM2_16BIT_Slice1Output2_InterruptHandler = InterruptHandler; +} + +void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)) +{ + PWM2_16BIT_Period_InterruptHandler = InterruptHandler; +} + +static void PWM2_16BIT_Slice1Output1_DefaultInterruptHandler(void) +{ + + +} + +static void PWM2_16BIT_Slice1Output2_DefaultInterruptHandler(void) +{ + + +} + +static void PWM2_16BIT_Period_DefaultInterruptHandler(void) +{ + + +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.p1 b/ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.p1 new file mode 100644 index 0000000..d0e9053 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.p1 @@ -0,0 +1,4030 @@ +Version 4.0 HI-TECH Software Intermediate Code +[v F22167 `(v ~T0 @X0 0 tf ] +[v F22169 `(v ~T0 @X0 0 tf ] +[v F22171 `(v ~T0 @X0 0 tf ] +"63791 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63791: extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); +[v _PWM2ERS `Vuc ~T0 @X0 0 e@1135 ] +"63811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63811: extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); +[v _PWM2CLK `Vuc ~T0 @X0 0 e@1136 ] +"63831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63831: extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); +[v _PWM2LDS `Vuc ~T0 @X0 0 e@1137 ] +"63858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63858: extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); +[v _PWM2PRL `Vuc ~T0 @X0 0 e@1138 ] +"63878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63878: extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); +[v _PWM2PRH `Vuc ~T0 @X0 0 e@1139 ] +"63898 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63898: extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); +[v _PWM2CPRE `Vuc ~T0 @X0 0 e@1140 ] +"63918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63918: extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); +[v _PWM2PIPOS `Vuc ~T0 @X0 0 e@1141 ] +"63938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63938: extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); +[v _PWM2GIR `Vuc ~T0 @X0 0 e@1142 ] +"63964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63964: extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); +[v _PWM2GIE `Vuc ~T0 @X0 0 e@1143 ] +"64029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64029: extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); +[v _PWM2S1CFG `Vuc ~T0 @X0 0 e@1145 ] +"64095 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64095: extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); +[v _PWM2S1P1L `Vuc ~T0 @X0 0 e@1146 ] +"64115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64115: extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); +[v _PWM2S1P1H `Vuc ~T0 @X0 0 e@1147 ] +"64142 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64142: extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); +[v _PWM2S1P2L `Vuc ~T0 @X0 0 e@1148 ] +"64162 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64162: extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); +[v _PWM2S1P2H `Vuc ~T0 @X0 0 e@1149 ] +"813 +[s S3039 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3039 . SPI2RXIF SPI2TXIF SPI2IF TU16BIF TMR3IF TMR3GIF PWM2PIF PWM2IF ] +"812 +[u S3038 `S3039 1 ] +[n S3038 . . ] +"824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 824: +[v _PIR5bits `VS3038 ~T0 @X0 0 e@1203 ] +"63944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63944: struct { +[s S2912 :1 `uc 1 :1 `uc 1 ] +[n S2912 . S1P1IF S1P2IF ] +"63943 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63943: typedef union { +[u S2911 `S2912 1 ] +[n S2911 . . ] +"63949 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63949: extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +[v _PWM2GIRbits `VS2911 ~T0 @X0 0 e@1142 ] +"65364 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65364: struct { +[s S3006 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3006 . SPI2RXIE SPI2TXIE SPI2IE TU16BIE TMR3IE TMR3GIE PWM2PIE PWM2IE ] +"65363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65363: typedef union { +[u S3005 `S3006 1 ] +[n S3005 . . ] +"65375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65375: extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +[v _PIE5bits `VS3005 ~T0 @X0 0 e@1187 ] +[v F22155 `(v ~T0 @X0 0 tf ] +"182 mcc_generated_files/pwm2_16bit.h +[; ;mcc_generated_files/pwm2_16bit.h: 182: void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)); +[v _PWM2_16BIT_Slice1Output1_SetInterruptHandler `(v ~T0 @X0 0 ef1`*F22155 ] +"59 mcc_generated_files/pwm2_16bit.c +[; ;mcc_generated_files/pwm2_16bit.c: 59: static void PWM2_16BIT_Slice1Output1_DefaultInterruptHandler(void); +[v _PWM2_16BIT_Slice1Output1_DefaultInterruptHandler `(v ~T0 @X0 0 sf ] +[v F22159 `(v ~T0 @X0 0 tf ] +"202 mcc_generated_files/pwm2_16bit.h +[; ;mcc_generated_files/pwm2_16bit.h: 202: void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)); +[v _PWM2_16BIT_Slice1Output2_SetInterruptHandler `(v ~T0 @X0 0 ef1`*F22159 ] +"60 mcc_generated_files/pwm2_16bit.c +[; ;mcc_generated_files/pwm2_16bit.c: 60: static void PWM2_16BIT_Slice1Output2_DefaultInterruptHandler(void); +[v _PWM2_16BIT_Slice1Output2_DefaultInterruptHandler `(v ~T0 @X0 0 sf ] +[v F22163 `(v ~T0 @X0 0 tf ] +"222 mcc_generated_files/pwm2_16bit.h +[; ;mcc_generated_files/pwm2_16bit.h: 222: void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)); +[v _PWM2_16BIT_Period_SetInterruptHandler `(v ~T0 @X0 0 ef1`*F22163 ] +"61 mcc_generated_files/pwm2_16bit.c +[; ;mcc_generated_files/pwm2_16bit.c: 61: static void PWM2_16BIT_Period_DefaultInterruptHandler(void); +[v _PWM2_16BIT_Period_DefaultInterruptHandler `(v ~T0 @X0 0 sf ] +"63990 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63990: extern volatile unsigned char PWM2CON __attribute__((address(0x478))); +[v _PWM2CON `Vuc ~T0 @X0 0 e@1144 ] +"63996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63996: struct { +[s S2916 :1 `uc 1 :1 `uc 1 :1 `uc 1 :4 `uc 1 :1 `uc 1 ] +[n S2916 . ERSNOW ERSPOL LD . EN ] +"63995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63995: typedef union { +[u S2915 `S2916 1 ] +[n S2915 . . ] +"64004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64004: extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +[v _PWM2CONbits `VS2915 ~T0 @X0 0 e@1144 ] +"63970 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63970: struct { +[s S2914 :1 `uc 1 :1 `uc 1 ] +[n S2914 . S1P1IE S1P2IE ] +"63969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63969: typedef union { +[u S2913 `S2914 1 ] +[n S2913 . . ] +"63975 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63975: extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +[v _PWM2GIEbits `VS2913 ~T0 @X0 0 e@1143 ] +[v F22189 `(v ~T0 @X0 0 tf ] +[v F22190 `(v ~T0 @X0 0 tf ] +[v F22192 `(v ~T0 @X0 0 tf ] +[v F22194 `(v ~T0 @X0 0 tf ] +[v F22196 `(v ~T0 @X0 0 tf ] +[v F22199 `(v ~T0 @X0 0 tf ] +[v F22201 `(v ~T0 @X0 0 tf ] +[v F22204 `(v ~T0 @X0 0 tf ] +[v F22206 `(v ~T0 @X0 0 tf ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"56 mcc_generated_files/pwm2_16bit.c +[; ;mcc_generated_files/pwm2_16bit.c: 56: static void (*PWM2_16BIT_Slice1Output1_InterruptHandler)(void); +[v _PWM2_16BIT_Slice1Output1_InterruptHandler `*F22167 ~T0 @X0 1 s ] +"57 +[; ;mcc_generated_files/pwm2_16bit.c: 57: static void (*PWM2_16BIT_Slice1Output2_InterruptHandler)(void); +[v _PWM2_16BIT_Slice1Output2_InterruptHandler `*F22169 ~T0 @X0 1 s ] +"58 +[; ;mcc_generated_files/pwm2_16bit.c: 58: static void (*PWM2_16BIT_Period_InterruptHandler)(void); +[v _PWM2_16BIT_Period_InterruptHandler `*F22171 ~T0 @X0 1 s ] +"63 +[; ;mcc_generated_files/pwm2_16bit.c: 63: void PWM2_16BIT_Initialize(void) +[v _PWM2_16BIT_Initialize `(v ~T0 @X0 1 ef ] +"64 +[; ;mcc_generated_files/pwm2_16bit.c: 64: { +{ +[e :U _PWM2_16BIT_Initialize ] +[f ] +"66 +[; ;mcc_generated_files/pwm2_16bit.c: 66: PWM2ERS = 0x00; +[e = _PWM2ERS -> -> 0 `i `uc ] +"69 +[; ;mcc_generated_files/pwm2_16bit.c: 69: PWM2CLK = 0x02; +[e = _PWM2CLK -> -> 2 `i `uc ] +"72 +[; ;mcc_generated_files/pwm2_16bit.c: 72: PWM2LDS = 0x00; +[e = _PWM2LDS -> -> 0 `i `uc ] +"75 +[; ;mcc_generated_files/pwm2_16bit.c: 75: PWM2PRL = 0x3D; +[e = _PWM2PRL -> -> 61 `i `uc ] +"78 +[; ;mcc_generated_files/pwm2_16bit.c: 78: PWM2PRH = 0x00; +[e = _PWM2PRH -> -> 0 `i `uc ] +"81 +[; ;mcc_generated_files/pwm2_16bit.c: 81: PWM2CPRE = 0xFE; +[e = _PWM2CPRE -> -> 254 `i `uc ] +"84 +[; ;mcc_generated_files/pwm2_16bit.c: 84: PWM2PIPOS = 0x00; +[e = _PWM2PIPOS -> -> 0 `i `uc ] +"87 +[; ;mcc_generated_files/pwm2_16bit.c: 87: PWM2GIR = 0x00; +[e = _PWM2GIR -> -> 0 `i `uc ] +"90 +[; ;mcc_generated_files/pwm2_16bit.c: 90: PWM2GIE = 0x00; +[e = _PWM2GIE -> -> 0 `i `uc ] +"93 +[; ;mcc_generated_files/pwm2_16bit.c: 93: PWM2S1CFG = 0x00; +[e = _PWM2S1CFG -> -> 0 `i `uc ] +"96 +[; ;mcc_generated_files/pwm2_16bit.c: 96: PWM2S1P1L = 0x1F; +[e = _PWM2S1P1L -> -> 31 `i `uc ] +"99 +[; ;mcc_generated_files/pwm2_16bit.c: 99: PWM2S1P1H = 0x00; +[e = _PWM2S1P1H -> -> 0 `i `uc ] +"102 +[; ;mcc_generated_files/pwm2_16bit.c: 102: PWM2S1P2L = 0x1F; +[e = _PWM2S1P2L -> -> 31 `i `uc ] +"105 +[; ;mcc_generated_files/pwm2_16bit.c: 105: PWM2S1P2H = 0x00; +[e = _PWM2S1P2H -> -> 0 `i `uc ] +"108 +[; ;mcc_generated_files/pwm2_16bit.c: 108: PIR5bits.PWM2PIF = 0; +[e = . . _PIR5bits 0 6 -> -> 0 `i `uc ] +"111 +[; ;mcc_generated_files/pwm2_16bit.c: 111: PIR5bits.PWM2IF = 0; +[e = . . _PIR5bits 0 7 -> -> 0 `i `uc ] +"114 +[; ;mcc_generated_files/pwm2_16bit.c: 114: PWM2GIRbits.S1P1IF = 0; +[e = . . _PWM2GIRbits 0 0 -> -> 0 `i `uc ] +"117 +[; ;mcc_generated_files/pwm2_16bit.c: 117: PWM2GIRbits.S1P2IF = 0; +[e = . . _PWM2GIRbits 0 1 -> -> 0 `i `uc ] +"120 +[; ;mcc_generated_files/pwm2_16bit.c: 120: PIE5bits.PWM2IE = 0; +[e = . . _PIE5bits 0 7 -> -> 0 `i `uc ] +"123 +[; ;mcc_generated_files/pwm2_16bit.c: 123: PIE5bits.PWM2PIE = 0; +[e = . . _PIE5bits 0 6 -> -> 0 `i `uc ] +"126 +[; ;mcc_generated_files/pwm2_16bit.c: 126: PWM2_16BIT_Slice1Output1_SetInterruptHandler(PWM2_16BIT_Slice1Output1_DefaultInterruptHandler); +[e ( _PWM2_16BIT_Slice1Output1_SetInterruptHandler (1 &U _PWM2_16BIT_Slice1Output1_DefaultInterruptHandler ] +"127 +[; ;mcc_generated_files/pwm2_16bit.c: 127: PWM2_16BIT_Slice1Output2_SetInterruptHandler(PWM2_16BIT_Slice1Output2_DefaultInterruptHandler); +[e ( _PWM2_16BIT_Slice1Output2_SetInterruptHandler (1 &U _PWM2_16BIT_Slice1Output2_DefaultInterruptHandler ] +"128 +[; ;mcc_generated_files/pwm2_16bit.c: 128: PWM2_16BIT_Period_SetInterruptHandler(PWM2_16BIT_Period_DefaultInterruptHandler); +[e ( _PWM2_16BIT_Period_SetInterruptHandler (1 &U _PWM2_16BIT_Period_DefaultInterruptHandler ] +"131 +[; ;mcc_generated_files/pwm2_16bit.c: 131: PWM2CON = 0x80; +[e = _PWM2CON -> -> 128 `i `uc ] +"132 +[; ;mcc_generated_files/pwm2_16bit.c: 132: } +[e :UE 3176 ] +} +"134 +[; ;mcc_generated_files/pwm2_16bit.c: 134: void PWM2_16BIT_Enable() +[v _PWM2_16BIT_Enable `(v ~T0 @X0 1 ef ] +"135 +[; ;mcc_generated_files/pwm2_16bit.c: 135: { +{ +[e :U _PWM2_16BIT_Enable ] +[f ] +"136 +[; ;mcc_generated_files/pwm2_16bit.c: 136: PWM2CON |= 0x80; +[e =| _PWM2CON -> -> 128 `i `Vuc ] +"137 +[; ;mcc_generated_files/pwm2_16bit.c: 137: } +[e :UE 3177 ] +} +"139 +[; ;mcc_generated_files/pwm2_16bit.c: 139: void PWM2_16BIT_Disable() +[v _PWM2_16BIT_Disable `(v ~T0 @X0 1 ef ] +"140 +[; ;mcc_generated_files/pwm2_16bit.c: 140: { +{ +[e :U _PWM2_16BIT_Disable ] +[f ] +"141 +[; ;mcc_generated_files/pwm2_16bit.c: 141: PWM2CON &= (~0x80); +[e =& _PWM2CON -> ~ -> 128 `i `Vuc ] +"142 +[; ;mcc_generated_files/pwm2_16bit.c: 142: } +[e :UE 3178 ] +} +"144 +[; ;mcc_generated_files/pwm2_16bit.c: 144: void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount) +[v _PWM2_16BIT_WritePeriodRegister `(v ~T0 @X0 1 ef1`us ] +"145 +[; ;mcc_generated_files/pwm2_16bit.c: 145: { +{ +[e :U _PWM2_16BIT_WritePeriodRegister ] +"144 +[; ;mcc_generated_files/pwm2_16bit.c: 144: void PWM2_16BIT_WritePeriodRegister(uint16_t periodCount) +[v _periodCount `us ~T0 @X0 1 r1 ] +"145 +[; ;mcc_generated_files/pwm2_16bit.c: 145: { +[f ] +"146 +[; ;mcc_generated_files/pwm2_16bit.c: 146: PWM2PRL = (uint8_t)periodCount; +[e = _PWM2PRL -> _periodCount `uc ] +"147 +[; ;mcc_generated_files/pwm2_16bit.c: 147: PWM2PRH = (uint8_t)(periodCount >> 8); +[e = _PWM2PRH -> >> -> _periodCount `ui -> 8 `i `uc ] +"148 +[; ;mcc_generated_files/pwm2_16bit.c: 148: } +[e :UE 3179 ] +} +"150 +[; ;mcc_generated_files/pwm2_16bit.c: 150: void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t registerValue) +[v _PWM2_16BIT_SetSlice1Output1DutyCycleRegister `(v ~T0 @X0 1 ef1`us ] +"151 +[; ;mcc_generated_files/pwm2_16bit.c: 151: { +{ +[e :U _PWM2_16BIT_SetSlice1Output1DutyCycleRegister ] +"150 +[; ;mcc_generated_files/pwm2_16bit.c: 150: void PWM2_16BIT_SetSlice1Output1DutyCycleRegister(uint16_t registerValue) +[v _registerValue `us ~T0 @X0 1 r1 ] +"151 +[; ;mcc_generated_files/pwm2_16bit.c: 151: { +[f ] +"152 +[; ;mcc_generated_files/pwm2_16bit.c: 152: PWM2S1P1L = (uint8_t)(registerValue); +[e = _PWM2S1P1L -> _registerValue `uc ] +"153 +[; ;mcc_generated_files/pwm2_16bit.c: 153: PWM2S1P1H = (uint8_t)(registerValue >> 8); +[e = _PWM2S1P1H -> >> -> _registerValue `ui -> 8 `i `uc ] +"154 +[; ;mcc_generated_files/pwm2_16bit.c: 154: } +[e :UE 3180 ] +} +"156 +[; ;mcc_generated_files/pwm2_16bit.c: 156: void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t registerValue) +[v _PWM2_16BIT_SetSlice1Output2DutyCycleRegister `(v ~T0 @X0 1 ef1`us ] +"157 +[; ;mcc_generated_files/pwm2_16bit.c: 157: { +{ +[e :U _PWM2_16BIT_SetSlice1Output2DutyCycleRegister ] +"156 +[; ;mcc_generated_files/pwm2_16bit.c: 156: void PWM2_16BIT_SetSlice1Output2DutyCycleRegister(uint16_t registerValue) +[v _registerValue `us ~T0 @X0 1 r1 ] +"157 +[; ;mcc_generated_files/pwm2_16bit.c: 157: { +[f ] +"158 +[; ;mcc_generated_files/pwm2_16bit.c: 158: PWM2S1P2L = (uint8_t)(registerValue); +[e = _PWM2S1P2L -> _registerValue `uc ] +"159 +[; ;mcc_generated_files/pwm2_16bit.c: 159: PWM2S1P2H = (uint8_t)(registerValue >> 8); +[e = _PWM2S1P2H -> >> -> _registerValue `ui -> 8 `i `uc ] +"160 +[; ;mcc_generated_files/pwm2_16bit.c: 160: } +[e :UE 3181 ] +} +"162 +[; ;mcc_generated_files/pwm2_16bit.c: 162: void PWM2_16BIT_LoadBufferRegisters(void) +[v _PWM2_16BIT_LoadBufferRegisters `(v ~T0 @X0 1 ef ] +"163 +[; ;mcc_generated_files/pwm2_16bit.c: 163: { +{ +[e :U _PWM2_16BIT_LoadBufferRegisters ] +[f ] +"165 +[; ;mcc_generated_files/pwm2_16bit.c: 165: PWM2CONbits.LD = 1; +[e = . . _PWM2CONbits 0 2 -> -> 1 `i `uc ] +"166 +[; ;mcc_generated_files/pwm2_16bit.c: 166: } +[e :UE 3182 ] +} +"168 +[; ;mcc_generated_files/pwm2_16bit.c: 168: void PWM2_16BIT_PWMI_ISR(void) +[v _PWM2_16BIT_PWMI_ISR `(v ~T0 @X0 1 ef ] +"169 +[; ;mcc_generated_files/pwm2_16bit.c: 169: { +{ +[e :U _PWM2_16BIT_PWMI_ISR ] +[f ] +"170 +[; ;mcc_generated_files/pwm2_16bit.c: 170: PIR5bits.PWM2IF = 0; +[e = . . _PIR5bits 0 7 -> -> 0 `i `uc ] +"171 +[; ;mcc_generated_files/pwm2_16bit.c: 171: if((PWM2GIEbits.S1P1IE == 1) && (PWM2GIRbits.S1P1IF == 1)) +[e $ ! && == -> . . _PWM2GIEbits 0 0 `i -> 1 `i == -> . . _PWM2GIRbits 0 0 `i -> 1 `i 3184 ] +"172 +[; ;mcc_generated_files/pwm2_16bit.c: 172: { +{ +"173 +[; ;mcc_generated_files/pwm2_16bit.c: 173: PWM2GIRbits.S1P1IF = 0; +[e = . . _PWM2GIRbits 0 0 -> -> 0 `i `uc ] +"174 +[; ;mcc_generated_files/pwm2_16bit.c: 174: if(PWM2_16BIT_Slice1Output1_InterruptHandler != ((void*)0)) +[e $ ! != _PWM2_16BIT_Slice1Output1_InterruptHandler -> -> -> 0 `i `*v `*F22189 3185 ] +"175 +[; ;mcc_generated_files/pwm2_16bit.c: 175: PWM2_16BIT_Slice1Output1_InterruptHandler(); +[e ( *U _PWM2_16BIT_Slice1Output1_InterruptHandler .. ] +[e :U 3185 ] +"176 +[; ;mcc_generated_files/pwm2_16bit.c: 176: } +} +[e $U 3186 ] +"177 +[; ;mcc_generated_files/pwm2_16bit.c: 177: else if((PWM2GIEbits.S1P2IE == 1) && (PWM2GIRbits.S1P2IF == 1)) +[e :U 3184 ] +[e $ ! && == -> . . _PWM2GIEbits 0 1 `i -> 1 `i == -> . . _PWM2GIRbits 0 1 `i -> 1 `i 3187 ] +"178 +[; ;mcc_generated_files/pwm2_16bit.c: 178: { +{ +"179 +[; ;mcc_generated_files/pwm2_16bit.c: 179: PWM2GIRbits.S1P2IF = 0; +[e = . . _PWM2GIRbits 0 1 -> -> 0 `i `uc ] +"180 +[; ;mcc_generated_files/pwm2_16bit.c: 180: if(PWM2_16BIT_Slice1Output2_InterruptHandler != ((void*)0)) +[e $ ! != _PWM2_16BIT_Slice1Output2_InterruptHandler -> -> -> 0 `i `*v `*F22190 3188 ] +"181 +[; ;mcc_generated_files/pwm2_16bit.c: 181: PWM2_16BIT_Slice1Output2_InterruptHandler(); +[e ( *U _PWM2_16BIT_Slice1Output2_InterruptHandler .. ] +[e :U 3188 ] +"182 +[; ;mcc_generated_files/pwm2_16bit.c: 182: } +} +[e :U 3187 ] +[e :U 3186 ] +"183 +[; ;mcc_generated_files/pwm2_16bit.c: 183: } +[e :UE 3183 ] +} +"185 +[; ;mcc_generated_files/pwm2_16bit.c: 185: void PWM2_16BIT_PWMPI_ISR(void) +[v _PWM2_16BIT_PWMPI_ISR `(v ~T0 @X0 1 ef ] +"186 +[; ;mcc_generated_files/pwm2_16bit.c: 186: { +{ +[e :U _PWM2_16BIT_PWMPI_ISR ] +[f ] +"187 +[; ;mcc_generated_files/pwm2_16bit.c: 187: PIR5bits.PWM2PIF = 0; +[e = . . _PIR5bits 0 6 -> -> 0 `i `uc ] +"188 +[; ;mcc_generated_files/pwm2_16bit.c: 188: if(PWM2_16BIT_Period_InterruptHandler != ((void*)0)) +[e $ ! != _PWM2_16BIT_Period_InterruptHandler -> -> -> 0 `i `*v `*F22192 3190 ] +"189 +[; ;mcc_generated_files/pwm2_16bit.c: 189: PWM2_16BIT_Period_InterruptHandler(); +[e ( *U _PWM2_16BIT_Period_InterruptHandler .. ] +[e :U 3190 ] +"190 +[; ;mcc_generated_files/pwm2_16bit.c: 190: } +[e :UE 3189 ] +} +"192 +[; ;mcc_generated_files/pwm2_16bit.c: 192: void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _PWM2_16BIT_Slice1Output1_SetInterruptHandler `(v ~T0 @X0 1 ef1`*F22194 ] +"193 +[; ;mcc_generated_files/pwm2_16bit.c: 193: { +{ +[e :U _PWM2_16BIT_Slice1Output1_SetInterruptHandler ] +"192 +[; ;mcc_generated_files/pwm2_16bit.c: 192: void PWM2_16BIT_Slice1Output1_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22196 ~T0 @X0 1 r1 ] +"193 +[; ;mcc_generated_files/pwm2_16bit.c: 193: { +[f ] +"194 +[; ;mcc_generated_files/pwm2_16bit.c: 194: PWM2_16BIT_Slice1Output1_InterruptHandler = InterruptHandler; +[e = _PWM2_16BIT_Slice1Output1_InterruptHandler _InterruptHandler ] +"195 +[; ;mcc_generated_files/pwm2_16bit.c: 195: } +[e :UE 3191 ] +} +"197 +[; ;mcc_generated_files/pwm2_16bit.c: 197: void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _PWM2_16BIT_Slice1Output2_SetInterruptHandler `(v ~T0 @X0 1 ef1`*F22199 ] +"198 +[; ;mcc_generated_files/pwm2_16bit.c: 198: { +{ +[e :U _PWM2_16BIT_Slice1Output2_SetInterruptHandler ] +"197 +[; ;mcc_generated_files/pwm2_16bit.c: 197: void PWM2_16BIT_Slice1Output2_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22201 ~T0 @X0 1 r1 ] +"198 +[; ;mcc_generated_files/pwm2_16bit.c: 198: { +[f ] +"199 +[; ;mcc_generated_files/pwm2_16bit.c: 199: PWM2_16BIT_Slice1Output2_InterruptHandler = InterruptHandler; +[e = _PWM2_16BIT_Slice1Output2_InterruptHandler _InterruptHandler ] +"200 +[; ;mcc_generated_files/pwm2_16bit.c: 200: } +[e :UE 3192 ] +} +"202 +[; ;mcc_generated_files/pwm2_16bit.c: 202: void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _PWM2_16BIT_Period_SetInterruptHandler `(v ~T0 @X0 1 ef1`*F22204 ] +"203 +[; ;mcc_generated_files/pwm2_16bit.c: 203: { +{ +[e :U _PWM2_16BIT_Period_SetInterruptHandler ] +"202 +[; ;mcc_generated_files/pwm2_16bit.c: 202: void PWM2_16BIT_Period_SetInterruptHandler(void (* InterruptHandler)(void)) +[v _InterruptHandler `*F22206 ~T0 @X0 1 r1 ] +"203 +[; ;mcc_generated_files/pwm2_16bit.c: 203: { +[f ] +"204 +[; ;mcc_generated_files/pwm2_16bit.c: 204: PWM2_16BIT_Period_InterruptHandler = InterruptHandler; +[e = _PWM2_16BIT_Period_InterruptHandler _InterruptHandler ] +"205 +[; ;mcc_generated_files/pwm2_16bit.c: 205: } +[e :UE 3193 ] +} +"207 +[; ;mcc_generated_files/pwm2_16bit.c: 207: static void PWM2_16BIT_Slice1Output1_DefaultInterruptHandler(void) +[v _PWM2_16BIT_Slice1Output1_DefaultInterruptHandler `(v ~T0 @X0 1 sf ] +"208 +[; ;mcc_generated_files/pwm2_16bit.c: 208: { +{ +[e :U _PWM2_16BIT_Slice1Output1_DefaultInterruptHandler ] +[f ] +"211 +[; ;mcc_generated_files/pwm2_16bit.c: 211: } +[e :UE 3194 ] +} +"213 +[; ;mcc_generated_files/pwm2_16bit.c: 213: static void PWM2_16BIT_Slice1Output2_DefaultInterruptHandler(void) +[v _PWM2_16BIT_Slice1Output2_DefaultInterruptHandler `(v ~T0 @X0 1 sf ] +"214 +[; ;mcc_generated_files/pwm2_16bit.c: 214: { +{ +[e :U _PWM2_16BIT_Slice1Output2_DefaultInterruptHandler ] +[f ] +"217 +[; ;mcc_generated_files/pwm2_16bit.c: 217: } +[e :UE 3195 ] +} +"219 +[; ;mcc_generated_files/pwm2_16bit.c: 219: static void PWM2_16BIT_Period_DefaultInterruptHandler(void) +[v _PWM2_16BIT_Period_DefaultInterruptHandler `(v ~T0 @X0 1 sf ] +"220 +[; ;mcc_generated_files/pwm2_16bit.c: 220: { +{ +[e :U _PWM2_16BIT_Period_DefaultInterruptHandler ] +[f ] +"223 +[; ;mcc_generated_files/pwm2_16bit.c: 223: } +[e :UE 3196 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.p1.d b/ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.p1.d new file mode 100644 index 0000000..033f4f9 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/pwm2_16bit.p1.d @@ -0,0 +1,3 @@ +build/default/debug/mcc_generated_files/pwm2_16bit.p1: \ +mcc_generated_files/pwm2_16bit.c \ +mcc_generated_files/pwm2_16bit.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/tmr0.i b/ETC.X/build/default/debug/mcc_generated_files/tmr0.i new file mode 100644 index 0000000..9adc6c2 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/tmr0.i @@ -0,0 +1,37639 @@ +# 1 "mcc_generated_files/tmr0.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/tmr0.c" 2 +# 51 "mcc_generated_files/tmr0.c" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 51 "mcc_generated_files/tmr0.c" 2 + +# 1 "mcc_generated_files/tmr0.h" 1 +# 55 "mcc_generated_files/tmr0.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 55 "mcc_generated_files/tmr0.h" 2 +# 106 "mcc_generated_files/tmr0.h" +void TMR0_Initialize(void); +# 135 "mcc_generated_files/tmr0.h" +void TMR0_StartTimer(void); +# 167 "mcc_generated_files/tmr0.h" +void TMR0_StopTimer(void); +# 202 "mcc_generated_files/tmr0.h" +uint8_t TMR0_ReadTimer(void); +# 241 "mcc_generated_files/tmr0.h" +void TMR0_WriteTimer(uint8_t timerVal); +# 278 "mcc_generated_files/tmr0.h" +void TMR0_Reload(uint8_t periodVal); +# 297 "mcc_generated_files/tmr0.h" +void TMR0_ISR(void); +# 315 "mcc_generated_files/tmr0.h" +void TMR0_CallBack(void); +# 333 "mcc_generated_files/tmr0.h" + void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +# 351 "mcc_generated_files/tmr0.h" +extern void (*TMR0_InterruptHandler)(void); +# 369 "mcc_generated_files/tmr0.h" +void TMR0_DefaultInterruptHandler(void); +# 52 "mcc_generated_files/tmr0.c" 2 + +# 1 "mcc_generated_files/../TEMPORIZATIONS.h" 1 +# 23 "mcc_generated_files/../TEMPORIZATIONS.h" +extern unsigned char ucCount500ms; +extern unsigned char ucCount1s; +extern unsigned char ucCount10s; +extern unsigned int uiCount30s; +extern unsigned int uiCount1min; +extern unsigned char ucCount50ms; + + + +void TEMPORIZATION_10ms (void); +void TEMPORIZATION_100ms (void); +void TEMPORIZATION_500ms (void); +void TEMPORIZATION_1s (void); +void TEMPORIZATION_10s (void); +void TEMPORIZATION_30s (void); +void TEMPORIZATION_1mins (void); +# 53 "mcc_generated_files/tmr0.c" 2 + + + + + + + +void (*TMR0_InterruptHandler)(void); + +void TMR0_Initialize(void) +{ + + + + T0CON1 = 0x48; + + + TMR0H = 0x61; + + + TMR0L = 0x00; + + + PIR3bits.TMR0IF = 0; + + + PIE3bits.TMR0IE = 1; + + + TMR0_SetInterruptHandler(TMR0_DefaultInterruptHandler); + + + T0CON0 = 0x80; +} + +void TMR0_StartTimer(void) +{ + + T0CON0bits.T0EN = 1; +} + +void TMR0_StopTimer(void) +{ + + T0CON0bits.T0EN = 0; +} + +uint8_t TMR0_ReadTimer(void) +{ + uint8_t readVal; + + + readVal = TMR0L; + + return readVal; +} + +void TMR0_WriteTimer(uint8_t timerVal) +{ + + TMR0L = timerVal; + } + +void TMR0_Reload(uint8_t periodVal) +{ + + TMR0H = periodVal; +} + +void TMR0_ISR(void) +{ + static volatile uint16_t CountCallBack = 0; + + + PIR3bits.TMR0IF = 0; + + if (++CountCallBack >= 10) + { + + TMR0_CallBack(); + + + CountCallBack = 0; + } + TEMPORIZATION_10ms(); + + +} + +void TMR0_CallBack(void) +{ + + + if(TMR0_InterruptHandler) + { + TMR0_InterruptHandler(); + } +} + +void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)){ + TMR0_InterruptHandler = InterruptHandler; +} + +void TMR0_DefaultInterruptHandler(void){ + + +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/tmr0.p1 b/ETC.X/build/default/debug/mcc_generated_files/tmr0.p1 new file mode 100644 index 0000000..45ed9df --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/tmr0.p1 @@ -0,0 +1,3804 @@ +Version 4.0 HI-TECH Software Intermediate Code +[v F22173 `(v ~T0 @X0 0 tf ] +"39040 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39040: extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); +[v _T0CON1 `Vuc ~T0 @X0 0 e@795 ] +"38688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38688: extern volatile unsigned char TMR0H __attribute__((address(0x319))); +[v _TMR0H `Vuc ~T0 @X0 0 e@793 ] +"38550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38550: extern volatile unsigned char TMR0L __attribute__((address(0x318))); +[v _TMR0L `Vuc ~T0 @X0 0 e@792 ] +"689 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 689: }; +[s S3035 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3035 . SPI1RXIF SPI1TXIF SPI1IF TMR2IF TMR1IF TMR1GIF CCP1IF TMR0IF ] +"688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 688: unsigned NVMADRL :8; +[u S3034 `S3035 1 ] +[n S3034 . . ] +"700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 700: } NVMADRLbits_t; +[v _PIR3bits `VS3034 ~T0 @X0 0 e@1201 ] +"65240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65240: struct { +[s S3002 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3002 . SPI1RXIE SPI1TXIE SPI1IE TMR2IE TMR1IE TMR1GIE CCP1IE TMR0IE ] +"65239 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65239: typedef union { +[u S3001 `S3002 1 ] +[n S3001 . . ] +"65251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65251: extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +[v _PIE3bits `VS3001 ~T0 @X0 0 e@1185 ] +[v F22153 `(v ~T0 @X0 0 tf ] +"333 mcc_generated_files/tmr0.h +[; ;mcc_generated_files/tmr0.h: 333: void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)); +[v _TMR0_SetInterruptHandler `(v ~T0 @X0 0 ef1`*F22153 ] +"369 +[; ;mcc_generated_files/tmr0.h: 369: void TMR0_DefaultInterruptHandler(void); +[v _TMR0_DefaultInterruptHandler `(v ~T0 @X0 0 ef ] +"38942 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38942: extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); +[v _T0CON0 `Vuc ~T0 @X0 0 e@794 ] +"38948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38948: struct { +[s S1818 :4 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1818 . OUTPS MD16 OUT . EN ] +"38955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38955: struct { +[s S1819 :4 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1819 . T0OUTPS T0MD16 T0OUT . T0EN ] +"38962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38962: struct { +[s S1820 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1820 . OUTPS0 OUTPS1 OUTPS2 OUTPS3 T016BIT ] +"38947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38947: typedef union { +[u S1817 `S1818 1 `S1819 1 `S1820 1 ] +[n S1817 . . . . ] +"38970 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38970: extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +[v _T0CON0bits `VS1817 ~T0 @X0 0 e@794 ] +"315 mcc_generated_files/tmr0.h +[; ;mcc_generated_files/tmr0.h: 315: void TMR0_CallBack(void); +[v _TMR0_CallBack `(v ~T0 @X0 0 ef ] +"32 mcc_generated_files/../TEMPORIZATIONS.h +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 32: void TEMPORIZATION_10ms (void); +[v _TEMPORIZATION_10ms `(v ~T0 @X0 0 ef ] +[v F22187 `(v ~T0 @X0 0 tf ] +[v F22189 `(v ~T0 @X0 0 tf ] +[v F22191 `(v ~T0 @X0 0 tf ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"60 mcc_generated_files/tmr0.c +[; ;mcc_generated_files/tmr0.c: 60: void (*TMR0_InterruptHandler)(void); +[v _TMR0_InterruptHandler `*F22173 ~T0 @X0 1 e ] +"62 +[; ;mcc_generated_files/tmr0.c: 62: void TMR0_Initialize(void) +[v _TMR0_Initialize `(v ~T0 @X0 1 ef ] +"63 +[; ;mcc_generated_files/tmr0.c: 63: { +{ +[e :U _TMR0_Initialize ] +[f ] +"67 +[; ;mcc_generated_files/tmr0.c: 67: T0CON1 = 0x48; +[e = _T0CON1 -> -> 72 `i `uc ] +"70 +[; ;mcc_generated_files/tmr0.c: 70: TMR0H = 0x61; +[e = _TMR0H -> -> 97 `i `uc ] +"73 +[; ;mcc_generated_files/tmr0.c: 73: TMR0L = 0x00; +[e = _TMR0L -> -> 0 `i `uc ] +"76 +[; ;mcc_generated_files/tmr0.c: 76: PIR3bits.TMR0IF = 0; +[e = . . _PIR3bits 0 7 -> -> 0 `i `uc ] +"79 +[; ;mcc_generated_files/tmr0.c: 79: PIE3bits.TMR0IE = 1; +[e = . . _PIE3bits 0 7 -> -> 1 `i `uc ] +"82 +[; ;mcc_generated_files/tmr0.c: 82: TMR0_SetInterruptHandler(TMR0_DefaultInterruptHandler); +[e ( _TMR0_SetInterruptHandler (1 &U _TMR0_DefaultInterruptHandler ] +"85 +[; ;mcc_generated_files/tmr0.c: 85: T0CON0 = 0x80; +[e = _T0CON0 -> -> 128 `i `uc ] +"86 +[; ;mcc_generated_files/tmr0.c: 86: } +[e :UE 3176 ] +} +"88 +[; ;mcc_generated_files/tmr0.c: 88: void TMR0_StartTimer(void) +[v _TMR0_StartTimer `(v ~T0 @X0 1 ef ] +"89 +[; ;mcc_generated_files/tmr0.c: 89: { +{ +[e :U _TMR0_StartTimer ] +[f ] +"91 +[; ;mcc_generated_files/tmr0.c: 91: T0CON0bits.T0EN = 1; +[e = . . _T0CON0bits 1 4 -> -> 1 `i `uc ] +"92 +[; ;mcc_generated_files/tmr0.c: 92: } +[e :UE 3177 ] +} +"94 +[; ;mcc_generated_files/tmr0.c: 94: void TMR0_StopTimer(void) +[v _TMR0_StopTimer `(v ~T0 @X0 1 ef ] +"95 +[; ;mcc_generated_files/tmr0.c: 95: { +{ +[e :U _TMR0_StopTimer ] +[f ] +"97 +[; ;mcc_generated_files/tmr0.c: 97: T0CON0bits.T0EN = 0; +[e = . . _T0CON0bits 1 4 -> -> 0 `i `uc ] +"98 +[; ;mcc_generated_files/tmr0.c: 98: } +[e :UE 3178 ] +} +"100 +[; ;mcc_generated_files/tmr0.c: 100: uint8_t TMR0_ReadTimer(void) +[v _TMR0_ReadTimer `(uc ~T0 @X0 1 ef ] +"101 +[; ;mcc_generated_files/tmr0.c: 101: { +{ +[e :U _TMR0_ReadTimer ] +[f ] +"102 +[; ;mcc_generated_files/tmr0.c: 102: uint8_t readVal; +[v _readVal `uc ~T0 @X0 1 a ] +"105 +[; ;mcc_generated_files/tmr0.c: 105: readVal = TMR0L; +[e = _readVal _TMR0L ] +"107 +[; ;mcc_generated_files/tmr0.c: 107: return readVal; +[e ) _readVal ] +[e $UE 3179 ] +"108 +[; ;mcc_generated_files/tmr0.c: 108: } +[e :UE 3179 ] +} +"110 +[; ;mcc_generated_files/tmr0.c: 110: void TMR0_WriteTimer(uint8_t timerVal) +[v _TMR0_WriteTimer `(v ~T0 @X0 1 ef1`uc ] +"111 +[; ;mcc_generated_files/tmr0.c: 111: { +{ +[e :U _TMR0_WriteTimer ] +"110 +[; ;mcc_generated_files/tmr0.c: 110: void TMR0_WriteTimer(uint8_t timerVal) +[v _timerVal `uc ~T0 @X0 1 r1 ] +"111 +[; ;mcc_generated_files/tmr0.c: 111: { +[f ] +"113 +[; ;mcc_generated_files/tmr0.c: 113: TMR0L = timerVal; +[e = _TMR0L _timerVal ] +"114 +[; ;mcc_generated_files/tmr0.c: 114: } +[e :UE 3180 ] +} +"116 +[; ;mcc_generated_files/tmr0.c: 116: void TMR0_Reload(uint8_t periodVal) +[v _TMR0_Reload `(v ~T0 @X0 1 ef1`uc ] +"117 +[; ;mcc_generated_files/tmr0.c: 117: { +{ +[e :U _TMR0_Reload ] +"116 +[; ;mcc_generated_files/tmr0.c: 116: void TMR0_Reload(uint8_t periodVal) +[v _periodVal `uc ~T0 @X0 1 r1 ] +"117 +[; ;mcc_generated_files/tmr0.c: 117: { +[f ] +"119 +[; ;mcc_generated_files/tmr0.c: 119: TMR0H = periodVal; +[e = _TMR0H _periodVal ] +"120 +[; ;mcc_generated_files/tmr0.c: 120: } +[e :UE 3181 ] +} +"122 +[; ;mcc_generated_files/tmr0.c: 122: void TMR0_ISR(void) +[v _TMR0_ISR `(v ~T0 @X0 1 ef ] +"123 +[; ;mcc_generated_files/tmr0.c: 123: { +{ +[e :U _TMR0_ISR ] +[f ] +"124 +[; ;mcc_generated_files/tmr0.c: 124: static volatile uint16_t CountCallBack = 0; +[v F22185 `Vus ~T0 @X0 1 s CountCallBack ] +[i F22185 +-> -> 0 `i `us +] +"127 +[; ;mcc_generated_files/tmr0.c: 127: PIR3bits.TMR0IF = 0; +[e = . . _PIR3bits 0 7 -> -> 0 `i `uc ] +"129 +[; ;mcc_generated_files/tmr0.c: 129: if (++CountCallBack >= 10) +[e $ ! >= -> =+ F22185 -> -> 1 `i `Vus `ui -> -> 10 `i `ui 3183 ] +"130 +[; ;mcc_generated_files/tmr0.c: 130: { +{ +"132 +[; ;mcc_generated_files/tmr0.c: 132: TMR0_CallBack(); +[e ( _TMR0_CallBack .. ] +"135 +[; ;mcc_generated_files/tmr0.c: 135: CountCallBack = 0; +[e = F22185 -> -> 0 `i `us ] +"136 +[; ;mcc_generated_files/tmr0.c: 136: } +} +[e :U 3183 ] +"137 +[; ;mcc_generated_files/tmr0.c: 137: TEMPORIZATION_10ms(); +[e ( _TEMPORIZATION_10ms .. ] +"140 +[; ;mcc_generated_files/tmr0.c: 140: } +[e :UE 3182 ] +} +"142 +[; ;mcc_generated_files/tmr0.c: 142: void TMR0_CallBack(void) +[v _TMR0_CallBack `(v ~T0 @X0 1 ef ] +"143 +[; ;mcc_generated_files/tmr0.c: 143: { +{ +[e :U _TMR0_CallBack ] +[f ] +"146 +[; ;mcc_generated_files/tmr0.c: 146: if(TMR0_InterruptHandler) +[e $ ! != _TMR0_InterruptHandler -> -> 0 `i `*F22187 3185 ] +"147 +[; ;mcc_generated_files/tmr0.c: 147: { +{ +"148 +[; ;mcc_generated_files/tmr0.c: 148: TMR0_InterruptHandler(); +[e ( *U _TMR0_InterruptHandler .. ] +"149 +[; ;mcc_generated_files/tmr0.c: 149: } +} +[e :U 3185 ] +"150 +[; ;mcc_generated_files/tmr0.c: 150: } +[e :UE 3184 ] +} +"152 +[; ;mcc_generated_files/tmr0.c: 152: void TMR0_SetInterruptHandler(void (* InterruptHandler)(void)){ +[v _TMR0_SetInterruptHandler `(v ~T0 @X0 1 ef1`*F22189 ] +{ +[e :U _TMR0_SetInterruptHandler ] +[v _InterruptHandler `*F22191 ~T0 @X0 1 r1 ] +[f ] +"153 +[; ;mcc_generated_files/tmr0.c: 153: TMR0_InterruptHandler = InterruptHandler; +[e = _TMR0_InterruptHandler _InterruptHandler ] +"154 +[; ;mcc_generated_files/tmr0.c: 154: } +[e :UE 3186 ] +} +"156 +[; ;mcc_generated_files/tmr0.c: 156: void TMR0_DefaultInterruptHandler(void){ +[v _TMR0_DefaultInterruptHandler `(v ~T0 @X0 1 ef ] +{ +[e :U _TMR0_DefaultInterruptHandler ] +[f ] +"159 +[; ;mcc_generated_files/tmr0.c: 159: } +[e :UE 3187 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/tmr0.p1.d b/ETC.X/build/default/debug/mcc_generated_files/tmr0.p1.d new file mode 100644 index 0000000..69ea360 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/tmr0.p1.d @@ -0,0 +1,4 @@ +build/default/debug/mcc_generated_files/tmr0.p1: \ +mcc_generated_files/tmr0.c \ +mcc_generated_files/tmr0.h \ +mcc_generated_files/../TEMPORIZATIONS.h diff --git a/ETC.X/build/default/debug/mcc_generated_files/tmr1.i b/ETC.X/build/default/debug/mcc_generated_files/tmr1.i new file mode 100644 index 0000000..248bf5b --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/tmr1.i @@ -0,0 +1,37714 @@ +# 1 "mcc_generated_files/tmr1.c" +# 1 "" 1 +# 1 "" 3 +# 288 "" 3 +# 1 "" 1 +# 1 "" 2 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\language_support.h" 1 3 +# 2 "" 2 +# 1 "mcc_generated_files/tmr1.c" 2 +# 51 "mcc_generated_files/tmr1.c" +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 18 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 3 +extern const char __xc8_OPTIM_SPEED; + +extern double __fpnormalize(double); + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\musl_xc8.h" 1 3 +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + + + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\features.h" 1 3 +# 10 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 18 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int wchar_t; +# 122 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned size_t; +# 168 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __int24 int24_t; +# 204 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef __uint24 uint24_t; +# 21 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdlib.h" 2 3 + + +int atoi (const char *); +long atol (const char *); +long long atoll (const char *); +double atof (const char *); + +float strtof (const char *restrict, char **restrict); +double strtod (const char *restrict, char **restrict); +long double strtold (const char *restrict, char **restrict); + + + +long strtol (const char *restrict, char **restrict, int); +unsigned long strtoul (const char *restrict, char **restrict, int); +long long strtoll (const char *restrict, char **restrict, int); +unsigned long long strtoull (const char *restrict, char **restrict, int); + +int rand (void); +void srand (unsigned); + + void abort (void); +int atexit (void (*) (void)); + void exit (int); + void _Exit (int); + +void *bsearch (const void *, const void *, size_t, size_t, int (*)(const void *, const void *)); + +__attribute__((nonreentrant)) void qsort (void *, size_t, size_t, int (*)(const void *, const void *)); + +int abs (int); +long labs (long); +long long llabs (long long); + +typedef struct { int quot, rem; } div_t; +typedef struct { long quot, rem; } ldiv_t; +typedef struct { long long quot, rem; } lldiv_t; + +div_t div (int, int); +ldiv_t ldiv (long, long); +lldiv_t lldiv (long long, long long); + +typedef struct { unsigned int quot, rem; } udiv_t; +typedef struct { unsigned long quot, rem; } uldiv_t; +udiv_t udiv (unsigned int, unsigned int); +uldiv_t uldiv (unsigned long, unsigned long); + + + + + +size_t __ctype_get_mb_cur_max(void); +# 4 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\xc8debug.h" 2 3 + + + + + + + + +#pragma intrinsic(__builtin_software_breakpoint) +extern void __builtin_software_breakpoint(void); +# 24 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 1 3 + + + +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 1 3 +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 1 3 +# 127 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uintptr_t; +# 142 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long intptr_t; +# 158 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef signed char int8_t; + + + + +typedef short int16_t; +# 173 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long int32_t; + + + + + +typedef long long int64_t; +# 188 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef long long intmax_t; + + + + + +typedef unsigned char uint8_t; + + + + +typedef unsigned short uint16_t; +# 209 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long uint32_t; + + + + + +typedef unsigned long long uint64_t; +# 229 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/alltypes.h" 3 +typedef unsigned long long uintmax_t; +# 22 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 + + +typedef int8_t int_fast8_t; + +typedef int64_t int_fast64_t; + + +typedef int8_t int_least8_t; +typedef int16_t int_least16_t; + +typedef int24_t int_least24_t; +typedef int24_t int_fast24_t; + +typedef int32_t int_least32_t; + +typedef int64_t int_least64_t; + + +typedef uint8_t uint_fast8_t; + +typedef uint64_t uint_fast64_t; + + +typedef uint8_t uint_least8_t; +typedef uint16_t uint_least16_t; + +typedef uint24_t uint_least24_t; +typedef uint24_t uint_fast24_t; + +typedef uint32_t uint_least32_t; + +typedef uint64_t uint_least64_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 3 +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\bits/stdint.h" 1 3 +typedef int16_t int_fast16_t; +typedef int32_t int_fast32_t; +typedef uint16_t uint_fast16_t; +typedef uint32_t uint_fast32_t; +# 144 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdint.h" 2 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\builtins.h" 2 3 + + +#pragma intrinsic(__nop) +extern void __nop(void); + + +#pragma intrinsic(_delay) +extern __attribute__((nonreentrant)) void _delay(uint32_t); +#pragma intrinsic(_delaywdt) +extern __attribute__((nonreentrant)) void _delaywdt(uint32_t); + +#pragma intrinsic(_delay3) +extern __attribute__((nonreentrant)) void _delay3(uint8_t); +# 25 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 + + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 1 3 + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 1 3 + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 1 3 +# 5 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\htc.h" 2 3 +# 6 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 1 3 +# 130 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 1 3 +# 45 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\__at.h" 1 3 +# 46 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 2 3 +# 361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BOOTREG __attribute__((address(0x038))); + +__asm("BOOTREG equ 038h"); + + +typedef union { + struct { + unsigned B :6; + unsigned BOOTDONE :1; + unsigned BPOUT :1; + }; +} BOOTREGbits_t; +extern volatile BOOTREGbits_t BOOTREGbits __attribute__((address(0x038))); +# 393 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCON __attribute__((address(0x039))); + +__asm("CLKRCON equ 039h"); + + +typedef union { + struct { + unsigned DIV :3; + unsigned DC :2; + unsigned :2; + unsigned EN :1; + }; + struct { + unsigned CLKRDIV0 :1; + unsigned CLKRDIV1 :1; + unsigned CLKRDIV2 :1; + unsigned CLKRDC0 :1; + unsigned CLKRDC1 :1; + unsigned :2; + unsigned CLKREN :1; + }; + struct { + unsigned DIV0 :1; + unsigned DIV1 :1; + unsigned DIV2 :1; + unsigned DC0 :1; + unsigned DC1 :1; + }; +} CLKRCONbits_t; +extern volatile CLKRCONbits_t CLKRCONbits __attribute__((address(0x039))); +# 497 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLKRCLK __attribute__((address(0x03A))); + +__asm("CLKRCLK equ 03Ah"); + + +typedef union { + struct { + unsigned CLK :5; + }; + struct { + unsigned CLKRCLK0 :1; + unsigned CLKRCLK1 :1; + unsigned CLKRCLK2 :1; + unsigned CLKRCLK3 :1; + unsigned CLKRCLK4 :1; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; +} CLKRCLKbits_t; +extern volatile CLKRCLKbits_t CLKRCLKbits __attribute__((address(0x03A))); +# 581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON0 __attribute__((address(0x040))); + +__asm("NVMCON0 equ 040h"); + + +typedef union { + struct { + unsigned GO :1; + }; + struct { + unsigned NOT_DONE :1; + }; + struct { + unsigned nDONE :1; + }; +} NVMCON0bits_t; +extern volatile NVMCON0bits_t NVMCON0bits __attribute__((address(0x040))); +# 617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMCON1 __attribute__((address(0x041))); + +__asm("NVMCON1 equ 041h"); + + +typedef union { + struct { + unsigned CMD :3; + unsigned :4; + unsigned WRERR :1; + }; + struct { + unsigned NVMCMD :3; + }; +} NVMCON1bits_t; +extern volatile NVMCON1bits_t NVMCON1bits __attribute__((address(0x041))); +# 652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMLOCK __attribute__((address(0x042))); + +__asm("NVMLOCK equ 042h"); + + +typedef union { + struct { + unsigned LOCK :8; + }; +} NVMLOCKbits_t; +extern volatile NVMLOCKbits_t NVMLOCKbits __attribute__((address(0x042))); +# 673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NVMADR __attribute__((address(0x043))); + + +__asm("NVMADR equ 043h"); + + + + +extern volatile unsigned char NVMADRL __attribute__((address(0x043))); + +__asm("NVMADRL equ 043h"); + + +typedef union { + struct { + unsigned NVMADRL :8; + }; + struct { + unsigned NVMADR0 :1; + unsigned NVMADR1 :1; + unsigned NVMADR2 :1; + unsigned NVMADR3 :1; + unsigned NVMADR4 :1; + unsigned NVMADR5 :1; + unsigned NVMADR6 :1; + unsigned NVMADR7 :1; + }; +} NVMADRLbits_t; +extern volatile NVMADRLbits_t NVMADRLbits __attribute__((address(0x043))); +# 751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRH __attribute__((address(0x044))); + +__asm("NVMADRH equ 044h"); + + +typedef union { + struct { + unsigned NVMADRH :8; + }; + struct { + unsigned NVMADR8 :1; + unsigned NVMADR9 :1; + unsigned NVMADR10 :1; + unsigned NVMADR11 :1; + unsigned NVMADR12 :1; + unsigned NVMADR13 :1; + unsigned NVMADR14 :1; + unsigned NVMADR15 :1; + }; +} NVMADRHbits_t; +extern volatile NVMADRHbits_t NVMADRHbits __attribute__((address(0x044))); +# 821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMADRU __attribute__((address(0x045))); + +__asm("NVMADRU equ 045h"); + + +typedef union { + struct { + unsigned NVMADRU :6; + }; + struct { + unsigned NVMADR16 :1; + unsigned NVMADR17 :1; + unsigned NVMADR18 :1; + unsigned NVMADR19 :1; + unsigned NVMADR20 :1; + unsigned NVMADR21 :1; + }; +} NVMADRUbits_t; +extern volatile NVMADRUbits_t NVMADRUbits __attribute__((address(0x045))); +# 879 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short NVMDAT __attribute__((address(0x046))); + +__asm("NVMDAT equ 046h"); + + + + +extern volatile unsigned char NVMDATL __attribute__((address(0x046))); + +__asm("NVMDATL equ 046h"); + + +typedef union { + struct { + unsigned NVMDATL :8; + }; + struct { + unsigned NVMDAT0 :1; + unsigned NVMDAT1 :1; + unsigned NVMDAT2 :1; + unsigned NVMDAT3 :1; + unsigned NVMDAT4 :1; + unsigned NVMDAT5 :1; + unsigned NVMDAT6 :1; + unsigned NVMDAT7 :1; + }; +} NVMDATLbits_t; +extern volatile NVMDATLbits_t NVMDATLbits __attribute__((address(0x046))); +# 956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NVMDATH __attribute__((address(0x047))); + +__asm("NVMDATH equ 047h"); + + +typedef union { + struct { + unsigned NVMDATH :8; + }; + struct { + unsigned NVMDAT8 :1; + unsigned NVMDAT9 :1; + unsigned NVMDAT10 :1; + unsigned NVMDAT11 :1; + unsigned NVMDAT12 :1; + unsigned NVMDAT13 :1; + unsigned NVMDAT14 :1; + unsigned NVMDAT15 :1; + }; +} NVMDATHbits_t; +extern volatile NVMDATHbits_t NVMDATHbits __attribute__((address(0x047))); +# 1026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char VREGCON __attribute__((address(0x048))); + +__asm("VREGCON equ 048h"); + + +typedef union { + struct { + unsigned VREGPM :2; + unsigned :2; + unsigned PMSYS :2; + }; + struct { + unsigned VREGPM0 :1; + unsigned VREGPM1 :1; + unsigned :2; + unsigned PMSYS0 :1; + unsigned PMSYS1 :1; + }; +} VREGCONbits_t; +extern volatile VREGCONbits_t VREGCONbits __attribute__((address(0x048))); +# 1080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BORCON __attribute__((address(0x049))); + +__asm("BORCON equ 049h"); + + +typedef union { + struct { + unsigned BORRDY :1; + unsigned :6; + unsigned SBOREN :1; + }; +} BORCONbits_t; +extern volatile BORCONbits_t BORCONbits __attribute__((address(0x049))); +# 1107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON0 __attribute__((address(0x04A))); + +__asm("HLVDCON0 equ 04Ah"); + + +typedef union { + struct { + unsigned INTL :1; + unsigned INTH :1; + unsigned :2; + unsigned RDY :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned HLVDINTL :1; + unsigned HLVDINTH :1; + unsigned :2; + unsigned HLVDRDY :1; + unsigned HLVDOUT :1; + unsigned :1; + unsigned HLVDEN :1; + }; +} HLVDCON0bits_t; +extern volatile HLVDCON0bits_t HLVDCON0bits __attribute__((address(0x04A))); +# 1187 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char HLVDCON1 __attribute__((address(0x04B))); + +__asm("HLVDCON1 equ 04Bh"); + + +typedef union { + struct { + unsigned SEL :4; + }; + struct { + unsigned SEL0 :1; + unsigned SEL1 :1; + unsigned SEL2 :1; + unsigned SEL3 :1; + }; + struct { + unsigned HLVDSEL0 :1; + unsigned HLVDSEL1 :1; + unsigned HLVDSEL2 :1; + unsigned HLVDSEL3 :1; + }; +} HLVDCON1bits_t; +extern volatile HLVDCON1bits_t HLVDCON1bits __attribute__((address(0x04B))); +# 1259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ZCDCON __attribute__((address(0x04C))); + +__asm("ZCDCON equ 04Ch"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + unsigned :2; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned SEN :1; + }; + struct { + unsigned ZCDINTN :1; + unsigned ZCDINTP :1; + unsigned :2; + unsigned ZCDPOL :1; + unsigned ZCDOUT :1; + unsigned :1; + unsigned ZCDSEN :1; + }; +} ZCDCONbits_t; +extern volatile ZCDCONbits_t ZCDCONbits __attribute__((address(0x04C))); +# 1339 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD0 __attribute__((address(0x060))); + +__asm("PMD0 equ 060h"); + + +typedef union { + struct { + unsigned IOCMD :1; + unsigned CLKRMD :1; + unsigned :1; + unsigned SCANMD :1; + unsigned CRCMD :1; + unsigned HLVDMD :1; + unsigned FVRMD :1; + unsigned SYSCMD :1; + }; + struct { + unsigned :5; + unsigned LVDMD :1; + }; +} PMD0bits_t; +extern volatile PMD0bits_t PMD0bits __attribute__((address(0x060))); +# 1405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD1 __attribute__((address(0x061))); + +__asm("PMD1 equ 061h"); + + +typedef union { + struct { + unsigned TMR0MD :1; + unsigned TMR1MD :1; + unsigned TMR2MD :1; + unsigned TMR3MD :1; + unsigned TMR4MD :1; + unsigned TMR5MD :1; + unsigned TMR6MD :1; + unsigned SMT1MD :1; + }; +} PMD1bits_t; +extern volatile PMD1bits_t PMD1bits __attribute__((address(0x061))); +# 1467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD2 __attribute__((address(0x062))); + +__asm("PMD2 equ 062h"); + + +typedef union { + struct { + unsigned TU16AMD :1; + unsigned TU16BMD :1; + unsigned :5; + unsigned CANMD :1; + }; + struct { + unsigned TU1MD :1; + unsigned TU2MD :1; + }; +} PMD2bits_t; +extern volatile PMD2bits_t PMD2bits __attribute__((address(0x062))); +# 1514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD3 __attribute__((address(0x063))); + +__asm("PMD3 equ 063h"); + + +typedef union { + struct { + unsigned ZCDMD :1; + unsigned CM1MD :1; + unsigned CM2MD :1; + unsigned :2; + unsigned ADCMD :1; + unsigned DACMD :1; + unsigned ACTMD :1; + }; +} PMD3bits_t; +extern volatile PMD3bits_t PMD3bits __attribute__((address(0x063))); +# 1565 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD4 __attribute__((address(0x064))); + +__asm("PMD4 equ 064h"); + + +typedef union { + struct { + unsigned NCO1MD :1; + unsigned NCO2MD :1; + unsigned NCO3MD :1; + unsigned DSM1MD :1; + unsigned CWG1MD :1; + unsigned CWG2MD :1; + unsigned CWG3MD :1; + }; +} PMD4bits_t; +extern volatile PMD4bits_t PMD4bits __attribute__((address(0x064))); +# 1621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD5 __attribute__((address(0x065))); + +__asm("PMD5 equ 065h"); + + +typedef union { + struct { + unsigned CCP1MD :1; + unsigned CCP2MD :1; + unsigned CCP3MD :1; + unsigned :1; + unsigned PWM1MD :1; + unsigned PWM2MD :1; + unsigned PWM3MD :1; + unsigned PWM4MD :1; + }; +} PMD5bits_t; +extern volatile PMD5bits_t PMD5bits __attribute__((address(0x065))); +# 1678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD6 __attribute__((address(0x066))); + +__asm("PMD6 equ 066h"); + + +typedef union { + struct { + unsigned I2C1MD :1; + unsigned SPI1MD :1; + unsigned SPI2MD :1; + unsigned U1MD :1; + unsigned U2MD :1; + unsigned U3MD :1; + unsigned U4MD :1; + unsigned U5MD :1; + }; +} PMD6bits_t; +extern volatile PMD6bits_t PMD6bits __attribute__((address(0x066))); +# 1740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD7 __attribute__((address(0x067))); + +__asm("PMD7 equ 067h"); + + +typedef union { + struct { + unsigned CLC1MD :1; + unsigned CLC2MD :1; + unsigned CLC3MD :1; + unsigned CLC4MD :1; + unsigned CLC5MD :1; + unsigned CLC6MD :1; + unsigned CLC7MD :1; + unsigned CLC8MD :1; + }; +} PMD7bits_t; +extern volatile PMD7bits_t PMD7bits __attribute__((address(0x067))); +# 1802 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PMD8 __attribute__((address(0x068))); + +__asm("PMD8 equ 068h"); + + +typedef union { + struct { + unsigned DMA1MD :1; + unsigned DMA2MD :1; + unsigned DMA3MD :1; + unsigned DMA4MD :1; + unsigned DMA5MD :1; + unsigned DMA6MD :1; + unsigned DMA7MD :1; + unsigned DMA8MD :1; + }; +} PMD8bits_t; +extern volatile PMD8bits_t PMD8bits __attribute__((address(0x068))); +# 1864 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON0 __attribute__((address(0x06A))); + +__asm("MD1CON0 equ 06Ah"); + + +typedef union { + struct { + unsigned BIT :1; + unsigned :3; + unsigned OPOL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MD1BIT :1; + unsigned :3; + unsigned MD1OPOL :1; + unsigned MD1OUT :1; + unsigned :1; + unsigned MD1EN :1; + }; +} MD1CON0bits_t; +extern volatile MD1CON0bits_t MD1CON0bits __attribute__((address(0x06A))); +# 1932 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CON1 __attribute__((address(0x06B))); + +__asm("MD1CON1 equ 06Bh"); + + +typedef union { + struct { + unsigned CLSYNC :1; + unsigned CLPOL :1; + unsigned :2; + unsigned CHSYNC :1; + unsigned CHPOL :1; + }; + struct { + unsigned MD1CLSYNC :1; + unsigned MD1CLPOL :1; + unsigned :2; + unsigned MD1CHSYNC :1; + unsigned MD1CHPOL :1; + }; +} MD1CON1bits_t; +extern volatile MD1CON1bits_t MD1CON1bits __attribute__((address(0x06B))); +# 1998 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRC __attribute__((address(0x06C))); + +__asm("MD1SRC equ 06Ch"); + + +typedef union { + struct { + unsigned MS :8; + }; + struct { + unsigned MS0 :1; + unsigned MS1 :1; + unsigned MS2 :1; + unsigned MS3 :1; + unsigned MS4 :1; + unsigned MS5 :1; + }; + struct { + unsigned MD1MS :8; + }; + struct { + unsigned MD1MS0 :1; + unsigned MD1MS1 :1; + unsigned MD1MS2 :1; + unsigned MD1MS3 :1; + unsigned MD1MS4 :1; + unsigned MD1MS5 :1; + }; +} MD1SRCbits_t; +extern volatile MD1SRCbits_t MD1SRCbits __attribute__((address(0x06C))); +# 2102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARL __attribute__((address(0x06D))); + +__asm("MD1CARL equ 06Dh"); + + +typedef union { + struct { + unsigned CL :8; + }; + struct { + unsigned CL0 :1; + unsigned CL1 :1; + unsigned CL2 :1; + unsigned CL3 :1; + unsigned CL4 :1; + }; + struct { + unsigned MD1CL :8; + }; + struct { + unsigned MD1CL0 :1; + unsigned MD1CL1 :1; + unsigned MD1CL2 :1; + unsigned MD1CL3 :1; + unsigned MD1CL4 :1; + }; +} MD1CARLbits_t; +extern volatile MD1CARLbits_t MD1CARLbits __attribute__((address(0x06D))); +# 2194 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARH __attribute__((address(0x06E))); + +__asm("MD1CARH equ 06Eh"); + + +typedef union { + struct { + unsigned CH :8; + }; + struct { + unsigned CH0 :1; + unsigned CH1 :1; + unsigned CH2 :1; + unsigned CH3 :1; + unsigned CH4 :1; + }; + struct { + unsigned MD1CH :8; + }; + struct { + unsigned MD1CH0 :1; + unsigned MD1CH1 :1; + unsigned MD1CH2 :1; + unsigned MD1CH3 :1; + unsigned MD1CH4 :1; + }; +} MD1CARHbits_t; +extern volatile MD1CARHbits_t MD1CARHbits __attribute__((address(0x06E))); +# 2286 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CMOUT __attribute__((address(0x06F))); + +__asm("CMOUT equ 06Fh"); + + +typedef union { + struct { + unsigned MC1OUT :1; + unsigned MC2OUT :1; + }; +} CMOUTbits_t; +extern volatile CMOUTbits_t CMOUTbits __attribute__((address(0x06F))); +# 2312 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON0 __attribute__((address(0x070))); + +__asm("CM1CON0 equ 070h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C1SYNC :1; + unsigned C1HYS :1; + unsigned :2; + unsigned C1POL :1; + unsigned :1; + unsigned C1OUT :1; + unsigned C1EN :1; + }; +} CM1CON0bits_t; +extern volatile CM1CON0bits_t CM1CON0bits __attribute__((address(0x070))); +# 2392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1CON1 __attribute__((address(0x071))); + +__asm("CM1CON1 equ 071h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C1INTN :1; + unsigned C1INTP :1; + }; +} CM1CON1bits_t; +extern volatile CM1CON1bits_t CM1CON1bits __attribute__((address(0x071))); +# 2432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1NCH __attribute__((address(0x072))); + +__asm("CM1NCH equ 072h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C1NCH0 :1; + unsigned C1NCH1 :1; + unsigned C1NCH2 :1; + }; +} CM1NCHbits_t; +extern volatile CM1NCHbits_t CM1NCHbits __attribute__((address(0x072))); +# 2492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM1PCH __attribute__((address(0x073))); + +__asm("CM1PCH equ 073h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C1PCH0 :1; + unsigned C1PCH1 :1; + unsigned C1PCH2 :1; + }; +} CM1PCHbits_t; +extern volatile CM1PCHbits_t CM1PCHbits __attribute__((address(0x073))); +# 2552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON0 __attribute__((address(0x074))); + +__asm("CM2CON0 equ 074h"); + + +typedef union { + struct { + unsigned SYNC :1; + unsigned HYS :1; + unsigned :2; + unsigned POL :1; + unsigned :1; + unsigned OUT :1; + unsigned EN :1; + }; + struct { + unsigned C2SYNC :1; + unsigned C2HYS :1; + unsigned :2; + unsigned C2POL :1; + unsigned :1; + unsigned C2OUT :1; + unsigned C2EN :1; + }; +} CM2CON0bits_t; +extern volatile CM2CON0bits_t CM2CON0bits __attribute__((address(0x074))); +# 2632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2CON1 __attribute__((address(0x075))); + +__asm("CM2CON1 equ 075h"); + + +typedef union { + struct { + unsigned INTN :1; + unsigned INTP :1; + }; + struct { + unsigned C2INTN :1; + unsigned C2INTP :1; + }; +} CM2CON1bits_t; +extern volatile CM2CON1bits_t CM2CON1bits __attribute__((address(0x075))); +# 2672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2NCH __attribute__((address(0x076))); + +__asm("CM2NCH equ 076h"); + + +typedef union { + struct { + unsigned NCH :3; + }; + struct { + unsigned NCH0 :1; + unsigned NCH1 :1; + unsigned NCH2 :1; + }; + struct { + unsigned C2NCH0 :1; + unsigned C2NCH1 :1; + unsigned C2NCH2 :1; + }; +} CM2NCHbits_t; +extern volatile CM2NCHbits_t CM2NCHbits __attribute__((address(0x076))); +# 2732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CM2PCH __attribute__((address(0x077))); + +__asm("CM2PCH equ 077h"); + + +typedef union { + struct { + unsigned PCH :3; + }; + struct { + unsigned PCH0 :1; + unsigned PCH1 :1; + unsigned PCH2 :1; + }; + struct { + unsigned C2PCH0 :1; + unsigned C2PCH1 :1; + unsigned C2PCH2 :1; + }; +} CM2PCHbits_t; +extern volatile CM2PCHbits_t CM2PCHbits __attribute__((address(0x077))); +# 2792 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON0 __attribute__((address(0x078))); + +__asm("WDTCON0 equ 078h"); + + +typedef union { + struct { + unsigned SEN :1; + unsigned WDTPS :5; + }; + struct { + unsigned SWDTEN :1; + }; + struct { + unsigned WDTSEN :1; + }; + struct { + unsigned :1; + unsigned WDTPS0 :1; + unsigned WDTPS1 :1; + unsigned WDTPS2 :1; + unsigned WDTPS3 :1; + unsigned WDTPS4 :1; + }; +} WDTCON0bits_t; +extern volatile WDTCON0bits_t WDTCON0bits __attribute__((address(0x078))); +# 2867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTCON1 __attribute__((address(0x079))); + +__asm("WDTCON1 equ 079h"); + + +typedef union { + struct { + unsigned WINDOW :3; + unsigned :1; + unsigned WDTCS :3; + }; + struct { + unsigned WINDOW0 :1; + unsigned WINDOW1 :1; + unsigned WINDOW2 :1; + }; + struct { + unsigned WDTWINDOW :3; + }; + struct { + unsigned WDTWINDOW0 :1; + unsigned WDTWINDOW1 :1; + unsigned WDTWINDOW2 :1; + unsigned :1; + unsigned WDTCS0 :1; + unsigned WDTCS1 :1; + unsigned WDTCS2 :1; + }; +} WDTCON1bits_t; +extern volatile WDTCON1bits_t WDTCON1bits __attribute__((address(0x079))); +# 2961 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSL __attribute__((address(0x07A))); + +__asm("WDTPSL equ 07Ah"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT0 :1; + unsigned PSCNT1 :1; + unsigned PSCNT2 :1; + unsigned PSCNT3 :1; + unsigned PSCNT4 :1; + unsigned PSCNT5 :1; + unsigned PSCNT6 :1; + unsigned PSCNT7 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT0 :1; + unsigned WDTPSCNT1 :1; + unsigned WDTPSCNT2 :1; + unsigned WDTPSCNT3 :1; + unsigned WDTPSCNT4 :1; + unsigned WDTPSCNT5 :1; + unsigned WDTPSCNT6 :1; + unsigned WDTPSCNT7 :1; + }; +} WDTPSLbits_t; +extern volatile WDTPSLbits_t WDTPSLbits __attribute__((address(0x07A))); +# 3089 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTPSH __attribute__((address(0x07B))); + +__asm("WDTPSH equ 07Bh"); + + +typedef union { + struct { + unsigned PSCNT :8; + }; + struct { + unsigned PSCNT8 :1; + unsigned PSCNT9 :1; + unsigned PSCNT10 :1; + unsigned PSCNT11 :1; + unsigned PSCNT12 :1; + unsigned PSCNT13 :1; + unsigned PSCNT14 :1; + unsigned PSCNT15 :1; + }; + struct { + unsigned WDTPSCNT :8; + }; + struct { + unsigned WDTPSCNT8 :1; + unsigned WDTPSCNT9 :1; + unsigned WDTPSCNT10 :1; + unsigned WDTPSCNT11 :1; + unsigned WDTPSCNT12 :1; + unsigned WDTPSCNT13 :1; + unsigned WDTPSCNT14 :1; + unsigned WDTPSCNT15 :1; + }; +} WDTPSHbits_t; +extern volatile WDTPSHbits_t WDTPSHbits __attribute__((address(0x07B))); +# 3217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WDTTMR __attribute__((address(0x07C))); + +__asm("WDTTMR equ 07Ch"); + + +typedef union { + struct { + unsigned PSCNT16 :1; + unsigned PSCNT17 :1; + unsigned STATE :1; + unsigned WDTTMR :5; + }; + struct { + unsigned WDTPSCNT16 :1; + unsigned WDTPSCNT17 :1; + unsigned WDTSTATE :1; + unsigned WDTTMR0 :1; + unsigned WDTTMR1 :1; + unsigned WDTTMR2 :1; + unsigned WDTTMR3 :1; + unsigned WDTTMR4 :1; + }; +} WDTTMRbits_t; +extern volatile WDTTMRbits_t WDTTMRbits __attribute__((address(0x07C))); +# 3305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1DAT __attribute__((address(0x07D))); + +__asm("DAC1DAT equ 07Dh"); + + + + +extern volatile unsigned char DAC1DATL __attribute__((address(0x07D))); + +__asm("DAC1DATL equ 07Dh"); + + +typedef union { + struct { + unsigned DAC1R :8; + }; + struct { + unsigned DAC1R0 :1; + unsigned DAC1R1 :1; + unsigned DAC1R2 :1; + unsigned DAC1R3 :1; + unsigned DAC1R4 :1; + unsigned DAC1R5 :1; + unsigned DAC1R6 :1; + unsigned DAC1R7 :1; + }; + struct { + unsigned DAC1RL :8; + }; +} DAC1DATLbits_t; +extern volatile DAC1DATLbits_t DAC1DATLbits __attribute__((address(0x07D))); +# 3390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DAC1CON __attribute__((address(0x07F))); + +__asm("DAC1CON equ 07Fh"); + + +typedef union { + struct { + unsigned NSS :2; + unsigned PSS :2; + unsigned OE :3; + unsigned EN :1; + }; + struct { + unsigned DAC1NSS :2; + unsigned DAC1PSS0 :1; + unsigned DAC1PSS1 :1; + unsigned DAC1OE :3; + unsigned DAC1EN :1; + }; + struct { + unsigned NSS0 :1; + unsigned :1; + unsigned PSS0 :1; + unsigned PSS1 :1; + unsigned OE0 :1; + unsigned OE1 :1; + }; +} DAC1CONbits_t; +extern volatile DAC1CONbits_t DAC1CONbits __attribute__((address(0x07F))); +# 3493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1RXB __attribute__((address(0x080))); + +__asm("SPI1RXB equ 080h"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI1RXBbits_t; +extern volatile SPI1RXBbits_t SPI1RXBbits __attribute__((address(0x080))); +# 3563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TXB __attribute__((address(0x081))); + +__asm("SPI1TXB equ 081h"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI1TXBbits_t; +extern volatile SPI1TXBbits_t SPI1TXBbits __attribute__((address(0x081))); +# 3633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI1TCNT __attribute__((address(0x082))); + +__asm("SPI1TCNT equ 082h"); + + + + +extern volatile unsigned char SPI1TCNTL __attribute__((address(0x082))); + +__asm("SPI1TCNTL equ 082h"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI1TCNTLbits_t; +extern volatile SPI1TCNTLbits_t SPI1TCNTLbits __attribute__((address(0x082))); +# 3660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TCNTH __attribute__((address(0x083))); + +__asm("SPI1TCNTH equ 083h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI1TCNTHbits_t; +extern volatile SPI1TCNTHbits_t SPI1TCNTHbits __attribute__((address(0x083))); +# 3680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON0 __attribute__((address(0x084))); + +__asm("SPI1CON0 equ 084h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI1BMODE :1; + unsigned SPI1MST :1; + unsigned SPI1LSBF :1; + unsigned :4; + unsigned SPI1SPIEN :1; + }; +} SPI1CON0bits_t; +extern volatile SPI1CON0bits_t SPI1CON0bits __attribute__((address(0x084))); +# 3746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON1 __attribute__((address(0x085))); + +__asm("SPI1CON1 equ 085h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI1SDOP :1; + unsigned SPI1SDIP :1; + unsigned SPI1SSP :1; + unsigned :1; + unsigned SPI1FST :1; + unsigned SPI1CKP :1; + unsigned SPI1CKE :1; + unsigned SPI1SMP :1; + }; +} SPI1CON1bits_t; +extern volatile SPI1CON1bits_t SPI1CON1bits __attribute__((address(0x085))); +# 3848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CON2 __attribute__((address(0x086))); + +__asm("SPI1CON2 equ 086h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI1RXR :1; + unsigned SPI1TXR :1; + unsigned SPI1SSET :1; + unsigned :3; + unsigned SPI1SSFLT :1; + unsigned SPI1BUSY :1; + }; +} SPI1CON2bits_t; +extern volatile SPI1CON2bits_t SPI1CON2bits __attribute__((address(0x086))); +# 3926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1STATUS __attribute__((address(0x087))); + +__asm("SPI1STATUS equ 087h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI1RXBF :1; + unsigned :1; + unsigned SPI1CLRBF :1; + unsigned SPI1RXRE :1; + unsigned :1; + unsigned SPI1TXBE :1; + unsigned :1; + unsigned SPI1TXWE :1; + }; +} SPI1STATUSbits_t; +extern volatile SPI1STATUSbits_t SPI1STATUSbits __attribute__((address(0x087))); +# 4008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1TWIDTH __attribute__((address(0x088))); + +__asm("SPI1TWIDTH equ 088h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI1TWIDTHbits_t; +extern volatile SPI1TWIDTHbits_t SPI1TWIDTHbits __attribute__((address(0x088))); +# 4048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1BAUD __attribute__((address(0x089))); + +__asm("SPI1BAUD equ 089h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI1BAUDbits_t; +extern volatile SPI1BAUDbits_t SPI1BAUDbits __attribute__((address(0x089))); +# 4118 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTF __attribute__((address(0x08A))); + +__asm("SPI1INTF equ 08Ah"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIF :1; + unsigned SPI1RXOIF :1; + unsigned :1; + unsigned SPI1EOSIF :1; + unsigned SPI1SOSIF :1; + unsigned SPI1TCZIF :1; + unsigned SPI1SRMTIF :1; + }; +} SPI1INTFbits_t; +extern volatile SPI1INTFbits_t SPI1INTFbits __attribute__((address(0x08A))); +# 4210 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1INTE __attribute__((address(0x08B))); + +__asm("SPI1INTE equ 08Bh"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI1TXUIE :1; + unsigned SPI1RXOIE :1; + unsigned :1; + unsigned SPI1EOSIE :1; + unsigned SPI1SOSIE :1; + unsigned SPI1TCZIE :1; + unsigned SPI1SRMTIE :1; + }; +} SPI1INTEbits_t; +extern volatile SPI1INTEbits_t SPI1INTEbits __attribute__((address(0x08B))); +# 4302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1CLK __attribute__((address(0x08C))); + +__asm("SPI1CLK equ 08Ch"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI1CLKSEL :8; + }; + struct { + unsigned SPI1CLKSEL0 :1; + unsigned SPI1CLKSEL1 :1; + unsigned SPI1CLKSEL2 :1; + unsigned SPI1CLKSEL3 :1; + unsigned SPI1CLKSEL4 :1; + }; +} SPI1CLKbits_t; +extern volatile SPI1CLKbits_t SPI1CLKbits __attribute__((address(0x08C))); +# 4394 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2RXB __attribute__((address(0x08D))); + +__asm("SPI2RXB equ 08Dh"); + + +typedef union { + struct { + unsigned RXB :8; + }; + struct { + unsigned RXB0 :1; + unsigned RXB1 :1; + unsigned RXB2 :1; + unsigned RXB3 :1; + unsigned RXB4 :1; + unsigned RXB5 :1; + unsigned RXB6 :1; + unsigned RXB7 :1; + }; +} SPI2RXBbits_t; +extern volatile SPI2RXBbits_t SPI2RXBbits __attribute__((address(0x08D))); +# 4464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TXB __attribute__((address(0x08E))); + +__asm("SPI2TXB equ 08Eh"); + + +typedef union { + struct { + unsigned TXB :8; + }; + struct { + unsigned TXB0 :1; + unsigned TXB1 :1; + unsigned TXB2 :1; + unsigned TXB3 :1; + unsigned TXB4 :1; + unsigned TXB5 :1; + unsigned TXB6 :1; + unsigned TXB7 :1; + }; +} SPI2TXBbits_t; +extern volatile SPI2TXBbits_t SPI2TXBbits __attribute__((address(0x08E))); +# 4534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short SPI2TCNT __attribute__((address(0x08F))); + +__asm("SPI2TCNT equ 08Fh"); + + + + +extern volatile unsigned char SPI2TCNTL __attribute__((address(0x08F))); + +__asm("SPI2TCNTL equ 08Fh"); + + +typedef union { + struct { + unsigned TCNTL :8; + }; +} SPI2TCNTLbits_t; +extern volatile SPI2TCNTLbits_t SPI2TCNTLbits __attribute__((address(0x08F))); +# 4561 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TCNTH __attribute__((address(0x090))); + +__asm("SPI2TCNTH equ 090h"); + + +typedef union { + struct { + unsigned TCNTH :3; + }; +} SPI2TCNTHbits_t; +extern volatile SPI2TCNTHbits_t SPI2TCNTHbits __attribute__((address(0x090))); +# 4581 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON0 __attribute__((address(0x091))); + +__asm("SPI2CON0 equ 091h"); + + +typedef union { + struct { + unsigned BMODE :1; + unsigned MST :1; + unsigned LSBF :1; + unsigned :4; + unsigned EN :1; + }; + struct { + unsigned SPI2BMODE :1; + unsigned SPI2MST :1; + unsigned SPI2LSBF :1; + unsigned :4; + unsigned SPI2SPIEN :1; + }; +} SPI2CON0bits_t; +extern volatile SPI2CON0bits_t SPI2CON0bits __attribute__((address(0x091))); +# 4647 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON1 __attribute__((address(0x092))); + +__asm("SPI2CON1 equ 092h"); + + +typedef union { + struct { + unsigned SDOP :1; + unsigned SDIP :1; + unsigned SSP :1; + unsigned :1; + unsigned FST :1; + unsigned CKP :1; + unsigned CKE :1; + unsigned SMP :1; + }; + struct { + unsigned SPI2SDOP :1; + unsigned SPI2SDIP :1; + unsigned SPI2SSP :1; + unsigned :1; + unsigned SPI2FST :1; + unsigned SPI2CKP :1; + unsigned SPI2CKE :1; + unsigned SPI2SMP :1; + }; +} SPI2CON1bits_t; +extern volatile SPI2CON1bits_t SPI2CON1bits __attribute__((address(0x092))); +# 4749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CON2 __attribute__((address(0x093))); + +__asm("SPI2CON2 equ 093h"); + + +typedef union { + struct { + unsigned RXR :1; + unsigned TXR :1; + unsigned SSET :1; + unsigned :3; + unsigned SSFLT :1; + unsigned BUSY :1; + }; + struct { + unsigned SPI2RXR :1; + unsigned SPI2TXR :1; + unsigned SPI2SSET :1; + unsigned :3; + unsigned SPI2SSFLT :1; + unsigned SPI2BUSY :1; + }; +} SPI2CON2bits_t; +extern volatile SPI2CON2bits_t SPI2CON2bits __attribute__((address(0x093))); +# 4827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2STATUS __attribute__((address(0x094))); + +__asm("SPI2STATUS equ 094h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; + struct { + unsigned SPI2RXBF :1; + unsigned :1; + unsigned SPI2CLRBF :1; + unsigned SPI2RXRE :1; + unsigned :1; + unsigned SPI2TXBE :1; + unsigned :1; + unsigned SPI2TXWE :1; + }; +} SPI2STATUSbits_t; +extern volatile SPI2STATUSbits_t SPI2STATUSbits __attribute__((address(0x094))); +# 4909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2TWIDTH __attribute__((address(0x095))); + +__asm("SPI2TWIDTH equ 095h"); + + +typedef union { + struct { + unsigned TWIDTH :3; + }; + struct { + unsigned TWIDTH0 :1; + unsigned TWIDTH1 :1; + unsigned TWIDTH2 :1; + }; +} SPI2TWIDTHbits_t; +extern volatile SPI2TWIDTHbits_t SPI2TWIDTHbits __attribute__((address(0x095))); +# 4949 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2BAUD __attribute__((address(0x096))); + +__asm("SPI2BAUD equ 096h"); + + +typedef union { + struct { + unsigned BAUD :8; + }; + struct { + unsigned BAUD0 :1; + unsigned BAUD1 :1; + unsigned BAUD2 :1; + unsigned BAUD3 :1; + unsigned BAUD4 :1; + unsigned BAUD5 :1; + unsigned BAUD6 :1; + unsigned BAUD7 :1; + }; +} SPI2BAUDbits_t; +extern volatile SPI2BAUDbits_t SPI2BAUDbits __attribute__((address(0x096))); +# 5019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTF __attribute__((address(0x097))); + +__asm("SPI2INTF equ 097h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIF :1; + unsigned RXOIF :1; + unsigned :1; + unsigned EOSIF :1; + unsigned SOSIF :1; + unsigned TCZIF :1; + unsigned SRMTIF :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIF :1; + unsigned SPI2RXOIF :1; + unsigned :1; + unsigned SPI2EOSIF :1; + unsigned SPI2SOSIF :1; + unsigned SPI2TCZIF :1; + unsigned SPI2SRMTIF :1; + }; +} SPI2INTFbits_t; +extern volatile SPI2INTFbits_t SPI2INTFbits __attribute__((address(0x097))); +# 5111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2INTE __attribute__((address(0x098))); + +__asm("SPI2INTE equ 098h"); + + +typedef union { + struct { + unsigned :1; + unsigned TXUIE :1; + unsigned RXOIE :1; + unsigned :1; + unsigned EOSIE :1; + unsigned SOSIE :1; + unsigned TCZIE :1; + unsigned SRMTIE :1; + }; + struct { + unsigned :1; + unsigned SPI2TXUIE :1; + unsigned SPI2RXOIE :1; + unsigned :1; + unsigned SPI2EOSIE :1; + unsigned SPI2SOSIE :1; + unsigned SPI2TCZIE :1; + unsigned SPI2SRMTIE :1; + }; +} SPI2INTEbits_t; +extern volatile SPI2INTEbits_t SPI2INTEbits __attribute__((address(0x098))); +# 5203 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2CLK __attribute__((address(0x099))); + +__asm("SPI2CLK equ 099h"); + + +typedef union { + struct { + unsigned CLKSEL :8; + }; + struct { + unsigned CLKSEL0 :1; + unsigned CLKSEL1 :1; + unsigned CLKSEL2 :1; + unsigned CLKSEL3 :1; + unsigned CLKSEL4 :1; + }; + struct { + unsigned SPI2CLKSEL :8; + }; + struct { + unsigned SPI2CLKSEL0 :1; + unsigned SPI2CLKSEL1 :1; + unsigned SPI2CLKSEL2 :1; + unsigned SPI2CLKSEL3 :1; + unsigned SPI2CLKSEL4 :1; + }; +} SPI2CLKbits_t; +extern volatile SPI2CLKbits_t SPI2CLKbits __attribute__((address(0x099))); +# 5295 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ACTCON __attribute__((address(0x0AC))); + +__asm("ACTCON equ 0ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned ACTORS :1; + unsigned :1; + unsigned ACTLOCK :1; + unsigned :2; + unsigned ACTUD :1; + unsigned ACTEN :1; + }; +} ACTCONbits_t; +extern volatile ACTCONbits_t ACTCONbits __attribute__((address(0x0AC))); +# 5336 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON1 __attribute__((address(0x0AD))); + +__asm("OSCCON1 equ 0ADh"); + + +typedef union { + struct { + unsigned NDIV :4; + unsigned NOSC :3; + }; + struct { + unsigned NDIV0 :1; + unsigned NDIV1 :1; + unsigned NDIV2 :1; + unsigned NDIV3 :1; + unsigned NOSC0 :1; + unsigned NOSC1 :1; + unsigned NOSC2 :1; + }; +} OSCCON1bits_t; +extern volatile OSCCON1bits_t OSCCON1bits __attribute__((address(0x0AD))); +# 5406 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON2 __attribute__((address(0x0AE))); + +__asm("OSCCON2 equ 0AEh"); + + +typedef union { + struct { + unsigned CDIV :4; + unsigned COSC :3; + }; + struct { + unsigned CDIV0 :1; + unsigned CDIV1 :1; + unsigned CDIV2 :1; + unsigned CDIV3 :1; + unsigned COSC0 :1; + unsigned COSC1 :1; + unsigned COSC2 :1; + }; +} OSCCON2bits_t; +extern volatile OSCCON2bits_t OSCCON2bits __attribute__((address(0x0AE))); +# 5476 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCCON3 __attribute__((address(0x0AF))); + +__asm("OSCCON3 equ 0AFh"); + + +typedef union { + struct { + unsigned :3; + unsigned NOSCR :1; + unsigned ORDY :1; + unsigned :1; + unsigned SOSCPWR :1; + unsigned CSWHOLD :1; + }; +} OSCCON3bits_t; +extern volatile OSCCON3bits_t OSCCON3bits __attribute__((address(0x0AF))); +# 5516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCTUNE __attribute__((address(0x0B0))); + +__asm("OSCTUNE equ 0B0h"); + + +typedef union { + struct { + unsigned TUN :6; + }; + struct { + unsigned TUN0 :1; + unsigned TUN1 :1; + unsigned TUN2 :1; + unsigned TUN3 :1; + unsigned TUN4 :1; + unsigned TUN5 :1; + }; +} OSCTUNEbits_t; +extern volatile OSCTUNEbits_t OSCTUNEbits __attribute__((address(0x0B0))); +# 5574 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCFRQ __attribute__((address(0x0B1))); + +__asm("OSCFRQ equ 0B1h"); + + +extern volatile unsigned char OSCFREQ __attribute__((address(0x0B1))); + +__asm("OSCFREQ equ 0B1h"); + + +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFRQbits_t; +extern volatile OSCFRQbits_t OSCFRQbits __attribute__((address(0x0B1))); +# 5623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned HFFRQ :4; + }; + struct { + unsigned FRQ0 :1; + unsigned FRQ1 :1; + unsigned FRQ2 :1; + unsigned FRQ3 :1; + }; +} OSCFREQbits_t; +extern volatile OSCFREQbits_t OSCFREQbits __attribute__((address(0x0B1))); +# 5664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCSTAT __attribute__((address(0x0B2))); + +__asm("OSCSTAT equ 0B2h"); + + +extern volatile unsigned char OSCSTAT1 __attribute__((address(0x0B2))); + +__asm("OSCSTAT1 equ 0B2h"); + + +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTATbits_t; +extern volatile OSCSTATbits_t OSCSTATbits __attribute__((address(0x0B2))); +# 5724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PLLR :1; + unsigned :1; + unsigned ADOR :1; + unsigned SOR :1; + unsigned LFOR :1; + unsigned MFOR :1; + unsigned HFOR :1; + unsigned EXTOR :1; + }; +} OSCSTAT1bits_t; +extern volatile OSCSTAT1bits_t OSCSTAT1bits __attribute__((address(0x0B2))); +# 5776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char OSCEN __attribute__((address(0x0B3))); + +__asm("OSCEN equ 0B3h"); + + +typedef union { + struct { + unsigned PLLEN :1; + unsigned :1; + unsigned ADOEN :1; + unsigned SOSCEN :1; + unsigned LFOEN :1; + unsigned MFOEN :1; + unsigned HFOEN :1; + unsigned EXTOEN :1; + }; +} OSCENbits_t; +extern volatile OSCENbits_t OSCENbits __attribute__((address(0x0B3))); +# 5833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRLOCK __attribute__((address(0x0B4))); + +__asm("PRLOCK equ 0B4h"); + + +typedef union { + struct { + unsigned PRLOCKED :1; + }; +} PRLOCKbits_t; +extern volatile PRLOCKbits_t PRLOCKbits __attribute__((address(0x0B4))); +# 5853 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANPR __attribute__((address(0x0B5))); + +__asm("SCANPR equ 0B5h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned SCANPR :3; + }; + struct { + unsigned SCANPR0 :1; + unsigned SCANPR1 :1; + unsigned SCANPR2 :1; + }; +} SCANPRbits_t; +extern volatile SCANPRbits_t SCANPRbits __attribute__((address(0x0B5))); +# 5921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA1PR __attribute__((address(0x0B6))); + +__asm("DMA1PR equ 0B6h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA1PR :3; + }; + struct { + unsigned DMA1PR0 :1; + unsigned DMA1PR1 :1; + unsigned DMA1PR2 :1; + }; +} DMA1PRbits_t; +extern volatile DMA1PRbits_t DMA1PRbits __attribute__((address(0x0B6))); +# 5989 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA2PR __attribute__((address(0x0B7))); + +__asm("DMA2PR equ 0B7h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA2PR :3; + }; + struct { + unsigned DMA2PR0 :1; + unsigned DMA2PR1 :1; + unsigned DMA2PR2 :1; + }; +} DMA2PRbits_t; +extern volatile DMA2PRbits_t DMA2PRbits __attribute__((address(0x0B7))); +# 6057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA3PR __attribute__((address(0x0B8))); + +__asm("DMA3PR equ 0B8h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA3PR :3; + }; + struct { + unsigned DMA3PR0 :1; + unsigned DMA3PR1 :1; + unsigned DMA3PR2 :1; + }; +} DMA3PRbits_t; +extern volatile DMA3PRbits_t DMA3PRbits __attribute__((address(0x0B8))); +# 6125 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA4PR __attribute__((address(0x0B9))); + +__asm("DMA4PR equ 0B9h"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA4PR :3; + }; + struct { + unsigned DMA4PR0 :1; + unsigned DMA4PR1 :1; + unsigned DMA4PR2 :1; + }; +} DMA4PRbits_t; +extern volatile DMA4PRbits_t DMA4PRbits __attribute__((address(0x0B9))); +# 6193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA5PR __attribute__((address(0x0BA))); + +__asm("DMA5PR equ 0BAh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA5PR :3; + }; + struct { + unsigned DMA5PR0 :1; + unsigned DMA5PR1 :1; + unsigned DMA5PR2 :1; + }; +} DMA5PRbits_t; +extern volatile DMA5PRbits_t DMA5PRbits __attribute__((address(0x0BA))); +# 6261 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA6PR __attribute__((address(0x0BB))); + +__asm("DMA6PR equ 0BBh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA6PR :3; + }; + struct { + unsigned DMA6PR0 :1; + unsigned DMA6PR1 :1; + unsigned DMA6PR2 :1; + }; +} DMA6PRbits_t; +extern volatile DMA6PRbits_t DMA6PRbits __attribute__((address(0x0BB))); +# 6329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA7PR __attribute__((address(0x0BC))); + +__asm("DMA7PR equ 0BCh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA7PR :3; + }; + struct { + unsigned DMA7PR0 :1; + unsigned DMA7PR1 :1; + unsigned DMA7PR2 :1; + }; +} DMA7PRbits_t; +extern volatile DMA7PRbits_t DMA7PRbits __attribute__((address(0x0BC))); +# 6397 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMA8PR __attribute__((address(0x0BD))); + +__asm("DMA8PR equ 0BDh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned DMA8PR :3; + }; + struct { + unsigned DMA8PR0 :1; + unsigned DMA8PR1 :1; + unsigned DMA8PR2 :1; + }; +} DMA8PRbits_t; +extern volatile DMA8PRbits_t DMA8PRbits __attribute__((address(0x0BD))); +# 6465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MAINPR __attribute__((address(0x0BE))); + +__asm("MAINPR equ 0BEh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned MAINPR :3; + }; + struct { + unsigned MAINPR0 :1; + unsigned MAINPR1 :1; + unsigned MAINPR2 :1; + }; +} MAINPRbits_t; +extern volatile MAINPRbits_t MAINPRbits __attribute__((address(0x0BE))); +# 6533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ISRPR __attribute__((address(0x0BF))); + +__asm("ISRPR equ 0BFh"); + + +typedef union { + struct { + unsigned PR :3; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + }; + struct { + unsigned ISRPR :3; + }; + struct { + unsigned ISRPR0 :1; + unsigned ISRPR1 :1; + unsigned ISRPR2 :1; + }; +} ISRPRbits_t; +extern volatile ISRPRbits_t ISRPRbits __attribute__((address(0x0BF))); +# 6601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCDATA __attribute__((address(0x0D4))); + +__asm("CLCDATA equ 0D4h"); + + +typedef union { + struct { + unsigned MCLC :8; + }; + struct { + unsigned MCLC0 :1; + unsigned MCLC1 :1; + unsigned MCLC2 :1; + unsigned MCLC3 :1; + unsigned MCLC4 :1; + unsigned MCLC5 :1; + unsigned MCLC6 :1; + unsigned MCLC7 :1; + }; + struct { + unsigned CLC1OUT :1; + unsigned CLC2OUT :1; + unsigned CLC3OUT :1; + unsigned CLC4OUT :1; + unsigned CLC5OUT :1; + unsigned CLC6OUT :1; + unsigned CLC7OUT :1; + unsigned CLC8OUT :1; + }; +} CLCDATAbits_t; +extern volatile CLCDATAbits_t CLCDATAbits __attribute__((address(0x0D4))); +# 6721 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCSELECT __attribute__((address(0x0D5))); + +__asm("CLCSELECT equ 0D5h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} CLCSELECTbits_t; +extern volatile CLCSELECTbits_t CLCSELECTbits __attribute__((address(0x0D5))); +# 6761 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnCON __attribute__((address(0x0D6))); + +__asm("CLCnCON equ 0D6h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned INTN :1; + unsigned INTP :1; + unsigned OUT :1; + unsigned OE :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} CLCnCONbits_t; +extern volatile CLCnCONbits_t CLCnCONbits __attribute__((address(0x0D6))); +# 6831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnPOL __attribute__((address(0x0D7))); + +__asm("CLCnPOL equ 0D7h"); + + +typedef union { + struct { + unsigned G1POL :1; + unsigned G2POL :1; + unsigned G3POL :1; + unsigned G4POL :1; + unsigned :3; + unsigned POL :1; + }; +} CLCnPOLbits_t; +extern volatile CLCnPOLbits_t CLCnPOLbits __attribute__((address(0x0D7))); +# 6876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL0 __attribute__((address(0x0D8))); + +__asm("CLCnSEL0 equ 0D8h"); + + +typedef union { + struct { + unsigned D1S :8; + }; + struct { + unsigned D1S0 :1; + unsigned D1S1 :1; + unsigned D1S2 :1; + unsigned D1S3 :1; + unsigned D1S4 :1; + unsigned D1S5 :1; + unsigned D1S6 :1; + unsigned D1S7 :1; + }; +} CLCnSEL0bits_t; +extern volatile CLCnSEL0bits_t CLCnSEL0bits __attribute__((address(0x0D8))); +# 6946 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL1 __attribute__((address(0x0D9))); + +__asm("CLCnSEL1 equ 0D9h"); + + +typedef union { + struct { + unsigned D2S :8; + }; + struct { + unsigned D2S0 :1; + unsigned D2S1 :1; + unsigned D2S2 :1; + unsigned D2S3 :1; + unsigned D2S4 :1; + unsigned D2S5 :1; + unsigned D2S6 :1; + unsigned D2S7 :1; + }; +} CLCnSEL1bits_t; +extern volatile CLCnSEL1bits_t CLCnSEL1bits __attribute__((address(0x0D9))); +# 7016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL2 __attribute__((address(0x0DA))); + +__asm("CLCnSEL2 equ 0DAh"); + + +typedef union { + struct { + unsigned D3S :8; + }; + struct { + unsigned D3S0 :1; + unsigned D3S1 :1; + unsigned D3S2 :1; + unsigned D3S3 :1; + unsigned D3S4 :1; + unsigned D3S5 :1; + unsigned D3S6 :1; + unsigned D3S7 :1; + }; +} CLCnSEL2bits_t; +extern volatile CLCnSEL2bits_t CLCnSEL2bits __attribute__((address(0x0DA))); +# 7086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnSEL3 __attribute__((address(0x0DB))); + +__asm("CLCnSEL3 equ 0DBh"); + + +typedef union { + struct { + unsigned D4S :8; + }; + struct { + unsigned D4S0 :1; + unsigned D4S1 :1; + unsigned D4S2 :1; + unsigned D4S3 :1; + unsigned D4S4 :1; + unsigned D4S5 :1; + unsigned D4S6 :1; + unsigned D4S7 :1; + }; +} CLCnSEL3bits_t; +extern volatile CLCnSEL3bits_t CLCnSEL3bits __attribute__((address(0x0DB))); +# 7156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS0 __attribute__((address(0x0DC))); + +__asm("CLCnGLS0 equ 0DCh"); + + +typedef union { + struct { + unsigned G1D1N :1; + unsigned G1D1T :1; + unsigned G1D2N :1; + unsigned G1D2T :1; + unsigned G1D3N :1; + unsigned G1D3T :1; + unsigned G1D4N :1; + unsigned G1D4T :1; + }; +} CLCnGLS0bits_t; +extern volatile CLCnGLS0bits_t CLCnGLS0bits __attribute__((address(0x0DC))); +# 7218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS1 __attribute__((address(0x0DD))); + +__asm("CLCnGLS1 equ 0DDh"); + + +typedef union { + struct { + unsigned G2D1N :1; + unsigned G2D1T :1; + unsigned G2D2N :1; + unsigned G2D2T :1; + unsigned G2D3N :1; + unsigned G2D3T :1; + unsigned G2D4N :1; + unsigned G2D4T :1; + }; +} CLCnGLS1bits_t; +extern volatile CLCnGLS1bits_t CLCnGLS1bits __attribute__((address(0x0DD))); +# 7280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS2 __attribute__((address(0x0DE))); + +__asm("CLCnGLS2 equ 0DEh"); + + +typedef union { + struct { + unsigned G3D1N :1; + unsigned G3D1T :1; + unsigned G3D2N :1; + unsigned G3D2T :1; + unsigned G3D3N :1; + unsigned G3D3T :1; + unsigned G3D4N :1; + unsigned G3D4T :1; + }; +} CLCnGLS2bits_t; +extern volatile CLCnGLS2bits_t CLCnGLS2bits __attribute__((address(0x0DE))); +# 7342 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCnGLS3 __attribute__((address(0x0DF))); + +__asm("CLCnGLS3 equ 0DFh"); + + +typedef union { + struct { + unsigned G4D1N :1; + unsigned G4D1T :1; + unsigned G4D2N :1; + unsigned G4D2T :1; + unsigned G4D3N :1; + unsigned G4D3T :1; + unsigned G4D4N :1; + unsigned G4D4T :1; + }; +} CLCnGLS3bits_t; +extern volatile CLCnGLS3bits_t CLCnGLS3bits __attribute__((address(0x0DF))); +# 7404 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMASELECT __attribute__((address(0x0E8))); + +__asm("DMASELECT equ 0E8h"); + + +typedef union { + struct { + unsigned SLCT :8; + }; + struct { + unsigned SLCT0 :1; + unsigned SLCT1 :1; + unsigned SLCT2 :1; + }; +} DMASELECTbits_t; +extern volatile DMASELECTbits_t DMASELECTbits __attribute__((address(0x0E8))); +# 7444 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnBUF __attribute__((address(0x0E9))); + +__asm("DMAnBUF equ 0E9h"); + + +typedef union { + struct { + unsigned BUF :8; + }; + struct { + unsigned BUF0 :1; + unsigned BUF1 :1; + unsigned BUF2 :1; + unsigned BUF3 :1; + unsigned BUF4 :1; + unsigned BUF5 :1; + unsigned BUF6 :1; + unsigned BUF7 :1; + }; +} DMAnBUFbits_t; +extern volatile DMAnBUFbits_t DMAnBUFbits __attribute__((address(0x0E9))); +# 7514 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDCNT __attribute__((address(0x0EA))); + +__asm("DMAnDCNT equ 0EAh"); + + + + +extern volatile unsigned char DMAnDCNTL __attribute__((address(0x0EA))); + +__asm("DMAnDCNTL equ 0EAh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT0 :1; + unsigned DCNT1 :1; + unsigned DCNT2 :1; + unsigned DCNT3 :1; + unsigned DCNT4 :1; + unsigned DCNT5 :1; + unsigned DCNT6 :1; + unsigned DCNT7 :1; + }; +} DMAnDCNTLbits_t; +extern volatile DMAnDCNTLbits_t DMAnDCNTLbits __attribute__((address(0x0EA))); +# 7591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDCNTH __attribute__((address(0x0EB))); + +__asm("DMAnDCNTH equ 0EBh"); + + +typedef union { + struct { + unsigned DCNT :8; + }; + struct { + unsigned DCNT8 :1; + unsigned DCNT9 :1; + unsigned DCNT10 :1; + unsigned DCNT11 :1; + }; +} DMAnDCNTHbits_t; +extern volatile DMAnDCNTHbits_t DMAnDCNTHbits __attribute__((address(0x0EB))); +# 7637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDPTR __attribute__((address(0x0EC))); + +__asm("DMAnDPTR equ 0ECh"); + + + + +extern volatile unsigned char DMAnDPTRL __attribute__((address(0x0EC))); + +__asm("DMAnDPTRL equ 0ECh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR0 :1; + unsigned DPTR1 :1; + unsigned DPTR2 :1; + unsigned DPTR3 :1; + unsigned DPTR4 :1; + unsigned DPTR5 :1; + unsigned DPTR6 :1; + unsigned DPTR7 :1; + }; +} DMAnDPTRLbits_t; +extern volatile DMAnDPTRLbits_t DMAnDPTRLbits __attribute__((address(0x0EC))); +# 7714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDPTRH __attribute__((address(0x0ED))); + +__asm("DMAnDPTRH equ 0EDh"); + + +typedef union { + struct { + unsigned DPTR :8; + }; + struct { + unsigned DPTR8 :1; + unsigned DPTR9 :1; + unsigned DPTR10 :1; + unsigned DPTR11 :1; + unsigned DPTR12 :1; + unsigned DPTR13 :1; + unsigned DPTR14 :1; + unsigned DPTR15 :1; + }; +} DMAnDPTRHbits_t; +extern volatile DMAnDPTRHbits_t DMAnDPTRHbits __attribute__((address(0x0ED))); +# 7784 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSZ __attribute__((address(0x0EE))); + +__asm("DMAnDSZ equ 0EEh"); + + + + +extern volatile unsigned char DMAnDSZL __attribute__((address(0x0EE))); + +__asm("DMAnDSZL equ 0EEh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ0 :1; + unsigned DSZ1 :1; + unsigned DSZ2 :1; + unsigned DSZ3 :1; + unsigned DSZ4 :1; + unsigned DSZ5 :1; + unsigned DSZ6 :1; + unsigned DSZ7 :1; + }; +} DMAnDSZLbits_t; +extern volatile DMAnDSZLbits_t DMAnDSZLbits __attribute__((address(0x0EE))); +# 7861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSZH __attribute__((address(0x0EF))); + +__asm("DMAnDSZH equ 0EFh"); + + +typedef union { + struct { + unsigned DSZ :8; + }; + struct { + unsigned DSZ8 :1; + unsigned DSZ9 :1; + unsigned DSZ10 :1; + unsigned DSZ11 :1; + }; +} DMAnDSZHbits_t; +extern volatile DMAnDSZHbits_t DMAnDSZHbits __attribute__((address(0x0EF))); +# 7907 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnDSA __attribute__((address(0x0F0))); + +__asm("DMAnDSA equ 0F0h"); + + + + +extern volatile unsigned char DMAnDSAL __attribute__((address(0x0F0))); + +__asm("DMAnDSAL equ 0F0h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA0 :1; + unsigned DSA1 :1; + unsigned DSA2 :1; + unsigned DSA3 :1; + unsigned DSA4 :1; + unsigned DSA5 :1; + unsigned DSA6 :1; + unsigned DSA7 :1; + }; +} DMAnDSALbits_t; +extern volatile DMAnDSALbits_t DMAnDSALbits __attribute__((address(0x0F0))); +# 7984 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnDSAH __attribute__((address(0x0F1))); + +__asm("DMAnDSAH equ 0F1h"); + + +typedef union { + struct { + unsigned DSA :8; + }; + struct { + unsigned DSA8 :1; + unsigned DSA9 :1; + unsigned DSA10 :1; + unsigned DSA11 :1; + unsigned DSA12 :1; + unsigned DSA13 :1; + unsigned DSA14 :1; + unsigned DSA15 :1; + }; +} DMAnDSAHbits_t; +extern volatile DMAnDSAHbits_t DMAnDSAHbits __attribute__((address(0x0F1))); +# 8054 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSCNT __attribute__((address(0x0F2))); + +__asm("DMAnSCNT equ 0F2h"); + + + + +extern volatile unsigned char DMAnSCNTL __attribute__((address(0x0F2))); + +__asm("DMAnSCNTL equ 0F2h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT0 :1; + unsigned SCNT1 :1; + unsigned SCNT2 :1; + unsigned SCNT3 :1; + unsigned SCNT4 :1; + unsigned SCNT5 :1; + unsigned SCNT6 :1; + unsigned SCNT7 :1; + }; +} DMAnSCNTLbits_t; +extern volatile DMAnSCNTLbits_t DMAnSCNTLbits __attribute__((address(0x0F2))); +# 8131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSCNTH __attribute__((address(0x0F3))); + +__asm("DMAnSCNTH equ 0F3h"); + + +typedef union { + struct { + unsigned SCNT :8; + }; + struct { + unsigned SCNT8 :1; + unsigned SCNT9 :1; + unsigned SCNT10 :1; + unsigned SCNT11 :1; + }; +} DMAnSCNTHbits_t; +extern volatile DMAnSCNTHbits_t DMAnSCNTHbits __attribute__((address(0x0F3))); +# 8178 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSPTR __attribute__((address(0x0F4))); + + +__asm("DMAnSPTR equ 0F4h"); + + + + +extern volatile unsigned char DMAnSPTRL __attribute__((address(0x0F4))); + +__asm("DMAnSPTRL equ 0F4h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR0 :1; + unsigned SPTR1 :1; + unsigned SPTR2 :1; + unsigned SPTR3 :1; + unsigned SPTR4 :1; + unsigned SPTR5 :1; + unsigned SPTR6 :1; + unsigned SPTR7 :1; + }; +} DMAnSPTRLbits_t; +extern volatile DMAnSPTRLbits_t DMAnSPTRLbits __attribute__((address(0x0F4))); +# 8256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRH __attribute__((address(0x0F5))); + +__asm("DMAnSPTRH equ 0F5h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR8 :1; + unsigned SPTR9 :1; + unsigned SPTR10 :1; + unsigned SPTR11 :1; + unsigned SPTR12 :1; + unsigned SPTR13 :1; + unsigned SPTR14 :1; + unsigned SPTR15 :1; + }; +} DMAnSPTRHbits_t; +extern volatile DMAnSPTRHbits_t DMAnSPTRHbits __attribute__((address(0x0F5))); +# 8326 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSPTRU __attribute__((address(0x0F6))); + +__asm("DMAnSPTRU equ 0F6h"); + + +typedef union { + struct { + unsigned SPTR :8; + }; + struct { + unsigned SPTR16 :1; + unsigned SPTR17 :1; + unsigned SPTR18 :1; + unsigned SPTR19 :1; + unsigned SPTR20 :1; + unsigned SPTR21 :1; + }; +} DMAnSPTRUbits_t; +extern volatile DMAnSPTRUbits_t DMAnSPTRUbits __attribute__((address(0x0F6))); +# 8384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short DMAnSSZ __attribute__((address(0x0F7))); + +__asm("DMAnSSZ equ 0F7h"); + + + + +extern volatile unsigned char DMAnSSZL __attribute__((address(0x0F7))); + +__asm("DMAnSSZL equ 0F7h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ0 :1; + unsigned SSZ1 :1; + unsigned SSZ2 :1; + unsigned SSZ3 :1; + unsigned SSZ4 :1; + unsigned SSZ5 :1; + unsigned SSZ6 :1; + unsigned SSZ7 :1; + }; +} DMAnSSZLbits_t; +extern volatile DMAnSSZLbits_t DMAnSSZLbits __attribute__((address(0x0F7))); +# 8461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSZH __attribute__((address(0x0F8))); + +__asm("DMAnSSZH equ 0F8h"); + + +typedef union { + struct { + unsigned SSZ :8; + }; + struct { + unsigned SSZ8 :1; + unsigned SSZ9 :1; + unsigned SSZ10 :1; + unsigned SSZ11 :1; + }; +} DMAnSSZHbits_t; +extern volatile DMAnSSZHbits_t DMAnSSZHbits __attribute__((address(0x0F8))); +# 8508 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 DMAnSSA __attribute__((address(0x0F9))); + + +__asm("DMAnSSA equ 0F9h"); + + + + +extern volatile unsigned char DMAnSSAL __attribute__((address(0x0F9))); + +__asm("DMAnSSAL equ 0F9h"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA0 :1; + unsigned SSA1 :1; + unsigned SSA2 :1; + unsigned SSA3 :1; + unsigned SSA4 :1; + unsigned SSA5 :1; + unsigned SSA6 :1; + unsigned SSA7 :1; + }; +} DMAnSSALbits_t; +extern volatile DMAnSSALbits_t DMAnSSALbits __attribute__((address(0x0F9))); +# 8586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAH __attribute__((address(0x0FA))); + +__asm("DMAnSSAH equ 0FAh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA8 :1; + unsigned SSA9 :1; + unsigned SSA10 :1; + unsigned SSA11 :1; + unsigned SSA12 :1; + unsigned SSA13 :1; + unsigned SSA14 :1; + unsigned SSA15 :1; + }; +} DMAnSSAHbits_t; +extern volatile DMAnSSAHbits_t DMAnSSAHbits __attribute__((address(0x0FA))); +# 8656 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSSAU __attribute__((address(0x0FB))); + +__asm("DMAnSSAU equ 0FBh"); + + +typedef union { + struct { + unsigned SSA :8; + }; + struct { + unsigned SSA16 :1; + unsigned SSA17 :1; + unsigned SSA18 :1; + unsigned SSA19 :1; + unsigned SSA20 :1; + unsigned SSA21 :1; + }; +} DMAnSSAUbits_t; +extern volatile DMAnSSAUbits_t DMAnSSAUbits __attribute__((address(0x0FB))); +# 8714 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON0 __attribute__((address(0x0FC))); + +__asm("DMAnCON0 equ 0FCh"); + + +typedef union { + struct { + unsigned XIP :1; + unsigned :1; + unsigned AIRQEN :1; + unsigned :2; + unsigned DGO :1; + unsigned SIRQEN :1; + unsigned EN :1; + }; +} DMAnCON0bits_t; +extern volatile DMAnCON0bits_t DMAnCON0bits __attribute__((address(0x0FC))); +# 8760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnCON1 __attribute__((address(0x0FD))); + +__asm("DMAnCON1 equ 0FDh"); + + +typedef union { + struct { + unsigned SSTP :1; + unsigned SMODE :2; + unsigned SMR :2; + unsigned DSTP :1; + unsigned DMODE :2; + }; +} DMAnCON1bits_t; +extern volatile DMAnCON1bits_t DMAnCON1bits __attribute__((address(0x0FD))); +# 8804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnAIRQ __attribute__((address(0x0FE))); + +__asm("DMAnAIRQ equ 0FEh"); + + +typedef union { + struct { + unsigned AIRQ :8; + }; + struct { + unsigned AIRQ0 :1; + unsigned AIRQ1 :1; + unsigned AIRQ2 :1; + unsigned AIRQ3 :1; + unsigned AIRQ4 :1; + unsigned AIRQ5 :1; + unsigned AIRQ6 :1; + unsigned AIRQ7 :1; + }; +} DMAnAIRQbits_t; +extern volatile DMAnAIRQbits_t DMAnAIRQbits __attribute__((address(0x0FE))); +# 8874 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char DMAnSIRQ __attribute__((address(0x0FF))); + +__asm("DMAnSIRQ equ 0FFh"); + + +typedef union { + struct { + unsigned SIRQ :8; + }; + struct { + unsigned SIRQ0 :1; + unsigned SIRQ1 :1; + unsigned SIRQ2 :1; + unsigned SIRQ3 :1; + unsigned SIRQ4 :1; + unsigned SIRQ5 :1; + unsigned SIRQ6 :1; + unsigned SIRQ7 :1; + }; +} DMAnSIRQbits_t; +extern volatile DMAnSIRQbits_t DMAnSIRQbits __attribute__((address(0x0FF))); +# 8944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONL __attribute__((address(0x100))); + +__asm("C1CONL equ 0100h"); + + +typedef union { + struct { + unsigned DNCNT :5; + unsigned ISOCRCEN :1; + unsigned PXEDIS :1; + unsigned CLKSEL0 :1; + }; + struct { + unsigned DNCNT0 :1; + unsigned DNCNT1 :1; + unsigned DNCNT2 :1; + unsigned DNCNT3 :1; + unsigned DNCNT4 :1; + }; +} C1CONLbits_t; +extern volatile C1CONLbits_t C1CONLbits __attribute__((address(0x100))); +# 9014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONH __attribute__((address(0x101))); + +__asm("C1CONH equ 0101h"); + + +typedef union { + struct { + unsigned WAKFIL :1; + unsigned WFT :2; + unsigned BUSY :1; + unsigned BRSDIS :1; + unsigned SIDL :1; + unsigned FRZ :1; + unsigned ON :1; + }; + struct { + unsigned :1; + unsigned WFT0 :1; + unsigned WFT1 :1; + }; +} C1CONHbits_t; +extern volatile C1CONHbits_t C1CONHbits __attribute__((address(0x101))); +# 9085 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONU __attribute__((address(0x102))); + +__asm("C1CONU equ 0102h"); + + +typedef union { + struct { + unsigned RTXAT :1; + unsigned ESIGM :1; + unsigned SERR2LOM :1; + unsigned STEF :1; + unsigned TXQEN :1; + unsigned OPMOD :3; + }; + struct { + unsigned :5; + unsigned OPMOD0 :1; + unsigned OPMOD1 :1; + unsigned OPMOD2 :1; + }; +} C1CONUbits_t; +extern volatile C1CONUbits_t C1CONUbits __attribute__((address(0x102))); +# 9156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1CONT __attribute__((address(0x103))); + +__asm("C1CONT equ 0103h"); + + +typedef union { + struct { + unsigned REQOP :3; + unsigned ABAT :1; + unsigned TXBWS :4; + }; + struct { + unsigned REQOP0 :1; + unsigned REQOP1 :1; + unsigned REQOP2 :1; + unsigned :1; + unsigned TXBWS0 :1; + unsigned TXBWS1 :1; + unsigned TXBWS2 :1; + unsigned TXBWS3 :1; + }; +} C1CONTbits_t; +extern volatile C1CONTbits_t C1CONTbits __attribute__((address(0x103))); +# 9233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGL __attribute__((address(0x104))); + +__asm("C1NBTCFGL equ 0104h"); + + +typedef union { + struct { + unsigned SJW :7; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + unsigned SJW4 :1; + unsigned SJW5 :1; + unsigned SJW6 :1; + }; +} C1NBTCFGLbits_t; +extern volatile C1NBTCFGLbits_t C1NBTCFGLbits __attribute__((address(0x104))); +# 9297 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGH __attribute__((address(0x105))); + +__asm("C1NBTCFGH equ 0105h"); + + +typedef union { + struct { + unsigned TSEG2 :7; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + unsigned TSEG24 :1; + unsigned TSEG25 :1; + unsigned TSEG26 :1; + }; +} C1NBTCFGHbits_t; +extern volatile C1NBTCFGHbits_t C1NBTCFGHbits __attribute__((address(0x105))); +# 9361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGU __attribute__((address(0x106))); + +__asm("C1NBTCFGU equ 0106h"); + + +typedef union { + struct { + unsigned TSEG1 :8; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + unsigned TSEG15 :1; + unsigned TSEG16 :1; + unsigned TSEG17 :1; + }; +} C1NBTCFGUbits_t; +extern volatile C1NBTCFGUbits_t C1NBTCFGUbits __attribute__((address(0x106))); +# 9431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1NBTCFGT __attribute__((address(0x107))); + +__asm("C1NBTCFGT equ 0107h"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1NBTCFGTbits_t; +extern volatile C1NBTCFGTbits_t C1NBTCFGTbits __attribute__((address(0x107))); +# 9501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGL __attribute__((address(0x108))); + +__asm("C1DBTCFGL equ 0108h"); + + +typedef union { + struct { + unsigned SJW :4; + }; + struct { + unsigned SJW0 :1; + unsigned SJW1 :1; + unsigned SJW2 :1; + unsigned SJW3 :1; + }; +} C1DBTCFGLbits_t; +extern volatile C1DBTCFGLbits_t C1DBTCFGLbits __attribute__((address(0x108))); +# 9547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGH __attribute__((address(0x109))); + +__asm("C1DBTCFGH equ 0109h"); + + +typedef union { + struct { + unsigned TSEG2 :4; + }; + struct { + unsigned TSEG20 :1; + unsigned TSEG21 :1; + unsigned TSEG22 :1; + unsigned TSEG23 :1; + }; +} C1DBTCFGHbits_t; +extern volatile C1DBTCFGHbits_t C1DBTCFGHbits __attribute__((address(0x109))); +# 9593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGU __attribute__((address(0x10A))); + +__asm("C1DBTCFGU equ 010Ah"); + + +typedef union { + struct { + unsigned TSEG1 :5; + }; + struct { + unsigned TSEG10 :1; + unsigned TSEG11 :1; + unsigned TSEG12 :1; + unsigned TSEG13 :1; + unsigned TSEG14 :1; + }; +} C1DBTCFGUbits_t; +extern volatile C1DBTCFGUbits_t C1DBTCFGUbits __attribute__((address(0x10A))); +# 9645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1DBTCFGT __attribute__((address(0x10B))); + +__asm("C1DBTCFGT equ 010Bh"); + + +typedef union { + struct { + unsigned BRP :8; + }; + struct { + unsigned BRP0 :1; + unsigned BRP1 :1; + unsigned BRP2 :1; + unsigned BRP3 :1; + unsigned BRP4 :1; + unsigned BRP5 :1; + unsigned BRP6 :1; + unsigned BRP7 :1; + }; +} C1DBTCFGTbits_t; +extern volatile C1DBTCFGTbits_t C1DBTCFGTbits __attribute__((address(0x10B))); +# 9715 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCL __attribute__((address(0x10C))); + +__asm("C1TDCL equ 010Ch"); + + +typedef union { + struct { + unsigned TDCV :6; + }; + struct { + unsigned TDCV0 :1; + unsigned TDCV1 :1; + unsigned TDCV2 :1; + unsigned TDCV3 :1; + unsigned TDCV4 :1; + unsigned TDCV5 :1; + }; +} C1TDCLbits_t; +extern volatile C1TDCLbits_t C1TDCLbits __attribute__((address(0x10C))); +# 9773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCH __attribute__((address(0x10D))); + +__asm("C1TDCH equ 010Dh"); + + +typedef union { + struct { + unsigned TDCO :7; + }; + struct { + unsigned TDCO0 :1; + unsigned TDCO1 :1; + unsigned TDCO2 :1; + unsigned TDCO3 :1; + unsigned TDCO4 :1; + unsigned TDCO5 :1; + unsigned TDCO6 :1; + }; +} C1TDCHbits_t; +extern volatile C1TDCHbits_t C1TDCHbits __attribute__((address(0x10D))); +# 9837 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCU __attribute__((address(0x10E))); + +__asm("C1TDCU equ 010Eh"); + + +typedef union { + struct { + unsigned TDCMOD :2; + }; + struct { + unsigned TDCMOD0 :1; + unsigned TDCMOD1 :1; + }; +} C1TDCUbits_t; +extern volatile C1TDCUbits_t C1TDCUbits __attribute__((address(0x10E))); +# 9871 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TDCT __attribute__((address(0x10F))); + +__asm("C1TDCT equ 010Fh"); + + +typedef union { + struct { + unsigned SID11EN :1; + unsigned EDGFLTEN :1; + }; +} C1TDCTbits_t; +extern volatile C1TDCTbits_t C1TDCTbits __attribute__((address(0x10F))); +# 9897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TBC __attribute__((address(0x110))); + +__asm("C1TBC equ 0110h"); + + + + +extern volatile unsigned char C1TBCL __attribute__((address(0x110))); + +__asm("C1TBCL equ 0110h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC0 :1; + unsigned TBC1 :1; + unsigned TBC2 :1; + unsigned TBC3 :1; + unsigned TBC4 :1; + unsigned TBC5 :1; + unsigned TBC6 :1; + unsigned TBC7 :1; + }; +} C1TBCLbits_t; +extern volatile C1TBCLbits_t C1TBCLbits __attribute__((address(0x110))); +# 9974 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCH __attribute__((address(0x111))); + +__asm("C1TBCH equ 0111h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC8 :1; + unsigned TBC9 :1; + unsigned TBC10 :1; + unsigned TBC11 :1; + unsigned TBC12 :1; + unsigned TBC13 :1; + unsigned TBC14 :1; + unsigned TBC15 :1; + }; +} C1TBCHbits_t; +extern volatile C1TBCHbits_t C1TBCHbits __attribute__((address(0x111))); +# 10044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCU __attribute__((address(0x112))); + +__asm("C1TBCU equ 0112h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC16 :1; + unsigned TBC17 :1; + unsigned TBC18 :1; + unsigned TBC19 :1; + unsigned TBC20 :1; + unsigned TBC21 :1; + unsigned TBC22 :1; + unsigned TBC23 :1; + }; +} C1TBCUbits_t; +extern volatile C1TBCUbits_t C1TBCUbits __attribute__((address(0x112))); +# 10114 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TBCT __attribute__((address(0x113))); + +__asm("C1TBCT equ 0113h"); + + +typedef union { + struct { + unsigned TBC :8; + }; + struct { + unsigned TBC24 :1; + unsigned TBC25 :1; + unsigned TBC26 :1; + unsigned TBC27 :1; + unsigned TBC28 :1; + unsigned TBC29 :1; + unsigned TBC30 :1; + unsigned TBC31 :1; + }; +} C1TBCTbits_t; +extern volatile C1TBCTbits_t C1TBCTbits __attribute__((address(0x113))); +# 10184 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONL __attribute__((address(0x114))); + +__asm("C1TSCONL equ 0114h"); + + +typedef union { + struct { + unsigned TBCPRE :8; + }; + struct { + unsigned TBCPRE0 :1; + unsigned TBCPRE1 :1; + unsigned TBCPRE2 :1; + unsigned TBCPRE3 :1; + unsigned TBCPRE4 :1; + unsigned TBCPRE5 :1; + unsigned TBCPRE6 :1; + unsigned TBCPRE7 :1; + }; +} C1TSCONLbits_t; +extern volatile C1TSCONLbits_t C1TSCONLbits __attribute__((address(0x114))); +# 10254 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONH __attribute__((address(0x115))); + +__asm("C1TSCONH equ 0115h"); + + +typedef union { + struct { + unsigned TBCPRE :2; + }; + struct { + unsigned TBCPRE8 :1; + unsigned TBCPRE9 :1; + }; +} C1TSCONHbits_t; +extern volatile C1TSCONHbits_t C1TSCONHbits __attribute__((address(0x115))); +# 10288 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONU __attribute__((address(0x116))); + +__asm("C1TSCONU equ 0116h"); + + +typedef union { + struct { + unsigned TBCEN :1; + unsigned TSEOF :1; + unsigned TSRES :1; + }; +} C1TSCONUbits_t; +extern volatile C1TSCONUbits_t C1TSCONUbits __attribute__((address(0x116))); +# 10320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TSCONT __attribute__((address(0x117))); + +__asm("C1TSCONT equ 0117h"); + + + + +extern volatile unsigned char C1VECL __attribute__((address(0x118))); + +__asm("C1VECL equ 0118h"); + + +typedef union { + struct { + unsigned ICODE :7; + }; +} C1VECLbits_t; +extern volatile C1VECLbits_t C1VECLbits __attribute__((address(0x118))); +# 10347 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECH __attribute__((address(0x119))); + +__asm("C1VECH equ 0119h"); + + +typedef union { + struct { + unsigned FILHIT :5; + }; +} C1VECHbits_t; +extern volatile C1VECHbits_t C1VECHbits __attribute__((address(0x119))); +# 10367 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECU __attribute__((address(0x11A))); + +__asm("C1VECU equ 011Ah"); + + +typedef union { + struct { + unsigned TXCODE :7; + }; +} C1VECUbits_t; +extern volatile C1VECUbits_t C1VECUbits __attribute__((address(0x11A))); +# 10387 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1VECT __attribute__((address(0x11B))); + +__asm("C1VECT equ 011Bh"); + + +typedef union { + struct { + unsigned RXCODE :7; + }; +} C1VECTbits_t; +extern volatile C1VECTbits_t C1VECTbits __attribute__((address(0x11B))); +# 10407 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTL __attribute__((address(0x11C))); + +__asm("C1INTL equ 011Ch"); + + +typedef union { + struct { + unsigned TXIF :1; + unsigned RXIF :1; + unsigned TBCIF :1; + unsigned MODIF :1; + unsigned TEFIF :1; + }; +} C1INTLbits_t; +extern volatile C1INTLbits_t C1INTLbits __attribute__((address(0x11C))); +# 10451 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTH __attribute__((address(0x11D))); + +__asm("C1INTH equ 011Dh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIF :1; + unsigned RXOVIF :1; + unsigned SERRIF :1; + unsigned CERRIF :1; + unsigned WAKIF :1; + unsigned IVMIF :1; + }; +} C1INTHbits_t; +extern volatile C1INTHbits_t C1INTHbits __attribute__((address(0x11D))); +# 10502 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTU __attribute__((address(0x11E))); + +__asm("C1INTU equ 011Eh"); + + +typedef union { + struct { + unsigned TXIE :1; + unsigned RXIE :1; + unsigned TBCIE :1; + unsigned MODIE :1; + unsigned TEFIE :1; + }; +} C1INTUbits_t; +extern volatile C1INTUbits_t C1INTUbits __attribute__((address(0x11E))); +# 10546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1INTT __attribute__((address(0x11F))); + +__asm("C1INTT equ 011Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned TXATIE :1; + unsigned RXOVIE :1; + unsigned SERRIE :1; + unsigned CERRIE :1; + unsigned WAKIE :1; + unsigned IVMIE :1; + }; +} C1INTTbits_t; +extern volatile C1INTTbits_t C1INTTbits __attribute__((address(0x11F))); +# 10597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXIF __attribute__((address(0x120))); + +__asm("C1RXIF equ 0120h"); + + + + +extern volatile unsigned char C1RXIFL __attribute__((address(0x120))); + +__asm("C1RXIFL equ 0120h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFIF :7; + }; + struct { + unsigned :1; + unsigned RFIF1 :1; + unsigned RFIF2 :1; + unsigned RFIF3 :1; + unsigned RFIF4 :1; + unsigned RFIF5 :1; + unsigned RFIF6 :1; + unsigned RFIF7 :1; + }; +} C1RXIFLbits_t; +extern volatile C1RXIFLbits_t C1RXIFLbits __attribute__((address(0x120))); +# 10670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFH __attribute__((address(0x121))); + +__asm("C1RXIFH equ 0121h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF8 :1; + unsigned RFIF9 :1; + unsigned RFIF10 :1; + unsigned RFIF11 :1; + unsigned RFIF12 :1; + unsigned RFIF13 :1; + unsigned RFIF14 :1; + unsigned RFIF15 :1; + }; +} C1RXIFHbits_t; +extern volatile C1RXIFHbits_t C1RXIFHbits __attribute__((address(0x121))); +# 10740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFU __attribute__((address(0x122))); + +__asm("C1RXIFU equ 0122h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF16 :1; + unsigned RFIF17 :1; + unsigned RFIF18 :1; + unsigned RFIF19 :1; + unsigned RFIF20 :1; + unsigned RFIF21 :1; + unsigned RFIF22 :1; + unsigned RFIF23 :1; + }; +} C1RXIFUbits_t; +extern volatile C1RXIFUbits_t C1RXIFUbits __attribute__((address(0x122))); +# 10810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXIFT __attribute__((address(0x123))); + +__asm("C1RXIFT equ 0123h"); + + +typedef union { + struct { + unsigned RFIF :8; + }; + struct { + unsigned RFIF24 :1; + unsigned RFIF25 :1; + unsigned RFIF26 :1; + unsigned RFIF27 :1; + unsigned RFIF28 :1; + unsigned RFIF29 :1; + unsigned RFIF30 :1; + unsigned RFIF31 :1; + }; +} C1RXIFTbits_t; +extern volatile C1RXIFTbits_t C1RXIFTbits __attribute__((address(0x123))); +# 10880 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short C1TXIF __attribute__((address(0x124))); + +__asm("C1TXIF equ 0124h"); + + + + +extern volatile unsigned char C1TXIFL __attribute__((address(0x124))); + +__asm("C1TXIFL equ 0124h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF0 :1; + unsigned TFIF1 :1; + unsigned TFIF2 :1; + unsigned TFIF3 :1; + unsigned TFIF4 :1; + unsigned TFIF5 :1; + unsigned TFIF6 :1; + unsigned TFIF7 :1; + }; +} C1TXIFLbits_t; +extern volatile C1TXIFLbits_t C1TXIFLbits __attribute__((address(0x124))); +# 10957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFH __attribute__((address(0x125))); + +__asm("C1TXIFH equ 0125h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF8 :1; + unsigned TFIF9 :1; + unsigned TFIF10 :1; + unsigned TFIF11 :1; + unsigned TFIF12 :1; + unsigned TFIF13 :1; + unsigned TFIF14 :1; + unsigned TFIF15 :1; + }; +} C1TXIFHbits_t; +extern volatile C1TXIFHbits_t C1TXIFHbits __attribute__((address(0x125))); +# 11027 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFU __attribute__((address(0x126))); + +__asm("C1TXIFU equ 0126h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF16 :1; + unsigned TFIF17 :1; + unsigned TFIF18 :1; + unsigned TFIF19 :1; + unsigned TFIF20 :1; + unsigned TFIF21 :1; + unsigned TFIF22 :1; + unsigned TFIF23 :1; + }; +} C1TXIFUbits_t; +extern volatile C1TXIFUbits_t C1TXIFUbits __attribute__((address(0x126))); +# 11097 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXIFT __attribute__((address(0x127))); + +__asm("C1TXIFT equ 0127h"); + + +typedef union { + struct { + unsigned TFIF :8; + }; + struct { + unsigned TFIF24 :1; + unsigned TFIF25 :1; + unsigned TFIF26 :1; + unsigned TFIF27 :1; + unsigned TFIF28 :1; + unsigned TFIF29 :1; + unsigned TFIF30 :1; + unsigned TFIF31 :1; + }; +} C1TXIFTbits_t; +extern volatile C1TXIFTbits_t C1TXIFTbits __attribute__((address(0x127))); +# 11167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1RXOVIF __attribute__((address(0x128))); + +__asm("C1RXOVIF equ 0128h"); + + + + +extern volatile unsigned char C1RXOVIFL __attribute__((address(0x128))); + +__asm("C1RXOVIFL equ 0128h"); + + +typedef union { + struct { + unsigned :1; + unsigned RFOVIF :7; + }; + struct { + unsigned :1; + unsigned RFOVIF1 :1; + unsigned RFOVIF2 :1; + unsigned RFOVIF3 :1; + unsigned RFOVIF4 :1; + unsigned RFOVIF5 :1; + unsigned RFOVIF6 :1; + unsigned RFOVIF7 :1; + }; +} C1RXOVIFLbits_t; +extern volatile C1RXOVIFLbits_t C1RXOVIFLbits __attribute__((address(0x128))); +# 11240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFH __attribute__((address(0x129))); + +__asm("C1RXOVIFH equ 0129h"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF8 :1; + unsigned RFOVIF9 :1; + unsigned RFOVIF10 :1; + unsigned RFOVIF11 :1; + unsigned RFOVIF12 :1; + unsigned RFOVIF13 :1; + unsigned RFOVIF14 :1; + unsigned RFOVIF15 :1; + }; +} C1RXOVIFHbits_t; +extern volatile C1RXOVIFHbits_t C1RXOVIFHbits __attribute__((address(0x129))); +# 11310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFU __attribute__((address(0x12A))); + +__asm("C1RXOVIFU equ 012Ah"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF16 :1; + unsigned RFOVIF17 :1; + unsigned RFOVIF18 :1; + unsigned RFOVIF19 :1; + unsigned RFOVIF20 :1; + unsigned RFOVIF21 :1; + unsigned RFOVIF22 :1; + unsigned RFOVIF23 :1; + }; +} C1RXOVIFUbits_t; +extern volatile C1RXOVIFUbits_t C1RXOVIFUbits __attribute__((address(0x12A))); +# 11380 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1RXOVIFT __attribute__((address(0x12B))); + +__asm("C1RXOVIFT equ 012Bh"); + + +typedef union { + struct { + unsigned RFOVIF :8; + }; + struct { + unsigned RFOVIF24 :1; + unsigned RFOVIF25 :1; + unsigned RFOVIF26 :1; + unsigned RFOVIF27 :1; + unsigned RFOVIF28 :1; + unsigned RFOVIF29 :1; + unsigned RFOVIF30 :1; + unsigned RFOVIF31 :1; + }; +} C1RXOVIFTbits_t; +extern volatile C1RXOVIFTbits_t C1RXOVIFTbits __attribute__((address(0x12B))); +# 11450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXATIF __attribute__((address(0x12C))); + +__asm("C1TXATIF equ 012Ch"); + + + + +extern volatile unsigned char C1TXATIFL __attribute__((address(0x12C))); + +__asm("C1TXATIFL equ 012Ch"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF0 :1; + unsigned TFATIF1 :1; + unsigned TFATIF2 :1; + unsigned TFATIF3 :1; + unsigned TFATIF4 :1; + unsigned TFATIF5 :1; + unsigned TFATIF6 :1; + unsigned TFATIF7 :1; + }; +} C1TXATIFLbits_t; +extern volatile C1TXATIFLbits_t C1TXATIFLbits __attribute__((address(0x12C))); +# 11527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFH __attribute__((address(0x12D))); + +__asm("C1TXATIFH equ 012Dh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF8 :1; + unsigned TFATIF9 :1; + unsigned TFATIF10 :1; + unsigned TFATIF11 :1; + unsigned TFATIF12 :1; + unsigned TFATIF13 :1; + unsigned TFATIF14 :1; + unsigned TFATIF15 :1; + }; +} C1TXATIFHbits_t; +extern volatile C1TXATIFHbits_t C1TXATIFHbits __attribute__((address(0x12D))); +# 11597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFU __attribute__((address(0x12E))); + +__asm("C1TXATIFU equ 012Eh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF16 :1; + unsigned TFATIF17 :1; + unsigned TFATIF18 :1; + unsigned TFATIF19 :1; + unsigned TFATIF20 :1; + unsigned TFATIF21 :1; + unsigned TFATIF22 :1; + unsigned TFATIF23 :1; + }; +} C1TXATIFUbits_t; +extern volatile C1TXATIFUbits_t C1TXATIFUbits __attribute__((address(0x12E))); +# 11667 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXATIFT __attribute__((address(0x12F))); + +__asm("C1TXATIFT equ 012Fh"); + + +typedef union { + struct { + unsigned TFATIF :8; + }; + struct { + unsigned TFATIF24 :1; + unsigned TFATIF25 :1; + unsigned TFATIF26 :1; + unsigned TFATIF27 :1; + unsigned TFATIF28 :1; + unsigned TFATIF29 :1; + unsigned TFATIF30 :1; + unsigned TFATIF31 :1; + }; +} C1TXATIFTbits_t; +extern volatile C1TXATIFTbits_t C1TXATIFTbits __attribute__((address(0x12F))); +# 11737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1TXREQ __attribute__((address(0x130))); + +__asm("C1TXREQ equ 0130h"); + + + + +extern volatile unsigned char C1TXREQL __attribute__((address(0x130))); + +__asm("C1TXREQL equ 0130h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ0 :1; + unsigned TXREQ1 :1; + unsigned TXREQ2 :1; + unsigned TXREQ3 :1; + unsigned TXREQ4 :1; + unsigned TXREQ5 :1; + unsigned TXREQ6 :1; + unsigned TXREQ7 :1; + }; +} C1TXREQLbits_t; +extern volatile C1TXREQLbits_t C1TXREQLbits __attribute__((address(0x130))); +# 11814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQH __attribute__((address(0x131))); + +__asm("C1TXREQH equ 0131h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ8 :1; + unsigned TXREQ9 :1; + unsigned TXREQ10 :1; + unsigned TXREQ11 :1; + unsigned TXREQ12 :1; + unsigned TXREQ13 :1; + unsigned TXREQ14 :1; + unsigned TXREQ15 :1; + }; +} C1TXREQHbits_t; +extern volatile C1TXREQHbits_t C1TXREQHbits __attribute__((address(0x131))); +# 11884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQU __attribute__((address(0x132))); + +__asm("C1TXREQU equ 0132h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ16 :1; + unsigned TXREQ17 :1; + unsigned TXREQ18 :1; + unsigned TXREQ19 :1; + unsigned TXREQ20 :1; + unsigned TXREQ21 :1; + unsigned TXREQ22 :1; + unsigned TXREQ23 :1; + }; +} C1TXREQUbits_t; +extern volatile C1TXREQUbits_t C1TXREQUbits __attribute__((address(0x132))); +# 11954 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXREQT __attribute__((address(0x133))); + +__asm("C1TXREQT equ 0133h"); + + +typedef union { + struct { + unsigned TXREQ :8; + }; + struct { + unsigned TXREQ24 :1; + unsigned TXREQ25 :1; + unsigned TXREQ26 :1; + unsigned TXREQ27 :1; + unsigned TXREQ28 :1; + unsigned TXREQ29 :1; + unsigned TXREQ30 :1; + unsigned TXREQ31 :1; + }; +} C1TXREQTbits_t; +extern volatile C1TXREQTbits_t C1TXREQTbits __attribute__((address(0x133))); +# 12024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECL __attribute__((address(0x134))); + +__asm("C1TRECL equ 0134h"); + + +typedef union { + struct { + unsigned RERRCNT :8; + }; + struct { + unsigned RERRCNT0 :1; + unsigned RERRCNT1 :1; + unsigned RERRCNT2 :1; + unsigned RERRCNT3 :1; + unsigned RERRCNT4 :1; + unsigned RERRCNT5 :1; + unsigned RERRCNT6 :1; + unsigned RERRCNT7 :1; + }; +} C1TRECLbits_t; +extern volatile C1TRECLbits_t C1TRECLbits __attribute__((address(0x134))); +# 12094 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECH __attribute__((address(0x135))); + +__asm("C1TRECH equ 0135h"); + + +typedef union { + struct { + unsigned TERRCNT :8; + }; + struct { + unsigned TERRCNT0 :1; + unsigned TERRCNT1 :1; + unsigned TERRCNT2 :1; + unsigned TERRCNT3 :1; + unsigned TERRCNT4 :1; + unsigned TERRCNT5 :1; + unsigned TERRCNT6 :1; + unsigned TERRCNT7 :1; + }; +} C1TRECHbits_t; +extern volatile C1TRECHbits_t C1TRECHbits __attribute__((address(0x135))); +# 12164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECU __attribute__((address(0x136))); + +__asm("C1TRECU equ 0136h"); + + +typedef union { + struct { + unsigned EWARN :1; + unsigned RXWARN :1; + unsigned TXWARN :1; + unsigned RXBP :1; + unsigned TXBP :1; + unsigned TXBO :1; + }; +} C1TRECUbits_t; +extern volatile C1TRECUbits_t C1TRECUbits __attribute__((address(0x136))); +# 12214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TRECT __attribute__((address(0x137))); + +__asm("C1TRECT equ 0137h"); + + + + +extern volatile unsigned char C1BDIAG0L __attribute__((address(0x138))); + +__asm("C1BDIAG0L equ 0138h"); + + +typedef union { + struct { + unsigned NRERRCNT :8; + }; + struct { + unsigned NRERRCNT0 :1; + unsigned NRERRCNT1 :1; + unsigned NRERRCNT2 :1; + unsigned NRERRCNT3 :1; + unsigned NRERRCNT4 :1; + unsigned NRERRCNT5 :1; + unsigned NRERRCNT6 :1; + unsigned NRERRCNT7 :1; + }; +} C1BDIAG0Lbits_t; +extern volatile C1BDIAG0Lbits_t C1BDIAG0Lbits __attribute__((address(0x138))); +# 12291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0H __attribute__((address(0x139))); + +__asm("C1BDIAG0H equ 0139h"); + + +typedef union { + struct { + unsigned NTERRCNT :8; + }; + struct { + unsigned NTERRCNT0 :1; + unsigned NTERRCNT1 :1; + unsigned NTERRCNT2 :1; + unsigned NTERRCNT3 :1; + unsigned NTERRCNT4 :1; + unsigned NTERRCNT5 :1; + unsigned NTERRCNT6 :1; + unsigned NTERRCNT7 :1; + }; +} C1BDIAG0Hbits_t; +extern volatile C1BDIAG0Hbits_t C1BDIAG0Hbits __attribute__((address(0x139))); +# 12361 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0U __attribute__((address(0x13A))); + +__asm("C1BDIAG0U equ 013Ah"); + + +typedef union { + struct { + unsigned DRERRCNT :8; + }; + struct { + unsigned DRERRCNT0 :1; + unsigned DRERRCNT1 :1; + unsigned DRERRCNT2 :1; + unsigned DRERRCNT3 :1; + unsigned DRERRCNT4 :1; + unsigned DRERRCNT5 :1; + unsigned DRERRCNT6 :1; + unsigned DRERRCNT7 :1; + }; +} C1BDIAG0Ubits_t; +extern volatile C1BDIAG0Ubits_t C1BDIAG0Ubits __attribute__((address(0x13A))); +# 12431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG0T __attribute__((address(0x13B))); + +__asm("C1BDIAG0T equ 013Bh"); + + +typedef union { + struct { + unsigned DTERRCNT :8; + }; + struct { + unsigned DTERRCNT0 :1; + unsigned DTERRCNT1 :1; + unsigned DTERRCNT2 :1; + unsigned DTERRCNT3 :1; + unsigned DTERRCNT4 :1; + unsigned DTERRCNT5 :1; + unsigned DTERRCNT6 :1; + unsigned DTERRCNT7 :1; + }; +} C1BDIAG0Tbits_t; +extern volatile C1BDIAG0Tbits_t C1BDIAG0Tbits __attribute__((address(0x13B))); +# 12501 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1L __attribute__((address(0x13C))); + +__asm("C1BDIAG1L equ 013Ch"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT0 :1; + unsigned EFMSGCNT1 :1; + unsigned EFMSGCNT2 :1; + unsigned EFMSGCNT3 :1; + unsigned EFMSGCNT4 :1; + unsigned EFMSGCNT5 :1; + unsigned EFMSGCNT6 :1; + unsigned EFMSGCNT7 :1; + }; +} C1BDIAG1Lbits_t; +extern volatile C1BDIAG1Lbits_t C1BDIAG1Lbits __attribute__((address(0x13C))); +# 12571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1H __attribute__((address(0x13D))); + +__asm("C1BDIAG1H equ 013Dh"); + + +typedef union { + struct { + unsigned EFMSGCNT :8; + }; + struct { + unsigned EFMSGCNT8 :1; + unsigned EFMSGCNT9 :1; + unsigned EFMSGCNT10 :1; + unsigned EFMSGCNT11 :1; + unsigned EFMSGCNT12 :1; + unsigned EFMSGCNT13 :1; + unsigned EFMSGCNT14 :1; + unsigned EFMSGCNT15 :1; + }; +} C1BDIAG1Hbits_t; +extern volatile C1BDIAG1Hbits_t C1BDIAG1Hbits __attribute__((address(0x13D))); +# 12641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1U __attribute__((address(0x13E))); + +__asm("C1BDIAG1U equ 013Eh"); + + +typedef union { + struct { + unsigned NBIT0ERR :1; + unsigned NBIT1ERR :1; + unsigned NACKERR :1; + unsigned NFORMERR :1; + unsigned NSTUFERR :1; + unsigned NCRCERR :1; + unsigned :1; + unsigned TXBOERR :1; + }; +} C1BDIAG1Ubits_t; +extern volatile C1BDIAG1Ubits_t C1BDIAG1Ubits __attribute__((address(0x13E))); +# 12698 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1BDIAG1T __attribute__((address(0x13F))); + +__asm("C1BDIAG1T equ 013Fh"); + + +typedef union { + struct { + unsigned DBIT0ERR :1; + unsigned DBIT1ERR :1; + unsigned :1; + unsigned DFORMERR :1; + unsigned DSTUFERR :1; + unsigned DCRCERR :1; + unsigned ESI :1; + unsigned DLCMM :1; + }; +} C1BDIAG1Tbits_t; +extern volatile C1BDIAG1Tbits_t C1BDIAG1Tbits __attribute__((address(0x13F))); +# 12755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONL __attribute__((address(0x140))); + +__asm("C1TEFCONL equ 0140h"); + + +typedef union { + struct { + unsigned TEFNEIE :1; + unsigned TEFHIE :1; + unsigned TEFFIE :1; + unsigned TEFOVIE :1; + unsigned :1; + unsigned TEFTSEN :1; + }; +} C1TEFCONLbits_t; +extern volatile C1TEFCONLbits_t C1TEFCONLbits __attribute__((address(0x140))); +# 12800 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONH __attribute__((address(0x141))); + +__asm("C1TEFCONH equ 0141h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned :1; + unsigned FRESET :1; + }; +} C1TEFCONHbits_t; +extern volatile C1TEFCONHbits_t C1TEFCONHbits __attribute__((address(0x141))); +# 12827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFCONU __attribute__((address(0x142))); + +__asm("C1TEFCONU equ 0142h"); + + + + +extern volatile unsigned char C1TEFCONT __attribute__((address(0x143))); + +__asm("C1TEFCONT equ 0143h"); + + +typedef union { + struct { + unsigned FSIZE :5; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + }; +} C1TEFCONTbits_t; +extern volatile C1TEFCONTbits_t C1TEFCONTbits __attribute__((address(0x143))); +# 12886 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAL __attribute__((address(0x144))); + +__asm("C1TEFSTAL equ 0144h"); + + +typedef union { + struct { + unsigned TEFNEIF :1; + unsigned TEFHIF :1; + unsigned TEFFIF :1; + unsigned TEFOVIF :1; + }; +} C1TEFSTALbits_t; +extern volatile C1TEFSTALbits_t C1TEFSTALbits __attribute__((address(0x144))); +# 12924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFSTAH __attribute__((address(0x145))); + +__asm("C1TEFSTAH equ 0145h"); + + + + +extern volatile unsigned char C1TEFSTAU __attribute__((address(0x146))); + +__asm("C1TEFSTAU equ 0146h"); + + + + +extern volatile unsigned char C1TEFSTAT __attribute__((address(0x147))); + +__asm("C1TEFSTAT equ 0147h"); + + + + +extern volatile unsigned long C1TEFUA __attribute__((address(0x148))); + +__asm("C1TEFUA equ 0148h"); + + + + +extern volatile unsigned char C1TEFUAL __attribute__((address(0x148))); + +__asm("C1TEFUAL equ 0148h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA0 :1; + unsigned TEFUA1 :1; + unsigned TEFUA2 :1; + unsigned TEFUA3 :1; + unsigned TEFUA4 :1; + unsigned TEFUA5 :1; + unsigned TEFUA6 :1; + unsigned TEFUA7 :1; + }; +} C1TEFUALbits_t; +extern volatile C1TEFUALbits_t C1TEFUALbits __attribute__((address(0x148))); +# 13022 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAH __attribute__((address(0x149))); + +__asm("C1TEFUAH equ 0149h"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA8 :1; + unsigned TEFUA9 :1; + unsigned TEFUA10 :1; + unsigned TEFUA11 :1; + unsigned TEFUA12 :1; + unsigned TEFUA13 :1; + unsigned TEFUA14 :1; + unsigned TEFUA15 :1; + }; +} C1TEFUAHbits_t; +extern volatile C1TEFUAHbits_t C1TEFUAHbits __attribute__((address(0x149))); +# 13092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAU __attribute__((address(0x14A))); + +__asm("C1TEFUAU equ 014Ah"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA16 :1; + unsigned TEFUA17 :1; + unsigned TEFUA18 :1; + unsigned TEFUA19 :1; + unsigned TEFUA20 :1; + unsigned TEFUA21 :1; + unsigned TEFUA22 :1; + unsigned TEFUA23 :1; + }; +} C1TEFUAUbits_t; +extern volatile C1TEFUAUbits_t C1TEFUAUbits __attribute__((address(0x14A))); +# 13162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TEFUAT __attribute__((address(0x14B))); + +__asm("C1TEFUAT equ 014Bh"); + + +typedef union { + struct { + unsigned TEFUA :8; + }; + struct { + unsigned TEFUA24 :1; + unsigned TEFUA25 :1; + unsigned TEFUA26 :1; + unsigned TEFUA27 :1; + unsigned TEFUA28 :1; + unsigned TEFUA29 :1; + unsigned TEFUA30 :1; + unsigned TEFUA31 :1; + }; +} C1TEFUATbits_t; +extern volatile C1TEFUATbits_t C1TEFUATbits __attribute__((address(0x14B))); +# 13232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOBA __attribute__((address(0x14C))); + +__asm("C1FIFOBA equ 014Ch"); + + + + +extern volatile unsigned char C1FIFOBAL __attribute__((address(0x14C))); + +__asm("C1FIFOBAL equ 014Ch"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA0 :1; + unsigned FIFOBA1 :1; + unsigned FIFOBA2 :1; + unsigned FIFOBA3 :1; + unsigned FIFOBA4 :1; + unsigned FIFOBA5 :1; + unsigned FIFOBA6 :1; + unsigned FIFOBA7 :1; + }; +} C1FIFOBALbits_t; +extern volatile C1FIFOBALbits_t C1FIFOBALbits __attribute__((address(0x14C))); +# 13309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAH __attribute__((address(0x14D))); + +__asm("C1FIFOBAH equ 014Dh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA8 :1; + unsigned FIFOBA9 :1; + unsigned FIFOBA10 :1; + unsigned FIFOBA11 :1; + unsigned FIFOBA12 :1; + unsigned FIFOBA13 :1; + unsigned FIFOBA14 :1; + unsigned FIFOBA15 :1; + }; +} C1FIFOBAHbits_t; +extern volatile C1FIFOBAHbits_t C1FIFOBAHbits __attribute__((address(0x14D))); +# 13379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAU __attribute__((address(0x14E))); + +__asm("C1FIFOBAU equ 014Eh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA16 :1; + unsigned FIFOBA17 :1; + unsigned FIFOBA18 :1; + unsigned FIFOBA19 :1; + unsigned FIFOBA20 :1; + unsigned FIFOBA21 :1; + unsigned FIFOBA22 :1; + unsigned FIFOBA23 :1; + }; +} C1FIFOBAUbits_t; +extern volatile C1FIFOBAUbits_t C1FIFOBAUbits __attribute__((address(0x14E))); +# 13449 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOBAT __attribute__((address(0x14F))); + +__asm("C1FIFOBAT equ 014Fh"); + + +typedef union { + struct { + unsigned FIFOBA :8; + }; + struct { + unsigned FIFOBA24 :1; + unsigned FIFOBA25 :1; + unsigned FIFOBA26 :1; + unsigned FIFOBA27 :1; + unsigned FIFOBA28 :1; + unsigned FIFOBA29 :1; + unsigned FIFOBA30 :1; + unsigned FIFOBA31 :1; + }; +} C1FIFOBATbits_t; +extern volatile C1FIFOBATbits_t C1FIFOBATbits __attribute__((address(0x14F))); +# 13519 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONL __attribute__((address(0x150))); + +__asm("C1TXQCONL equ 0150h"); + + +typedef union { + struct { + unsigned TXQNIE :1; + unsigned :1; + unsigned TXQEIE :1; + unsigned :1; + unsigned TXATIE :1; + unsigned :2; + unsigned TXEN :1; + }; +} C1TXQCONLbits_t; +extern volatile C1TXQCONLbits_t C1TXQCONLbits __attribute__((address(0x150))); +# 13560 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONH __attribute__((address(0x151))); + +__asm("C1TXQCONH equ 0151h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1TXQCONHbits_t; +extern volatile C1TXQCONHbits_t C1TXQCONHbits __attribute__((address(0x151))); +# 13592 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONU __attribute__((address(0x152))); + +__asm("C1TXQCONU equ 0152h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1TXQCONUbits_t; +extern volatile C1TXQCONUbits_t C1TXQCONUbits __attribute__((address(0x152))); +# 13662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQCONT __attribute__((address(0x153))); + +__asm("C1TXQCONT equ 0153h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1TXQCONTbits_t; +extern volatile C1TXQCONTbits_t C1TXQCONTbits __attribute__((address(0x153))); +# 13738 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAL __attribute__((address(0x154))); + +__asm("C1TXQSTAL equ 0154h"); + + +typedef union { + struct { + unsigned TXQNIF :1; + unsigned :1; + unsigned TXQEIF :1; + unsigned :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1TXQSTALbits_t; +extern volatile C1TXQSTALbits_t C1TXQSTALbits __attribute__((address(0x154))); +# 13790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAH __attribute__((address(0x155))); + +__asm("C1TXQSTAH equ 0155h"); + + +typedef union { + struct { + unsigned TXQCI :5; + }; + struct { + unsigned TXQCI0 :1; + unsigned TXQCI1 :1; + unsigned TXQCI2 :1; + unsigned TXQCI3 :1; + unsigned TXQCI4 :1; + }; +} C1TXQSTAHbits_t; +extern volatile C1TXQSTAHbits_t C1TXQSTAHbits __attribute__((address(0x155))); +# 13842 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQSTAU __attribute__((address(0x156))); + +__asm("C1TXQSTAU equ 0156h"); + + + + +extern volatile unsigned char C1TXQSTAT __attribute__((address(0x157))); + +__asm("C1TXQSTAT equ 0157h"); + + + + +extern volatile unsigned long C1TXQUA __attribute__((address(0x158))); + +__asm("C1TXQUA equ 0158h"); + + + + +extern volatile unsigned char C1TXQUAL __attribute__((address(0x158))); + +__asm("C1TXQUAL equ 0158h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA0 :1; + unsigned TXQUA1 :1; + unsigned TXQUA2 :1; + unsigned TXQUA3 :1; + unsigned TXQUA4 :1; + unsigned TXQUA5 :1; + unsigned TXQUA6 :1; + unsigned TXQUA7 :1; + }; +} C1TXQUALbits_t; +extern volatile C1TXQUALbits_t C1TXQUALbits __attribute__((address(0x158))); +# 13933 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAH __attribute__((address(0x159))); + +__asm("C1TXQUAH equ 0159h"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA8 :1; + unsigned TXQUA9 :1; + unsigned TXQUA10 :1; + unsigned TXQUA11 :1; + unsigned TXQUA12 :1; + unsigned TXQUA13 :1; + unsigned TXQUA14 :1; + unsigned TXQUA15 :1; + }; +} C1TXQUAHbits_t; +extern volatile C1TXQUAHbits_t C1TXQUAHbits __attribute__((address(0x159))); +# 14003 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAU __attribute__((address(0x15A))); + +__asm("C1TXQUAU equ 015Ah"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA16 :1; + unsigned TXQUA17 :1; + unsigned TXQUA18 :1; + unsigned TXQUA19 :1; + unsigned TXQUA20 :1; + unsigned TXQUA21 :1; + unsigned TXQUA22 :1; + unsigned TXQUA23 :1; + }; +} C1TXQUAUbits_t; +extern volatile C1TXQUAUbits_t C1TXQUAUbits __attribute__((address(0x15A))); +# 14073 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1TXQUAT __attribute__((address(0x15B))); + +__asm("C1TXQUAT equ 015Bh"); + + +typedef union { + struct { + unsigned TXQUA :8; + }; + struct { + unsigned TXQUA24 :1; + unsigned TXQUA25 :1; + unsigned TXQUA26 :1; + unsigned TXQUA27 :1; + unsigned TXQUA28 :1; + unsigned TXQUA29 :1; + unsigned TXQUA30 :1; + unsigned TXQUA31 :1; + }; +} C1TXQUATbits_t; +extern volatile C1TXQUATbits_t C1TXQUATbits __attribute__((address(0x15B))); +# 14143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON1 __attribute__((address(0x15C))); + +__asm("C1FIFOCON1 equ 015Ch"); + + + + +extern volatile unsigned char C1FIFOCON1L __attribute__((address(0x15C))); + +__asm("C1FIFOCON1L equ 015Ch"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON1Lbits_t; +extern volatile C1FIFOCON1Lbits_t C1FIFOCON1Lbits __attribute__((address(0x15C))); +# 14212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1H __attribute__((address(0x15D))); + +__asm("C1FIFOCON1H equ 015Dh"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON1Hbits_t; +extern volatile C1FIFOCON1Hbits_t C1FIFOCON1Hbits __attribute__((address(0x15D))); +# 14244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1U __attribute__((address(0x15E))); + +__asm("C1FIFOCON1U equ 015Eh"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON1Ubits_t; +extern volatile C1FIFOCON1Ubits_t C1FIFOCON1Ubits __attribute__((address(0x15E))); +# 14314 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON1T __attribute__((address(0x15F))); + +__asm("C1FIFOCON1T equ 015Fh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON1Tbits_t; +extern volatile C1FIFOCON1Tbits_t C1FIFOCON1Tbits __attribute__((address(0x15F))); +# 14390 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA1 __attribute__((address(0x160))); + +__asm("C1FIFOSTA1 equ 0160h"); + + + + +extern volatile unsigned char C1FIFOSTA1L __attribute__((address(0x160))); + +__asm("C1FIFOSTA1L equ 0160h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA1Lbits_t; +extern volatile C1FIFOSTA1Lbits_t C1FIFOSTA1Lbits __attribute__((address(0x160))); +# 14459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1H __attribute__((address(0x161))); + +__asm("C1FIFOSTA1H equ 0161h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA1Hbits_t; +extern volatile C1FIFOSTA1Hbits_t C1FIFOSTA1Hbits __attribute__((address(0x161))); +# 14511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA1U __attribute__((address(0x162))); + +__asm("C1FIFOSTA1U equ 0162h"); + + + + +extern volatile unsigned char C1FIFOSTA1T __attribute__((address(0x163))); + +__asm("C1FIFOSTA1T equ 0163h"); + + + + +extern volatile unsigned long C1FIFOUA1 __attribute__((address(0x164))); + +__asm("C1FIFOUA1 equ 0164h"); + + + + +extern volatile unsigned char C1FIFOUA1L __attribute__((address(0x164))); + +__asm("C1FIFOUA1L equ 0164h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA1Lbits_t; +extern volatile C1FIFOUA1Lbits_t C1FIFOUA1Lbits __attribute__((address(0x164))); +# 14602 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1H __attribute__((address(0x165))); + +__asm("C1FIFOUA1H equ 0165h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA1Hbits_t; +extern volatile C1FIFOUA1Hbits_t C1FIFOUA1Hbits __attribute__((address(0x165))); +# 14672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1U __attribute__((address(0x166))); + +__asm("C1FIFOUA1U equ 0166h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA1Ubits_t; +extern volatile C1FIFOUA1Ubits_t C1FIFOUA1Ubits __attribute__((address(0x166))); +# 14742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA1T __attribute__((address(0x167))); + +__asm("C1FIFOUA1T equ 0167h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA1Tbits_t; +extern volatile C1FIFOUA1Tbits_t C1FIFOUA1Tbits __attribute__((address(0x167))); +# 14812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON2 __attribute__((address(0x168))); + +__asm("C1FIFOCON2 equ 0168h"); + + + + +extern volatile unsigned char C1FIFOCON2L __attribute__((address(0x168))); + +__asm("C1FIFOCON2L equ 0168h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON2Lbits_t; +extern volatile C1FIFOCON2Lbits_t C1FIFOCON2Lbits __attribute__((address(0x168))); +# 14881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2H __attribute__((address(0x169))); + +__asm("C1FIFOCON2H equ 0169h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON2Hbits_t; +extern volatile C1FIFOCON2Hbits_t C1FIFOCON2Hbits __attribute__((address(0x169))); +# 14913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2U __attribute__((address(0x16A))); + +__asm("C1FIFOCON2U equ 016Ah"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON2Ubits_t; +extern volatile C1FIFOCON2Ubits_t C1FIFOCON2Ubits __attribute__((address(0x16A))); +# 14983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON2T __attribute__((address(0x16B))); + +__asm("C1FIFOCON2T equ 016Bh"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON2Tbits_t; +extern volatile C1FIFOCON2Tbits_t C1FIFOCON2Tbits __attribute__((address(0x16B))); +# 15059 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA2 __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2 equ 016Ch"); + + + + +extern volatile unsigned char C1FIFOSTA2L __attribute__((address(0x16C))); + +__asm("C1FIFOSTA2L equ 016Ch"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA2Lbits_t; +extern volatile C1FIFOSTA2Lbits_t C1FIFOSTA2Lbits __attribute__((address(0x16C))); +# 15128 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2H __attribute__((address(0x16D))); + +__asm("C1FIFOSTA2H equ 016Dh"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA2Hbits_t; +extern volatile C1FIFOSTA2Hbits_t C1FIFOSTA2Hbits __attribute__((address(0x16D))); +# 15180 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA2U __attribute__((address(0x16E))); + +__asm("C1FIFOSTA2U equ 016Eh"); + + + + +extern volatile unsigned char C1FIFOSTA2T __attribute__((address(0x16F))); + +__asm("C1FIFOSTA2T equ 016Fh"); + + + + +extern volatile unsigned long C1FIFOUA2 __attribute__((address(0x170))); + +__asm("C1FIFOUA2 equ 0170h"); + + + + +extern volatile unsigned char C1FIFOUA2L __attribute__((address(0x170))); + +__asm("C1FIFOUA2L equ 0170h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA2Lbits_t; +extern volatile C1FIFOUA2Lbits_t C1FIFOUA2Lbits __attribute__((address(0x170))); +# 15271 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2H __attribute__((address(0x171))); + +__asm("C1FIFOUA2H equ 0171h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA2Hbits_t; +extern volatile C1FIFOUA2Hbits_t C1FIFOUA2Hbits __attribute__((address(0x171))); +# 15341 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2U __attribute__((address(0x172))); + +__asm("C1FIFOUA2U equ 0172h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA2Ubits_t; +extern volatile C1FIFOUA2Ubits_t C1FIFOUA2Ubits __attribute__((address(0x172))); +# 15411 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA2T __attribute__((address(0x173))); + +__asm("C1FIFOUA2T equ 0173h"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA2Tbits_t; +extern volatile C1FIFOUA2Tbits_t C1FIFOUA2Tbits __attribute__((address(0x173))); +# 15481 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOCON3 __attribute__((address(0x174))); + +__asm("C1FIFOCON3 equ 0174h"); + + + + +extern volatile unsigned char C1FIFOCON3L __attribute__((address(0x174))); + +__asm("C1FIFOCON3L equ 0174h"); + + +typedef union { + struct { + unsigned TFNRFNIE :1; + unsigned TFHRFHIE :1; + unsigned TFERFFIE :1; + unsigned RXOVIE :1; + unsigned TXATIE :1; + unsigned RXTSEN :1; + unsigned RTREN :1; + unsigned TXEN :1; + }; +} C1FIFOCON3Lbits_t; +extern volatile C1FIFOCON3Lbits_t C1FIFOCON3Lbits __attribute__((address(0x174))); +# 15550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3H __attribute__((address(0x175))); + +__asm("C1FIFOCON3H equ 0175h"); + + +typedef union { + struct { + unsigned UINC :1; + unsigned TXREQ :1; + unsigned FRESET :1; + }; +} C1FIFOCON3Hbits_t; +extern volatile C1FIFOCON3Hbits_t C1FIFOCON3Hbits __attribute__((address(0x175))); +# 15582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3U __attribute__((address(0x176))); + +__asm("C1FIFOCON3U equ 0176h"); + + +typedef union { + struct { + unsigned TXPRI :5; + unsigned TXAT :2; + }; + struct { + unsigned TXPRI0 :1; + unsigned TXPRI1 :1; + unsigned TXPRI2 :1; + unsigned TXPRI3 :1; + unsigned TXPRI4 :1; + unsigned TXAT0 :1; + unsigned TXAT1 :1; + }; +} C1FIFOCON3Ubits_t; +extern volatile C1FIFOCON3Ubits_t C1FIFOCON3Ubits __attribute__((address(0x176))); +# 15652 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOCON3T __attribute__((address(0x177))); + +__asm("C1FIFOCON3T equ 0177h"); + + +typedef union { + struct { + unsigned FSIZE :5; + unsigned PLSIZE :3; + }; + struct { + unsigned FSIZE0 :1; + unsigned FSIZE1 :1; + unsigned FSIZE2 :1; + unsigned FSIZE3 :1; + unsigned FSIZE4 :1; + unsigned PLSIZE0 :1; + unsigned PLSIZE1 :1; + unsigned PLSIZE2 :1; + }; +} C1FIFOCON3Tbits_t; +extern volatile C1FIFOCON3Tbits_t C1FIFOCON3Tbits __attribute__((address(0x177))); +# 15728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FIFOSTA3 __attribute__((address(0x178))); + +__asm("C1FIFOSTA3 equ 0178h"); + + + + +extern volatile unsigned char C1FIFOSTA3L __attribute__((address(0x178))); + +__asm("C1FIFOSTA3L equ 0178h"); + + +typedef union { + struct { + unsigned TFNRFNIF :1; + unsigned TFHRFHIF :1; + unsigned TFERFFIF :1; + unsigned RXOVIF :1; + unsigned TXATIF :1; + unsigned TXERR :1; + unsigned TXLARB :1; + unsigned TXABT :1; + }; +} C1FIFOSTA3Lbits_t; +extern volatile C1FIFOSTA3Lbits_t C1FIFOSTA3Lbits __attribute__((address(0x178))); +# 15797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3H __attribute__((address(0x179))); + +__asm("C1FIFOSTA3H equ 0179h"); + + +typedef union { + struct { + unsigned FIFOCI :5; + }; + struct { + unsigned FIFOCI0 :1; + unsigned FIFOCI1 :1; + unsigned FIFOCI2 :1; + unsigned FIFOCI3 :1; + unsigned FIFOCI4 :1; + }; +} C1FIFOSTA3Hbits_t; +extern volatile C1FIFOSTA3Hbits_t C1FIFOSTA3Hbits __attribute__((address(0x179))); +# 15849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOSTA3U __attribute__((address(0x17A))); + +__asm("C1FIFOSTA3U equ 017Ah"); + + + + +extern volatile unsigned char C1FIFOSTA3T __attribute__((address(0x17B))); + +__asm("C1FIFOSTA3T equ 017Bh"); + + + + +extern volatile unsigned long C1FIFOUA3 __attribute__((address(0x17C))); + +__asm("C1FIFOUA3 equ 017Ch"); + + + + +extern volatile unsigned char C1FIFOUA3L __attribute__((address(0x17C))); + +__asm("C1FIFOUA3L equ 017Ch"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA0 :1; + unsigned FIFOUA1 :1; + unsigned FIFOUA2 :1; + unsigned FIFOUA3 :1; + unsigned FIFOUA4 :1; + unsigned FIFOUA5 :1; + unsigned FIFOUA6 :1; + unsigned FIFOUA7 :1; + }; +} C1FIFOUA3Lbits_t; +extern volatile C1FIFOUA3Lbits_t C1FIFOUA3Lbits __attribute__((address(0x17C))); +# 15940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3H __attribute__((address(0x17D))); + +__asm("C1FIFOUA3H equ 017Dh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA8 :1; + unsigned FIFOUA9 :1; + unsigned FIFOUA10 :1; + unsigned FIFOUA11 :1; + unsigned FIFOUA12 :1; + unsigned FIFOUA13 :1; + unsigned FIFOUA14 :1; + unsigned FIFOUA15 :1; + }; +} C1FIFOUA3Hbits_t; +extern volatile C1FIFOUA3Hbits_t C1FIFOUA3Hbits __attribute__((address(0x17D))); +# 16010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3U __attribute__((address(0x17E))); + +__asm("C1FIFOUA3U equ 017Eh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA16 :1; + unsigned FIFOUA17 :1; + unsigned FIFOUA18 :1; + unsigned FIFOUA19 :1; + unsigned FIFOUA20 :1; + unsigned FIFOUA21 :1; + unsigned FIFOUA22 :1; + unsigned FIFOUA23 :1; + }; +} C1FIFOUA3Ubits_t; +extern volatile C1FIFOUA3Ubits_t C1FIFOUA3Ubits __attribute__((address(0x17E))); +# 16080 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FIFOUA3T __attribute__((address(0x17F))); + +__asm("C1FIFOUA3T equ 017Fh"); + + +typedef union { + struct { + unsigned FIFOUA :8; + }; + struct { + unsigned FIFOUA24 :1; + unsigned FIFOUA25 :1; + unsigned FIFOUA26 :1; + unsigned FIFOUA27 :1; + unsigned FIFOUA28 :1; + unsigned FIFOUA29 :1; + unsigned FIFOUA30 :1; + unsigned FIFOUA31 :1; + }; +} C1FIFOUA3Tbits_t; +extern volatile C1FIFOUA3Tbits_t C1FIFOUA3Tbits __attribute__((address(0x17F))); +# 16150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0L __attribute__((address(0x180))); + +__asm("C1FLTCON0L equ 0180h"); + + +typedef union { + struct { + unsigned F0BP :5; + unsigned :2; + unsigned FLTEN0 :1; + }; + struct { + unsigned F0BP0 :1; + unsigned F0BP1 :1; + unsigned F0BP2 :1; + unsigned F0BP3 :1; + unsigned F0BP4 :1; + }; +} C1FLTCON0Lbits_t; +extern volatile C1FLTCON0Lbits_t C1FLTCON0Lbits __attribute__((address(0x180))); +# 16209 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0H __attribute__((address(0x181))); + +__asm("C1FLTCON0H equ 0181h"); + + +typedef union { + struct { + unsigned F1BP :5; + unsigned :2; + unsigned FLTEN1 :1; + }; + struct { + unsigned F1BP0 :1; + unsigned F1BP1 :1; + unsigned F1BP2 :1; + unsigned F1BP3 :1; + unsigned F1BP4 :1; + }; +} C1FLTCON0Hbits_t; +extern volatile C1FLTCON0Hbits_t C1FLTCON0Hbits __attribute__((address(0x181))); +# 16268 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0U __attribute__((address(0x182))); + +__asm("C1FLTCON0U equ 0182h"); + + +typedef union { + struct { + unsigned F2BP :5; + unsigned :2; + unsigned FLTEN2 :1; + }; + struct { + unsigned F2BP0 :1; + unsigned F2BP1 :1; + unsigned F2BP2 :1; + unsigned F2BP3 :1; + unsigned F2BP4 :1; + }; +} C1FLTCON0Ubits_t; +extern volatile C1FLTCON0Ubits_t C1FLTCON0Ubits __attribute__((address(0x182))); +# 16327 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON0T __attribute__((address(0x183))); + +__asm("C1FLTCON0T equ 0183h"); + + +typedef union { + struct { + unsigned F3BP :5; + unsigned :2; + unsigned FLTEN3 :1; + }; + struct { + unsigned F3BP0 :1; + unsigned F3BP1 :1; + unsigned F3BP2 :1; + unsigned F3BP3 :1; + unsigned F3BP4 :1; + }; +} C1FLTCON0Tbits_t; +extern volatile C1FLTCON0Tbits_t C1FLTCON0Tbits __attribute__((address(0x183))); +# 16386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1L __attribute__((address(0x184))); + +__asm("C1FLTCON1L equ 0184h"); + + +typedef union { + struct { + unsigned F4BP :5; + unsigned :2; + unsigned FLTEN4 :1; + }; + struct { + unsigned F4BP0 :1; + unsigned F4BP1 :1; + unsigned F4BP2 :1; + unsigned F4BP3 :1; + unsigned F4BP4 :1; + }; +} C1FLTCON1Lbits_t; +extern volatile C1FLTCON1Lbits_t C1FLTCON1Lbits __attribute__((address(0x184))); +# 16445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1H __attribute__((address(0x185))); + +__asm("C1FLTCON1H equ 0185h"); + + +typedef union { + struct { + unsigned F5BP :5; + unsigned :2; + unsigned FLTEN5 :1; + }; + struct { + unsigned F5BP0 :1; + unsigned F5BP1 :1; + unsigned F5BP2 :1; + unsigned F5BP3 :1; + unsigned F5BP4 :1; + }; +} C1FLTCON1Hbits_t; +extern volatile C1FLTCON1Hbits_t C1FLTCON1Hbits __attribute__((address(0x185))); +# 16504 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1U __attribute__((address(0x186))); + +__asm("C1FLTCON1U equ 0186h"); + + +typedef union { + struct { + unsigned F6BP :5; + unsigned :2; + unsigned FLTEN6 :1; + }; + struct { + unsigned F6BP0 :1; + unsigned F6BP1 :1; + unsigned F6BP2 :1; + unsigned F6BP3 :1; + unsigned F6BP4 :1; + }; +} C1FLTCON1Ubits_t; +extern volatile C1FLTCON1Ubits_t C1FLTCON1Ubits __attribute__((address(0x186))); +# 16563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON1T __attribute__((address(0x187))); + +__asm("C1FLTCON1T equ 0187h"); + + +typedef union { + struct { + unsigned F7BP :5; + unsigned :2; + unsigned FLTEN7 :1; + }; + struct { + unsigned F7BP0 :1; + unsigned F7BP1 :1; + unsigned F7BP2 :1; + unsigned F7BP3 :1; + unsigned F7BP4 :1; + }; +} C1FLTCON1Tbits_t; +extern volatile C1FLTCON1Tbits_t C1FLTCON1Tbits __attribute__((address(0x187))); +# 16622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2L __attribute__((address(0x188))); + +__asm("C1FLTCON2L equ 0188h"); + + +typedef union { + struct { + unsigned F8BP :5; + unsigned :2; + unsigned FLTEN8 :1; + }; + struct { + unsigned F8BP0 :1; + unsigned F8BP1 :1; + unsigned F8BP2 :1; + unsigned F8BP3 :1; + unsigned F8BP4 :1; + }; +} C1FLTCON2Lbits_t; +extern volatile C1FLTCON2Lbits_t C1FLTCON2Lbits __attribute__((address(0x188))); +# 16681 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2H __attribute__((address(0x189))); + +__asm("C1FLTCON2H equ 0189h"); + + +typedef union { + struct { + unsigned F9BP :5; + unsigned :2; + unsigned FLTEN9 :1; + }; + struct { + unsigned F9BP0 :1; + unsigned F9BP1 :1; + unsigned F9BP2 :1; + unsigned F9BP3 :1; + unsigned F9BP4 :1; + }; +} C1FLTCON2Hbits_t; +extern volatile C1FLTCON2Hbits_t C1FLTCON2Hbits __attribute__((address(0x189))); +# 16740 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2U __attribute__((address(0x18A))); + +__asm("C1FLTCON2U equ 018Ah"); + + +typedef union { + struct { + unsigned F10BP :5; + unsigned :2; + unsigned FLTEN10 :1; + }; + struct { + unsigned F10BP0 :1; + unsigned F10BP1 :1; + unsigned F10BP2 :1; + unsigned F10BP3 :1; + unsigned F10BP4 :1; + }; +} C1FLTCON2Ubits_t; +extern volatile C1FLTCON2Ubits_t C1FLTCON2Ubits __attribute__((address(0x18A))); +# 16799 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTCON2T __attribute__((address(0x18B))); + +__asm("C1FLTCON2T equ 018Bh"); + + +typedef union { + struct { + unsigned F11BP :5; + unsigned :2; + unsigned FLTEN11 :1; + }; + struct { + unsigned F11BP0 :1; + unsigned F11BP1 :1; + unsigned F11BP2 :1; + unsigned F11BP3 :1; + unsigned F11BP4 :1; + }; +} C1FLTCON2Tbits_t; +extern volatile C1FLTCON2Tbits_t C1FLTCON2Tbits __attribute__((address(0x18B))); +# 16858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ0 __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0 equ 018Ch"); + + + + +extern volatile unsigned char C1FLTOBJ0L __attribute__((address(0x18C))); + +__asm("C1FLTOBJ0L equ 018Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ0Lbits_t; +extern volatile C1FLTOBJ0Lbits_t C1FLTOBJ0Lbits __attribute__((address(0x18C))); +# 16935 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0H __attribute__((address(0x18D))); + +__asm("C1FLTOBJ0H equ 018Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ0Hbits_t; +extern volatile C1FLTOBJ0Hbits_t C1FLTOBJ0Hbits __attribute__((address(0x18D))); +# 17011 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0U __attribute__((address(0x18E))); + +__asm("C1FLTOBJ0U equ 018Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ0Ubits_t; +extern volatile C1FLTOBJ0Ubits_t C1FLTOBJ0Ubits __attribute__((address(0x18E))); +# 17081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ0T __attribute__((address(0x18F))); + +__asm("C1FLTOBJ0T equ 018Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ0Tbits_t; +extern volatile C1FLTOBJ0Tbits_t C1FLTOBJ0Tbits __attribute__((address(0x18F))); +# 17145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK0 __attribute__((address(0x190))); + +__asm("C1MASK0 equ 0190h"); + + + + +extern volatile unsigned char C1MASK0L __attribute__((address(0x190))); + +__asm("C1MASK0L equ 0190h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK0Lbits_t; +extern volatile C1MASK0Lbits_t C1MASK0Lbits __attribute__((address(0x190))); +# 17222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0H __attribute__((address(0x191))); + +__asm("C1MASK0H equ 0191h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK0Hbits_t; +extern volatile C1MASK0Hbits_t C1MASK0Hbits __attribute__((address(0x191))); +# 17298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0U __attribute__((address(0x192))); + +__asm("C1MASK0U equ 0192h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK0Ubits_t; +extern volatile C1MASK0Ubits_t C1MASK0Ubits __attribute__((address(0x192))); +# 17368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK0T __attribute__((address(0x193))); + +__asm("C1MASK0T equ 0193h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK0Tbits_t; +extern volatile C1MASK0Tbits_t C1MASK0Tbits __attribute__((address(0x193))); +# 17432 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ1 __attribute__((address(0x194))); + +__asm("C1FLTOBJ1 equ 0194h"); + + + + +extern volatile unsigned char C1FLTOBJ1L __attribute__((address(0x194))); + +__asm("C1FLTOBJ1L equ 0194h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ1Lbits_t; +extern volatile C1FLTOBJ1Lbits_t C1FLTOBJ1Lbits __attribute__((address(0x194))); +# 17509 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1H __attribute__((address(0x195))); + +__asm("C1FLTOBJ1H equ 0195h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ1Hbits_t; +extern volatile C1FLTOBJ1Hbits_t C1FLTOBJ1Hbits __attribute__((address(0x195))); +# 17585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1U __attribute__((address(0x196))); + +__asm("C1FLTOBJ1U equ 0196h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ1Ubits_t; +extern volatile C1FLTOBJ1Ubits_t C1FLTOBJ1Ubits __attribute__((address(0x196))); +# 17655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ1T __attribute__((address(0x197))); + +__asm("C1FLTOBJ1T equ 0197h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ1Tbits_t; +extern volatile C1FLTOBJ1Tbits_t C1FLTOBJ1Tbits __attribute__((address(0x197))); +# 17719 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK1 __attribute__((address(0x198))); + +__asm("C1MASK1 equ 0198h"); + + + + +extern volatile unsigned char C1MASK1L __attribute__((address(0x198))); + +__asm("C1MASK1L equ 0198h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK1Lbits_t; +extern volatile C1MASK1Lbits_t C1MASK1Lbits __attribute__((address(0x198))); +# 17796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1H __attribute__((address(0x199))); + +__asm("C1MASK1H equ 0199h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK1Hbits_t; +extern volatile C1MASK1Hbits_t C1MASK1Hbits __attribute__((address(0x199))); +# 17872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1U __attribute__((address(0x19A))); + +__asm("C1MASK1U equ 019Ah"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK1Ubits_t; +extern volatile C1MASK1Ubits_t C1MASK1Ubits __attribute__((address(0x19A))); +# 17942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK1T __attribute__((address(0x19B))); + +__asm("C1MASK1T equ 019Bh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK1Tbits_t; +extern volatile C1MASK1Tbits_t C1MASK1Tbits __attribute__((address(0x19B))); +# 18006 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ2 __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2 equ 019Ch"); + + + + +extern volatile unsigned char C1FLTOBJ2L __attribute__((address(0x19C))); + +__asm("C1FLTOBJ2L equ 019Ch"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ2Lbits_t; +extern volatile C1FLTOBJ2Lbits_t C1FLTOBJ2Lbits __attribute__((address(0x19C))); +# 18083 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2H __attribute__((address(0x19D))); + +__asm("C1FLTOBJ2H equ 019Dh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ2Hbits_t; +extern volatile C1FLTOBJ2Hbits_t C1FLTOBJ2Hbits __attribute__((address(0x19D))); +# 18159 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2U __attribute__((address(0x19E))); + +__asm("C1FLTOBJ2U equ 019Eh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ2Ubits_t; +extern volatile C1FLTOBJ2Ubits_t C1FLTOBJ2Ubits __attribute__((address(0x19E))); +# 18229 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ2T __attribute__((address(0x19F))); + +__asm("C1FLTOBJ2T equ 019Fh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ2Tbits_t; +extern volatile C1FLTOBJ2Tbits_t C1FLTOBJ2Tbits __attribute__((address(0x19F))); +# 18293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK2 __attribute__((address(0x1A0))); + +__asm("C1MASK2 equ 01A0h"); + + + + +extern volatile unsigned char C1MASK2L __attribute__((address(0x1A0))); + +__asm("C1MASK2L equ 01A0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK2Lbits_t; +extern volatile C1MASK2Lbits_t C1MASK2Lbits __attribute__((address(0x1A0))); +# 18370 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2H __attribute__((address(0x1A1))); + +__asm("C1MASK2H equ 01A1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK2Hbits_t; +extern volatile C1MASK2Hbits_t C1MASK2Hbits __attribute__((address(0x1A1))); +# 18446 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2U __attribute__((address(0x1A2))); + +__asm("C1MASK2U equ 01A2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK2Ubits_t; +extern volatile C1MASK2Ubits_t C1MASK2Ubits __attribute__((address(0x1A2))); +# 18516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK2T __attribute__((address(0x1A3))); + +__asm("C1MASK2T equ 01A3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK2Tbits_t; +extern volatile C1MASK2Tbits_t C1MASK2Tbits __attribute__((address(0x1A3))); +# 18580 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ3 __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3 equ 01A4h"); + + + + +extern volatile unsigned char C1FLTOBJ3L __attribute__((address(0x1A4))); + +__asm("C1FLTOBJ3L equ 01A4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ3Lbits_t; +extern volatile C1FLTOBJ3Lbits_t C1FLTOBJ3Lbits __attribute__((address(0x1A4))); +# 18657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3H __attribute__((address(0x1A5))); + +__asm("C1FLTOBJ3H equ 01A5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ3Hbits_t; +extern volatile C1FLTOBJ3Hbits_t C1FLTOBJ3Hbits __attribute__((address(0x1A5))); +# 18733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3U __attribute__((address(0x1A6))); + +__asm("C1FLTOBJ3U equ 01A6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ3Ubits_t; +extern volatile C1FLTOBJ3Ubits_t C1FLTOBJ3Ubits __attribute__((address(0x1A6))); +# 18803 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ3T __attribute__((address(0x1A7))); + +__asm("C1FLTOBJ3T equ 01A7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ3Tbits_t; +extern volatile C1FLTOBJ3Tbits_t C1FLTOBJ3Tbits __attribute__((address(0x1A7))); +# 18867 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK3 __attribute__((address(0x1A8))); + +__asm("C1MASK3 equ 01A8h"); + + + + +extern volatile unsigned char C1MASK3L __attribute__((address(0x1A8))); + +__asm("C1MASK3L equ 01A8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK3Lbits_t; +extern volatile C1MASK3Lbits_t C1MASK3Lbits __attribute__((address(0x1A8))); +# 18944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3H __attribute__((address(0x1A9))); + +__asm("C1MASK3H equ 01A9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK3Hbits_t; +extern volatile C1MASK3Hbits_t C1MASK3Hbits __attribute__((address(0x1A9))); +# 19020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3U __attribute__((address(0x1AA))); + +__asm("C1MASK3U equ 01AAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK3Ubits_t; +extern volatile C1MASK3Ubits_t C1MASK3Ubits __attribute__((address(0x1AA))); +# 19090 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK3T __attribute__((address(0x1AB))); + +__asm("C1MASK3T equ 01ABh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK3Tbits_t; +extern volatile C1MASK3Tbits_t C1MASK3Tbits __attribute__((address(0x1AB))); +# 19154 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ4 __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4 equ 01ACh"); + + + + +extern volatile unsigned char C1FLTOBJ4L __attribute__((address(0x1AC))); + +__asm("C1FLTOBJ4L equ 01ACh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ4Lbits_t; +extern volatile C1FLTOBJ4Lbits_t C1FLTOBJ4Lbits __attribute__((address(0x1AC))); +# 19231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4H __attribute__((address(0x1AD))); + +__asm("C1FLTOBJ4H equ 01ADh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ4Hbits_t; +extern volatile C1FLTOBJ4Hbits_t C1FLTOBJ4Hbits __attribute__((address(0x1AD))); +# 19307 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4U __attribute__((address(0x1AE))); + +__asm("C1FLTOBJ4U equ 01AEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ4Ubits_t; +extern volatile C1FLTOBJ4Ubits_t C1FLTOBJ4Ubits __attribute__((address(0x1AE))); +# 19377 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ4T __attribute__((address(0x1AF))); + +__asm("C1FLTOBJ4T equ 01AFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ4Tbits_t; +extern volatile C1FLTOBJ4Tbits_t C1FLTOBJ4Tbits __attribute__((address(0x1AF))); +# 19441 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK4 __attribute__((address(0x1B0))); + +__asm("C1MASK4 equ 01B0h"); + + + + +extern volatile unsigned char C1MASK4L __attribute__((address(0x1B0))); + +__asm("C1MASK4L equ 01B0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK4Lbits_t; +extern volatile C1MASK4Lbits_t C1MASK4Lbits __attribute__((address(0x1B0))); +# 19518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4H __attribute__((address(0x1B1))); + +__asm("C1MASK4H equ 01B1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK4Hbits_t; +extern volatile C1MASK4Hbits_t C1MASK4Hbits __attribute__((address(0x1B1))); +# 19594 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4U __attribute__((address(0x1B2))); + +__asm("C1MASK4U equ 01B2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK4Ubits_t; +extern volatile C1MASK4Ubits_t C1MASK4Ubits __attribute__((address(0x1B2))); +# 19664 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK4T __attribute__((address(0x1B3))); + +__asm("C1MASK4T equ 01B3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK4Tbits_t; +extern volatile C1MASK4Tbits_t C1MASK4Tbits __attribute__((address(0x1B3))); +# 19728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ5 __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5 equ 01B4h"); + + + + +extern volatile unsigned char C1FLTOBJ5L __attribute__((address(0x1B4))); + +__asm("C1FLTOBJ5L equ 01B4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ5Lbits_t; +extern volatile C1FLTOBJ5Lbits_t C1FLTOBJ5Lbits __attribute__((address(0x1B4))); +# 19805 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5H __attribute__((address(0x1B5))); + +__asm("C1FLTOBJ5H equ 01B5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ5Hbits_t; +extern volatile C1FLTOBJ5Hbits_t C1FLTOBJ5Hbits __attribute__((address(0x1B5))); +# 19881 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5U __attribute__((address(0x1B6))); + +__asm("C1FLTOBJ5U equ 01B6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ5Ubits_t; +extern volatile C1FLTOBJ5Ubits_t C1FLTOBJ5Ubits __attribute__((address(0x1B6))); +# 19951 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ5T __attribute__((address(0x1B7))); + +__asm("C1FLTOBJ5T equ 01B7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ5Tbits_t; +extern volatile C1FLTOBJ5Tbits_t C1FLTOBJ5Tbits __attribute__((address(0x1B7))); +# 20015 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK5 __attribute__((address(0x1B8))); + +__asm("C1MASK5 equ 01B8h"); + + + + +extern volatile unsigned char C1MASK5L __attribute__((address(0x1B8))); + +__asm("C1MASK5L equ 01B8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK5Lbits_t; +extern volatile C1MASK5Lbits_t C1MASK5Lbits __attribute__((address(0x1B8))); +# 20092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5H __attribute__((address(0x1B9))); + +__asm("C1MASK5H equ 01B9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK5Hbits_t; +extern volatile C1MASK5Hbits_t C1MASK5Hbits __attribute__((address(0x1B9))); +# 20168 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5U __attribute__((address(0x1BA))); + +__asm("C1MASK5U equ 01BAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK5Ubits_t; +extern volatile C1MASK5Ubits_t C1MASK5Ubits __attribute__((address(0x1BA))); +# 20238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK5T __attribute__((address(0x1BB))); + +__asm("C1MASK5T equ 01BBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK5Tbits_t; +extern volatile C1MASK5Tbits_t C1MASK5Tbits __attribute__((address(0x1BB))); +# 20302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ6 __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6 equ 01BCh"); + + + + +extern volatile unsigned char C1FLTOBJ6L __attribute__((address(0x1BC))); + +__asm("C1FLTOBJ6L equ 01BCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ6Lbits_t; +extern volatile C1FLTOBJ6Lbits_t C1FLTOBJ6Lbits __attribute__((address(0x1BC))); +# 20379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6H __attribute__((address(0x1BD))); + +__asm("C1FLTOBJ6H equ 01BDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ6Hbits_t; +extern volatile C1FLTOBJ6Hbits_t C1FLTOBJ6Hbits __attribute__((address(0x1BD))); +# 20455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6U __attribute__((address(0x1BE))); + +__asm("C1FLTOBJ6U equ 01BEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ6Ubits_t; +extern volatile C1FLTOBJ6Ubits_t C1FLTOBJ6Ubits __attribute__((address(0x1BE))); +# 20525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ6T __attribute__((address(0x1BF))); + +__asm("C1FLTOBJ6T equ 01BFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ6Tbits_t; +extern volatile C1FLTOBJ6Tbits_t C1FLTOBJ6Tbits __attribute__((address(0x1BF))); +# 20589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK6 __attribute__((address(0x1C0))); + +__asm("C1MASK6 equ 01C0h"); + + + + +extern volatile unsigned char C1MASK6L __attribute__((address(0x1C0))); + +__asm("C1MASK6L equ 01C0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK6Lbits_t; +extern volatile C1MASK6Lbits_t C1MASK6Lbits __attribute__((address(0x1C0))); +# 20666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6H __attribute__((address(0x1C1))); + +__asm("C1MASK6H equ 01C1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK6Hbits_t; +extern volatile C1MASK6Hbits_t C1MASK6Hbits __attribute__((address(0x1C1))); +# 20742 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6U __attribute__((address(0x1C2))); + +__asm("C1MASK6U equ 01C2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK6Ubits_t; +extern volatile C1MASK6Ubits_t C1MASK6Ubits __attribute__((address(0x1C2))); +# 20812 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK6T __attribute__((address(0x1C3))); + +__asm("C1MASK6T equ 01C3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK6Tbits_t; +extern volatile C1MASK6Tbits_t C1MASK6Tbits __attribute__((address(0x1C3))); +# 20876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ7 __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7 equ 01C4h"); + + + + +extern volatile unsigned char C1FLTOBJ7L __attribute__((address(0x1C4))); + +__asm("C1FLTOBJ7L equ 01C4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ7Lbits_t; +extern volatile C1FLTOBJ7Lbits_t C1FLTOBJ7Lbits __attribute__((address(0x1C4))); +# 20953 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7H __attribute__((address(0x1C5))); + +__asm("C1FLTOBJ7H equ 01C5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ7Hbits_t; +extern volatile C1FLTOBJ7Hbits_t C1FLTOBJ7Hbits __attribute__((address(0x1C5))); +# 21029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7U __attribute__((address(0x1C6))); + +__asm("C1FLTOBJ7U equ 01C6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ7Ubits_t; +extern volatile C1FLTOBJ7Ubits_t C1FLTOBJ7Ubits __attribute__((address(0x1C6))); +# 21099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ7T __attribute__((address(0x1C7))); + +__asm("C1FLTOBJ7T equ 01C7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ7Tbits_t; +extern volatile C1FLTOBJ7Tbits_t C1FLTOBJ7Tbits __attribute__((address(0x1C7))); +# 21163 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK7 __attribute__((address(0x1C8))); + +__asm("C1MASK7 equ 01C8h"); + + + + +extern volatile unsigned char C1MASK7L __attribute__((address(0x1C8))); + +__asm("C1MASK7L equ 01C8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK7Lbits_t; +extern volatile C1MASK7Lbits_t C1MASK7Lbits __attribute__((address(0x1C8))); +# 21240 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7H __attribute__((address(0x1C9))); + +__asm("C1MASK7H equ 01C9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK7Hbits_t; +extern volatile C1MASK7Hbits_t C1MASK7Hbits __attribute__((address(0x1C9))); +# 21316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7U __attribute__((address(0x1CA))); + +__asm("C1MASK7U equ 01CAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK7Ubits_t; +extern volatile C1MASK7Ubits_t C1MASK7Ubits __attribute__((address(0x1CA))); +# 21386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK7T __attribute__((address(0x1CB))); + +__asm("C1MASK7T equ 01CBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK7Tbits_t; +extern volatile C1MASK7Tbits_t C1MASK7Tbits __attribute__((address(0x1CB))); +# 21450 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ8 __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8 equ 01CCh"); + + + + +extern volatile unsigned char C1FLTOBJ8L __attribute__((address(0x1CC))); + +__asm("C1FLTOBJ8L equ 01CCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ8Lbits_t; +extern volatile C1FLTOBJ8Lbits_t C1FLTOBJ8Lbits __attribute__((address(0x1CC))); +# 21527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8H __attribute__((address(0x1CD))); + +__asm("C1FLTOBJ8H equ 01CDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ8Hbits_t; +extern volatile C1FLTOBJ8Hbits_t C1FLTOBJ8Hbits __attribute__((address(0x1CD))); +# 21603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8U __attribute__((address(0x1CE))); + +__asm("C1FLTOBJ8U equ 01CEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ8Ubits_t; +extern volatile C1FLTOBJ8Ubits_t C1FLTOBJ8Ubits __attribute__((address(0x1CE))); +# 21673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ8T __attribute__((address(0x1CF))); + +__asm("C1FLTOBJ8T equ 01CFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ8Tbits_t; +extern volatile C1FLTOBJ8Tbits_t C1FLTOBJ8Tbits __attribute__((address(0x1CF))); +# 21737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK8 __attribute__((address(0x1D0))); + +__asm("C1MASK8 equ 01D0h"); + + + + +extern volatile unsigned char C1MASK8L __attribute__((address(0x1D0))); + +__asm("C1MASK8L equ 01D0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK8Lbits_t; +extern volatile C1MASK8Lbits_t C1MASK8Lbits __attribute__((address(0x1D0))); +# 21814 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8H __attribute__((address(0x1D1))); + +__asm("C1MASK8H equ 01D1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK8Hbits_t; +extern volatile C1MASK8Hbits_t C1MASK8Hbits __attribute__((address(0x1D1))); +# 21890 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8U __attribute__((address(0x1D2))); + +__asm("C1MASK8U equ 01D2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK8Ubits_t; +extern volatile C1MASK8Ubits_t C1MASK8Ubits __attribute__((address(0x1D2))); +# 21960 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK8T __attribute__((address(0x1D3))); + +__asm("C1MASK8T equ 01D3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK8Tbits_t; +extern volatile C1MASK8Tbits_t C1MASK8Tbits __attribute__((address(0x1D3))); +# 22024 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ9 __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9 equ 01D4h"); + + + + +extern volatile unsigned char C1FLTOBJ9L __attribute__((address(0x1D4))); + +__asm("C1FLTOBJ9L equ 01D4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ9Lbits_t; +extern volatile C1FLTOBJ9Lbits_t C1FLTOBJ9Lbits __attribute__((address(0x1D4))); +# 22101 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9H __attribute__((address(0x1D5))); + +__asm("C1FLTOBJ9H equ 01D5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ9Hbits_t; +extern volatile C1FLTOBJ9Hbits_t C1FLTOBJ9Hbits __attribute__((address(0x1D5))); +# 22177 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9U __attribute__((address(0x1D6))); + +__asm("C1FLTOBJ9U equ 01D6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ9Ubits_t; +extern volatile C1FLTOBJ9Ubits_t C1FLTOBJ9Ubits __attribute__((address(0x1D6))); +# 22247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ9T __attribute__((address(0x1D7))); + +__asm("C1FLTOBJ9T equ 01D7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ9Tbits_t; +extern volatile C1FLTOBJ9Tbits_t C1FLTOBJ9Tbits __attribute__((address(0x1D7))); +# 22311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK9 __attribute__((address(0x1D8))); + +__asm("C1MASK9 equ 01D8h"); + + + + +extern volatile unsigned char C1MASK9L __attribute__((address(0x1D8))); + +__asm("C1MASK9L equ 01D8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK9Lbits_t; +extern volatile C1MASK9Lbits_t C1MASK9Lbits __attribute__((address(0x1D8))); +# 22388 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9H __attribute__((address(0x1D9))); + +__asm("C1MASK9H equ 01D9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK9Hbits_t; +extern volatile C1MASK9Hbits_t C1MASK9Hbits __attribute__((address(0x1D9))); +# 22464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9U __attribute__((address(0x1DA))); + +__asm("C1MASK9U equ 01DAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK9Ubits_t; +extern volatile C1MASK9Ubits_t C1MASK9Ubits __attribute__((address(0x1DA))); +# 22534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK9T __attribute__((address(0x1DB))); + +__asm("C1MASK9T equ 01DBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK9Tbits_t; +extern volatile C1MASK9Tbits_t C1MASK9Tbits __attribute__((address(0x1DB))); +# 22598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ10 __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10 equ 01DCh"); + + + + +extern volatile unsigned char C1FLTOBJ10L __attribute__((address(0x1DC))); + +__asm("C1FLTOBJ10L equ 01DCh"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ10Lbits_t; +extern volatile C1FLTOBJ10Lbits_t C1FLTOBJ10Lbits __attribute__((address(0x1DC))); +# 22675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10H __attribute__((address(0x1DD))); + +__asm("C1FLTOBJ10H equ 01DDh"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ10Hbits_t; +extern volatile C1FLTOBJ10Hbits_t C1FLTOBJ10Hbits __attribute__((address(0x1DD))); +# 22751 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10U __attribute__((address(0x1DE))); + +__asm("C1FLTOBJ10U equ 01DEh"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ10Ubits_t; +extern volatile C1FLTOBJ10Ubits_t C1FLTOBJ10Ubits __attribute__((address(0x1DE))); +# 22821 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ10T __attribute__((address(0x1DF))); + +__asm("C1FLTOBJ10T equ 01DFh"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ10Tbits_t; +extern volatile C1FLTOBJ10Tbits_t C1FLTOBJ10Tbits __attribute__((address(0x1DF))); +# 22885 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK10 __attribute__((address(0x1E0))); + +__asm("C1MASK10 equ 01E0h"); + + + + +extern volatile unsigned char C1MASK10L __attribute__((address(0x1E0))); + +__asm("C1MASK10L equ 01E0h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK10Lbits_t; +extern volatile C1MASK10Lbits_t C1MASK10Lbits __attribute__((address(0x1E0))); +# 22962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10H __attribute__((address(0x1E1))); + +__asm("C1MASK10H equ 01E1h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK10Hbits_t; +extern volatile C1MASK10Hbits_t C1MASK10Hbits __attribute__((address(0x1E1))); +# 23038 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10U __attribute__((address(0x1E2))); + +__asm("C1MASK10U equ 01E2h"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK10Ubits_t; +extern volatile C1MASK10Ubits_t C1MASK10Ubits __attribute__((address(0x1E2))); +# 23108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK10T __attribute__((address(0x1E3))); + +__asm("C1MASK10T equ 01E3h"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK10Tbits_t; +extern volatile C1MASK10Tbits_t C1MASK10Tbits __attribute__((address(0x1E3))); +# 23172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1FLTOBJ11 __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11 equ 01E4h"); + + + + +extern volatile unsigned char C1FLTOBJ11L __attribute__((address(0x1E4))); + +__asm("C1FLTOBJ11L equ 01E4h"); + + +typedef union { + struct { + unsigned SID :8; + }; + struct { + unsigned SID0 :1; + unsigned SID1 :1; + unsigned SID2 :1; + unsigned SID3 :1; + unsigned SID4 :1; + unsigned SID5 :1; + unsigned SID6 :1; + unsigned SID7 :1; + }; +} C1FLTOBJ11Lbits_t; +extern volatile C1FLTOBJ11Lbits_t C1FLTOBJ11Lbits __attribute__((address(0x1E4))); +# 23249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11H __attribute__((address(0x1E5))); + +__asm("C1FLTOBJ11H equ 01E5h"); + + +typedef union { + struct { + unsigned SID :3; + unsigned EID :5; + }; + struct { + unsigned SID8 :1; + unsigned SID9 :1; + unsigned SID10 :1; + unsigned EID0 :1; + unsigned EID1 :1; + unsigned EID2 :1; + unsigned EID3 :1; + unsigned EID4 :1; + }; +} C1FLTOBJ11Hbits_t; +extern volatile C1FLTOBJ11Hbits_t C1FLTOBJ11Hbits __attribute__((address(0x1E5))); +# 23325 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11U __attribute__((address(0x1E6))); + +__asm("C1FLTOBJ11U equ 01E6h"); + + +typedef union { + struct { + unsigned EID :8; + }; + struct { + unsigned EID5 :1; + unsigned EID6 :1; + unsigned EID7 :1; + unsigned EID8 :1; + unsigned EID9 :1; + unsigned EID10 :1; + unsigned EID11 :1; + unsigned EID12 :1; + }; +} C1FLTOBJ11Ubits_t; +extern volatile C1FLTOBJ11Ubits_t C1FLTOBJ11Ubits __attribute__((address(0x1E6))); +# 23395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1FLTOBJ11T __attribute__((address(0x1E7))); + +__asm("C1FLTOBJ11T equ 01E7h"); + + +typedef union { + struct { + unsigned EID :5; + unsigned SID11 :1; + unsigned EXIDE :1; + }; + struct { + unsigned EID13 :1; + unsigned EID14 :1; + unsigned EID15 :1; + unsigned EID16 :1; + unsigned EID17 :1; + }; +} C1FLTOBJ11Tbits_t; +extern volatile C1FLTOBJ11Tbits_t C1FLTOBJ11Tbits __attribute__((address(0x1E7))); +# 23459 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long C1MASK11 __attribute__((address(0x1E8))); + +__asm("C1MASK11 equ 01E8h"); + + + + +extern volatile unsigned char C1MASK11L __attribute__((address(0x1E8))); + +__asm("C1MASK11L equ 01E8h"); + + +typedef union { + struct { + unsigned MSID :8; + }; + struct { + unsigned MSID0 :1; + unsigned MSID1 :1; + unsigned MSID2 :1; + unsigned MSID3 :1; + unsigned MSID4 :1; + unsigned MSID5 :1; + unsigned MSID6 :1; + unsigned MSID7 :1; + }; +} C1MASK11Lbits_t; +extern volatile C1MASK11Lbits_t C1MASK11Lbits __attribute__((address(0x1E8))); +# 23536 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11H __attribute__((address(0x1E9))); + +__asm("C1MASK11H equ 01E9h"); + + +typedef union { + struct { + unsigned MSID :3; + unsigned MEID :5; + }; + struct { + unsigned MSID8 :1; + unsigned MSID9 :1; + unsigned MSID10 :1; + unsigned MEID0 :1; + unsigned MEID1 :1; + unsigned MEID2 :1; + unsigned MEID3 :1; + unsigned MEID4 :1; + }; +} C1MASK11Hbits_t; +extern volatile C1MASK11Hbits_t C1MASK11Hbits __attribute__((address(0x1E9))); +# 23612 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11U __attribute__((address(0x1EA))); + +__asm("C1MASK11U equ 01EAh"); + + +typedef union { + struct { + unsigned MEID :8; + }; + struct { + unsigned MEID5 :1; + unsigned MEID6 :1; + unsigned MEID7 :1; + unsigned MEID8 :1; + unsigned MEID9 :1; + unsigned MEID10 :1; + unsigned MEID11 :1; + unsigned MEID12 :1; + }; +} C1MASK11Ubits_t; +extern volatile C1MASK11Ubits_t C1MASK11Ubits __attribute__((address(0x1EA))); +# 23682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char C1MASK11T __attribute__((address(0x1EB))); + +__asm("C1MASK11T equ 01EBh"); + + +typedef union { + struct { + unsigned MEID :5; + unsigned MSID11 :1; + unsigned MIDE :1; + }; + struct { + unsigned MEID13 :1; + unsigned MEID14 :1; + unsigned MEID15 :1; + unsigned MEID16 :1; + unsigned MEID17 :1; + }; +} C1MASK11Tbits_t; +extern volatile C1MASK11Tbits_t C1MASK11Tbits __attribute__((address(0x1EB))); +# 23746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PPSLOCK __attribute__((address(0x200))); + +__asm("PPSLOCK equ 0200h"); + + +typedef union { + struct { + unsigned PPSLOCKED :1; + }; +} PPSLOCKbits_t; +extern volatile PPSLOCKbits_t PPSLOCKbits __attribute__((address(0x200))); +# 23766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA0PPS __attribute__((address(0x201))); + +__asm("RA0PPS equ 0201h"); + + +typedef union { + struct { + unsigned RA0PPS0 :1; + unsigned RA0PPS1 :1; + unsigned RA0PPS2 :1; + unsigned RA0PPS3 :1; + unsigned RA0PPS4 :1; + unsigned RA0PPS5 :1; + }; +} RA0PPSbits_t; +extern volatile RA0PPSbits_t RA0PPSbits __attribute__((address(0x201))); +# 23816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA1PPS __attribute__((address(0x202))); + +__asm("RA1PPS equ 0202h"); + + +typedef union { + struct { + unsigned RA1PPS0 :1; + unsigned RA1PPS1 :1; + unsigned RA1PPS2 :1; + unsigned RA1PPS3 :1; + unsigned RA1PPS4 :1; + unsigned RA1PPS5 :1; + }; +} RA1PPSbits_t; +extern volatile RA1PPSbits_t RA1PPSbits __attribute__((address(0x202))); +# 23866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA2PPS __attribute__((address(0x203))); + +__asm("RA2PPS equ 0203h"); + + +typedef union { + struct { + unsigned RA2PPS0 :1; + unsigned RA2PPS1 :1; + unsigned RA2PPS2 :1; + unsigned RA2PPS3 :1; + unsigned RA2PPS4 :1; + unsigned RA2PPS5 :1; + }; +} RA2PPSbits_t; +extern volatile RA2PPSbits_t RA2PPSbits __attribute__((address(0x203))); +# 23916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA3PPS __attribute__((address(0x204))); + +__asm("RA3PPS equ 0204h"); + + +typedef union { + struct { + unsigned RA3PPS0 :1; + unsigned RA3PPS1 :1; + unsigned RA3PPS2 :1; + unsigned RA3PPS3 :1; + unsigned RA3PPS4 :1; + unsigned RA3PPS5 :1; + }; +} RA3PPSbits_t; +extern volatile RA3PPSbits_t RA3PPSbits __attribute__((address(0x204))); +# 23966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA4PPS __attribute__((address(0x205))); + +__asm("RA4PPS equ 0205h"); + + +typedef union { + struct { + unsigned RA4PPS0 :1; + unsigned RA4PPS1 :1; + unsigned RA4PPS2 :1; + unsigned RA4PPS3 :1; + unsigned RA4PPS4 :1; + unsigned RA4PPS5 :1; + }; +} RA4PPSbits_t; +extern volatile RA4PPSbits_t RA4PPSbits __attribute__((address(0x205))); +# 24016 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA5PPS __attribute__((address(0x206))); + +__asm("RA5PPS equ 0206h"); + + +typedef union { + struct { + unsigned RA5PPS0 :1; + unsigned RA5PPS1 :1; + unsigned RA5PPS2 :1; + unsigned RA5PPS3 :1; + unsigned RA5PPS4 :1; + unsigned RA5PPS5 :1; + }; +} RA5PPSbits_t; +extern volatile RA5PPSbits_t RA5PPSbits __attribute__((address(0x206))); +# 24066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA6PPS __attribute__((address(0x207))); + +__asm("RA6PPS equ 0207h"); + + +typedef union { + struct { + unsigned RA6PPS0 :1; + unsigned RA6PPS1 :1; + unsigned RA6PPS2 :1; + unsigned RA6PPS3 :1; + unsigned RA6PPS4 :1; + unsigned RA6PPS5 :1; + }; +} RA6PPSbits_t; +extern volatile RA6PPSbits_t RA6PPSbits __attribute__((address(0x207))); +# 24116 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RA7PPS __attribute__((address(0x208))); + +__asm("RA7PPS equ 0208h"); + + +typedef union { + struct { + unsigned RA7PPS0 :1; + unsigned RA7PPS1 :1; + unsigned RA7PPS2 :1; + unsigned RA7PPS3 :1; + unsigned RA7PPS4 :1; + unsigned RA7PPS5 :1; + }; +} RA7PPSbits_t; +extern volatile RA7PPSbits_t RA7PPSbits __attribute__((address(0x208))); +# 24166 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB0PPS __attribute__((address(0x209))); + +__asm("RB0PPS equ 0209h"); + + +typedef union { + struct { + unsigned RB0PPS0 :1; + unsigned RB0PPS1 :1; + unsigned RB0PPS2 :1; + unsigned RB0PPS3 :1; + unsigned RB0PPS4 :1; + unsigned RB0PPS5 :1; + }; +} RB0PPSbits_t; +extern volatile RB0PPSbits_t RB0PPSbits __attribute__((address(0x209))); +# 24216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1PPS __attribute__((address(0x20A))); + +__asm("RB1PPS equ 020Ah"); + + +typedef union { + struct { + unsigned RB1PPS0 :1; + unsigned RB1PPS1 :1; + unsigned RB1PPS2 :1; + unsigned RB1PPS3 :1; + unsigned RB1PPS4 :1; + unsigned RB1PPS5 :1; + }; +} RB1PPSbits_t; +extern volatile RB1PPSbits_t RB1PPSbits __attribute__((address(0x20A))); +# 24266 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2PPS __attribute__((address(0x20B))); + +__asm("RB2PPS equ 020Bh"); + + +typedef union { + struct { + unsigned RB2PPS0 :1; + unsigned RB2PPS1 :1; + unsigned RB2PPS2 :1; + unsigned RB2PPS3 :1; + unsigned RB2PPS4 :1; + unsigned RB2PPS5 :1; + }; +} RB2PPSbits_t; +extern volatile RB2PPSbits_t RB2PPSbits __attribute__((address(0x20B))); +# 24316 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB3PPS __attribute__((address(0x20C))); + +__asm("RB3PPS equ 020Ch"); + + +typedef union { + struct { + unsigned RB3PPS0 :1; + unsigned RB3PPS1 :1; + unsigned RB3PPS2 :1; + unsigned RB3PPS3 :1; + unsigned RB3PPS4 :1; + unsigned RB3PPS5 :1; + }; +} RB3PPSbits_t; +extern volatile RB3PPSbits_t RB3PPSbits __attribute__((address(0x20C))); +# 24366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB4PPS __attribute__((address(0x20D))); + +__asm("RB4PPS equ 020Dh"); + + +typedef union { + struct { + unsigned RB4PPS0 :1; + unsigned RB4PPS1 :1; + unsigned RB4PPS2 :1; + unsigned RB4PPS3 :1; + unsigned RB4PPS4 :1; + unsigned RB4PPS5 :1; + }; +} RB4PPSbits_t; +extern volatile RB4PPSbits_t RB4PPSbits __attribute__((address(0x20D))); +# 24416 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB5PPS __attribute__((address(0x20E))); + +__asm("RB5PPS equ 020Eh"); + + +typedef union { + struct { + unsigned RB5PPS0 :1; + unsigned RB5PPS1 :1; + unsigned RB5PPS2 :1; + unsigned RB5PPS3 :1; + unsigned RB5PPS4 :1; + unsigned RB5PPS5 :1; + }; +} RB5PPSbits_t; +extern volatile RB5PPSbits_t RB5PPSbits __attribute__((address(0x20E))); +# 24466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB6PPS __attribute__((address(0x20F))); + +__asm("RB6PPS equ 020Fh"); + + +typedef union { + struct { + unsigned RB6PPS0 :1; + unsigned RB6PPS1 :1; + unsigned RB6PPS2 :1; + unsigned RB6PPS3 :1; + unsigned RB6PPS4 :1; + unsigned RB6PPS5 :1; + }; +} RB6PPSbits_t; +extern volatile RB6PPSbits_t RB6PPSbits __attribute__((address(0x20F))); +# 24516 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB7PPS __attribute__((address(0x210))); + +__asm("RB7PPS equ 0210h"); + + +typedef union { + struct { + unsigned RB7PPS0 :1; + unsigned RB7PPS1 :1; + unsigned RB7PPS2 :1; + unsigned RB7PPS3 :1; + unsigned RB7PPS4 :1; + unsigned RB7PPS5 :1; + }; +} RB7PPSbits_t; +extern volatile RB7PPSbits_t RB7PPSbits __attribute__((address(0x210))); +# 24566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC0PPS __attribute__((address(0x211))); + +__asm("RC0PPS equ 0211h"); + + +typedef union { + struct { + unsigned RC0PPS0 :1; + unsigned RC0PPS1 :1; + unsigned RC0PPS2 :1; + unsigned RC0PPS3 :1; + unsigned RC0PPS4 :1; + unsigned RC0PPS5 :1; + }; +} RC0PPSbits_t; +extern volatile RC0PPSbits_t RC0PPSbits __attribute__((address(0x211))); +# 24616 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC1PPS __attribute__((address(0x212))); + +__asm("RC1PPS equ 0212h"); + + +typedef union { + struct { + unsigned RC1PPS0 :1; + unsigned RC1PPS1 :1; + unsigned RC1PPS2 :1; + unsigned RC1PPS3 :1; + unsigned RC1PPS4 :1; + unsigned RC1PPS5 :1; + }; +} RC1PPSbits_t; +extern volatile RC1PPSbits_t RC1PPSbits __attribute__((address(0x212))); +# 24666 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC2PPS __attribute__((address(0x213))); + +__asm("RC2PPS equ 0213h"); + + +typedef union { + struct { + unsigned RC2PPS0 :1; + unsigned RC2PPS1 :1; + unsigned RC2PPS2 :1; + unsigned RC2PPS3 :1; + unsigned RC2PPS4 :1; + unsigned RC2PPS5 :1; + }; +} RC2PPSbits_t; +extern volatile RC2PPSbits_t RC2PPSbits __attribute__((address(0x213))); +# 24716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3PPS __attribute__((address(0x214))); + +__asm("RC3PPS equ 0214h"); + + +typedef union { + struct { + unsigned RC3PPS0 :1; + unsigned RC3PPS1 :1; + unsigned RC3PPS2 :1; + unsigned RC3PPS3 :1; + unsigned RC3PPS4 :1; + unsigned RC3PPS5 :1; + }; +} RC3PPSbits_t; +extern volatile RC3PPSbits_t RC3PPSbits __attribute__((address(0x214))); +# 24766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4PPS __attribute__((address(0x215))); + +__asm("RC4PPS equ 0215h"); + + +typedef union { + struct { + unsigned RC4PPS0 :1; + unsigned RC4PPS1 :1; + unsigned RC4PPS2 :1; + unsigned RC4PPS3 :1; + unsigned RC4PPS4 :1; + unsigned RC4PPS5 :1; + }; +} RC4PPSbits_t; +extern volatile RC4PPSbits_t RC4PPSbits __attribute__((address(0x215))); +# 24816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC5PPS __attribute__((address(0x216))); + +__asm("RC5PPS equ 0216h"); + + +typedef union { + struct { + unsigned RC5PPS0 :1; + unsigned RC5PPS1 :1; + unsigned RC5PPS2 :1; + unsigned RC5PPS3 :1; + unsigned RC5PPS4 :1; + unsigned RC5PPS5 :1; + }; +} RC5PPSbits_t; +extern volatile RC5PPSbits_t RC5PPSbits __attribute__((address(0x216))); +# 24866 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC6PPS __attribute__((address(0x217))); + +__asm("RC6PPS equ 0217h"); + + +typedef union { + struct { + unsigned RC6PPS0 :1; + unsigned RC6PPS1 :1; + unsigned RC6PPS2 :1; + unsigned RC6PPS3 :1; + unsigned RC6PPS4 :1; + unsigned RC6PPS5 :1; + }; +} RC6PPSbits_t; +extern volatile RC6PPSbits_t RC6PPSbits __attribute__((address(0x217))); +# 24916 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC7PPS __attribute__((address(0x218))); + +__asm("RC7PPS equ 0218h"); + + +typedef union { + struct { + unsigned RC7PPS0 :1; + unsigned RC7PPS1 :1; + unsigned RC7PPS2 :1; + unsigned RC7PPS3 :1; + unsigned RC7PPS4 :1; + unsigned RC7PPS5 :1; + }; +} RC7PPSbits_t; +extern volatile RC7PPSbits_t RC7PPSbits __attribute__((address(0x218))); +# 24966 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CANRXPPS __attribute__((address(0x23D))); + +__asm("CANRXPPS equ 023Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CANRXPPS0 :1; + unsigned CANRXPPS1 :1; + unsigned CANRXPPS2 :1; + unsigned CANRXPPS3 :1; + unsigned CANRXPPS4 :1; + }; + struct { + unsigned CANRXPPS :5; + }; +} CANRXPPSbits_t; +extern volatile CANRXPPSbits_t CANRXPPSbits __attribute__((address(0x23D))); +# 25032 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT0PPS __attribute__((address(0x23E))); + +__asm("INT0PPS equ 023Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :1; + }; + struct { + unsigned INT0PPS0 :1; + unsigned INT0PPS1 :1; + unsigned INT0PPS2 :1; + unsigned INT0PPS3 :1; + }; + struct { + unsigned INT0PPS :4; + }; +} INT0PPSbits_t; +extern volatile INT0PPSbits_t INT0PPSbits __attribute__((address(0x23E))); +# 25092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT1PPS __attribute__((address(0x23F))); + +__asm("INT1PPS equ 023Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned INT1PPS0 :1; + unsigned INT1PPS1 :1; + unsigned INT1PPS2 :1; + unsigned INT1PPS3 :1; + unsigned INT1PPS4 :1; + }; + struct { + unsigned INT1PPS :5; + }; +} INT1PPSbits_t; +extern volatile INT1PPSbits_t INT1PPSbits __attribute__((address(0x23F))); +# 25158 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INT2PPS __attribute__((address(0x240))); + +__asm("INT2PPS equ 0240h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned INT2PPS0 :1; + unsigned INT2PPS1 :1; + unsigned INT2PPS2 :1; + unsigned INT2PPS3 :1; + unsigned INT2PPS4 :1; + unsigned INT2PPS5 :1; + }; + struct { + unsigned INT2PPS :6; + }; +} INT2PPSbits_t; +extern volatile INT2PPSbits_t INT2PPSbits __attribute__((address(0x240))); +# 25230 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CKIPPS __attribute__((address(0x241))); + +__asm("T0CKIPPS equ 0241h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T0CKIPPS :6; + }; + struct { + unsigned T0CKIPPS0 :1; + unsigned T0CKIPPS1 :1; + unsigned T0CKIPPS2 :1; + unsigned T0CKIPPS3 :1; + unsigned T0CKIPPS4 :1; + unsigned T0CKIPPS5 :1; + }; +} T0CKIPPSbits_t; +extern volatile T0CKIPPSbits_t T0CKIPPSbits __attribute__((address(0x241))); +# 25302 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CKIPPS __attribute__((address(0x242))); + +__asm("T1CKIPPS equ 0242h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T1CKIPPS0 :1; + unsigned T1CKIPPS1 :1; + unsigned T1CKIPPS2 :1; + unsigned T1CKIPPS3 :1; + unsigned T1CKIPPS4 :1; + unsigned T1CKIPPS5 :1; + }; + struct { + unsigned T1CKIPPS :6; + }; +} T1CKIPPSbits_t; +extern volatile T1CKIPPSbits_t T1CKIPPSbits __attribute__((address(0x242))); +# 25374 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GPPS __attribute__((address(0x243))); + +__asm("T1GPPS equ 0243h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T1GPPS0 :1; + unsigned T1GPPS1 :1; + unsigned T1GPPS2 :1; + unsigned T1GPPS3 :1; + unsigned T1GPPS4 :1; + }; + struct { + unsigned T1GPPS :5; + }; +} T1GPPSbits_t; +extern volatile T1GPPSbits_t T1GPPSbits __attribute__((address(0x243))); +# 25440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CKIPPS __attribute__((address(0x244))); + +__asm("T3CKIPPS equ 0244h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T3CKIPPS0 :1; + unsigned T3CKIPPS1 :1; + unsigned T3CKIPPS2 :1; + unsigned T3CKIPPS3 :1; + unsigned T3CKIPPS4 :1; + unsigned T3CKIPPS5 :1; + }; + struct { + unsigned T3CKIPPS :6; + }; +} T3CKIPPSbits_t; +extern volatile T3CKIPPSbits_t T3CKIPPSbits __attribute__((address(0x244))); +# 25512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GPPS __attribute__((address(0x245))); + +__asm("T3GPPS equ 0245h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T3GPPS0 :1; + unsigned T3GPPS1 :1; + unsigned T3GPPS2 :1; + unsigned T3GPPS3 :1; + unsigned T3GPPS4 :1; + }; + struct { + unsigned T3GPPS :5; + }; +} T3GPPSbits_t; +extern volatile T3GPPSbits_t T3GPPSbits __attribute__((address(0x245))); +# 25578 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CKIPPS __attribute__((address(0x246))); + +__asm("T5CKIPPS equ 0246h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned T5CKIPPS0 :1; + unsigned T5CKIPPS1 :1; + unsigned T5CKIPPS2 :1; + unsigned T5CKIPPS3 :1; + unsigned T5CKIPPS4 :1; + unsigned T5CKIPPS5 :1; + }; + struct { + unsigned T5CKIPPS :6; + }; +} T5CKIPPSbits_t; +extern volatile T5CKIPPSbits_t T5CKIPPSbits __attribute__((address(0x246))); +# 25650 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GPPS __attribute__((address(0x247))); + +__asm("T5GPPS equ 0247h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T5GPPS0 :1; + unsigned T5GPPS1 :1; + unsigned T5GPPS2 :1; + unsigned T5GPPS3 :1; + unsigned T5GPPS4 :1; + }; + struct { + unsigned T5GPPS :5; + }; +} T5GPPSbits_t; +extern volatile T5GPPSbits_t T5GPPSbits __attribute__((address(0x247))); +# 25716 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2INPPS __attribute__((address(0x248))); + +__asm("T2INPPS equ 0248h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T2INPPS0 :1; + unsigned T2INPPS1 :1; + unsigned T2INPPS2 :1; + unsigned T2INPPS3 :1; + unsigned T2INPPS4 :1; + }; + struct { + unsigned T2INPPS :5; + }; +} T2INPPSbits_t; +extern volatile T2INPPSbits_t T2INPPSbits __attribute__((address(0x248))); +# 25782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4INPPS __attribute__((address(0x249))); + +__asm("T4INPPS equ 0249h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T4INPPS0 :1; + unsigned T4INPPS1 :1; + unsigned T4INPPS2 :1; + unsigned T4INPPS3 :1; + unsigned T4INPPS4 :1; + }; + struct { + unsigned T4INPPS :5; + }; +} T4INPPSbits_t; +extern volatile T4INPPSbits_t T4INPPSbits __attribute__((address(0x249))); +# 25848 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6INPPS __attribute__((address(0x24A))); + +__asm("T6INPPS equ 024Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned T6INPPS0 :1; + unsigned T6INPPS1 :1; + unsigned T6INPPS2 :1; + unsigned T6INPPS3 :1; + unsigned T6INPPS4 :1; + }; + struct { + unsigned T6INPPS :5; + }; +} T6INPPSbits_t; +extern volatile T6INPPSbits_t T6INPPSbits __attribute__((address(0x24A))); +# 25914 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN0PPS __attribute__((address(0x24B))); + +__asm("TUIN0PPS equ 024Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN0PPS :6; + }; + struct { + unsigned TUIN0PPS0 :1; + unsigned TUIN0PPS1 :1; + unsigned TUIN0PPS2 :1; + unsigned TUIN0PPS3 :1; + unsigned TUIN0PPS4 :1; + unsigned TUIN0PPS5 :1; + }; +} TUIN0PPSbits_t; +extern volatile TUIN0PPSbits_t TUIN0PPSbits __attribute__((address(0x24B))); +# 25986 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN1PPS __attribute__((address(0x24C))); + +__asm("TUIN1PPS equ 024Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned TUIN1PPS :6; + }; + struct { + unsigned TUIN1PPS0 :1; + unsigned TUIN1PPS1 :1; + unsigned TUIN1PPS2 :1; + unsigned TUIN1PPS3 :1; + unsigned TUIN1PPS4 :1; + unsigned TUIN1PPS5 :1; + }; +} TUIN1PPSbits_t; +extern volatile TUIN1PPSbits_t TUIN1PPSbits __attribute__((address(0x24C))); +# 26058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN2PPS __attribute__((address(0x24D))); + +__asm("TUIN2PPS equ 024Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN2PPS :5; + }; + struct { + unsigned TUIN2PPS0 :1; + unsigned TUIN2PPS1 :1; + unsigned TUIN2PPS2 :1; + unsigned TUIN2PPS3 :1; + unsigned TUIN2PPS4 :1; + }; +} TUIN2PPSbits_t; +extern volatile TUIN2PPSbits_t TUIN2PPSbits __attribute__((address(0x24D))); +# 26124 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUIN3PPS __attribute__((address(0x24E))); + +__asm("TUIN3PPS equ 024Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned TUIN3PPS :5; + }; + struct { + unsigned TUIN3PPS0 :1; + unsigned TUIN3PPS1 :1; + unsigned TUIN3PPS2 :1; + unsigned TUIN3PPS3 :1; + unsigned TUIN3PPS4 :1; + }; +} TUIN3PPSbits_t; +extern volatile TUIN3PPSbits_t TUIN3PPSbits __attribute__((address(0x24E))); +# 26190 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1PPS __attribute__((address(0x24F))); + +__asm("CCP1PPS equ 024Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP1PPS0 :1; + unsigned CCP1PPS1 :1; + unsigned CCP1PPS2 :1; + unsigned CCP1PPS3 :1; + unsigned CCP1PPS4 :1; + unsigned CCP1PPS5 :1; + }; + struct { + unsigned CCP1PPS :6; + }; +} CCP1PPSbits_t; +extern volatile CCP1PPSbits_t CCP1PPSbits __attribute__((address(0x24F))); +# 26262 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2PPS __attribute__((address(0x250))); + +__asm("CCP2PPS equ 0250h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned CCP2PPS0 :1; + unsigned CCP2PPS1 :1; + unsigned CCP2PPS2 :1; + unsigned CCP2PPS3 :1; + unsigned CCP2PPS4 :1; + unsigned CCP2PPS5 :1; + }; + struct { + unsigned CCP2PPS :6; + }; +} CCP2PPSbits_t; +extern volatile CCP2PPSbits_t CCP2PPSbits __attribute__((address(0x250))); +# 26334 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3PPS __attribute__((address(0x251))); + +__asm("CCP3PPS equ 0251h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CCP3PPS0 :1; + unsigned CCP3PPS1 :1; + unsigned CCP3PPS2 :1; + unsigned CCP3PPS3 :1; + unsigned CCP3PPS4 :1; + }; + struct { + unsigned CCP3PPS :5; + }; +} CCP3PPSbits_t; +extern volatile CCP3PPSbits_t CCP3PPSbits __attribute__((address(0x251))); +# 26400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERSPPS __attribute__((address(0x253))); + +__asm("PWM1ERSPPS equ 0253h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM1ERSPPS :5; + }; + struct { + unsigned PWM1ERSPPS0 :1; + unsigned PWM1ERSPPS1 :1; + unsigned PWM1ERSPPS2 :1; + unsigned PWM1ERSPPS3 :1; + unsigned PWM1ERSPPS4 :1; + }; +} PWM1ERSPPSbits_t; +extern volatile PWM1ERSPPSbits_t PWM1ERSPPSbits __attribute__((address(0x253))); +# 26466 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERSPPS __attribute__((address(0x254))); + +__asm("PWM2ERSPPS equ 0254h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWM2ERSPPS :6; + }; + struct { + unsigned PWM2ERSPPS0 :1; + unsigned PWM2ERSPPS1 :1; + unsigned PWM2ERSPPS2 :1; + unsigned PWM2ERSPPS3 :1; + unsigned PWM2ERSPPS4 :1; + unsigned PWM2ERSPPS5 :1; + }; +} PWM2ERSPPSbits_t; +extern volatile PWM2ERSPPSbits_t PWM2ERSPPSbits __attribute__((address(0x254))); +# 26538 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERSPPS __attribute__((address(0x255))); + +__asm("PWM3ERSPPS equ 0255h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned PWM3ERSPPS :5; + }; + struct { + unsigned PWM3ERSPPS0 :1; + unsigned PWM3ERSPPS1 :1; + unsigned PWM3ERSPPS2 :1; + unsigned PWM3ERSPPS3 :1; + unsigned PWM3ERSPPS4 :1; + }; +} PWM3ERSPPSbits_t; +extern volatile PWM3ERSPPSbits_t PWM3ERSPPSbits __attribute__((address(0x255))); +# 26604 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERSPPS __attribute__((address(0x256))); + +__asm("PWM4ERSPPS equ 0256h"); + + + + +extern volatile unsigned char PWMIN0PPS __attribute__((address(0x257))); + +__asm("PWMIN0PPS equ 0257h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN0PPS :6; + }; + struct { + unsigned PWMIN0PPS0 :1; + unsigned PWMIN0PPS1 :1; + unsigned PWMIN0PPS2 :1; + unsigned PWMIN0PPS3 :1; + unsigned PWMIN0PPS4 :1; + unsigned PWMIN0PPS5 :1; + }; +} PWMIN0PPSbits_t; +extern volatile PWMIN0PPSbits_t PWMIN0PPSbits __attribute__((address(0x257))); +# 26683 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMIN1PPS __attribute__((address(0x258))); + +__asm("PWMIN1PPS equ 0258h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned PWMIN1PPS :6; + }; + struct { + unsigned PWMIN1PPS0 :1; + unsigned PWMIN1PPS1 :1; + unsigned PWMIN1PPS2 :1; + unsigned PWMIN1PPS3 :1; + unsigned PWMIN1PPS4 :1; + unsigned PWMIN1PPS5 :1; + }; +} PWMIN1PPSbits_t; +extern volatile PWMIN1PPSbits_t PWMIN1PPSbits __attribute__((address(0x258))); +# 26755 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WINPPS __attribute__((address(0x259))); + +__asm("SMT1WINPPS equ 0259h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1WINPPS :6; + }; + struct { + unsigned SMT1WINPPS0 :1; + unsigned SMT1WINPPS1 :1; + unsigned SMT1WINPPS2 :1; + unsigned SMT1WINPPS3 :1; + unsigned SMT1WINPPS4 :1; + unsigned SMT1WINPPS5 :1; + }; +} SMT1WINPPSbits_t; +extern volatile SMT1WINPPSbits_t SMT1WINPPSbits __attribute__((address(0x259))); +# 26827 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIGPPS __attribute__((address(0x25A))); + +__asm("SMT1SIGPPS equ 025Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned SMT1SIGPPS :6; + }; + struct { + unsigned SMT1SIGPPS0 :1; + unsigned SMT1SIGPPS1 :1; + unsigned SMT1SIGPPS2 :1; + unsigned SMT1SIGPPS3 :1; + unsigned SMT1SIGPPS4 :1; + unsigned SMT1SIGPPS5 :1; + }; +} SMT1SIGPPSbits_t; +extern volatile SMT1SIGPPSbits_t SMT1SIGPPSbits __attribute__((address(0x25A))); +# 26899 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1PPS __attribute__((address(0x25B))); + +__asm("CWG1PPS equ 025Bh"); + + +extern volatile unsigned char CWG1INPPS __attribute__((address(0x25B))); + +__asm("CWG1INPPS equ 025Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1PPSbits_t; +extern volatile CWG1PPSbits_t CWG1PPSbits __attribute__((address(0x25B))); +# 27008 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG1INPPS :5; + }; + struct { + unsigned CWG1INPPS0 :1; + unsigned CWG1INPPS1 :1; + unsigned CWG1INPPS2 :1; + unsigned CWG1INPPS3 :1; + unsigned CWG1INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG1INPPSbits_t; +extern volatile CWG1INPPSbits_t CWG1INPPSbits __attribute__((address(0x25B))); +# 27109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2PPS __attribute__((address(0x25C))); + +__asm("CWG2PPS equ 025Ch"); + + +extern volatile unsigned char CWG2INPPS __attribute__((address(0x25C))); + +__asm("CWG2INPPS equ 025Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2PPSbits_t; +extern volatile CWG2PPSbits_t CWG2PPSbits __attribute__((address(0x25C))); +# 27218 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG2INPPS :5; + }; + struct { + unsigned CWG2INPPS0 :1; + unsigned CWG2INPPS1 :1; + unsigned CWG2INPPS2 :1; + unsigned CWG2INPPS3 :1; + unsigned CWG2INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG2INPPSbits_t; +extern volatile CWG2INPPSbits_t CWG2INPPSbits __attribute__((address(0x25C))); +# 27319 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3PPS __attribute__((address(0x25D))); + +__asm("CWG3PPS equ 025Dh"); + + +extern volatile unsigned char CWG3INPPS __attribute__((address(0x25D))); + +__asm("CWG3INPPS equ 025Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3PPSbits_t; +extern volatile CWG3PPSbits_t CWG3PPSbits __attribute__((address(0x25D))); +# 27428 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CWGINPPS0 :1; + unsigned CWGINPPS1 :1; + unsigned CWGINPPS2 :1; + unsigned CWGINPPS3 :1; + unsigned CWGINPPS4 :1; + }; + struct { + unsigned CWG3INPPS :5; + }; + struct { + unsigned CWG3INPPS0 :1; + unsigned CWG3INPPS1 :1; + unsigned CWG3INPPS2 :1; + unsigned CWG3INPPS3 :1; + unsigned CWG3INPPS4 :1; + }; + struct { + unsigned CWGINPPS :5; + }; +} CWG3INPPSbits_t; +extern volatile CWG3INPPSbits_t CWG3INPPSbits __attribute__((address(0x25D))); +# 27529 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARLPPS __attribute__((address(0x25E))); + +__asm("MD1CARLPPS equ 025Eh"); + + +extern volatile unsigned char MDCARLPPS __attribute__((address(0x25E))); + +__asm("MDCARLPPS equ 025Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MD1CARLPPSbits_t; +extern volatile MD1CARLPPSbits_t MD1CARLPPSbits __attribute__((address(0x25E))); +# 27598 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARLPPS0 :1; + unsigned MDCARLPPS1 :1; + unsigned MDCARLPPS2 :1; + unsigned MDCARLPPS3 :1; + unsigned MDCARLPPS4 :1; + }; + struct { + unsigned MDCARLPPS :5; + }; +} MDCARLPPSbits_t; +extern volatile MDCARLPPSbits_t MDCARLPPSbits __attribute__((address(0x25E))); +# 27659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1CARHPPS __attribute__((address(0x25F))); + +__asm("MD1CARHPPS equ 025Fh"); + + +extern volatile unsigned char MDCARHPPS __attribute__((address(0x25F))); + +__asm("MDCARHPPS equ 025Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MD1CARHPPSbits_t; +extern volatile MD1CARHPPSbits_t MD1CARHPPSbits __attribute__((address(0x25F))); +# 27728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDCARHPPS0 :1; + unsigned MDCARHPPS1 :1; + unsigned MDCARHPPS2 :1; + unsigned MDCARHPPS3 :1; + unsigned MDCARHPPS4 :1; + }; + struct { + unsigned MDCARHPPS :5; + }; +} MDCARHPPSbits_t; +extern volatile MDCARHPPSbits_t MDCARHPPSbits __attribute__((address(0x25F))); +# 27789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char MD1SRCPPS __attribute__((address(0x260))); + +__asm("MD1SRCPPS equ 0260h"); + + +extern volatile unsigned char MDSRCPPS __attribute__((address(0x260))); + +__asm("MDSRCPPS equ 0260h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MD1SRCPPSbits_t; +extern volatile MD1SRCPPSbits_t MD1SRCPPSbits __attribute__((address(0x260))); +# 27858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned MDSRCPPS0 :1; + unsigned MDSRCPPS1 :1; + unsigned MDSRCPPS2 :1; + unsigned MDSRCPPS3 :1; + unsigned MDSRCPPS4 :1; + }; + struct { + unsigned MDSRCPPS :5; + }; +} MDSRCPPSbits_t; +extern volatile MDSRCPPSbits_t MDSRCPPSbits __attribute__((address(0x260))); +# 27919 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN0PPS __attribute__((address(0x261))); + +__asm("CLCIN0PPS equ 0261h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN0PPS0 :1; + unsigned CLCIN0PPS1 :1; + unsigned CLCIN0PPS2 :1; + unsigned CLCIN0PPS3 :1; + unsigned CLCIN0PPS4 :1; + }; + struct { + unsigned CLCIN0PPS :5; + }; +} CLCIN0PPSbits_t; +extern volatile CLCIN0PPSbits_t CLCIN0PPSbits __attribute__((address(0x261))); +# 27985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN1PPS __attribute__((address(0x262))); + +__asm("CLCIN1PPS equ 0262h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN1PPS0 :1; + unsigned CLCIN1PPS1 :1; + unsigned CLCIN1PPS2 :1; + unsigned CLCIN1PPS3 :1; + unsigned CLCIN1PPS4 :1; + }; + struct { + unsigned CLCIN1PPS :5; + }; +} CLCIN1PPSbits_t; +extern volatile CLCIN1PPSbits_t CLCIN1PPSbits __attribute__((address(0x262))); +# 28051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN2PPS __attribute__((address(0x263))); + +__asm("CLCIN2PPS equ 0263h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN2PPS0 :1; + unsigned CLCIN2PPS1 :1; + unsigned CLCIN2PPS2 :1; + unsigned CLCIN2PPS3 :1; + unsigned CLCIN2PPS4 :1; + }; + struct { + unsigned CLCIN2PPS :5; + }; +} CLCIN2PPSbits_t; +extern volatile CLCIN2PPSbits_t CLCIN2PPSbits __attribute__((address(0x263))); +# 28117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN3PPS __attribute__((address(0x264))); + +__asm("CLCIN3PPS equ 0264h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN3PPS0 :1; + unsigned CLCIN3PPS1 :1; + unsigned CLCIN3PPS2 :1; + unsigned CLCIN3PPS3 :1; + unsigned CLCIN3PPS4 :1; + }; + struct { + unsigned CLCIN3PPS :5; + }; +} CLCIN3PPSbits_t; +extern volatile CLCIN3PPSbits_t CLCIN3PPSbits __attribute__((address(0x264))); +# 28183 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN4PPS __attribute__((address(0x265))); + +__asm("CLCIN4PPS equ 0265h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN4PPS0 :1; + unsigned CLCIN4PPS1 :1; + unsigned CLCIN4PPS2 :1; + unsigned CLCIN4PPS3 :1; + unsigned CLCIN4PPS4 :1; + }; + struct { + unsigned CLCIN4PPS :5; + }; +} CLCIN4PPSbits_t; +extern volatile CLCIN4PPSbits_t CLCIN4PPSbits __attribute__((address(0x265))); +# 28249 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN5PPS __attribute__((address(0x266))); + +__asm("CLCIN5PPS equ 0266h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN5PPS0 :1; + unsigned CLCIN5PPS1 :1; + unsigned CLCIN5PPS2 :1; + unsigned CLCIN5PPS3 :1; + unsigned CLCIN5PPS4 :1; + }; + struct { + unsigned CLCIN5PPS :5; + }; +} CLCIN5PPSbits_t; +extern volatile CLCIN5PPSbits_t CLCIN5PPSbits __attribute__((address(0x266))); +# 28315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN6PPS __attribute__((address(0x267))); + +__asm("CLCIN6PPS equ 0267h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN6PPS0 :1; + unsigned CLCIN6PPS1 :1; + unsigned CLCIN6PPS2 :1; + unsigned CLCIN6PPS3 :1; + unsigned CLCIN6PPS4 :1; + }; + struct { + unsigned CLCIN6PPS :5; + }; +} CLCIN6PPSbits_t; +extern volatile CLCIN6PPSbits_t CLCIN6PPSbits __attribute__((address(0x267))); +# 28381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CLCIN7PPS __attribute__((address(0x268))); + +__asm("CLCIN7PPS equ 0268h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned CLCIN7PPS0 :1; + unsigned CLCIN7PPS1 :1; + unsigned CLCIN7PPS2 :1; + unsigned CLCIN7PPS3 :1; + unsigned CLCIN7PPS4 :1; + }; + struct { + unsigned CLCIN7PPS :5; + }; +} CLCIN7PPSbits_t; +extern volatile CLCIN7PPSbits_t CLCIN7PPSbits __attribute__((address(0x268))); +# 28447 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACTPPS __attribute__((address(0x269))); + +__asm("ADACTPPS equ 0269h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned ADACTPPS0 :1; + unsigned ADACTPPS1 :1; + unsigned ADACTPPS2 :1; + unsigned ADACTPPS3 :1; + unsigned ADACTPPS4 :1; + }; + struct { + unsigned ADACTPPS :5; + }; +} ADACTPPSbits_t; +extern volatile ADACTPPSbits_t ADACTPPSbits __attribute__((address(0x269))); +# 28513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SCKPPS __attribute__((address(0x26A))); + +__asm("SPI1SCKPPS equ 026Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SCKPPS :5; + }; + struct { + unsigned SPI1SCKPPS0 :1; + unsigned SPI1SCKPPS1 :1; + unsigned SPI1SCKPPS2 :1; + unsigned SPI1SCKPPS3 :1; + unsigned SPI1SCKPPS4 :1; + }; +} SPI1SCKPPSbits_t; +extern volatile SPI1SCKPPSbits_t SPI1SCKPPSbits __attribute__((address(0x26A))); +# 28579 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SDIPPS __attribute__((address(0x26B))); + +__asm("SPI1SDIPPS equ 026Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SDIPPS :5; + }; + struct { + unsigned SPI1SDIPPS0 :1; + unsigned SPI1SDIPPS1 :1; + unsigned SPI1SDIPPS2 :1; + unsigned SPI1SDIPPS3 :1; + unsigned SPI1SDIPPS4 :1; + }; +} SPI1SDIPPSbits_t; +extern volatile SPI1SDIPPSbits_t SPI1SDIPPSbits __attribute__((address(0x26B))); +# 28645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI1SSPPS __attribute__((address(0x26C))); + +__asm("SPI1SSPPS equ 026Ch"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI1SSPPS :5; + }; + struct { + unsigned SPI1SSPPS0 :1; + unsigned SPI1SSPPS1 :1; + unsigned SPI1SSPPS2 :1; + unsigned SPI1SSPPS3 :1; + unsigned SPI1SSPPS4 :1; + }; +} SPI1SSPPSbits_t; +extern volatile SPI1SSPPSbits_t SPI1SSPPSbits __attribute__((address(0x26C))); +# 28711 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SCKPPS __attribute__((address(0x26D))); + +__asm("SPI2SCKPPS equ 026Dh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SCKPPS :5; + }; + struct { + unsigned SPI2SCKPPS0 :1; + unsigned SPI2SCKPPS1 :1; + unsigned SPI2SCKPPS2 :1; + unsigned SPI2SCKPPS3 :1; + unsigned SPI2SCKPPS4 :1; + }; +} SPI2SCKPPSbits_t; +extern volatile SPI2SCKPPSbits_t SPI2SCKPPSbits __attribute__((address(0x26D))); +# 28777 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SDIPPS __attribute__((address(0x26E))); + +__asm("SPI2SDIPPS equ 026Eh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SDIPPS :5; + }; + struct { + unsigned SPI2SDIPPS0 :1; + unsigned SPI2SDIPPS1 :1; + unsigned SPI2SDIPPS2 :1; + unsigned SPI2SDIPPS3 :1; + unsigned SPI2SDIPPS4 :1; + }; +} SPI2SDIPPSbits_t; +extern volatile SPI2SDIPPSbits_t SPI2SDIPPSbits __attribute__((address(0x26E))); +# 28843 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SPI2SSPPS __attribute__((address(0x26F))); + +__asm("SPI2SSPPS equ 026Fh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned SPI2SSPPS :5; + }; + struct { + unsigned SPI2SSPPS0 :1; + unsigned SPI2SSPPS1 :1; + unsigned SPI2SSPPS2 :1; + unsigned SPI2SSPPS3 :1; + unsigned SPI2SSPPS4 :1; + }; +} SPI2SSPPSbits_t; +extern volatile SPI2SSPPSbits_t SPI2SSPPSbits __attribute__((address(0x26F))); +# 28909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SDAPPS __attribute__((address(0x270))); + +__asm("I2C1SDAPPS equ 0270h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SDAPPS :5; + }; + struct { + unsigned I2C1SDAPPS0 :1; + unsigned I2C1SDAPPS1 :1; + unsigned I2C1SDAPPS2 :1; + unsigned I2C1SDAPPS3 :1; + unsigned I2C1SDAPPS4 :1; + }; +} I2C1SDAPPSbits_t; +extern volatile I2C1SDAPPSbits_t I2C1SDAPPSbits __attribute__((address(0x270))); +# 28975 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1SCLPPS __attribute__((address(0x271))); + +__asm("I2C1SCLPPS equ 0271h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned I2C1SCLPPS :5; + }; + struct { + unsigned I2C1SCLPPS0 :1; + unsigned I2C1SCLPPS1 :1; + unsigned I2C1SCLPPS2 :1; + unsigned I2C1SCLPPS3 :1; + unsigned I2C1SCLPPS4 :1; + }; +} I2C1SCLPPSbits_t; +extern volatile I2C1SCLPPSbits_t I2C1SCLPPSbits __attribute__((address(0x271))); +# 29041 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXPPS __attribute__((address(0x272))); + +__asm("U1RXPPS equ 0272h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1RXPPS :6; + }; + struct { + unsigned U1RXPPS0 :1; + unsigned U1RXPPS1 :1; + unsigned U1RXPPS2 :1; + unsigned U1RXPPS3 :1; + unsigned U1RXPPS4 :1; + unsigned U1RXPPS5 :1; + }; +} U1RXPPSbits_t; +extern volatile U1RXPPSbits_t U1RXPPSbits __attribute__((address(0x272))); +# 29113 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CTSPPS __attribute__((address(0x273))); + +__asm("U1CTSPPS equ 0273h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U1CTSPPS :6; + }; + struct { + unsigned U1CTSPPS0 :1; + unsigned U1CTSPPS1 :1; + unsigned U1CTSPPS2 :1; + unsigned U1CTSPPS3 :1; + unsigned U1CTSPPS4 :1; + unsigned U1CTSPPS5 :1; + }; +} U1CTSPPSbits_t; +extern volatile U1CTSPPSbits_t U1CTSPPSbits __attribute__((address(0x273))); +# 29185 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXPPS __attribute__((address(0x274))); + +__asm("U2RXPPS equ 0274h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2RXPPS :5; + }; + struct { + unsigned U2RXPPS0 :1; + unsigned U2RXPPS1 :1; + unsigned U2RXPPS2 :1; + unsigned U2RXPPS3 :1; + unsigned U2RXPPS4 :1; + }; +} U2RXPPSbits_t; +extern volatile U2RXPPSbits_t U2RXPPSbits __attribute__((address(0x274))); +# 29251 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CTSPPS __attribute__((address(0x275))); + +__asm("U2CTSPPS equ 0275h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U2CTSPPS :5; + }; + struct { + unsigned U2CTSPPS0 :1; + unsigned U2CTSPPS1 :1; + unsigned U2CTSPPS2 :1; + unsigned U2CTSPPS3 :1; + unsigned U2CTSPPS4 :1; + }; +} U2CTSPPSbits_t; +extern volatile U2CTSPPSbits_t U2CTSPPSbits __attribute__((address(0x275))); +# 29317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXPPS __attribute__((address(0x276))); + +__asm("U3RXPPS equ 0276h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3RXPPS :6; + }; + struct { + unsigned U3RXPPS0 :1; + unsigned U3RXPPS1 :1; + unsigned U3RXPPS2 :1; + unsigned U3RXPPS3 :1; + unsigned U3RXPPS4 :1; + unsigned U3RXPPS5 :1; + }; +} U3RXPPSbits_t; +extern volatile U3RXPPSbits_t U3RXPPSbits __attribute__((address(0x276))); +# 29389 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CTSPPS __attribute__((address(0x277))); + +__asm("U3CTSPPS equ 0277h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U3CTSPPS :6; + }; + struct { + unsigned U3CTSPPS0 :1; + unsigned U3CTSPPS1 :1; + unsigned U3CTSPPS2 :1; + unsigned U3CTSPPS3 :1; + unsigned U3CTSPPS4 :1; + unsigned U3CTSPPS5 :1; + }; +} U3CTSPPSbits_t; +extern volatile U3CTSPPSbits_t U3CTSPPSbits __attribute__((address(0x277))); +# 29461 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXPPS __attribute__((address(0x278))); + +__asm("U4RXPPS equ 0278h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4RXPPS :5; + }; + struct { + unsigned U4RXPPS0 :1; + unsigned U4RXPPS1 :1; + unsigned U4RXPPS2 :1; + unsigned U4RXPPS3 :1; + unsigned U4RXPPS4 :1; + }; +} U4RXPPSbits_t; +extern volatile U4RXPPSbits_t U4RXPPSbits __attribute__((address(0x278))); +# 29527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CTSPPS __attribute__((address(0x279))); + +__asm("U4CTSPPS equ 0279h"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :2; + }; + struct { + unsigned U4CTSPPS :5; + }; + struct { + unsigned U4CTSPPS0 :1; + unsigned U4CTSPPS1 :1; + unsigned U4CTSPPS2 :1; + unsigned U4CTSPPS3 :1; + unsigned U4CTSPPS4 :1; + }; +} U4CTSPPSbits_t; +extern volatile U4CTSPPSbits_t U4CTSPPSbits __attribute__((address(0x279))); +# 29593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXPPS __attribute__((address(0x27A))); + +__asm("U5RXPPS equ 027Ah"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5RXPPS :6; + }; + struct { + unsigned U5RXPPS0 :1; + unsigned U5RXPPS1 :1; + unsigned U5RXPPS2 :1; + unsigned U5RXPPS3 :1; + unsigned U5RXPPS4 :1; + unsigned U5RXPPS5 :1; + }; +} U5RXPPSbits_t; +extern volatile U5RXPPSbits_t U5RXPPSbits __attribute__((address(0x27A))); +# 29665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CTSPPS __attribute__((address(0x27B))); + +__asm("U5CTSPPS equ 027Bh"); + + +typedef union { + struct { + unsigned PIN :3; + unsigned PORT :3; + }; + struct { + unsigned U5CTSPPS :6; + }; + struct { + unsigned U5CTSPPS0 :1; + unsigned U5CTSPPS1 :1; + unsigned U5CTSPPS2 :1; + unsigned U5CTSPPS3 :1; + unsigned U5CTSPPS4 :1; + unsigned U5CTSPPS5 :1; + }; +} U5CTSPPSbits_t; +extern volatile U5CTSPPSbits_t U5CTSPPSbits __attribute__((address(0x27B))); +# 29737 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC4I2C __attribute__((address(0x286))); + +__asm("RC4I2C equ 0286h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC4I2Cbits_t; +extern volatile RC4I2Cbits_t RC4I2Cbits __attribute__((address(0x286))); +# 29869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RC3I2C __attribute__((address(0x287))); + +__asm("RC3I2C equ 0287h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RC3I2Cbits_t; +extern volatile RC3I2Cbits_t RC3I2Cbits __attribute__((address(0x287))); +# 30001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB2I2C __attribute__((address(0x288))); + +__asm("RB2I2C equ 0288h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB2I2Cbits_t; +extern volatile RB2I2Cbits_t RB2I2Cbits __attribute__((address(0x288))); +# 30133 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char RB1I2C __attribute__((address(0x289))); + +__asm("RB1I2C equ 0289h"); + + +typedef union { + struct { + unsigned TH :2; + unsigned :2; + unsigned PU :2; + unsigned SLEW :2; + }; + struct { + unsigned TH0 :1; + unsigned TH1 :1; + unsigned :2; + unsigned PU0 :1; + unsigned PU1 :1; + unsigned SLEW0 :1; + unsigned SLEW1 :1; + }; + struct { + unsigned I2CTH :2; + unsigned :2; + unsigned I2CPU :2; + unsigned I2CSLEW :2; + }; + struct { + unsigned I2CTH0 :1; + unsigned I2CTH1 :1; + unsigned :2; + unsigned I2CPU0 :1; + unsigned I2CPU1 :1; + unsigned I2CSLEW0 :1; + unsigned I2CSLEW1 :1; + }; +} RB1I2Cbits_t; +extern volatile RB1I2Cbits_t RB1I2Cbits __attribute__((address(0x289))); +# 30265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1RXB __attribute__((address(0x28A))); + +__asm("I2C1RXB equ 028Ah"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} I2C1RXBbits_t; +extern volatile I2C1RXBbits_t I2C1RXBbits __attribute__((address(0x28A))); +# 30285 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1TXB __attribute__((address(0x28B))); + +__asm("I2C1TXB equ 028Bh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} I2C1TXBbits_t; +extern volatile I2C1TXBbits_t I2C1TXBbits __attribute__((address(0x28B))); +# 30305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTL __attribute__((address(0x28C))); + +__asm("I2C1CNTL equ 028Ch"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} I2C1CNTLbits_t; +extern volatile I2C1CNTLbits_t I2C1CNTLbits __attribute__((address(0x28C))); +# 30375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CNTH __attribute__((address(0x28D))); + +__asm("I2C1CNTH equ 028Dh"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned CNT8 :1; + unsigned CNT9 :1; + unsigned CNT10 :1; + unsigned CNT11 :1; + unsigned CNT12 :1; + unsigned CNT13 :1; + unsigned CNT14 :1; + unsigned CNT15 :1; + }; +} I2C1CNTHbits_t; +extern volatile I2C1CNTHbits_t I2C1CNTHbits __attribute__((address(0x28D))); +# 30445 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB0 __attribute__((address(0x28E))); + +__asm("I2C1ADB0 equ 028Eh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB0bits_t; +extern volatile I2C1ADB0bits_t I2C1ADB0bits __attribute__((address(0x28E))); +# 30465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADB1 __attribute__((address(0x28F))); + +__asm("I2C1ADB1 equ 028Fh"); + + +typedef union { + struct { + unsigned ADB :8; + }; +} I2C1ADB1bits_t; +extern volatile I2C1ADB1bits_t I2C1ADB1bits __attribute__((address(0x28F))); +# 30485 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR0 __attribute__((address(0x290))); + +__asm("I2C1ADR0 equ 0290h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR0bits_t; +extern volatile I2C1ADR0bits_t I2C1ADR0bits __attribute__((address(0x290))); +# 30505 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR1 __attribute__((address(0x291))); + +__asm("I2C1ADR1 equ 0291h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR1bits_t; +extern volatile I2C1ADR1bits_t I2C1ADR1bits __attribute__((address(0x291))); +# 30526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR2 __attribute__((address(0x292))); + +__asm("I2C1ADR2 equ 0292h"); + + +typedef union { + struct { + unsigned ADR :8; + }; +} I2C1ADR2bits_t; +extern volatile I2C1ADR2bits_t I2C1ADR2bits __attribute__((address(0x292))); +# 30546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ADR3 __attribute__((address(0x293))); + +__asm("I2C1ADR3 equ 0293h"); + + +typedef union { + struct { + unsigned :1; + unsigned ADR :7; + }; +} I2C1ADR3bits_t; +extern volatile I2C1ADR3bits_t I2C1ADR3bits __attribute__((address(0x293))); +# 30567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON0 __attribute__((address(0x294))); + +__asm("I2C1CON0 equ 0294h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned MDR :1; + unsigned CSTR :1; + unsigned S :1; + unsigned RSEN :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned I2CEN :1; + }; +} I2C1CON0bits_t; +extern volatile I2C1CON0bits_t I2C1CON0bits __attribute__((address(0x294))); +# 30644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON1 __attribute__((address(0x295))); + +__asm("I2C1CON1 equ 0295h"); + + +typedef union { + struct { + unsigned CSD :1; + unsigned TXU :1; + unsigned RXO :1; + unsigned P :1; + unsigned ACKT :1; + unsigned ACKSTAT :1; + unsigned ACKDT :1; + unsigned ACKCNT :1; + }; +} I2C1CON1bits_t; +extern volatile I2C1CON1bits_t I2C1CON1bits __attribute__((address(0x295))); +# 30706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CON2 __attribute__((address(0x296))); + +__asm("I2C1CON2 equ 0296h"); + + +typedef union { + struct { + unsigned BFRET :2; + unsigned SDAHT :2; + unsigned ABD :1; + unsigned FME :1; + unsigned GCEN :1; + unsigned ACNT :1; + }; + struct { + unsigned BFRET0 :1; + unsigned BFRET1 :1; + unsigned SDAHT0 :1; + unsigned SDAHT1 :1; + }; +} I2C1CON2bits_t; +extern volatile I2C1CON2bits_t I2C1CON2bits __attribute__((address(0x296))); +# 30782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1ERR __attribute__((address(0x297))); + +__asm("I2C1ERR equ 0297h"); + + +typedef union { + struct { + unsigned NACKIE :1; + unsigned BCLIE :1; + unsigned BTOIE :1; + unsigned :1; + unsigned NACKIF :1; + unsigned BCLIF :1; + unsigned BTOIF :1; + }; + struct { + unsigned NACK1IE :1; + unsigned BCL1IE :1; + unsigned BTO1IE :1; + unsigned :1; + unsigned NACK1IF :1; + unsigned BCL1IF :1; + unsigned BTO1IF :1; + }; +} I2C1ERRbits_t; +extern volatile I2C1ERRbits_t I2C1ERRbits __attribute__((address(0x297))); +# 30872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT0 __attribute__((address(0x298))); + +__asm("I2C1STAT0 equ 0298h"); + + +typedef union { + struct { + unsigned :3; + unsigned D :1; + unsigned R :1; + unsigned MMA :1; + unsigned SMA :1; + unsigned BFRE :1; + }; + struct { + unsigned :3; + unsigned DATA :1; + unsigned READ :1; + }; + struct { + unsigned :3; + unsigned NOT_ADDRESS :1; + unsigned NOT_WRITE :1; + }; + struct { + unsigned :3; + unsigned NOT_A :1; + unsigned NOT_W :1; + }; +} I2C1STAT0bits_t; +extern volatile I2C1STAT0bits_t I2C1STAT0bits __attribute__((address(0x298))); +# 30962 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1STAT1 __attribute__((address(0x299))); + +__asm("I2C1STAT1 equ 0299h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned :1; + unsigned CLRBF :1; + unsigned RXRE :1; + unsigned :1; + unsigned TXBE :1; + unsigned :1; + unsigned TXWE :1; + }; +} I2C1STAT1bits_t; +extern volatile I2C1STAT1bits_t I2C1STAT1bits __attribute__((address(0x299))); +# 31009 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIR __attribute__((address(0x29A))); + +__asm("I2C1PIR equ 029Ah"); + + +typedef union { + struct { + unsigned SCIF :1; + unsigned RSCIF :1; + unsigned PCIF :1; + unsigned ADRIF :1; + unsigned WRIF :1; + unsigned :1; + unsigned ACKTIF :1; + unsigned CNTIF :1; + }; + struct { + unsigned SC1IF :1; + unsigned RSC1IF :1; + unsigned PC1IF :1; + unsigned ADR1IF :1; + unsigned WR1IF :1; + unsigned :1; + unsigned ACKT1IF :1; + unsigned CNT1IF :1; + }; +} I2C1PIRbits_t; +extern volatile I2C1PIRbits_t I2C1PIRbits __attribute__((address(0x29A))); +# 31111 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1PIE __attribute__((address(0x29B))); + +__asm("I2C1PIE equ 029Bh"); + + +typedef union { + struct { + unsigned SCIE :1; + unsigned RSCIE :1; + unsigned PCIE :1; + unsigned ADRIE :1; + unsigned WRIE :1; + unsigned :1; + unsigned ACKTIE :1; + unsigned CNTIE :1; + }; + struct { + unsigned SC1IE :1; + unsigned RSC1IE :1; + unsigned PC1IE :1; + unsigned ADR1IE :1; + unsigned WR1IE :1; + unsigned :1; + unsigned ACKT1IE :1; + unsigned CNT1IE :1; + }; +} I2C1PIEbits_t; +extern volatile I2C1PIEbits_t I2C1PIEbits __attribute__((address(0x29B))); +# 31213 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTO __attribute__((address(0x29C))); + +__asm("I2C1BTO equ 029Ch"); + + +typedef union { + struct { + unsigned TOTIME :6; + unsigned TOBY32 :1; + unsigned TOREC :1; + }; + struct { + unsigned TOTIME0 :1; + unsigned TOTIME1 :1; + unsigned TOTIME2 :1; + unsigned TOTIME3 :1; + unsigned TOTIME4 :1; + unsigned TOTIME5 :1; + }; +} I2C1BTObits_t; +extern volatile I2C1BTObits_t I2C1BTObits __attribute__((address(0x29C))); +# 31283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BAUD __attribute__((address(0x29D))); + +__asm("I2C1BAUD equ 029Dh"); + + +typedef union { + struct { + unsigned BAUD :8; + }; +} I2C1BAUDbits_t; +extern volatile I2C1BAUDbits_t I2C1BAUDbits __attribute__((address(0x29D))); +# 31303 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1CLK __attribute__((address(0x29E))); + +__asm("I2C1CLK equ 029Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned I2CCLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned I2CCLK0 :1; + unsigned I2CCLK1 :1; + unsigned I2CCLK2 :1; + unsigned I2CCLK3 :1; + unsigned I2CCLK4 :1; + }; +} I2C1CLKbits_t; +extern volatile I2C1CLKbits_t I2C1CLKbits __attribute__((address(0x29E))); +# 31395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char I2C1BTOC __attribute__((address(0x29F))); + +__asm("I2C1BTOC equ 029Fh"); + + +typedef union { + struct { + unsigned BTOC :4; + }; + struct { + unsigned I2CBTOC :4; + }; + struct { + unsigned BTOC0 :1; + unsigned BTOC1 :1; + unsigned BTOC2 :1; + unsigned BTOC3 :1; + }; + struct { + unsigned I2CBTOC0 :1; + unsigned I2CBTOC1 :1; + unsigned I2CBTOC2 :1; + unsigned I2CBTOC3 :1; + }; +} I2C1BTOCbits_t; +extern volatile I2C1BTOCbits_t I2C1BTOCbits __attribute__((address(0x29F))); +# 31475 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXB __attribute__((address(0x2A1))); + +__asm("U1RXB equ 02A1h"); + + +extern volatile unsigned char U1RXBL __attribute__((address(0x2A1))); + +__asm("U1RXBL equ 02A1h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBbits_t; +extern volatile U1RXBbits_t U1RXBbits __attribute__((address(0x2A1))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U1RXBLbits_t; +extern volatile U1RXBLbits_t U1RXBLbits __attribute__((address(0x2A1))); +# 31513 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1RXCHK __attribute__((address(0x2A2))); + +__asm("U1RXCHK equ 02A2h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U1RXCHKbits_t; +extern volatile U1RXCHKbits_t U1RXCHKbits __attribute__((address(0x2A2))); +# 31533 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXB __attribute__((address(0x2A3))); + +__asm("U1TXB equ 02A3h"); + + +extern volatile unsigned char U1TXBL __attribute__((address(0x2A3))); + +__asm("U1TXBL equ 02A3h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBbits_t; +extern volatile U1TXBbits_t U1TXBbits __attribute__((address(0x2A3))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U1TXBLbits_t; +extern volatile U1TXBLbits_t U1TXBLbits __attribute__((address(0x2A3))); +# 31571 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1TXCHK __attribute__((address(0x2A4))); + +__asm("U1TXCHK equ 02A4h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U1TXCHKbits_t; +extern volatile U1TXCHKbits_t U1TXCHKbits __attribute__((address(0x2A4))); +# 31591 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P1 __attribute__((address(0x2A5))); + +__asm("U1P1 equ 02A5h"); + + + + +extern volatile unsigned char U1P1L __attribute__((address(0x2A5))); + +__asm("U1P1L equ 02A5h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U1P1Lbits_t; +extern volatile U1P1Lbits_t U1P1Lbits __attribute__((address(0x2A5))); +# 31618 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P1H __attribute__((address(0x2A6))); + +__asm("U1P1H equ 02A6h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U1P1Hbits_t; +extern volatile U1P1Hbits_t U1P1Hbits __attribute__((address(0x2A6))); +# 31638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P2 __attribute__((address(0x2A7))); + +__asm("U1P2 equ 02A7h"); + + + + +extern volatile unsigned char U1P2L __attribute__((address(0x2A7))); + +__asm("U1P2L equ 02A7h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U1P2Lbits_t; +extern volatile U1P2Lbits_t U1P2Lbits __attribute__((address(0x2A7))); +# 31665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P2H __attribute__((address(0x2A8))); + +__asm("U1P2H equ 02A8h"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U1P2Hbits_t; +extern volatile U1P2Hbits_t U1P2Hbits __attribute__((address(0x2A8))); +# 31685 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1P3 __attribute__((address(0x2A9))); + +__asm("U1P3 equ 02A9h"); + + + + +extern volatile unsigned char U1P3L __attribute__((address(0x2A9))); + +__asm("U1P3L equ 02A9h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U1P3Lbits_t; +extern volatile U1P3Lbits_t U1P3Lbits __attribute__((address(0x2A9))); +# 31712 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1P3H __attribute__((address(0x2AA))); + +__asm("U1P3H equ 02AAh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U1P3Hbits_t; +extern volatile U1P3Hbits_t U1P3Hbits __attribute__((address(0x2AA))); +# 31732 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON0 __attribute__((address(0x2AB))); + +__asm("U1CON0 equ 02ABh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U1MODE :4; + unsigned U1RXEN :1; + unsigned U1TXEN :1; + unsigned U1ABDEN :1; + unsigned U1BRGS :1; + }; + struct { + unsigned U1MODE0 :1; + unsigned U1MODE1 :1; + unsigned U1MODE2 :1; + unsigned U1MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U1CON0bits_t; +extern volatile U1CON0bits_t U1CON0bits __attribute__((address(0x2AB))); +# 31860 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON1 __attribute__((address(0x2AC))); + +__asm("U1CON1 equ 02ACh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U1SENDB :1; + unsigned U1BRKOVR :1; + unsigned :1; + unsigned U1RXBIMD :1; + unsigned U1WUE :1; + unsigned :2; + unsigned U1ON :1; + }; +} U1CON1bits_t; +extern volatile U1CON1bits_t U1CON1bits __attribute__((address(0x2AC))); +# 31940 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1CON2 __attribute__((address(0x2AD))); + +__asm("U1CON2 equ 02ADh"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U1FLO :2; + unsigned U1TXPOL :1; + unsigned U1C0EN :1; + unsigned U1STP :2; + unsigned U1RXPOL :1; + unsigned U1RUNOVF :1; + }; + struct { + unsigned U1FLO0 :1; + unsigned U1FLO1 :1; + unsigned :2; + unsigned U1STP0 :1; + unsigned U1STP1 :1; + }; +} U1CON2bits_t; +extern volatile U1CON2bits_t U1CON2bits __attribute__((address(0x2AD))); +# 32082 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U1BRG __attribute__((address(0x2AE))); + +__asm("U1BRG equ 02AEh"); + + + + +extern volatile unsigned char U1BRGL __attribute__((address(0x2AE))); + +__asm("U1BRGL equ 02AEh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U1BRGLbits_t; +extern volatile U1BRGLbits_t U1BRGLbits __attribute__((address(0x2AE))); +# 32109 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1BRGH __attribute__((address(0x2AF))); + +__asm("U1BRGH equ 02AFh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U1BRGHbits_t; +extern volatile U1BRGHbits_t U1BRGHbits __attribute__((address(0x2AF))); +# 32129 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1FIFO __attribute__((address(0x2B0))); + +__asm("U1FIFO equ 02B0h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U1RXBF :1; + unsigned U1RXBE :1; + unsigned U1XON :1; + unsigned U1RXIDL :1; + unsigned U1TXBF :1; + unsigned U1TXBE :1; + unsigned U1STPMD :1; + unsigned U1TXWRE :1; + }; + struct { + unsigned :3; + unsigned U1RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U1FIFObits_t; +extern volatile U1FIFObits_t U1FIFObits __attribute__((address(0x2B0))); +# 32259 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1UIR __attribute__((address(0x2B1))); + +__asm("U1UIR equ 02B1h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U1ABDIE :1; + unsigned :3; + unsigned U1ABDIF :1; + unsigned U1WUIF :1; + }; +} U1UIRbits_t; +extern volatile U1UIRbits_t U1UIRbits __attribute__((address(0x2B1))); +# 32315 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIR __attribute__((address(0x2B2))); + +__asm("U1ERRIR equ 02B2h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U1TXCIF :1; + unsigned U1RXFOIF :1; + unsigned U1RXBKIF :1; + unsigned U1FERIF :1; + unsigned U1CERIF :1; + unsigned U1ABDOVF :1; + unsigned U1PERIF :1; + unsigned U1TXMTIF :1; + }; +} U1ERRIRbits_t; +extern volatile U1ERRIRbits_t U1ERRIRbits __attribute__((address(0x2B2))); +# 32427 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U1ERRIE __attribute__((address(0x2B3))); + +__asm("U1ERRIE equ 02B3h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U1TXCIE :1; + unsigned U1RXFOIE :1; + unsigned U1RXBKIE :1; + unsigned U1FERIE :1; + unsigned U1CERIE :1; + unsigned U1ABDOVE :1; + unsigned U1PERIE :1; + unsigned U1TXMTIE :1; + }; +} U1ERRIEbits_t; +extern volatile U1ERRIEbits_t U1ERRIEbits __attribute__((address(0x2B3))); +# 32539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXB __attribute__((address(0x2B4))); + +__asm("U2RXB equ 02B4h"); + + +extern volatile unsigned char U2RXBL __attribute__((address(0x2B4))); + +__asm("U2RXBL equ 02B4h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBbits_t; +extern volatile U2RXBbits_t U2RXBbits __attribute__((address(0x2B4))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U2RXBLbits_t; +extern volatile U2RXBLbits_t U2RXBLbits __attribute__((address(0x2B4))); +# 32577 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2RXCHK __attribute__((address(0x2B5))); + +__asm("U2RXCHK equ 02B5h"); + + +typedef union { + struct { + unsigned RXCHK :8; + }; +} U2RXCHKbits_t; +extern volatile U2RXCHKbits_t U2RXCHKbits __attribute__((address(0x2B5))); +# 32597 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXB __attribute__((address(0x2B6))); + +__asm("U2TXB equ 02B6h"); + + +extern volatile unsigned char U2TXBL __attribute__((address(0x2B6))); + +__asm("U2TXBL equ 02B6h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBbits_t; +extern volatile U2TXBbits_t U2TXBbits __attribute__((address(0x2B6))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U2TXBLbits_t; +extern volatile U2TXBLbits_t U2TXBLbits __attribute__((address(0x2B6))); +# 32635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2TXCHK __attribute__((address(0x2B7))); + +__asm("U2TXCHK equ 02B7h"); + + +typedef union { + struct { + unsigned TXCHK :8; + }; +} U2TXCHKbits_t; +extern volatile U2TXCHKbits_t U2TXCHKbits __attribute__((address(0x2B7))); +# 32655 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P1 __attribute__((address(0x2B8))); + +__asm("U2P1 equ 02B8h"); + + + + +extern volatile unsigned char U2P1L __attribute__((address(0x2B8))); + +__asm("U2P1L equ 02B8h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U2P1Lbits_t; +extern volatile U2P1Lbits_t U2P1Lbits __attribute__((address(0x2B8))); +# 32682 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P1H __attribute__((address(0x2B9))); + +__asm("U2P1H equ 02B9h"); + + +typedef union { + struct { + unsigned P1H :1; + }; +} U2P1Hbits_t; +extern volatile U2P1Hbits_t U2P1Hbits __attribute__((address(0x2B9))); +# 32702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P2 __attribute__((address(0x2BA))); + +__asm("U2P2 equ 02BAh"); + + + + +extern volatile unsigned char U2P2L __attribute__((address(0x2BA))); + +__asm("U2P2L equ 02BAh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U2P2Lbits_t; +extern volatile U2P2Lbits_t U2P2Lbits __attribute__((address(0x2BA))); +# 32729 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P2H __attribute__((address(0x2BB))); + +__asm("U2P2H equ 02BBh"); + + +typedef union { + struct { + unsigned P2H :1; + }; +} U2P2Hbits_t; +extern volatile U2P2Hbits_t U2P2Hbits __attribute__((address(0x2BB))); +# 32749 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2P3 __attribute__((address(0x2BC))); + +__asm("U2P3 equ 02BCh"); + + + + +extern volatile unsigned char U2P3L __attribute__((address(0x2BC))); + +__asm("U2P3L equ 02BCh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U2P3Lbits_t; +extern volatile U2P3Lbits_t U2P3Lbits __attribute__((address(0x2BC))); +# 32776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2P3H __attribute__((address(0x2BD))); + +__asm("U2P3H equ 02BDh"); + + +typedef union { + struct { + unsigned P3H :1; + }; +} U2P3Hbits_t; +extern volatile U2P3Hbits_t U2P3Hbits __attribute__((address(0x2BD))); +# 32796 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON0 __attribute__((address(0x2BE))); + +__asm("U2CON0 equ 02BEh"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned U2MODE :4; + unsigned U2RXEN :1; + unsigned U2TXEN :1; + unsigned U2ABDEN :1; + unsigned U2BRGS :1; + }; + struct { + unsigned U2MODE0 :1; + unsigned U2MODE1 :1; + unsigned U2MODE2 :1; + unsigned U2MODE3 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U2CON0bits_t; +extern volatile U2CON0bits_t U2CON0bits __attribute__((address(0x2BE))); +# 32924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON1 __attribute__((address(0x2BF))); + +__asm("U2CON1 equ 02BFh"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U2SENDB :1; + unsigned U2BRKOVR :1; + unsigned :1; + unsigned U2RXBIMD :1; + unsigned U2WUE :1; + unsigned :2; + unsigned U2ON :1; + }; +} U2CON1bits_t; +extern volatile U2CON1bits_t U2CON1bits __attribute__((address(0x2BF))); +# 33004 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2CON2 __attribute__((address(0x2C0))); + +__asm("U2CON2 equ 02C0h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned C0EN :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U2FLO :2; + unsigned U2TXPOL :1; + unsigned U2C0EN :1; + unsigned U2STP :2; + unsigned U2RXPOL :1; + unsigned U2RUNOVF :1; + }; + struct { + unsigned U2FLO0 :1; + unsigned U2FLO1 :1; + unsigned :2; + unsigned U2STP0 :1; + unsigned U2STP1 :1; + }; +} U2CON2bits_t; +extern volatile U2CON2bits_t U2CON2bits __attribute__((address(0x2C0))); +# 33146 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U2BRG __attribute__((address(0x2C1))); + +__asm("U2BRG equ 02C1h"); + + + + +extern volatile unsigned char U2BRGL __attribute__((address(0x2C1))); + +__asm("U2BRGL equ 02C1h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U2BRGLbits_t; +extern volatile U2BRGLbits_t U2BRGLbits __attribute__((address(0x2C1))); +# 33173 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2BRGH __attribute__((address(0x2C2))); + +__asm("U2BRGH equ 02C2h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U2BRGHbits_t; +extern volatile U2BRGHbits_t U2BRGHbits __attribute__((address(0x2C2))); +# 33193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2FIFO __attribute__((address(0x2C3))); + +__asm("U2FIFO equ 02C3h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U2RXBF :1; + unsigned U2RXBE :1; + unsigned U2XON :1; + unsigned U2RXIDL :1; + unsigned U2TXBF :1; + unsigned U2TXBE :1; + unsigned U2STPMD :1; + unsigned U2TXWRE :1; + }; + struct { + unsigned :3; + unsigned U2RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U2FIFObits_t; +extern volatile U2FIFObits_t U2FIFObits __attribute__((address(0x2C3))); +# 33323 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2UIR __attribute__((address(0x2C4))); + +__asm("U2UIR equ 02C4h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U2ABDIE :1; + unsigned :3; + unsigned U2ABDIF :1; + unsigned U2WUIF :1; + }; +} U2UIRbits_t; +extern volatile U2UIRbits_t U2UIRbits __attribute__((address(0x2C4))); +# 33379 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIR __attribute__((address(0x2C5))); + +__asm("U2ERRIR equ 02C5h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U2TXCIF :1; + unsigned U2RXFOIF :1; + unsigned U2RXBKIF :1; + unsigned U2FERIF :1; + unsigned U2CERIF :1; + unsigned U2ABDOVF :1; + unsigned U2PERIF :1; + unsigned U2TXMTIF :1; + }; +} U2ERRIRbits_t; +extern volatile U2ERRIRbits_t U2ERRIRbits __attribute__((address(0x2C5))); +# 33491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U2ERRIE __attribute__((address(0x2C6))); + +__asm("U2ERRIE equ 02C6h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U2TXCIE :1; + unsigned U2RXFOIE :1; + unsigned U2RXBKIE :1; + unsigned U2FERIE :1; + unsigned U2CERIE :1; + unsigned U2ABDOVE :1; + unsigned U2PERIE :1; + unsigned U2TXMTIE :1; + }; +} U2ERRIEbits_t; +extern volatile U2ERRIEbits_t U2ERRIEbits __attribute__((address(0x2C6))); +# 33603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3RXB __attribute__((address(0x2C7))); + +__asm("U3RXB equ 02C7h"); + + +extern volatile unsigned char U3RXBL __attribute__((address(0x2C7))); + +__asm("U3RXBL equ 02C7h"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBbits_t; +extern volatile U3RXBbits_t U3RXBbits __attribute__((address(0x2C7))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U3RXBLbits_t; +extern volatile U3RXBLbits_t U3RXBLbits __attribute__((address(0x2C7))); +# 33641 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3TXB __attribute__((address(0x2C9))); + +__asm("U3TXB equ 02C9h"); + + +extern volatile unsigned char U3TXBL __attribute__((address(0x2C9))); + +__asm("U3TXBL equ 02C9h"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBbits_t; +extern volatile U3TXBbits_t U3TXBbits __attribute__((address(0x2C9))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U3TXBLbits_t; +extern volatile U3TXBLbits_t U3TXBLbits __attribute__((address(0x2C9))); +# 33679 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P1 __attribute__((address(0x2CB))); + +__asm("U3P1 equ 02CBh"); + + + + +extern volatile unsigned char U3P1L __attribute__((address(0x2CB))); + +__asm("U3P1L equ 02CBh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U3P1Lbits_t; +extern volatile U3P1Lbits_t U3P1Lbits __attribute__((address(0x2CB))); +# 33706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P2 __attribute__((address(0x2CD))); + +__asm("U3P2 equ 02CDh"); + + + + +extern volatile unsigned char U3P2L __attribute__((address(0x2CD))); + +__asm("U3P2L equ 02CDh"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U3P2Lbits_t; +extern volatile U3P2Lbits_t U3P2Lbits __attribute__((address(0x2CD))); +# 33733 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3P3 __attribute__((address(0x2CF))); + +__asm("U3P3 equ 02CFh"); + + + + +extern volatile unsigned char U3P3L __attribute__((address(0x2CF))); + +__asm("U3P3L equ 02CFh"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U3P3Lbits_t; +extern volatile U3P3Lbits_t U3P3Lbits __attribute__((address(0x2CF))); +# 33760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON0 __attribute__((address(0x2D1))); + +__asm("U3CON0 equ 02D1h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U3MODE :4; + unsigned U3RXEN :1; + unsigned U3TXEN :1; + unsigned U3ABDEN :1; + unsigned U3BRGS :1; + }; + struct { + unsigned U3MODE0 :1; + unsigned U3MODE1 :1; + unsigned U3MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U3CON0bits_t; +extern volatile U3CON0bits_t U3CON0bits __attribute__((address(0x2D1))); +# 33876 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON1 __attribute__((address(0x2D2))); + +__asm("U3CON1 equ 02D2h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U3SENDB :1; + unsigned U3BRKOVR :1; + unsigned :1; + unsigned U3RXBIMD :1; + unsigned U3WUE :1; + unsigned :2; + unsigned U3ON :1; + }; +} U3CON1bits_t; +extern volatile U3CON1bits_t U3CON1bits __attribute__((address(0x2D2))); +# 33956 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3CON2 __attribute__((address(0x2D3))); + +__asm("U3CON2 equ 02D3h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U3FLO :2; + unsigned U3TXPOL :1; + unsigned :1; + unsigned U3STP :2; + unsigned U3RXPOL :1; + unsigned U3RUNOVF :1; + }; + struct { + unsigned U3FLO0 :1; + unsigned U3FLO1 :1; + unsigned :2; + unsigned U3STP0 :1; + unsigned U3STP1 :1; + }; +} U3CON2bits_t; +extern volatile U3CON2bits_t U3CON2bits __attribute__((address(0x2D3))); +# 34088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U3BRG __attribute__((address(0x2D4))); + +__asm("U3BRG equ 02D4h"); + + + + +extern volatile unsigned char U3BRGL __attribute__((address(0x2D4))); + +__asm("U3BRGL equ 02D4h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U3BRGLbits_t; +extern volatile U3BRGLbits_t U3BRGLbits __attribute__((address(0x2D4))); +# 34115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3BRGH __attribute__((address(0x2D5))); + +__asm("U3BRGH equ 02D5h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U3BRGHbits_t; +extern volatile U3BRGHbits_t U3BRGHbits __attribute__((address(0x2D5))); +# 34135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3FIFO __attribute__((address(0x2D6))); + +__asm("U3FIFO equ 02D6h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U3RXBF :1; + unsigned U3RXBE :1; + unsigned U3XON :1; + unsigned U3RXIDL :1; + unsigned U3TXBF :1; + unsigned U3TXBE :1; + unsigned U3STPMD :1; + unsigned U3TXWRE :1; + }; + struct { + unsigned :3; + unsigned U3RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U3FIFObits_t; +extern volatile U3FIFObits_t U3FIFObits __attribute__((address(0x2D6))); +# 34265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3UIR __attribute__((address(0x2D7))); + +__asm("U3UIR equ 02D7h"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U3ABDIE :1; + unsigned :3; + unsigned U3ABDIF :1; + unsigned U3WUIF :1; + }; +} U3UIRbits_t; +extern volatile U3UIRbits_t U3UIRbits __attribute__((address(0x2D7))); +# 34321 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIR __attribute__((address(0x2D8))); + +__asm("U3ERRIR equ 02D8h"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U3TXCIF :1; + unsigned U3RXFOIF :1; + unsigned U3RXBKIF :1; + unsigned U3FERIF :1; + unsigned U3CERIF :1; + unsigned U3ABDOVF :1; + unsigned U3PERIF :1; + unsigned U3TXMTIF :1; + }; +} U3ERRIRbits_t; +extern volatile U3ERRIRbits_t U3ERRIRbits __attribute__((address(0x2D8))); +# 34433 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U3ERRIE __attribute__((address(0x2D9))); + +__asm("U3ERRIE equ 02D9h"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U3TXCIE :1; + unsigned U3RXFOIE :1; + unsigned U3RXBKIE :1; + unsigned U3FERIE :1; + unsigned U3CERIE :1; + unsigned U3ABDOVE :1; + unsigned U3PERIE :1; + unsigned U3TXMTIE :1; + }; +} U3ERRIEbits_t; +extern volatile U3ERRIEbits_t U3ERRIEbits __attribute__((address(0x2D9))); +# 34545 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4RXB __attribute__((address(0x2DA))); + +__asm("U4RXB equ 02DAh"); + + +extern volatile unsigned char U4RXBL __attribute__((address(0x2DA))); + +__asm("U4RXBL equ 02DAh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBbits_t; +extern volatile U4RXBbits_t U4RXBbits __attribute__((address(0x2DA))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U4RXBLbits_t; +extern volatile U4RXBLbits_t U4RXBLbits __attribute__((address(0x2DA))); +# 34583 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4TXB __attribute__((address(0x2DC))); + +__asm("U4TXB equ 02DCh"); + + +extern volatile unsigned char U4TXBL __attribute__((address(0x2DC))); + +__asm("U4TXBL equ 02DCh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBbits_t; +extern volatile U4TXBbits_t U4TXBbits __attribute__((address(0x2DC))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U4TXBLbits_t; +extern volatile U4TXBLbits_t U4TXBLbits __attribute__((address(0x2DC))); +# 34621 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P1 __attribute__((address(0x2DE))); + +__asm("U4P1 equ 02DEh"); + + + + +extern volatile unsigned char U4P1L __attribute__((address(0x2DE))); + +__asm("U4P1L equ 02DEh"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U4P1Lbits_t; +extern volatile U4P1Lbits_t U4P1Lbits __attribute__((address(0x2DE))); +# 34648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P2 __attribute__((address(0x2E0))); + +__asm("U4P2 equ 02E0h"); + + + + +extern volatile unsigned char U4P2L __attribute__((address(0x2E0))); + +__asm("U4P2L equ 02E0h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U4P2Lbits_t; +extern volatile U4P2Lbits_t U4P2Lbits __attribute__((address(0x2E0))); +# 34675 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4P3 __attribute__((address(0x2E2))); + +__asm("U4P3 equ 02E2h"); + + + + +extern volatile unsigned char U4P3L __attribute__((address(0x2E2))); + +__asm("U4P3L equ 02E2h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U4P3Lbits_t; +extern volatile U4P3Lbits_t U4P3Lbits __attribute__((address(0x2E2))); +# 34702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON0 __attribute__((address(0x2E4))); + +__asm("U4CON0 equ 02E4h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U4MODE :4; + unsigned U4RXEN :1; + unsigned U4TXEN :1; + unsigned U4ABDEN :1; + unsigned U4BRGS :1; + }; + struct { + unsigned U4MODE0 :1; + unsigned U4MODE1 :1; + unsigned U4MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U4CON0bits_t; +extern volatile U4CON0bits_t U4CON0bits __attribute__((address(0x2E4))); +# 34818 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON1 __attribute__((address(0x2E5))); + +__asm("U4CON1 equ 02E5h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U4SENDB :1; + unsigned U4BRKOVR :1; + unsigned :1; + unsigned U4RXBIMD :1; + unsigned U4WUE :1; + unsigned :2; + unsigned U4ON :1; + }; +} U4CON1bits_t; +extern volatile U4CON1bits_t U4CON1bits __attribute__((address(0x2E5))); +# 34898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4CON2 __attribute__((address(0x2E6))); + +__asm("U4CON2 equ 02E6h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U4FLO :2; + unsigned U4TXPOL :1; + unsigned :1; + unsigned U4STP :2; + unsigned U4RXPOL :1; + unsigned U4RUNOVF :1; + }; + struct { + unsigned U4FLO0 :1; + unsigned U4FLO1 :1; + unsigned :2; + unsigned U4STP0 :1; + unsigned U4STP1 :1; + }; +} U4CON2bits_t; +extern volatile U4CON2bits_t U4CON2bits __attribute__((address(0x2E6))); +# 35030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U4BRG __attribute__((address(0x2E7))); + +__asm("U4BRG equ 02E7h"); + + + + +extern volatile unsigned char U4BRGL __attribute__((address(0x2E7))); + +__asm("U4BRGL equ 02E7h"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U4BRGLbits_t; +extern volatile U4BRGLbits_t U4BRGLbits __attribute__((address(0x2E7))); +# 35057 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4BRGH __attribute__((address(0x2E8))); + +__asm("U4BRGH equ 02E8h"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U4BRGHbits_t; +extern volatile U4BRGHbits_t U4BRGHbits __attribute__((address(0x2E8))); +# 35077 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4FIFO __attribute__((address(0x2E9))); + +__asm("U4FIFO equ 02E9h"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U4RXBF :1; + unsigned U4RXBE :1; + unsigned U4XON :1; + unsigned U4RXIDL :1; + unsigned U4TXBF :1; + unsigned U4TXBE :1; + unsigned U4STPMD :1; + unsigned U4TXWRE :1; + }; + struct { + unsigned :3; + unsigned U4RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U4FIFObits_t; +extern volatile U4FIFObits_t U4FIFObits __attribute__((address(0x2E9))); +# 35207 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4UIR __attribute__((address(0x2EA))); + +__asm("U4UIR equ 02EAh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U4ABDIE :1; + unsigned :3; + unsigned U4ABDIF :1; + unsigned U4WUIF :1; + }; +} U4UIRbits_t; +extern volatile U4UIRbits_t U4UIRbits __attribute__((address(0x2EA))); +# 35263 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIR __attribute__((address(0x2EB))); + +__asm("U4ERRIR equ 02EBh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U4TXCIF :1; + unsigned U4RXFOIF :1; + unsigned U4RXBKIF :1; + unsigned U4FERIF :1; + unsigned U4CERIF :1; + unsigned U4ABDOVF :1; + unsigned U4PERIF :1; + unsigned U4TXMTIF :1; + }; +} U4ERRIRbits_t; +extern volatile U4ERRIRbits_t U4ERRIRbits __attribute__((address(0x2EB))); +# 35375 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U4ERRIE __attribute__((address(0x2EC))); + +__asm("U4ERRIE equ 02ECh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U4TXCIE :1; + unsigned U4RXFOIE :1; + unsigned U4RXBKIE :1; + unsigned U4FERIE :1; + unsigned U4CERIE :1; + unsigned U4ABDOVE :1; + unsigned U4PERIE :1; + unsigned U4TXMTIE :1; + }; +} U4ERRIEbits_t; +extern volatile U4ERRIEbits_t U4ERRIEbits __attribute__((address(0x2EC))); +# 35487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5RXB __attribute__((address(0x2ED))); + +__asm("U5RXB equ 02EDh"); + + +extern volatile unsigned char U5RXBL __attribute__((address(0x2ED))); + +__asm("U5RXBL equ 02EDh"); + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBbits_t; +extern volatile U5RXBbits_t U5RXBbits __attribute__((address(0x2ED))); + + + + + + + +typedef union { + struct { + unsigned RXB :8; + }; +} U5RXBLbits_t; +extern volatile U5RXBLbits_t U5RXBLbits __attribute__((address(0x2ED))); +# 35525 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5TXB __attribute__((address(0x2EF))); + +__asm("U5TXB equ 02EFh"); + + +extern volatile unsigned char U5TXBL __attribute__((address(0x2EF))); + +__asm("U5TXBL equ 02EFh"); + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBbits_t; +extern volatile U5TXBbits_t U5TXBbits __attribute__((address(0x2EF))); + + + + + + + +typedef union { + struct { + unsigned TXB :8; + }; +} U5TXBLbits_t; +extern volatile U5TXBLbits_t U5TXBLbits __attribute__((address(0x2EF))); +# 35563 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P1 __attribute__((address(0x2F1))); + +__asm("U5P1 equ 02F1h"); + + + + +extern volatile unsigned char U5P1L __attribute__((address(0x2F1))); + +__asm("U5P1L equ 02F1h"); + + +typedef union { + struct { + unsigned P1L :8; + }; +} U5P1Lbits_t; +extern volatile U5P1Lbits_t U5P1Lbits __attribute__((address(0x2F1))); +# 35590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P2 __attribute__((address(0x2F3))); + +__asm("U5P2 equ 02F3h"); + + + + +extern volatile unsigned char U5P2L __attribute__((address(0x2F3))); + +__asm("U5P2L equ 02F3h"); + + +typedef union { + struct { + unsigned P2L :8; + }; +} U5P2Lbits_t; +extern volatile U5P2Lbits_t U5P2Lbits __attribute__((address(0x2F3))); +# 35617 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5P3 __attribute__((address(0x2F5))); + +__asm("U5P3 equ 02F5h"); + + + + +extern volatile unsigned char U5P3L __attribute__((address(0x2F5))); + +__asm("U5P3L equ 02F5h"); + + +typedef union { + struct { + unsigned P3L :8; + }; +} U5P3Lbits_t; +extern volatile U5P3Lbits_t U5P3Lbits __attribute__((address(0x2F5))); +# 35644 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON0 __attribute__((address(0x2F7))); + +__asm("U5CON0 equ 02F7h"); + + +typedef union { + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; + struct { + unsigned U5MODE :4; + unsigned U5RXEN :1; + unsigned U5TXEN :1; + unsigned U5ABDEN :1; + unsigned U5BRGS :1; + }; + struct { + unsigned U5MODE0 :1; + unsigned U5MODE1 :1; + unsigned U5MODE2 :1; + }; + struct { + unsigned MODE :4; + unsigned RXEN :1; + unsigned TXEN :1; + unsigned ABDEN :1; + unsigned BRGS :1; + }; +} U5CON0bits_t; +extern volatile U5CON0bits_t U5CON0bits __attribute__((address(0x2F7))); +# 35760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON1 __attribute__((address(0x2F8))); + +__asm("U5CON1 equ 02F8h"); + + +typedef union { + struct { + unsigned SENDB :1; + unsigned BRKOVR :1; + unsigned :1; + unsigned RXBIMD :1; + unsigned WUE :1; + unsigned :2; + unsigned ON :1; + }; + struct { + unsigned U5SENDB :1; + unsigned U5BRKOVR :1; + unsigned :1; + unsigned U5RXBIMD :1; + unsigned U5WUE :1; + unsigned :2; + unsigned U5ON :1; + }; +} U5CON1bits_t; +extern volatile U5CON1bits_t U5CON1bits __attribute__((address(0x2F8))); +# 35840 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5CON2 __attribute__((address(0x2F9))); + +__asm("U5CON2 equ 02F9h"); + + +typedef union { + struct { + unsigned FLO :2; + unsigned TXPOL :1; + unsigned :1; + unsigned STP :2; + unsigned RXPOL :1; + unsigned RUNOVF :1; + }; + struct { + unsigned FLO0 :1; + unsigned FLO1 :1; + unsigned :2; + unsigned STP0 :1; + unsigned STP1 :1; + }; + struct { + unsigned U5FLO :2; + unsigned U5TXPOL :1; + unsigned :1; + unsigned U5STP :2; + unsigned U5RXPOL :1; + unsigned U5RUNOVF :1; + }; + struct { + unsigned U5FLO0 :1; + unsigned U5FLO1 :1; + unsigned :2; + unsigned U5STP0 :1; + unsigned U5STP1 :1; + }; +} U5CON2bits_t; +extern volatile U5CON2bits_t U5CON2bits __attribute__((address(0x2F9))); +# 35972 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short U5BRG __attribute__((address(0x2FA))); + +__asm("U5BRG equ 02FAh"); + + + + +extern volatile unsigned char U5BRGL __attribute__((address(0x2FA))); + +__asm("U5BRGL equ 02FAh"); + + +typedef union { + struct { + unsigned BRGL :8; + }; +} U5BRGLbits_t; +extern volatile U5BRGLbits_t U5BRGLbits __attribute__((address(0x2FA))); +# 35999 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5BRGH __attribute__((address(0x2FB))); + +__asm("U5BRGH equ 02FBh"); + + +typedef union { + struct { + unsigned BRGH :8; + }; +} U5BRGHbits_t; +extern volatile U5BRGHbits_t U5BRGHbits __attribute__((address(0x2FB))); +# 36019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5FIFO __attribute__((address(0x2FC))); + +__asm("U5FIFO equ 02FCh"); + + +typedef union { + struct { + unsigned RXBF :1; + unsigned RXBE :1; + unsigned XON :1; + unsigned RXIDL :1; + unsigned TXBF :1; + unsigned TXBE :1; + unsigned STPMD :1; + unsigned TXWRE :1; + }; + struct { + unsigned U5RXBF :1; + unsigned U5RXBE :1; + unsigned U5XON :1; + unsigned U5RXIDL :1; + unsigned U5TXBF :1; + unsigned U5TXBE :1; + unsigned U5STPMD :1; + unsigned U5TXWRE :1; + }; + struct { + unsigned :3; + unsigned U5RCIDL :1; + }; + struct { + unsigned :3; + unsigned RCIDL :1; + }; +} U5FIFObits_t; +extern volatile U5FIFObits_t U5FIFObits __attribute__((address(0x2FC))); +# 36149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5UIR __attribute__((address(0x2FD))); + +__asm("U5UIR equ 02FDh"); + + +typedef union { + struct { + unsigned :2; + unsigned ABDIE :1; + unsigned :3; + unsigned ABDIF :1; + unsigned WUIF :1; + }; + struct { + unsigned :2; + unsigned U5ABDIE :1; + unsigned :3; + unsigned U5ABDIF :1; + unsigned U5WUIF :1; + }; +} U5UIRbits_t; +extern volatile U5UIRbits_t U5UIRbits __attribute__((address(0x2FD))); +# 36205 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIR __attribute__((address(0x2FE))); + +__asm("U5ERRIR equ 02FEh"); + + +typedef union { + struct { + unsigned TXCIF :1; + unsigned RXFOIF :1; + unsigned RXBKIF :1; + unsigned FERIF :1; + unsigned CERIF :1; + unsigned ABDOVF :1; + unsigned PERIF :1; + unsigned TXMTIF :1; + }; + struct { + unsigned U5TXCIF :1; + unsigned U5RXFOIF :1; + unsigned U5RXBKIF :1; + unsigned U5FERIF :1; + unsigned U5CERIF :1; + unsigned U5ABDOVF :1; + unsigned U5PERIF :1; + unsigned U5TXMTIF :1; + }; +} U5ERRIRbits_t; +extern volatile U5ERRIRbits_t U5ERRIRbits __attribute__((address(0x2FE))); +# 36317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char U5ERRIE __attribute__((address(0x2FF))); + +__asm("U5ERRIE equ 02FFh"); + + +typedef union { + struct { + unsigned TXCIE :1; + unsigned RXFOIE :1; + unsigned RXBKIE :1; + unsigned FERIE :1; + unsigned CERIE :1; + unsigned ABDOVE :1; + unsigned PERIE :1; + unsigned TXMTIE :1; + }; + struct { + unsigned U5TXCIE :1; + unsigned U5RXFOIE :1; + unsigned U5RXBKIE :1; + unsigned U5FERIE :1; + unsigned U5CERIE :1; + unsigned U5ABDOVE :1; + unsigned U5PERIE :1; + unsigned U5TXMTIE :1; + }; +} U5ERRIEbits_t; +extern volatile U5ERRIEbits_t U5ERRIEbits __attribute__((address(0x2FF))); +# 36430 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1TMR __attribute__((address(0x300))); + + +__asm("SMT1TMR equ 0300h"); + + + + +extern volatile unsigned char SMT1TMRL __attribute__((address(0x300))); + +__asm("SMT1TMRL equ 0300h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR0 :1; + unsigned TMR1 :1; + unsigned TMR2 :1; + unsigned TMR3 :1; + unsigned TMR4 :1; + unsigned TMR5 :1; + unsigned TMR6 :1; + unsigned TMR7 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR0 :1; + unsigned SMT1TMR1 :1; + unsigned SMT1TMR2 :1; + unsigned SMT1TMR3 :1; + unsigned SMT1TMR4 :1; + unsigned SMT1TMR5 :1; + unsigned SMT1TMR6 :1; + unsigned SMT1TMR7 :1; + }; +} SMT1TMRLbits_t; +extern volatile SMT1TMRLbits_t SMT1TMRLbits __attribute__((address(0x300))); +# 36566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRH __attribute__((address(0x301))); + +__asm("SMT1TMRH equ 0301h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR8 :1; + unsigned TMR9 :1; + unsigned TMR10 :1; + unsigned TMR11 :1; + unsigned TMR12 :1; + unsigned TMR13 :1; + unsigned TMR14 :1; + unsigned TMR15 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR8 :1; + unsigned SMT1TMR9 :1; + unsigned SMT1TMR10 :1; + unsigned SMT1TMR11 :1; + unsigned SMT1TMR12 :1; + unsigned SMT1TMR13 :1; + unsigned SMT1TMR14 :1; + unsigned SMT1TMR15 :1; + }; +} SMT1TMRHbits_t; +extern volatile SMT1TMRHbits_t SMT1TMRHbits __attribute__((address(0x301))); +# 36694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1TMRU __attribute__((address(0x302))); + +__asm("SMT1TMRU equ 0302h"); + + +typedef union { + struct { + unsigned TMR :8; + }; + struct { + unsigned TMR16 :1; + unsigned TMR17 :1; + unsigned TMR18 :1; + unsigned TMR19 :1; + unsigned TMR20 :1; + unsigned TMR21 :1; + unsigned TMR22 :1; + unsigned TMR23 :1; + }; + struct { + unsigned SMT1TMR :8; + }; + struct { + unsigned SMT1TMR16 :1; + unsigned SMT1TMR17 :1; + unsigned SMT1TMR18 :1; + unsigned SMT1TMR19 :1; + unsigned SMT1TMR20 :1; + unsigned SMT1TMR21 :1; + unsigned SMT1TMR22 :1; + unsigned SMT1TMR23 :1; + }; +} SMT1TMRUbits_t; +extern volatile SMT1TMRUbits_t SMT1TMRUbits __attribute__((address(0x302))); +# 36823 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPR __attribute__((address(0x303))); + + +__asm("SMT1CPR equ 0303h"); + + + + +extern volatile unsigned char SMT1CPRL __attribute__((address(0x303))); + +__asm("SMT1CPRL equ 0303h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR0 :1; + unsigned CPR1 :1; + unsigned CPR2 :1; + unsigned CPR3 :1; + unsigned CPR4 :1; + unsigned CPR5 :1; + unsigned CPR6 :1; + unsigned CPR7 :1; + }; + struct { + unsigned SMT1CPR :8; + }; + struct { + unsigned SMT1CPR0 :1; + unsigned SMT1CPR1 :1; + unsigned SMT1CPR2 :1; + unsigned SMT1CPR3 :1; + unsigned SMT1CPR4 :1; + unsigned SMT1CPR5 :1; + unsigned SMT1CPR6 :1; + unsigned SMT1CPR7 :1; + }; +} SMT1CPRLbits_t; +extern volatile SMT1CPRLbits_t SMT1CPRLbits __attribute__((address(0x303))); +# 36959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRH __attribute__((address(0x304))); + +__asm("SMT1CPRH equ 0304h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR8 :1; + unsigned CPR9 :1; + unsigned CPR10 :1; + unsigned CPR11 :1; + unsigned CPR12 :1; + unsigned CPR13 :1; + unsigned CPR14 :1; + unsigned CPR15 :1; + }; + struct { + unsigned SMT1CPR8 :1; + unsigned SMT1CPR9 :1; + unsigned SMT1CPR10 :1; + unsigned SMT1CPR11 :1; + unsigned SMT1CPR12 :1; + unsigned SMT1CPR13 :1; + unsigned SMT1CPR14 :1; + unsigned SMT1CPR15 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRHbits_t; +extern volatile SMT1CPRHbits_t SMT1CPRHbits __attribute__((address(0x304))); +# 37087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPRU __attribute__((address(0x305))); + +__asm("SMT1CPRU equ 0305h"); + + +typedef union { + struct { + unsigned CPR :8; + }; + struct { + unsigned CPR16 :1; + unsigned CPR17 :1; + unsigned CPR18 :1; + unsigned CPR19 :1; + unsigned CPR20 :1; + unsigned CPR21 :1; + unsigned CPR22 :1; + unsigned CPR23 :1; + }; + struct { + unsigned SMT1CPR16 :1; + unsigned SMT1CPR17 :1; + unsigned SMT1CPR18 :1; + unsigned SMT1CPR19 :1; + unsigned SMT1CPR20 :1; + unsigned SMT1CPR21 :1; + unsigned SMT1CPR22 :1; + unsigned SMT1CPR23 :1; + }; + struct { + unsigned SMT1CPR :8; + }; +} SMT1CPRUbits_t; +extern volatile SMT1CPRUbits_t SMT1CPRUbits __attribute__((address(0x305))); +# 37216 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1CPW __attribute__((address(0x306))); + + +__asm("SMT1CPW equ 0306h"); + + + + +extern volatile unsigned char SMT1CPWL __attribute__((address(0x306))); + +__asm("SMT1CPWL equ 0306h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW0 :1; + unsigned CPW1 :1; + unsigned CPW2 :1; + unsigned CPW3 :1; + unsigned CPW4 :1; + unsigned CPW5 :1; + unsigned CPW6 :1; + unsigned CPW7 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW0 :1; + unsigned SMT1CPW1 :1; + unsigned SMT1CPW2 :1; + unsigned SMT1CPW3 :1; + unsigned SMT1CPW4 :1; + unsigned SMT1CPW5 :1; + unsigned SMT1CPW6 :1; + unsigned SMT1CPW7 :1; + }; +} SMT1CPWLbits_t; +extern volatile SMT1CPWLbits_t SMT1CPWLbits __attribute__((address(0x306))); +# 37352 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWH __attribute__((address(0x307))); + +__asm("SMT1CPWH equ 0307h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW8 :1; + unsigned CPW9 :1; + unsigned CPW10 :1; + unsigned CPW11 :1; + unsigned CPW12 :1; + unsigned CPW13 :1; + unsigned CPW14 :1; + unsigned CPW15 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW8 :1; + unsigned SMT1CPW9 :1; + unsigned SMT1CPW10 :1; + unsigned SMT1CPW11 :1; + unsigned SMT1CPW12 :1; + unsigned SMT1CPW13 :1; + unsigned SMT1CPW14 :1; + unsigned SMT1CPW15 :1; + }; +} SMT1CPWHbits_t; +extern volatile SMT1CPWHbits_t SMT1CPWHbits __attribute__((address(0x307))); +# 37480 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CPWU __attribute__((address(0x308))); + +__asm("SMT1CPWU equ 0308h"); + + +typedef union { + struct { + unsigned CPW :8; + }; + struct { + unsigned CPW16 :1; + unsigned CPW17 :1; + unsigned CPW18 :1; + unsigned CPW19 :1; + unsigned CPW20 :1; + unsigned CPW21 :1; + unsigned CPW22 :1; + unsigned CPW23 :1; + }; + struct { + unsigned SMT1CPW :8; + }; + struct { + unsigned SMT1CPW16 :1; + unsigned SMT1CPW17 :1; + unsigned SMT1CPW18 :1; + unsigned SMT1CPW19 :1; + unsigned SMT1CPW20 :1; + unsigned SMT1CPW21 :1; + unsigned SMT1CPW22 :1; + unsigned SMT1CPW23 :1; + }; +} SMT1CPWUbits_t; +extern volatile SMT1CPWUbits_t SMT1CPWUbits __attribute__((address(0x308))); +# 37609 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SMT1PR __attribute__((address(0x309))); + + +__asm("SMT1PR equ 0309h"); + + + + +extern volatile unsigned char SMT1PRL __attribute__((address(0x309))); + +__asm("SMT1PRL equ 0309h"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR0 :1; + unsigned PR1 :1; + unsigned PR2 :1; + unsigned PR3 :1; + unsigned PR4 :1; + unsigned PR5 :1; + unsigned PR6 :1; + unsigned PR7 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR0 :1; + unsigned SMT1PR1 :1; + unsigned SMT1PR2 :1; + unsigned SMT1PR3 :1; + unsigned SMT1PR4 :1; + unsigned SMT1PR5 :1; + unsigned SMT1PR6 :1; + unsigned SMT1PR7 :1; + }; +} SMT1PRLbits_t; +extern volatile SMT1PRLbits_t SMT1PRLbits __attribute__((address(0x309))); +# 37745 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRH __attribute__((address(0x30A))); + +__asm("SMT1PRH equ 030Ah"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR8 :1; + unsigned PR9 :1; + unsigned PR10 :1; + unsigned PR11 :1; + unsigned PR12 :1; + unsigned PR13 :1; + unsigned PR14 :1; + unsigned PR15 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR8 :1; + unsigned SMT1PR9 :1; + unsigned SMT1PR10 :1; + unsigned SMT1PR11 :1; + unsigned SMT1PR12 :1; + unsigned SMT1PR13 :1; + unsigned SMT1PR14 :1; + unsigned SMT1PR15 :1; + }; +} SMT1PRHbits_t; +extern volatile SMT1PRHbits_t SMT1PRHbits __attribute__((address(0x30A))); +# 37873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1PRU __attribute__((address(0x30B))); + +__asm("SMT1PRU equ 030Bh"); + + +typedef union { + struct { + unsigned PR :8; + }; + struct { + unsigned PR16 :1; + unsigned PR17 :1; + unsigned PR18 :1; + unsigned PR19 :1; + unsigned PR20 :1; + unsigned PR21 :1; + unsigned PR22 :1; + unsigned PR23 :1; + }; + struct { + unsigned SMT1PR :8; + }; + struct { + unsigned SMT1PR16 :1; + unsigned SMT1PR17 :1; + unsigned SMT1PR18 :1; + unsigned SMT1PR19 :1; + unsigned SMT1PR20 :1; + unsigned SMT1PR21 :1; + unsigned SMT1PR22 :1; + unsigned SMT1PR23 :1; + }; +} SMT1PRUbits_t; +extern volatile SMT1PRUbits_t SMT1PRUbits __attribute__((address(0x30B))); +# 38001 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON0 __attribute__((address(0x30C))); + +__asm("SMT1CON0 equ 030Ch"); + + +typedef union { + struct { + unsigned PS :2; + unsigned CPOL :1; + unsigned SPOL :1; + unsigned WPOL :1; + unsigned STP :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned SMT1PS :2; + unsigned SMT1CPOL :1; + unsigned SMT1SPOL :1; + unsigned SMT1WOL :1; + unsigned SMT1STP :1; + unsigned :1; + unsigned SMT1EN :1; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + }; + struct { + unsigned SMT1PS0 :1; + unsigned SMT1PS1 :1; + }; +} SMT1CON0bits_t; +extern volatile SMT1CON0bits_t SMT1CON0bits __attribute__((address(0x30C))); +# 38119 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CON1 __attribute__((address(0x30D))); + +__asm("SMT1CON1 equ 030Dh"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned :2; + unsigned REPEAT :1; + unsigned GO :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned :2; + unsigned SMT1REPEAT :1; + unsigned SMT1GO :1; + }; + struct { + unsigned SMT1MODE :4; + }; +} SMT1CON1bits_t; +extern volatile SMT1CON1bits_t SMT1CON1bits __attribute__((address(0x30D))); +# 38199 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1STAT __attribute__((address(0x30E))); + +__asm("SMT1STAT equ 030Eh"); + + +typedef union { + struct { + unsigned AS :1; + unsigned WS :1; + unsigned TS :1; + unsigned :2; + unsigned RST :1; + unsigned CPWUP :1; + unsigned CPRUP :1; + }; + struct { + unsigned SMT1AS :1; + unsigned SMT1WS :1; + unsigned SMT1TS :1; + unsigned :2; + unsigned SMT1RESET :1; + unsigned SMT1CPWUP :1; + unsigned SMT1CPRUP :1; + }; + struct { + unsigned :5; + unsigned SMT1RST :1; + }; +} SMT1STATbits_t; +extern volatile SMT1STATbits_t SMT1STATbits __attribute__((address(0x30E))); +# 38298 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1CLK __attribute__((address(0x30F))); + +__asm("SMT1CLK equ 030Fh"); + + +typedef union { + struct { + unsigned CSEL :3; + }; + struct { + unsigned CSEL0 :1; + unsigned CSEL1 :1; + unsigned CSEL2 :1; + }; + struct { + unsigned SMT1CSEL :3; + }; + struct { + unsigned SMT1CSEL0 :1; + unsigned SMT1CSEL1 :1; + unsigned SMT1CSEL2 :1; + }; +} SMT1CLKbits_t; +extern volatile SMT1CLKbits_t SMT1CLKbits __attribute__((address(0x30F))); +# 38366 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1SIG __attribute__((address(0x310))); + +__asm("SMT1SIG equ 0310h"); + + +typedef union { + struct { + unsigned SSEL :5; + }; + struct { + unsigned SSEL0 :1; + unsigned SSEL1 :1; + unsigned SSEL2 :1; + unsigned SSEL3 :1; + unsigned SSEL4 :1; + }; + struct { + unsigned SMT1SSEL :5; + }; + struct { + unsigned SMT1SSEL0 :1; + unsigned SMT1SSEL1 :1; + unsigned SMT1SSEL2 :1; + unsigned SMT1SSEL3 :1; + unsigned SMT1SSEL4 :1; + }; +} SMT1SIGbits_t; +extern volatile SMT1SIGbits_t SMT1SIGbits __attribute__((address(0x310))); +# 38458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SMT1WIN __attribute__((address(0x311))); + +__asm("SMT1WIN equ 0311h"); + + +typedef union { + struct { + unsigned WSEL :5; + }; + struct { + unsigned WSEL0 :1; + unsigned WSEL1 :1; + unsigned WSEL2 :1; + unsigned WSEL3 :1; + unsigned WSEL4 :1; + }; + struct { + unsigned SMT1WSEL :5; + }; + struct { + unsigned SMT1WSEL0 :1; + unsigned SMT1WSEL1 :1; + unsigned SMT1WSEL2 :1; + unsigned SMT1WSEL3 :1; + unsigned SMT1WSEL4 :1; + }; +} SMT1WINbits_t; +extern volatile SMT1WINbits_t SMT1WINbits __attribute__((address(0x311))); +# 38550 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0L __attribute__((address(0x318))); + +__asm("TMR0L equ 0318h"); + + +extern volatile unsigned char TMR0 __attribute__((address(0x318))); + +__asm("TMR0 equ 0318h"); + + +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0Lbits_t; +extern volatile TMR0Lbits_t TMR0Lbits __attribute__((address(0x318))); +# 38623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0L :8; + }; + struct { + unsigned TMR0L0 :1; + unsigned TMR0L1 :1; + unsigned TMR0L2 :1; + unsigned TMR0L3 :1; + unsigned TMR0L4 :1; + unsigned TMR0L5 :1; + unsigned TMR0L6 :1; + unsigned TMR0L7 :1; + }; +} TMR0bits_t; +extern volatile TMR0bits_t TMR0bits __attribute__((address(0x318))); +# 38688 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR0H __attribute__((address(0x319))); + +__asm("TMR0H equ 0319h"); + + +extern volatile unsigned char PR0 __attribute__((address(0x319))); + +__asm("PR0 equ 0319h"); + + +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} TMR0Hbits_t; +extern volatile TMR0Hbits_t TMR0Hbits __attribute__((address(0x319))); +# 38819 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned TMR0H :8; + }; + struct { + unsigned TMR0H0 :1; + unsigned TMR0H1 :1; + unsigned TMR0H2 :1; + unsigned TMR0H3 :1; + unsigned TMR0H4 :1; + unsigned TMR0H5 :1; + unsigned TMR0H6 :1; + unsigned TMR0H7 :1; + }; + struct { + unsigned T0PR0 :1; + unsigned T0PR1 :1; + unsigned T0PR2 :1; + unsigned T0PR3 :1; + unsigned T0PR4 :1; + unsigned T0PR5 :1; + unsigned T0PR6 :1; + unsigned T0PR7 :1; + }; + struct { + unsigned T0PR :8; + }; +} PR0bits_t; +extern volatile PR0bits_t PR0bits __attribute__((address(0x319))); +# 38942 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON0 __attribute__((address(0x31A))); + +__asm("T0CON0 equ 031Ah"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned MD16 :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned T0OUTPS :4; + unsigned T0MD16 :1; + unsigned T0OUT :1; + unsigned :1; + unsigned T0EN :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned T016BIT :1; + }; +} T0CON0bits_t; +extern volatile T0CON0bits_t T0CON0bits __attribute__((address(0x31A))); +# 39040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T0CON1 __attribute__((address(0x31B))); + +__asm("T0CON1 equ 031Bh"); + + +typedef union { + struct { + unsigned CKPS :4; + unsigned ASYNC :1; + unsigned CS :3; + }; + struct { + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned CKPS3 :1; + unsigned T0ASYNC :1; + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + }; + struct { + unsigned T0CKPS :4; + unsigned :1; + unsigned T0CS :3; + }; + struct { + unsigned T0CKPS0 :1; + unsigned T0CKPS1 :1; + unsigned T0CKPS2 :1; + unsigned T0CKPS3 :1; + unsigned :1; + unsigned T0CS0 :1; + unsigned T0CS1 :1; + unsigned T0CS2 :1; + }; +} T0CON1bits_t; +extern volatile T0CON1bits_t T0CON1bits __attribute__((address(0x31B))); +# 39182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1L __attribute__((address(0x31C))); + +__asm("TMR1L equ 031Ch"); + + +typedef union { + struct { + unsigned TMR1L :8; + }; + struct { + unsigned TMR1L0 :1; + unsigned TMR1L1 :1; + unsigned TMR1L2 :1; + unsigned TMR1L3 :1; + unsigned TMR1L4 :1; + unsigned TMR1L5 :1; + unsigned TMR1L6 :1; + unsigned TMR1L7 :1; + }; +} TMR1Lbits_t; +extern volatile TMR1Lbits_t TMR1Lbits __attribute__((address(0x31C))); +# 39252 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR1H __attribute__((address(0x31D))); + +__asm("TMR1H equ 031Dh"); + + +typedef union { + struct { + unsigned TMR1H :8; + }; + struct { + unsigned TMR1H0 :1; + unsigned TMR1H1 :1; + unsigned TMR1H2 :1; + unsigned TMR1H3 :1; + unsigned TMR1H4 :1; + unsigned TMR1H5 :1; + unsigned TMR1H6 :1; + unsigned TMR1H7 :1; + }; +} TMR1Hbits_t; +extern volatile TMR1Hbits_t TMR1Hbits __attribute__((address(0x31D))); +# 39322 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CON __attribute__((address(0x31E))); + +__asm("T1CON equ 031Eh"); + + +extern volatile unsigned char TMR1CON __attribute__((address(0x31E))); + +__asm("TMR1CON equ 031Eh"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} T1CONbits_t; +extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +# 39421 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR1ON :1; + unsigned T1RD16 :1; + unsigned NOT_T1SYNC :1; + unsigned :1; + unsigned T1CKPS0 :1; + unsigned T1CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD161 :1; + }; +} TMR1CONbits_t; +extern volatile TMR1CONbits_t TMR1CONbits __attribute__((address(0x31E))); +# 39512 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GCON __attribute__((address(0x31F))); + +__asm("T1GCON equ 031Fh"); + + +extern volatile unsigned char TMR1GCON __attribute__((address(0x31F))); + +__asm("TMR1GCON equ 031Fh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} T1GCONbits_t; +extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +# 39623 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T1GVAL :1; + unsigned T1GGO :1; + unsigned T1GSPM :1; + unsigned T1GTM :1; + unsigned T1GPOL :1; + unsigned T1GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T1DONE :1; + }; +} TMR1GCONbits_t; +extern volatile TMR1GCONbits_t TMR1GCONbits __attribute__((address(0x31F))); +# 39726 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1GATE __attribute__((address(0x320))); + +__asm("T1GATE equ 0320h"); + + +extern volatile unsigned char TMR1GATE __attribute__((address(0x320))); + +__asm("TMR1GATE equ 0320h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} T1GATEbits_t; +extern volatile T1GATEbits_t T1GATEbits __attribute__((address(0x320))); +# 39813 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T1GSS0 :1; + unsigned T1GSS1 :1; + unsigned T1GSS2 :1; + unsigned T1GSS3 :1; + unsigned T1GSS4 :1; + }; +} TMR1GATEbits_t; +extern volatile TMR1GATEbits_t TMR1GATEbits __attribute__((address(0x320))); +# 39892 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T1CLK __attribute__((address(0x321))); + +__asm("T1CLK equ 0321h"); + + +extern volatile unsigned char TMR1CLK __attribute__((address(0x321))); + +__asm("TMR1CLK equ 0321h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T1CLKbits_t; +extern volatile T1CLKbits_t T1CLKbits __attribute__((address(0x321))); +# 39979 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T1CS0 :1; + unsigned T1CS1 :1; + unsigned T1CS2 :1; + unsigned T1CS3 :1; + unsigned T1CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR1CLKbits_t; +extern volatile TMR1CLKbits_t TMR1CLKbits __attribute__((address(0x321))); +# 40058 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2TMR __attribute__((address(0x322))); + +__asm("T2TMR equ 0322h"); + + +extern volatile unsigned char TMR2 __attribute__((address(0x322))); + +__asm("TMR2 equ 0322h"); + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} T2TMRbits_t; +extern volatile T2TMRbits_t T2TMRbits __attribute__((address(0x322))); + + + + + + + +typedef union { + struct { + unsigned TMR2 :8; + }; +} TMR2bits_t; +extern volatile TMR2bits_t TMR2bits __attribute__((address(0x322))); +# 40096 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2PR __attribute__((address(0x323))); + +__asm("T2PR equ 0323h"); + + +extern volatile unsigned char PR2 __attribute__((address(0x323))); + +__asm("PR2 equ 0323h"); + + +typedef union { + struct { + unsigned PR2 :8; + }; +} T2PRbits_t; +extern volatile T2PRbits_t T2PRbits __attribute__((address(0x323))); + + + + + + + +typedef union { + struct { + unsigned PR2 :8; + }; +} PR2bits_t; +extern volatile PR2bits_t PR2bits __attribute__((address(0x323))); +# 40134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CON __attribute__((address(0x324))); + +__asm("T2CON equ 0324h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T2OUTPS :4; + unsigned T2CKPS :3; + unsigned T2ON :1; + }; + struct { + unsigned T2OUTPS0 :1; + unsigned T2OUTPS1 :1; + unsigned T2OUTPS2 :1; + unsigned T2OUTPS3 :1; + unsigned T2CKPS0 :1; + unsigned T2CKPS1 :1; + unsigned T2CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR2ON :1; + }; +} T2CONbits_t; +extern volatile T2CONbits_t T2CONbits __attribute__((address(0x324))); +# 40280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2HLT __attribute__((address(0x325))); + +__asm("T2HLT equ 0325h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T2MODE :5; + unsigned T2CKSYNC :1; + unsigned T2CKPOL :1; + unsigned T2PSYNC :1; + }; + struct { + unsigned T2MODE0 :1; + unsigned T2MODE1 :1; + unsigned T2MODE2 :1; + unsigned T2MODE3 :1; + unsigned T2MODE4 :1; + }; +} T2HLTbits_t; +extern volatile T2HLTbits_t T2HLTbits __attribute__((address(0x325))); +# 40408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2CLKCON __attribute__((address(0x326))); + +__asm("T2CLKCON equ 0326h"); + + +extern volatile unsigned char T2CLK __attribute__((address(0x326))); + +__asm("T2CLK equ 0326h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKCONbits_t; +extern volatile T2CLKCONbits_t T2CLKCONbits __attribute__((address(0x326))); +# 40491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T2CS :4; + }; + struct { + unsigned T2CS0 :1; + unsigned T2CS1 :1; + unsigned T2CS2 :1; + unsigned T2CS3 :1; + }; +} T2CLKbits_t; +extern volatile T2CLKbits_t T2CLKbits __attribute__((address(0x326))); +# 40566 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T2RST __attribute__((address(0x327))); + +__asm("T2RST equ 0327h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T2RSEL :5; + }; + struct { + unsigned T2RSEL0 :1; + unsigned T2RSEL1 :1; + unsigned T2RSEL2 :1; + unsigned T2RSEL3 :1; + unsigned T2RSEL4 :1; + }; +} T2RSTbits_t; +extern volatile T2RSTbits_t T2RSTbits __attribute__((address(0x327))); +# 40658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3L __attribute__((address(0x328))); + +__asm("TMR3L equ 0328h"); + + +typedef union { + struct { + unsigned TMR3L :8; + }; + struct { + unsigned TMR3L0 :1; + unsigned TMR3L1 :1; + unsigned TMR3L2 :1; + unsigned TMR3L3 :1; + unsigned TMR3L4 :1; + unsigned TMR3L5 :1; + unsigned TMR3L6 :1; + unsigned TMR3L7 :1; + }; +} TMR3Lbits_t; +extern volatile TMR3Lbits_t TMR3Lbits __attribute__((address(0x328))); +# 40728 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR3H __attribute__((address(0x329))); + +__asm("TMR3H equ 0329h"); + + +typedef union { + struct { + unsigned TMR3H :8; + }; + struct { + unsigned TMR3H0 :1; + unsigned TMR3H1 :1; + unsigned TMR3H2 :1; + unsigned TMR3H3 :1; + unsigned TMR3H4 :1; + unsigned TMR3H5 :1; + unsigned TMR3H6 :1; + unsigned TMR3H7 :1; + }; +} TMR3Hbits_t; +extern volatile TMR3Hbits_t TMR3Hbits __attribute__((address(0x329))); +# 40798 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CON __attribute__((address(0x32A))); + +__asm("T3CON equ 032Ah"); + + +extern volatile unsigned char TMR3CON __attribute__((address(0x32A))); + +__asm("TMR3CON equ 032Ah"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} T3CONbits_t; +extern volatile T3CONbits_t T3CONbits __attribute__((address(0x32A))); +# 40897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR3ON :1; + unsigned T3RD16 :1; + unsigned NOT_T3SYNC :1; + unsigned :1; + unsigned T3CKPS0 :1; + unsigned T3CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD163 :1; + }; +} TMR3CONbits_t; +extern volatile TMR3CONbits_t TMR3CONbits __attribute__((address(0x32A))); +# 40988 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GCON __attribute__((address(0x32B))); + +__asm("T3GCON equ 032Bh"); + + +extern volatile unsigned char TMR3GCON __attribute__((address(0x32B))); + +__asm("TMR3GCON equ 032Bh"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} T3GCONbits_t; +extern volatile T3GCONbits_t T3GCONbits __attribute__((address(0x32B))); +# 41099 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T3GVAL :1; + unsigned T3GGO :1; + unsigned T3GSPM :1; + unsigned T3GTM :1; + unsigned T3GPOL :1; + unsigned T3GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T3DONE :1; + }; +} TMR3GCONbits_t; +extern volatile TMR3GCONbits_t TMR3GCONbits __attribute__((address(0x32B))); +# 41202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3GATE __attribute__((address(0x32C))); + +__asm("T3GATE equ 032Ch"); + + +extern volatile unsigned char TMR3GATE __attribute__((address(0x32C))); + +__asm("TMR3GATE equ 032Ch"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} T3GATEbits_t; +extern volatile T3GATEbits_t T3GATEbits __attribute__((address(0x32C))); +# 41289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T3GSS0 :1; + unsigned T3GSS1 :1; + unsigned T3GSS2 :1; + unsigned T3GSS3 :1; + unsigned T3GSS4 :1; + }; +} TMR3GATEbits_t; +extern volatile TMR3GATEbits_t TMR3GATEbits __attribute__((address(0x32C))); +# 41368 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T3CLK __attribute__((address(0x32D))); + +__asm("T3CLK equ 032Dh"); + + +extern volatile unsigned char TMR3CLK __attribute__((address(0x32D))); + +__asm("TMR3CLK equ 032Dh"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T3CLKbits_t; +extern volatile T3CLKbits_t T3CLKbits __attribute__((address(0x32D))); +# 41455 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T3CS0 :1; + unsigned T3CS1 :1; + unsigned T3CS2 :1; + unsigned T3CS3 :1; + unsigned T3CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR3CLKbits_t; +extern volatile TMR3CLKbits_t TMR3CLKbits __attribute__((address(0x32D))); +# 41534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4TMR __attribute__((address(0x32E))); + +__asm("T4TMR equ 032Eh"); + + +extern volatile unsigned char TMR4 __attribute__((address(0x32E))); + +__asm("TMR4 equ 032Eh"); + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} T4TMRbits_t; +extern volatile T4TMRbits_t T4TMRbits __attribute__((address(0x32E))); + + + + + + + +typedef union { + struct { + unsigned TMR4 :8; + }; +} TMR4bits_t; +extern volatile TMR4bits_t TMR4bits __attribute__((address(0x32E))); +# 41572 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4PR __attribute__((address(0x32F))); + +__asm("T4PR equ 032Fh"); + + +extern volatile unsigned char PR4 __attribute__((address(0x32F))); + +__asm("PR4 equ 032Fh"); + + +typedef union { + struct { + unsigned PR4 :8; + }; +} T4PRbits_t; +extern volatile T4PRbits_t T4PRbits __attribute__((address(0x32F))); + + + + + + + +typedef union { + struct { + unsigned PR4 :8; + }; +} PR4bits_t; +extern volatile PR4bits_t PR4bits __attribute__((address(0x32F))); +# 41610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CON __attribute__((address(0x330))); + +__asm("T4CON equ 0330h"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T4OUTPS :4; + unsigned T4CKPS :3; + unsigned T4ON :1; + }; + struct { + unsigned T4OUTPS0 :1; + unsigned T4OUTPS1 :1; + unsigned T4OUTPS2 :1; + unsigned T4OUTPS3 :1; + unsigned T4CKPS0 :1; + unsigned T4CKPS1 :1; + unsigned T4CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR4ON :1; + }; +} T4CONbits_t; +extern volatile T4CONbits_t T4CONbits __attribute__((address(0x330))); +# 41756 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4HLT __attribute__((address(0x331))); + +__asm("T4HLT equ 0331h"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T4MODE :5; + unsigned T4CKSYNC :1; + unsigned T4CKPOL :1; + unsigned T4PSYNC :1; + }; + struct { + unsigned T4MODE0 :1; + unsigned T4MODE1 :1; + unsigned T4MODE2 :1; + unsigned T4MODE3 :1; + unsigned T4MODE4 :1; + }; +} T4HLTbits_t; +extern volatile T4HLTbits_t T4HLTbits __attribute__((address(0x331))); +# 41884 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4CLKCON __attribute__((address(0x332))); + +__asm("T4CLKCON equ 0332h"); + + +extern volatile unsigned char T4CLK __attribute__((address(0x332))); + +__asm("T4CLK equ 0332h"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKCONbits_t; +extern volatile T4CLKCONbits_t T4CLKCONbits __attribute__((address(0x332))); +# 41967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T4CS :4; + }; + struct { + unsigned T4CS0 :1; + unsigned T4CS1 :1; + unsigned T4CS2 :1; + unsigned T4CS3 :1; + }; +} T4CLKbits_t; +extern volatile T4CLKbits_t T4CLKbits __attribute__((address(0x332))); +# 42042 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T4RST __attribute__((address(0x333))); + +__asm("T4RST equ 0333h"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T4RSEL :5; + }; + struct { + unsigned T4RSEL0 :1; + unsigned T4RSEL1 :1; + unsigned T4RSEL2 :1; + unsigned T4RSEL3 :1; + unsigned T4RSEL4 :1; + }; +} T4RSTbits_t; +extern volatile T4RSTbits_t T4RSTbits __attribute__((address(0x333))); +# 42134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5L __attribute__((address(0x334))); + +__asm("TMR5L equ 0334h"); + + +typedef union { + struct { + unsigned TMR5L :8; + }; + struct { + unsigned TMR5L0 :1; + unsigned TMR5L1 :1; + unsigned TMR5L2 :1; + unsigned TMR5L3 :1; + unsigned TMR5L4 :1; + unsigned TMR5L5 :1; + unsigned TMR5L6 :1; + unsigned TMR5L7 :1; + }; +} TMR5Lbits_t; +extern volatile TMR5Lbits_t TMR5Lbits __attribute__((address(0x334))); +# 42204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TMR5H __attribute__((address(0x335))); + +__asm("TMR5H equ 0335h"); + + +typedef union { + struct { + unsigned TMR5H :8; + }; + struct { + unsigned TMR5H0 :1; + unsigned TMR5H1 :1; + unsigned TMR5H2 :1; + unsigned TMR5H3 :1; + unsigned TMR5H4 :1; + unsigned TMR5H5 :1; + unsigned TMR5H6 :1; + unsigned TMR5H7 :1; + }; +} TMR5Hbits_t; +extern volatile TMR5Hbits_t TMR5Hbits __attribute__((address(0x335))); +# 42274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CON __attribute__((address(0x336))); + +__asm("T5CON equ 0336h"); + + +extern volatile unsigned char TMR5CON __attribute__((address(0x336))); + +__asm("TMR5CON equ 0336h"); + + +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} T5CONbits_t; +extern volatile T5CONbits_t T5CONbits __attribute__((address(0x336))); +# 42373 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned ON :1; + unsigned RD16 :1; + unsigned NOT_SYNC :1; + unsigned :1; + unsigned CKPS :2; + }; + struct { + unsigned TMR5ON :1; + unsigned T5RD16 :1; + unsigned NOT_T5SYNC :1; + unsigned :1; + unsigned T5CKPS0 :1; + unsigned T5CKPS1 :1; + }; + struct { + unsigned :4; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + }; + struct { + unsigned :1; + unsigned RD165 :1; + }; +} TMR5CONbits_t; +extern volatile TMR5CONbits_t TMR5CONbits __attribute__((address(0x336))); +# 42464 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GCON __attribute__((address(0x337))); + +__asm("T5GCON equ 0337h"); + + +extern volatile unsigned char TMR5GCON __attribute__((address(0x337))); + +__asm("TMR5GCON equ 0337h"); + + +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} T5GCONbits_t; +extern volatile T5GCONbits_t T5GCONbits __attribute__((address(0x337))); +# 42575 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned :2; + unsigned GVAL :1; + unsigned GGO :1; + unsigned GSPM :1; + unsigned GTM :1; + unsigned GPOL :1; + unsigned GE :1; + }; + struct { + unsigned :2; + unsigned T5GVAL :1; + unsigned T5GGO :1; + unsigned T5GSPM :1; + unsigned T5GTM :1; + unsigned T5GPOL :1; + unsigned T5GE :1; + }; + struct { + unsigned :3; + unsigned NOT_DONE :1; + }; + struct { + unsigned :3; + unsigned NOT_T5DONE :1; + }; +} TMR5GCONbits_t; +extern volatile TMR5GCONbits_t TMR5GCONbits __attribute__((address(0x337))); +# 42678 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5GATE __attribute__((address(0x338))); + +__asm("T5GATE equ 0338h"); + + +extern volatile unsigned char TMR5GATE __attribute__((address(0x338))); + +__asm("TMR5GATE equ 0338h"); + + +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} T5GATEbits_t; +extern volatile T5GATEbits_t T5GATEbits __attribute__((address(0x338))); +# 42765 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned GSS :8; + }; + struct { + unsigned GSS0 :1; + unsigned GSS1 :1; + unsigned GSS2 :1; + unsigned GSS3 :1; + unsigned GSS4 :1; + }; + struct { + unsigned T5GSS0 :1; + unsigned T5GSS1 :1; + unsigned T5GSS2 :1; + unsigned T5GSS3 :1; + unsigned T5GSS4 :1; + }; +} TMR5GATEbits_t; +extern volatile TMR5GATEbits_t TMR5GATEbits __attribute__((address(0x338))); +# 42844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T5CLK __attribute__((address(0x339))); + +__asm("T5CLK equ 0339h"); + + +extern volatile unsigned char TMR5CLK __attribute__((address(0x339))); + +__asm("TMR5CLK equ 0339h"); + + +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} T5CLKbits_t; +extern volatile T5CLKbits_t T5CLKbits __attribute__((address(0x339))); +# 42931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :8; + }; + struct { + unsigned T5CS0 :1; + unsigned T5CS1 :1; + unsigned T5CS2 :1; + unsigned T5CS3 :1; + unsigned T5CS4 :1; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + }; +} TMR5CLKbits_t; +extern volatile TMR5CLKbits_t TMR5CLKbits __attribute__((address(0x339))); +# 43010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6TMR __attribute__((address(0x33A))); + +__asm("T6TMR equ 033Ah"); + + +extern volatile unsigned char TMR6 __attribute__((address(0x33A))); + +__asm("TMR6 equ 033Ah"); + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} T6TMRbits_t; +extern volatile T6TMRbits_t T6TMRbits __attribute__((address(0x33A))); + + + + + + + +typedef union { + struct { + unsigned TMR6 :8; + }; +} TMR6bits_t; +extern volatile TMR6bits_t TMR6bits __attribute__((address(0x33A))); +# 43048 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6PR __attribute__((address(0x33B))); + +__asm("T6PR equ 033Bh"); + + +extern volatile unsigned char PR6 __attribute__((address(0x33B))); + +__asm("PR6 equ 033Bh"); + + +typedef union { + struct { + unsigned PR6 :8; + }; +} T6PRbits_t; +extern volatile T6PRbits_t T6PRbits __attribute__((address(0x33B))); + + + + + + + +typedef union { + struct { + unsigned PR6 :8; + }; +} PR6bits_t; +extern volatile PR6bits_t PR6bits __attribute__((address(0x33B))); +# 43086 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CON __attribute__((address(0x33C))); + +__asm("T6CON equ 033Ch"); + + +typedef union { + struct { + unsigned OUTPS :4; + unsigned CKPS :3; + unsigned ON :1; + }; + struct { + unsigned T6OUTPS :4; + unsigned T6CKPS :3; + unsigned T6ON :1; + }; + struct { + unsigned T6OUTPS0 :1; + unsigned T6OUTPS1 :1; + unsigned T6OUTPS2 :1; + unsigned T6OUTPS3 :1; + unsigned T6CKPS0 :1; + unsigned T6CKPS1 :1; + unsigned T6CKPS2 :1; + }; + struct { + unsigned OUTPS0 :1; + unsigned OUTPS1 :1; + unsigned OUTPS2 :1; + unsigned OUTPS3 :1; + unsigned CKPS0 :1; + unsigned CKPS1 :1; + unsigned CKPS2 :1; + unsigned TMR6ON :1; + }; +} T6CONbits_t; +extern volatile T6CONbits_t T6CONbits __attribute__((address(0x33C))); +# 43232 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6HLT __attribute__((address(0x33D))); + +__asm("T6HLT equ 033Dh"); + + +typedef union { + struct { + unsigned MODE :5; + unsigned CKSYNC :1; + unsigned CKPOL :1; + unsigned PSYNC :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + unsigned MODE4 :1; + }; + struct { + unsigned T6MODE :5; + unsigned T6CKSYNC :1; + unsigned T6CKPOL :1; + unsigned T6PSYNC :1; + }; + struct { + unsigned T6MODE0 :1; + unsigned T6MODE1 :1; + unsigned T6MODE2 :1; + unsigned T6MODE3 :1; + unsigned T6MODE4 :1; + }; +} T6HLTbits_t; +extern volatile T6HLTbits_t T6HLTbits __attribute__((address(0x33D))); +# 43360 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6CLKCON __attribute__((address(0x33E))); + +__asm("T6CLKCON equ 033Eh"); + + +extern volatile unsigned char T6CLK __attribute__((address(0x33E))); + +__asm("T6CLK equ 033Eh"); + + +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKCONbits_t; +extern volatile T6CLKCONbits_t T6CLKCONbits __attribute__((address(0x33E))); +# 43443 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :4; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + }; + struct { + unsigned T6CS :4; + }; + struct { + unsigned T6CS0 :1; + unsigned T6CS1 :1; + unsigned T6CS2 :1; + unsigned T6CS3 :1; + }; +} T6CLKbits_t; +extern volatile T6CLKbits_t T6CLKbits __attribute__((address(0x33E))); +# 43518 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char T6RST __attribute__((address(0x33F))); + +__asm("T6RST equ 033Fh"); + + +typedef union { + struct { + unsigned RSEL :5; + }; + struct { + unsigned RSEL0 :1; + unsigned RSEL1 :1; + unsigned RSEL2 :1; + unsigned RSEL3 :1; + unsigned RSEL4 :1; + }; + struct { + unsigned T6RSEL :5; + }; + struct { + unsigned T6RSEL0 :1; + unsigned T6RSEL1 :1; + unsigned T6RSEL2 :1; + unsigned T6RSEL3 :1; + unsigned T6RSEL4 :1; + }; +} T6RSTbits_t; +extern volatile T6RSTbits_t T6RSTbits __attribute__((address(0x33F))); +# 43610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR1 __attribute__((address(0x340))); + +__asm("CCPR1 equ 0340h"); + + + + +extern volatile unsigned char CCPR1L __attribute__((address(0x340))); + +__asm("CCPR1L equ 0340h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR1Lbits_t; +extern volatile CCPR1Lbits_t CCPR1Lbits __attribute__((address(0x340))); +# 43637 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR1H __attribute__((address(0x341))); + +__asm("CCPR1H equ 0341h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR1Hbits_t; +extern volatile CCPR1Hbits_t CCPR1Hbits __attribute__((address(0x341))); +# 43657 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CON __attribute__((address(0x342))); + +__asm("CCP1CON equ 0342h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP1MODE :4; + unsigned CCP1FMT :1; + unsigned CCP1OUT :1; + unsigned :1; + unsigned CCP1EN :1; + }; + struct { + unsigned CCP1MODE0 :1; + unsigned CCP1MODE1 :1; + unsigned CCP1MODE2 :1; + unsigned CCP1MODE3 :1; + }; +} CCP1CONbits_t; +extern volatile CCP1CONbits_t CCP1CONbits __attribute__((address(0x342))); +# 43775 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP1CAP __attribute__((address(0x343))); + +__asm("CCP1CAP equ 0343h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP1CTS :8; + }; + struct { + unsigned CCP1CTS0 :1; + unsigned CCP1CTS1 :1; + unsigned CCP1CTS2 :1; + unsigned CCP1CTS3 :1; + }; +} CCP1CAPbits_t; +extern volatile CCP1CAPbits_t CCP1CAPbits __attribute__((address(0x343))); +# 43855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR2 __attribute__((address(0x344))); + +__asm("CCPR2 equ 0344h"); + + + + +extern volatile unsigned char CCPR2L __attribute__((address(0x344))); + +__asm("CCPR2L equ 0344h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR2Lbits_t; +extern volatile CCPR2Lbits_t CCPR2Lbits __attribute__((address(0x344))); +# 43882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR2H __attribute__((address(0x345))); + +__asm("CCPR2H equ 0345h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR2Hbits_t; +extern volatile CCPR2Hbits_t CCPR2Hbits __attribute__((address(0x345))); +# 43902 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CON __attribute__((address(0x346))); + +__asm("CCP2CON equ 0346h"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP2MODE :4; + unsigned CCP2FMT :1; + unsigned CCP2OUT :1; + unsigned :1; + unsigned CCP2EN :1; + }; + struct { + unsigned CCP2MODE0 :1; + unsigned CCP2MODE1 :1; + unsigned CCP2MODE2 :1; + unsigned CCP2MODE3 :1; + }; +} CCP2CONbits_t; +extern volatile CCP2CONbits_t CCP2CONbits __attribute__((address(0x346))); +# 44020 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP2CAP __attribute__((address(0x347))); + +__asm("CCP2CAP equ 0347h"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP2CTS :8; + }; + struct { + unsigned CCP2CTS0 :1; + unsigned CCP2CTS1 :1; + unsigned CCP2CTS2 :1; + unsigned CCP2CTS3 :1; + }; +} CCP2CAPbits_t; +extern volatile CCP2CAPbits_t CCP2CAPbits __attribute__((address(0x347))); +# 44100 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short CCPR3 __attribute__((address(0x348))); + +__asm("CCPR3 equ 0348h"); + + + + +extern volatile unsigned char CCPR3L __attribute__((address(0x348))); + +__asm("CCPR3L equ 0348h"); + + +typedef union { + struct { + unsigned RL :8; + }; +} CCPR3Lbits_t; +extern volatile CCPR3Lbits_t CCPR3Lbits __attribute__((address(0x348))); +# 44127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPR3H __attribute__((address(0x349))); + +__asm("CCPR3H equ 0349h"); + + +typedef union { + struct { + unsigned RH :8; + }; +} CCPR3Hbits_t; +extern volatile CCPR3Hbits_t CCPR3Hbits __attribute__((address(0x349))); +# 44147 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CON __attribute__((address(0x34A))); + +__asm("CCP3CON equ 034Ah"); + + +typedef union { + struct { + unsigned MODE :4; + unsigned FMT :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned MODE3 :1; + }; + struct { + unsigned CCP3MODE :4; + unsigned CCP3FMT :1; + unsigned CCP3OUT :1; + unsigned :1; + unsigned CCP3EN :1; + }; + struct { + unsigned CCP3MODE0 :1; + unsigned CCP3MODE1 :1; + unsigned CCP3MODE2 :1; + unsigned CCP3MODE3 :1; + }; +} CCP3CONbits_t; +extern volatile CCP3CONbits_t CCP3CONbits __attribute__((address(0x34A))); +# 44265 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCP3CAP __attribute__((address(0x34B))); + +__asm("CCP3CAP equ 034Bh"); + + +typedef union { + struct { + unsigned CTS :8; + }; + struct { + unsigned CTS0 :1; + unsigned CTS1 :1; + unsigned CTS2 :1; + unsigned CTS3 :1; + }; + struct { + unsigned CCP3CTS :8; + }; + struct { + unsigned CCP3CTS0 :1; + unsigned CCP3CTS1 :1; + unsigned CCP3CTS2 :1; + unsigned CCP3CTS3 :1; + }; +} CCP3CAPbits_t; +extern volatile CCP3CAPbits_t CCP3CAPbits __attribute__((address(0x34B))); +# 44345 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CCPTMRS0 __attribute__((address(0x34C))); + +__asm("CCPTMRS0 equ 034Ch"); + + +typedef union { + struct { + unsigned C1TSEL :2; + unsigned C2TSEL :2; + unsigned C3TSEL :2; + }; + struct { + unsigned C1TSEL0 :1; + unsigned C1TSEL1 :1; + unsigned C2TSEL0 :1; + unsigned C2TSEL1 :1; + unsigned C3TSEL0 :1; + unsigned C3TSEL1 :1; + }; +} CCPTMRS0bits_t; +extern volatile CCPTMRS0bits_t CCPTMRS0bits __attribute__((address(0x34C))); +# 44415 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCDATA __attribute__((address(0x34F))); + +__asm("CRCDATA equ 034Fh"); + + + + +extern volatile unsigned char CRCDATAL __attribute__((address(0x34F))); + +__asm("CRCDATAL equ 034Fh"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA0 :1; + unsigned DATA1 :1; + unsigned DATA2 :1; + unsigned DATA3 :1; + unsigned DATA4 :1; + unsigned DATA5 :1; + unsigned DATA6 :1; + unsigned DATA7 :1; + }; +} CRCDATALbits_t; +extern volatile CRCDATALbits_t CRCDATALbits __attribute__((address(0x34F))); +# 44492 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAH __attribute__((address(0x350))); + +__asm("CRCDATAH equ 0350h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA8 :1; + unsigned DATA9 :1; + unsigned DATA10 :1; + unsigned DATA11 :1; + unsigned DATA12 :1; + unsigned DATA13 :1; + unsigned DATA14 :1; + unsigned DATA15 :1; + }; +} CRCDATAHbits_t; +extern volatile CRCDATAHbits_t CRCDATAHbits __attribute__((address(0x350))); +# 44562 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAU __attribute__((address(0x351))); + +__asm("CRCDATAU equ 0351h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA16 :1; + unsigned DATA17 :1; + unsigned DATA18 :1; + unsigned DATA19 :1; + unsigned DATA20 :1; + unsigned DATA21 :1; + unsigned DATA22 :1; + unsigned DATA23 :1; + }; +} CRCDATAUbits_t; +extern volatile CRCDATAUbits_t CRCDATAUbits __attribute__((address(0x351))); +# 44632 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCDATAT __attribute__((address(0x352))); + +__asm("CRCDATAT equ 0352h"); + + +typedef union { + struct { + unsigned DATA :8; + }; + struct { + unsigned DATA24 :1; + unsigned DATA25 :1; + unsigned DATA26 :1; + unsigned DATA27 :1; + unsigned DATA28 :1; + unsigned DATA29 :1; + unsigned DATA30 :1; + unsigned DATA31 :1; + }; +} CRCDATATbits_t; +extern volatile CRCDATATbits_t CRCDATATbits __attribute__((address(0x352))); +# 44702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned long CRCOUT __attribute__((address(0x353))); + +__asm("CRCOUT equ 0353h"); + + +extern volatile unsigned long CRCSHFT __attribute__((address(0x353))); + +__asm("CRCSHFT equ 0353h"); + +extern volatile unsigned long CRCXOR __attribute__((address(0x353))); + +__asm("CRCXOR equ 0353h"); + + + + +extern volatile unsigned char CRCOUTL __attribute__((address(0x353))); + +__asm("CRCOUTL equ 0353h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT0 :1; + unsigned OUT1 :1; + unsigned OUT2 :1; + unsigned OUT3 :1; + unsigned OUT4 :1; + unsigned OUT5 :1; + unsigned OUT6 :1; + unsigned OUT7 :1; + }; +} CRCOUTLbits_t; +extern volatile CRCOUTLbits_t CRCOUTLbits __attribute__((address(0x353))); +# 44788 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTL __attribute__((address(0x353))); + +__asm("CRCSHFTL equ 0353h"); + + +extern volatile unsigned char CRCSHIFTL __attribute__((address(0x353))); + +__asm("CRCSHIFTL equ 0353h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHFTLbits_t; +extern volatile CRCSHFTLbits_t CRCSHFTLbits __attribute__((address(0x353))); +# 44861 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT0 :1; + unsigned SHIFT1 :1; + unsigned SHIFT2 :1; + unsigned SHIFT3 :1; + unsigned SHIFT4 :1; + unsigned SHIFT5 :1; + unsigned SHIFT6 :1; + unsigned SHIFT7 :1; + }; +} CRCSHIFTLbits_t; +extern volatile CRCSHIFTLbits_t CRCSHIFTLbits __attribute__((address(0x353))); +# 44926 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORL __attribute__((address(0x353))); + +__asm("CRCXORL equ 0353h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR0 :1; + unsigned XOR1 :1; + unsigned XOR2 :1; + unsigned XOR3 :1; + unsigned XOR4 :1; + unsigned XOR5 :1; + unsigned XOR6 :1; + unsigned XOR7 :1; + }; +} CRCXORLbits_t; +extern volatile CRCXORLbits_t CRCXORLbits __attribute__((address(0x353))); +# 44996 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTH __attribute__((address(0x354))); + +__asm("CRCOUTH equ 0354h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT8 :1; + unsigned OUT9 :1; + unsigned OUT10 :1; + unsigned OUT11 :1; + unsigned OUT12 :1; + unsigned OUT13 :1; + unsigned OUT14 :1; + unsigned OUT15 :1; + }; +} CRCOUTHbits_t; +extern volatile CRCOUTHbits_t CRCOUTHbits __attribute__((address(0x354))); +# 45066 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTH __attribute__((address(0x354))); + +__asm("CRCSHFTH equ 0354h"); + + +extern volatile unsigned char CRCSHIFTH __attribute__((address(0x354))); + +__asm("CRCSHIFTH equ 0354h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHFTHbits_t; +extern volatile CRCSHFTHbits_t CRCSHFTHbits __attribute__((address(0x354))); +# 45139 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT8 :1; + unsigned SHIFT9 :1; + unsigned SHIFT10 :1; + unsigned SHIFT11 :1; + unsigned SHIFT12 :1; + unsigned SHIFT13 :1; + unsigned SHIFT14 :1; + unsigned SHIFT15 :1; + }; +} CRCSHIFTHbits_t; +extern volatile CRCSHIFTHbits_t CRCSHIFTHbits __attribute__((address(0x354))); +# 45204 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORH __attribute__((address(0x354))); + +__asm("CRCXORH equ 0354h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR8 :1; + unsigned XOR9 :1; + unsigned XOR10 :1; + unsigned XOR11 :1; + unsigned XOR12 :1; + unsigned XOR13 :1; + unsigned XOR14 :1; + unsigned XOR15 :1; + }; +} CRCXORHbits_t; +extern volatile CRCXORHbits_t CRCXORHbits __attribute__((address(0x354))); +# 45274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTU __attribute__((address(0x355))); + +__asm("CRCOUTU equ 0355h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT16 :1; + unsigned OUT17 :1; + unsigned OUT18 :1; + unsigned OUT19 :1; + unsigned OUT20 :1; + unsigned OUT21 :1; + unsigned OUT22 :1; + unsigned OUT23 :1; + }; +} CRCOUTUbits_t; +extern volatile CRCOUTUbits_t CRCOUTUbits __attribute__((address(0x355))); +# 45344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTU __attribute__((address(0x355))); + +__asm("CRCSHFTU equ 0355h"); + + +extern volatile unsigned char CRCSHIFTU __attribute__((address(0x355))); + +__asm("CRCSHIFTU equ 0355h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHFTUbits_t; +extern volatile CRCSHFTUbits_t CRCSHFTUbits __attribute__((address(0x355))); +# 45417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT16 :1; + unsigned SHIFT17 :1; + unsigned SHIFT18 :1; + unsigned SHIFT19 :1; + unsigned SHIFT20 :1; + unsigned SHIFT21 :1; + unsigned SHIFT22 :1; + unsigned SHIFT23 :1; + }; +} CRCSHIFTUbits_t; +extern volatile CRCSHIFTUbits_t CRCSHIFTUbits __attribute__((address(0x355))); +# 45482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORU __attribute__((address(0x355))); + +__asm("CRCXORU equ 0355h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR16 :1; + unsigned XOR17 :1; + unsigned XOR18 :1; + unsigned XOR19 :1; + unsigned XOR20 :1; + unsigned XOR21 :1; + unsigned XOR22 :1; + unsigned XOR23 :1; + }; +} CRCXORUbits_t; +extern volatile CRCXORUbits_t CRCXORUbits __attribute__((address(0x355))); +# 45552 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCOUTT __attribute__((address(0x356))); + +__asm("CRCOUTT equ 0356h"); + + +typedef union { + struct { + unsigned OUT :8; + }; + struct { + unsigned OUT24 :1; + unsigned OUT25 :1; + unsigned OUT26 :1; + unsigned OUT27 :1; + unsigned OUT28 :1; + unsigned OUT29 :1; + unsigned OUT30 :1; + unsigned OUT31 :1; + }; +} CRCOUTTbits_t; +extern volatile CRCOUTTbits_t CRCOUTTbits __attribute__((address(0x356))); +# 45622 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCSHFTT __attribute__((address(0x356))); + +__asm("CRCSHFTT equ 0356h"); + + +extern volatile unsigned char CRCSHIFTT __attribute__((address(0x356))); + +__asm("CRCSHIFTT equ 0356h"); + + +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHFTTbits_t; +extern volatile CRCSHFTTbits_t CRCSHFTTbits __attribute__((address(0x356))); +# 45695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned SHIFT :8; + }; + struct { + unsigned SHIFT24 :1; + unsigned SHIFT25 :1; + unsigned SHIFT26 :1; + unsigned SHIFT27 :1; + unsigned SHIFT28 :1; + unsigned SHIFT29 :1; + unsigned SHIFT30 :1; + unsigned SHIFT31 :1; + }; +} CRCSHIFTTbits_t; +extern volatile CRCSHIFTTbits_t CRCSHIFTTbits __attribute__((address(0x356))); +# 45760 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCXORT __attribute__((address(0x356))); + +__asm("CRCXORT equ 0356h"); + + +typedef union { + struct { + unsigned XOR :8; + }; + struct { + unsigned XOR24 :1; + unsigned XOR25 :1; + unsigned XOR26 :1; + unsigned XOR27 :1; + unsigned XOR28 :1; + unsigned XOR29 :1; + unsigned XOR30 :1; + unsigned XOR31 :1; + }; +} CRCXORTbits_t; +extern volatile CRCXORTbits_t CRCXORTbits __attribute__((address(0x356))); +# 45830 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON0 __attribute__((address(0x357))); + +__asm("CRCCON0 equ 0357h"); + + +typedef union { + struct { + unsigned FULL :1; + unsigned LENDIAN :1; + unsigned SETUP :2; + unsigned ACCMOD :1; + unsigned CRCBUSY :1; + unsigned CRCGO :1; + unsigned CRCEN :1; + }; + struct { + unsigned :1; + unsigned SHIFTM :1; + unsigned SETUP0 :1; + unsigned SETUP1 :1; + unsigned ACCM :1; + unsigned BUSY :1; + unsigned GO :1; + unsigned EN :1; + }; +} CRCCON0bits_t; +extern volatile CRCCON0bits_t CRCCON0bits __attribute__((address(0x357))); +# 45931 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON1 __attribute__((address(0x358))); + +__asm("CRCCON1 equ 0358h"); + + +typedef union { + struct { + unsigned PLEN :5; + }; + struct { + unsigned PLEN0 :1; + unsigned PLEN1 :1; + unsigned PLEN2 :1; + unsigned PLEN3 :1; + unsigned PLEN4 :1; + }; +} CRCCON1bits_t; +extern volatile CRCCON1bits_t CRCCON1bits __attribute__((address(0x358))); +# 45983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CRCCON2 __attribute__((address(0x359))); + +__asm("CRCCON2 equ 0359h"); + + +typedef union { + struct { + unsigned DLEN :5; + }; + struct { + unsigned DLEN0 :1; + unsigned DLEN1 :1; + unsigned DLEN2 :1; + unsigned DLEN3 :1; + unsigned DLEN4 :1; + }; +} CRCCON2bits_t; +extern volatile CRCCON2bits_t CRCCON2bits __attribute__((address(0x359))); +# 46036 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANLADR __attribute__((address(0x35A))); + + +__asm("SCANLADR equ 035Ah"); + + + + +extern volatile unsigned char SCANLADRL __attribute__((address(0x35A))); + +__asm("SCANLADRL equ 035Ah"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR0 :1; + unsigned LADR1 :1; + unsigned LADR2 :1; + unsigned LADR3 :1; + unsigned LADR4 :1; + unsigned LADR5 :1; + unsigned LADR6 :1; + unsigned LADR7 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR0 :1; + unsigned SCANLADR1 :1; + unsigned SCANLADR2 :1; + unsigned SCANLADR3 :1; + unsigned SCANLADR4 :1; + unsigned SCANLADR5 :1; + unsigned SCANLADR6 :1; + unsigned SCANLADR7 :1; + }; +} SCANLADRLbits_t; +extern volatile SCANLADRLbits_t SCANLADRLbits __attribute__((address(0x35A))); +# 46172 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRH __attribute__((address(0x35B))); + +__asm("SCANLADRH equ 035Bh"); + + +typedef union { + struct { + unsigned LADR :8; + }; + struct { + unsigned LADR8 :1; + unsigned LADR9 :1; + unsigned LADR10 :1; + unsigned LADR11 :1; + unsigned LADR12 :1; + unsigned LADR13 :1; + unsigned LADR14 :1; + unsigned LADR15 :1; + }; + struct { + unsigned SCANLADR :8; + }; + struct { + unsigned SCANLADR8 :1; + unsigned SCANLADR9 :1; + unsigned SCANLADR10 :1; + unsigned SCANLADR11 :1; + unsigned SCANLADR12 :1; + unsigned SCANLADR13 :1; + unsigned SCANLADR14 :1; + unsigned SCANLADR15 :1; + }; +} SCANLADRHbits_t; +extern volatile SCANLADRHbits_t SCANLADRHbits __attribute__((address(0x35B))); +# 46300 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANLADRU __attribute__((address(0x35C))); + +__asm("SCANLADRU equ 035Ch"); + + +typedef union { + struct { + unsigned LADR :6; + }; + struct { + unsigned LADR16 :1; + unsigned LADR17 :1; + unsigned LADR18 :1; + unsigned LADR19 :1; + unsigned LADR20 :1; + unsigned LADR21 :1; + }; + struct { + unsigned SCANLADR :6; + }; + struct { + unsigned SCANLADR16 :1; + unsigned SCANLADR17 :1; + unsigned SCANLADR18 :1; + unsigned SCANLADR19 :1; + unsigned SCANLADR20 :1; + unsigned SCANLADR21 :1; + }; +} SCANLADRUbits_t; +extern volatile SCANLADRUbits_t SCANLADRUbits __attribute__((address(0x35C))); +# 46405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 SCANHADR __attribute__((address(0x35D))); + + +__asm("SCANHADR equ 035Dh"); + + + + +extern volatile unsigned char SCANHADRL __attribute__((address(0x35D))); + +__asm("SCANHADRL equ 035Dh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR0 :1; + unsigned HADR1 :1; + unsigned HADR2 :1; + unsigned HADR3 :1; + unsigned HADR4 :1; + unsigned HADR5 :1; + unsigned HADR6 :1; + unsigned HADR7 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR0 :1; + unsigned SCANHADR1 :1; + unsigned SCANHADR2 :1; + unsigned SCANHADR3 :1; + unsigned SCANHADR4 :1; + unsigned SCANHADR5 :1; + unsigned SCANHADR6 :1; + unsigned SCANHADR7 :1; + }; +} SCANHADRLbits_t; +extern volatile SCANHADRLbits_t SCANHADRLbits __attribute__((address(0x35D))); +# 46541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRH __attribute__((address(0x35E))); + +__asm("SCANHADRH equ 035Eh"); + + +typedef union { + struct { + unsigned HADR :8; + }; + struct { + unsigned HADR8 :1; + unsigned HADR9 :1; + unsigned HADR10 :1; + unsigned HADR11 :1; + unsigned HADR12 :1; + unsigned HADR13 :1; + unsigned HADR14 :1; + unsigned HADR15 :1; + }; + struct { + unsigned SCANHADR :8; + }; + struct { + unsigned SCANHADR8 :1; + unsigned SCANHADR9 :1; + unsigned SCANHADR10 :1; + unsigned SCANHADR11 :1; + unsigned SCANHADR12 :1; + unsigned SCANHADR13 :1; + unsigned SCANHADR14 :1; + unsigned SCANHADR15 :1; + }; +} SCANHADRHbits_t; +extern volatile SCANHADRHbits_t SCANHADRHbits __attribute__((address(0x35E))); +# 46669 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANHADRU __attribute__((address(0x35F))); + +__asm("SCANHADRU equ 035Fh"); + + +typedef union { + struct { + unsigned HADR :6; + }; + struct { + unsigned HADR16 :1; + unsigned HADR17 :1; + unsigned HADR18 :1; + unsigned HADR19 :1; + unsigned HADR20 :1; + unsigned HADR21 :1; + }; + struct { + unsigned SCANHADR :6; + }; + struct { + unsigned SCANHADR16 :1; + unsigned SCANHADR17 :1; + unsigned SCANHADR18 :1; + unsigned SCANHADR19 :1; + unsigned SCANHADR20 :1; + unsigned SCANHADR21 :1; + }; +} SCANHADRUbits_t; +extern volatile SCANHADRUbits_t SCANHADRUbits __attribute__((address(0x35F))); +# 46773 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANCON0 __attribute__((address(0x360))); + +__asm("SCANCON0 equ 0360h"); + + +typedef union { + struct { + unsigned BUSY :1; + unsigned BURSTMD :1; + unsigned MREG :1; + unsigned :2; + unsigned SGO :1; + unsigned TRIGEN :1; + unsigned EN :1; + }; + struct { + unsigned :7; + unsigned SCANEN :1; + }; +} SCANCON0bits_t; +extern volatile SCANCON0bits_t SCANCON0bits __attribute__((address(0x360))); +# 46833 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SCANTRIG __attribute__((address(0x361))); + +__asm("SCANTRIG equ 0361h"); + + +typedef union { + struct { + unsigned TSEL :8; + }; + struct { + unsigned TSEL0 :1; + unsigned TSEL1 :1; + unsigned TSEL2 :1; + unsigned TSEL3 :1; + unsigned TSEL4 :1; + }; + struct { + unsigned SCANTSEL :8; + }; +} SCANTRIGbits_t; +extern volatile SCANTRIGbits_t SCANTRIGbits __attribute__((address(0x361))); +# 46893 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR0 __attribute__((address(0x362))); + +__asm("IPR0 equ 0362h"); + + +typedef union { + struct { + unsigned SWIP :1; + unsigned HLVDIP :1; + unsigned OSFIP :1; + unsigned CSWIP :1; + unsigned TU16AIP :1; + unsigned CLC1IP :1; + unsigned CANIP :1; + unsigned IOCIP :1; + }; +} IPR0bits_t; +extern volatile IPR0bits_t IPR0bits __attribute__((address(0x362))); +# 46955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR1 __attribute__((address(0x363))); + +__asm("IPR1 equ 0363h"); + + +typedef union { + struct { + unsigned INT0IP :1; + unsigned ZCDIP :1; + unsigned ADIP :1; + unsigned ACTIP :1; + unsigned C1IP :1; + unsigned SMT1IP :1; + unsigned SMT1PRAIP :1; + unsigned SMT1PWAIP :1; + }; +} IPR1bits_t; +extern volatile IPR1bits_t IPR1bits __attribute__((address(0x363))); +# 47017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR2 __attribute__((address(0x364))); + +__asm("IPR2 equ 0364h"); + + +typedef union { + struct { + unsigned ADTIP :1; + unsigned ADCH2IP :1; + unsigned ADCH3IP :1; + unsigned ADCH4IP :1; + unsigned DMA1SCNTIP :1; + unsigned DMA1DCNTIP :1; + unsigned DMA1ORIP :1; + unsigned DMA1AIP :1; + }; + struct { + unsigned ADCH1IP :1; + }; +} IPR2bits_t; +extern volatile IPR2bits_t IPR2bits __attribute__((address(0x364))); +# 47087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR3 __attribute__((address(0x365))); + +__asm("IPR3 equ 0365h"); + + +typedef union { + struct { + unsigned SPI1RXIP :1; + unsigned SPI1TXIP :1; + unsigned SPI1IP :1; + unsigned TMR2IP :1; + unsigned TMR1IP :1; + unsigned TMR1GIP :1; + unsigned CCP1IP :1; + unsigned TMR0IP :1; + }; +} IPR3bits_t; +extern volatile IPR3bits_t IPR3bits __attribute__((address(0x365))); +# 47149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR4 __attribute__((address(0x366))); + +__asm("IPR4 equ 0366h"); + + +typedef union { + struct { + unsigned U1RXIP :1; + unsigned U1TXIP :1; + unsigned U1EIP :1; + unsigned U1IP :1; + unsigned CANRXIP :1; + unsigned CANTXIP :1; + unsigned PWM1PIP :1; + unsigned PWM1IP :1; + }; +} IPR4bits_t; +extern volatile IPR4bits_t IPR4bits __attribute__((address(0x366))); +# 47211 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR5 __attribute__((address(0x367))); + +__asm("IPR5 equ 0367h"); + + +typedef union { + struct { + unsigned SPI2RXIP :1; + unsigned SPI2TXIP :1; + unsigned SPI2IP :1; + unsigned TU16BIP :1; + unsigned TMR3IP :1; + unsigned TMR3GIP :1; + unsigned PWM2PIP :1; + unsigned PWM2IP :1; + }; +} IPR5bits_t; +extern volatile IPR5bits_t IPR5bits __attribute__((address(0x367))); +# 47273 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR6 __attribute__((address(0x368))); + +__asm("IPR6 equ 0368h"); + + +typedef union { + struct { + unsigned INT1IP :1; + unsigned CLC2IP :1; + unsigned CWG1IP :1; + unsigned NCO1IP :1; + unsigned DMA2SCNTIP :1; + unsigned DMA2DCNTIP :1; + unsigned DMA2ORIP :1; + unsigned DMA2AIP :1; + }; +} IPR6bits_t; +extern volatile IPR6bits_t IPR6bits __attribute__((address(0x368))); +# 47335 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR7 __attribute__((address(0x369))); + +__asm("IPR7 equ 0369h"); + + +typedef union { + struct { + unsigned I2C1RXIP :1; + unsigned I2C1TXIP :1; + unsigned I2C1IP :1; + unsigned I2C1EIP :1; + unsigned :1; + unsigned CLC3IP :1; + unsigned PWM3PIP :1; + unsigned PWM3IP :1; + }; +} IPR7bits_t; +extern volatile IPR7bits_t IPR7bits __attribute__((address(0x369))); +# 47392 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR8 __attribute__((address(0x36A))); + +__asm("IPR8 equ 036Ah"); + + +typedef union { + struct { + unsigned U2RXIP :1; + unsigned U2TXIP :1; + unsigned U2EIP :1; + unsigned U2IP :1; + unsigned TMR5IP :1; + unsigned TMR5GIP :1; + unsigned CCP2IP :1; + unsigned SCANIP :1; + }; +} IPR8bits_t; +extern volatile IPR8bits_t IPR8bits __attribute__((address(0x36A))); +# 47454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR9 __attribute__((address(0x36B))); + +__asm("IPR9 equ 036Bh"); + + +typedef union { + struct { + unsigned U3RXIP :1; + unsigned U3TXIP :1; + unsigned U3EIP :1; + unsigned U3IP :1; + unsigned :1; + unsigned CLC4IP :1; + unsigned PWM4PIP :1; + unsigned PWM4IP :1; + }; +} IPR9bits_t; +extern volatile IPR9bits_t IPR9bits __attribute__((address(0x36B))); +# 47511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR10 __attribute__((address(0x36C))); + +__asm("IPR10 equ 036Ch"); + + +typedef union { + struct { + unsigned INT2IP :1; + unsigned CLC5IP :1; + unsigned CWG2IP :1; + unsigned NCO2IP :1; + unsigned DMA3SCNTIP :1; + unsigned DMA3DCNTIP :1; + unsigned DMA3ORIP :1; + unsigned DMA3AIP :1; + }; +} IPR10bits_t; +extern volatile IPR10bits_t IPR10bits __attribute__((address(0x36C))); +# 47573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR11 __attribute__((address(0x36D))); + +__asm("IPR11 equ 036Dh"); + + +typedef union { + struct { + unsigned CCP3IP :1; + unsigned CLC6IP :1; + unsigned CWG3IP :1; + unsigned TMR4IP :1; + unsigned DMA4SCNTIP :1; + unsigned DMA4DCNTIP :1; + unsigned DMA4ORIP :1; + unsigned DMA4AIP :1; + }; +} IPR11bits_t; +extern volatile IPR11bits_t IPR11bits __attribute__((address(0x36D))); +# 47635 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR12 __attribute__((address(0x36E))); + +__asm("IPR12 equ 036Eh"); + + +typedef union { + struct { + unsigned U4RXIP :1; + unsigned U4TXIP :1; + unsigned U4EIP :1; + unsigned U4IP :1; + unsigned DMA5SCNTIP :1; + unsigned DMA5DCNTIP :1; + unsigned DMA5ORIP :1; + unsigned DMA5AIP :1; + }; +} IPR12bits_t; +extern volatile IPR12bits_t IPR12bits __attribute__((address(0x36E))); +# 47697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR13 __attribute__((address(0x36F))); + +__asm("IPR13 equ 036Fh"); + + +typedef union { + struct { + unsigned U5RXIP :1; + unsigned U5TXIP :1; + unsigned U5EIP :1; + unsigned U5IP :1; + unsigned DMA6SCNTIP :1; + unsigned DMA6DCNTIP :1; + unsigned DMA6ORIP :1; + unsigned DMA6AIP :1; + }; +} IPR13bits_t; +extern volatile IPR13bits_t IPR13bits __attribute__((address(0x36F))); +# 47759 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR14 __attribute__((address(0x370))); + +__asm("IPR14 equ 0370h"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IP :1; + unsigned C2IP :1; + unsigned NCO3IP :1; + unsigned DMA7SCNTIP :1; + unsigned DMA7DCNTIP :1; + unsigned DMA7ORIP :1; + unsigned DMA7AIP :1; + }; +} IPR14bits_t; +extern volatile IPR14bits_t IPR14bits __attribute__((address(0x370))); +# 47816 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IPR15 __attribute__((address(0x371))); + +__asm("IPR15 equ 0371h"); + + +typedef union { + struct { + unsigned NVMIP :1; + unsigned CLC8IP :1; + unsigned CRCIP :1; + unsigned TMR6IP :1; + unsigned DMA8SCNTIP :1; + unsigned DMA8DCNTIP :1; + unsigned DMA8ORIP :1; + unsigned DMA8AIP :1; + }; +} IPR15bits_t; +extern volatile IPR15bits_t IPR15bits __attribute__((address(0x371))); +# 47878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_CSHAD __attribute__((address(0x373))); + +__asm("STATUS_CSHAD equ 0373h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_CSHADbits_t; +extern volatile STATUS_CSHADbits_t STATUS_CSHADbits __attribute__((address(0x373))); +# 47967 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_CSHAD __attribute__((address(0x374))); + +__asm("WREG_CSHAD equ 0374h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_CSHADbits_t; +extern volatile WREG_CSHADbits_t WREG_CSHADbits __attribute__((address(0x374))); +# 47987 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_CSHAD __attribute__((address(0x375))); + +__asm("BSR_CSHAD equ 0375h"); + + + + +extern volatile unsigned char SHADCON __attribute__((address(0x376))); + +__asm("SHADCON equ 0376h"); + + +typedef union { + struct { + unsigned SHADLO :1; + }; +} SHADCONbits_t; +extern volatile SHADCONbits_t SHADCONbits __attribute__((address(0x376))); +# 48014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS_SHAD __attribute__((address(0x377))); + +__asm("STATUS_SHAD equ 0377h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUS_SHADbits_t; +extern volatile STATUS_SHADbits_t STATUS_SHADbits __attribute__((address(0x377))); +# 48103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG_SHAD __attribute__((address(0x378))); + +__asm("WREG_SHAD equ 0378h"); + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREG_SHADbits_t; +extern volatile WREG_SHADbits_t WREG_SHADbits __attribute__((address(0x378))); +# 48123 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR_SHAD __attribute__((address(0x379))); + +__asm("BSR_SHAD equ 0379h"); + + + + +extern volatile unsigned char PCLATH_SHAD __attribute__((address(0x37A))); + +__asm("PCLATH_SHAD equ 037Ah"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATH_SHADbits_t; +extern volatile PCLATH_SHADbits_t PCLATH_SHADbits __attribute__((address(0x37A))); +# 48150 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU_SHAD __attribute__((address(0x37B))); + +__asm("PCLATU_SHAD equ 037Bh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATU_SHADbits_t; +extern volatile PCLATU_SHADbits_t PCLATU_SHADbits __attribute__((address(0x37B))); +# 48170 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0SH __attribute__((address(0x37C))); + +__asm("FSR0SH equ 037Ch"); + + + + +extern volatile unsigned char FSR0L_SHAD __attribute__((address(0x37C))); + +__asm("FSR0L_SHAD equ 037Ch"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0L_SHADbits_t; +extern volatile FSR0L_SHADbits_t FSR0L_SHADbits __attribute__((address(0x37C))); +# 48197 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H_SHAD __attribute__((address(0x37D))); + +__asm("FSR0H_SHAD equ 037Dh"); + + +typedef union { + struct { + unsigned FSR0H :6; + }; +} FSR0H_SHADbits_t; +extern volatile FSR0H_SHADbits_t FSR0H_SHADbits __attribute__((address(0x37D))); +# 48217 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR1SH __attribute__((address(0x37E))); + +__asm("FSR1SH equ 037Eh"); + + + + +extern volatile unsigned char FSR1L_SHAD __attribute__((address(0x37E))); + +__asm("FSR1L_SHAD equ 037Eh"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1L_SHADbits_t; +extern volatile FSR1L_SHADbits_t FSR1L_SHADbits __attribute__((address(0x37E))); +# 48244 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H_SHAD __attribute__((address(0x37F))); + +__asm("FSR1H_SHAD equ 037Fh"); + + +typedef union { + struct { + unsigned FSR1H :6; + }; +} FSR1H_SHADbits_t; +extern volatile FSR1H_SHADbits_t FSR1H_SHADbits __attribute__((address(0x37F))); +# 48264 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2SH __attribute__((address(0x380))); + +__asm("FSR2SH equ 0380h"); + + + + +extern volatile unsigned char FSR2L_SHAD __attribute__((address(0x380))); + +__asm("FSR2L_SHAD equ 0380h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2L_SHADbits_t; +extern volatile FSR2L_SHADbits_t FSR2L_SHADbits __attribute__((address(0x380))); +# 48291 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H_SHAD __attribute__((address(0x381))); + +__asm("FSR2H_SHAD equ 0381h"); + + +typedef union { + struct { + unsigned FSR2H :6; + }; +} FSR2H_SHADbits_t; +extern volatile FSR2H_SHADbits_t FSR2H_SHADbits __attribute__((address(0x381))); +# 48311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PRODSH __attribute__((address(0x382))); + +__asm("PRODSH equ 0382h"); + + + + +extern volatile unsigned char PRODL_SHAD __attribute__((address(0x382))); + +__asm("PRODL_SHAD equ 0382h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODL_SHADbits_t; +extern volatile PRODL_SHADbits_t PRODL_SHADbits __attribute__((address(0x382))); +# 48338 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH_SHAD __attribute__((address(0x383))); + +__asm("PRODH_SHAD equ 0383h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODH_SHADbits_t; +extern volatile PRODH_SHADbits_t PRODH_SHADbits __attribute__((address(0x383))); +# 48358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON0 __attribute__((address(0x387))); + +__asm("TU16ACON0 equ 0387h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16ACIE :1; + unsigned TU16AZIE :1; + unsigned TU16APRIE :1; + unsigned TU16ARDSEL :1; + unsigned TU16AOPOL :1; + unsigned TU16AOM :1; + unsigned TU16ACPOL :1; + unsigned TU16AON :1; + }; +} TU16ACON0bits_t; +extern volatile TU16ACON0bits_t TU16ACON0bits __attribute__((address(0x387))); +# 48470 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACON1 __attribute__((address(0x388))); + +__asm("TU16ACON1 equ 0388h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16ACIF :1; + unsigned TU16AZIF :1; + unsigned TU16APRIF :1; + unsigned TU16ACAPT :1; + unsigned TU16ALIMIT :1; + unsigned TU16ACLR :1; + unsigned TMRAOSEN :1; + unsigned TU16ARUN :1; + }; +} TU16ACON1bits_t; +extern volatile TU16ACON1bits_t TU16ACON1bits __attribute__((address(0x388))); +# 48582 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AHLT __attribute__((address(0x389))); + +__asm("TU16AHLT equ 0389h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16ASTOP :2; + unsigned TU16ARESET :2; + unsigned TU16ASTART :2; + unsigned TU16ACSYNC :1; + unsigned TU16AEPOL :1; + }; + struct { + unsigned TU16ASTOP0 :1; + unsigned TU16ASTOP1 :1; + unsigned TU16ARESET0 :1; + unsigned TU16ARESET1 :1; + unsigned TU16ASTART0 :1; + unsigned TU16ASTART1 :1; + }; +} TU16AHLTbits_t; +extern volatile TU16AHLTbits_t TU16AHLTbits __attribute__((address(0x389))); +# 48734 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APS __attribute__((address(0x38A))); + +__asm("TU16APS equ 038Ah"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16APS0 :1; + unsigned TU16APS1 :1; + unsigned TU16APS2 :1; + unsigned TU16APS3 :1; + unsigned TU16APS4 :1; + unsigned TU16APS5 :1; + unsigned TU16APS6 :1; + unsigned TU16APS7 :1; + }; + struct { + unsigned TU16APS :8; + }; +} TU16APSbits_t; +extern volatile TU16APSbits_t TU16APSbits __attribute__((address(0x38A))); +# 48862 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16ATMR __attribute__((address(0x38B))); + +__asm("TU16ATMR equ 038Bh"); + + +extern volatile unsigned short TU16ACR __attribute__((address(0x38B))); + +__asm("TU16ACR equ 038Bh"); + + + + +extern volatile unsigned char TU16ATMRL __attribute__((address(0x38B))); + +__asm("TU16ATMRL equ 038Bh"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16ATMRL0 :1; + unsigned TU16ATMRL1 :1; + unsigned TU16ATMRL2 :1; + unsigned TU16ATMRL3 :1; + unsigned TU16ATMRL4 :1; + unsigned TU16ATMRL5 :1; + unsigned TU16ATMRL6 :1; + unsigned TU16ATMRL7 :1; + }; + struct { + unsigned TU16ATMR0 :1; + unsigned TU16ATMR1 :1; + unsigned TU16ATMR2 :1; + unsigned TU16ATMR3 :1; + unsigned TU16ATMR4 :1; + unsigned TU16ATMR5 :1; + unsigned TU16ATMR6 :1; + unsigned TU16ATMR7 :1; + }; +} TU16ATMRLbits_t; +extern volatile TU16ATMRLbits_t TU16ATMRLbits __attribute__((address(0x38B))); +# 49044 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRL __attribute__((address(0x38B))); + +__asm("TU16ACRL equ 038Bh"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16ACRL0 :1; + unsigned TU16ACRL1 :1; + unsigned TU16ACRL2 :1; + unsigned TU16ACRL3 :1; + unsigned TU16ACRL4 :1; + unsigned TU16ACRL5 :1; + unsigned TU16ACRL6 :1; + unsigned TU16ACRL7 :1; + }; + struct { + unsigned TU16ACR0 :1; + unsigned TU16ACR1 :1; + unsigned TU16ACR2 :1; + unsigned TU16ACR3 :1; + unsigned TU16ACR4 :1; + unsigned TU16ACR5 :1; + unsigned TU16ACR6 :1; + unsigned TU16ACR7 :1; + }; +} TU16ACRLbits_t; +extern volatile TU16ACRLbits_t TU16ACRLbits __attribute__((address(0x38B))); +# 49214 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ATMRH __attribute__((address(0x38C))); + +__asm("TU16ATMRH equ 038Ch"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16ATMRH0 :1; + unsigned TU16ATMRH1 :1; + unsigned TU16ATMRH2 :1; + unsigned TU16ATMRH3 :1; + unsigned TU16ATMRH4 :1; + unsigned TU16ATMRH5 :1; + unsigned TU16ATMRH6 :1; + unsigned TU16ATMRH7 :1; + }; + struct { + unsigned TU16ATMR8 :1; + unsigned TU16ATMR9 :1; + unsigned TU16ATMR10 :1; + unsigned TU16ATMR11 :1; + unsigned TU16ATMR12 :1; + unsigned TU16ATMR13 :1; + unsigned TU16ATMR14 :1; + unsigned TU16ATMR15 :1; + }; +} TU16ATMRHbits_t; +extern volatile TU16ATMRHbits_t TU16ATMRHbits __attribute__((address(0x38C))); +# 49384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACRH __attribute__((address(0x38C))); + +__asm("TU16ACRH equ 038Ch"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16ACRH0 :1; + unsigned TU16ACRH1 :1; + unsigned TU16ACRH2 :1; + unsigned TU16ACRH3 :1; + unsigned TU16ACRH4 :1; + unsigned TU16ACRH5 :1; + unsigned TU16ACRH6 :1; + unsigned TU16ACRH7 :1; + }; + struct { + unsigned TU16ACR8 :1; + unsigned TU16ACR9 :1; + unsigned TU16ACR10 :1; + unsigned TU16ACR11 :1; + unsigned TU16ACR12 :1; + unsigned TU16ACR13 :1; + unsigned TU16ACR14 :1; + unsigned TU16ACR15 :1; + }; +} TU16ACRHbits_t; +extern volatile TU16ACRHbits_t TU16ACRHbits __attribute__((address(0x38C))); +# 49554 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16APR __attribute__((address(0x38D))); + +__asm("TU16APR equ 038Dh"); + + + + +extern volatile unsigned char TU16APRL __attribute__((address(0x38D))); + +__asm("TU16APRL equ 038Dh"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16APRL0 :1; + unsigned TU16APRL1 :1; + unsigned TU16APRL2 :1; + unsigned TU16APRL3 :1; + unsigned TU16APRL4 :1; + unsigned TU16APRL5 :1; + unsigned TU16APRL6 :1; + unsigned TU16APRL7 :1; + }; + struct { + unsigned TU16APR0 :1; + unsigned TU16APR1 :1; + unsigned TU16APR2 :1; + unsigned TU16APR3 :1; + unsigned TU16APR4 :1; + unsigned TU16APR5 :1; + unsigned TU16APR6 :1; + unsigned TU16APR7 :1; + }; +} TU16APRLbits_t; +extern volatile TU16APRLbits_t TU16APRLbits __attribute__((address(0x38D))); +# 49731 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16APRH __attribute__((address(0x38E))); + +__asm("TU16APRH equ 038Eh"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16APRH0 :1; + unsigned TU16APRH1 :1; + unsigned TU16APRH2 :1; + unsigned TU16APRH3 :1; + unsigned TU16APRH4 :1; + unsigned TU16APRH5 :1; + unsigned TU16APRH6 :1; + unsigned TU16APRH7 :1; + }; + struct { + unsigned TU16APR8 :1; + unsigned TU16APR9 :1; + unsigned TU16APR10 :1; + unsigned TU16APR11 :1; + unsigned TU16APR12 :1; + unsigned TU16APR13 :1; + unsigned TU16APR14 :1; + unsigned TU16APR15 :1; + }; +} TU16APRHbits_t; +extern volatile TU16APRHbits_t TU16APRHbits __attribute__((address(0x38E))); +# 49901 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16ACLK __attribute__((address(0x38F))); + +__asm("TU16ACLK equ 038Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16ACLK0 :1; + unsigned TU16ACLK1 :1; + unsigned TU16ACLK2 :1; + unsigned TU16ACLK3 :1; + unsigned TU16ACLK4 :1; + }; +} TU16ACLKbits_t; +extern volatile TU16ACLKbits_t TU16ACLKbits __attribute__((address(0x38F))); +# 49985 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16AERS __attribute__((address(0x390))); + +__asm("TU16AERS equ 0390h"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16AERS0 :1; + unsigned TU16AERS1 :1; + unsigned TU16AERS2 :1; + unsigned TU16AERS3 :1; + unsigned TU16AERS4 :1; + unsigned TU16AERS5 :1; + }; +} TU16AERSbits_t; +extern volatile TU16AERSbits_t TU16AERSbits __attribute__((address(0x390))); +# 50081 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON0 __attribute__((address(0x393))); + +__asm("TU16BCON0 equ 0393h"); + + +typedef union { + struct { + unsigned CIE :1; + unsigned ZIE :1; + unsigned PRIE :1; + unsigned RDSEL :1; + unsigned OPOL :1; + unsigned OM :1; + unsigned CPOL :1; + unsigned ON :1; + }; + struct { + unsigned TU16BCIE :1; + unsigned TU16BZIE :1; + unsigned TU16BPRIE :1; + unsigned TU16BRDSEL :1; + unsigned TU16BOPOL :1; + unsigned TU16BOM :1; + unsigned TU16BCPOL :1; + unsigned TU16BON :1; + }; +} TU16BCON0bits_t; +extern volatile TU16BCON0bits_t TU16BCON0bits __attribute__((address(0x393))); +# 50193 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCON1 __attribute__((address(0x394))); + +__asm("TU16BCON1 equ 0394h"); + + +typedef union { + struct { + unsigned CIF :1; + unsigned ZIF :1; + unsigned PRIF :1; + unsigned CAPT :1; + unsigned LIMIT :1; + unsigned CLR :1; + unsigned OSEN :1; + unsigned RUN :1; + }; + struct { + unsigned TU16BCIF :1; + unsigned TU16BZIF :1; + unsigned TU16BPRIF :1; + unsigned TU16BCAPT :1; + unsigned TU16BLIMIT :1; + unsigned TU16BCLR :1; + unsigned TMRBOSEN :1; + unsigned TU16BRUN :1; + }; +} TU16BCON1bits_t; +extern volatile TU16BCON1bits_t TU16BCON1bits __attribute__((address(0x394))); +# 50305 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BHLT __attribute__((address(0x395))); + +__asm("TU16BHLT equ 0395h"); + + +typedef union { + struct { + unsigned STOP :2; + unsigned RESET :2; + unsigned START :2; + unsigned CSYNC :1; + unsigned EPOL :1; + }; + struct { + unsigned STOP0 :1; + unsigned STOP1 :1; + unsigned RESET0 :1; + unsigned RESET1 :1; + unsigned START0 :1; + unsigned START1 :1; + }; + struct { + unsigned TU16BSTOP :2; + unsigned TU16BRESET :2; + unsigned TU16BSTART :2; + unsigned TU16BCSYNC :1; + unsigned TU16BEPOL :1; + }; + struct { + unsigned TU16BSTOP0 :1; + unsigned TU16BSTOP1 :1; + unsigned TU16BRESET0 :1; + unsigned TU16BRESET1 :1; + unsigned TU16BSTART0 :1; + unsigned TU16BSTART1 :1; + }; +} TU16BHLTbits_t; +extern volatile TU16BHLTbits_t TU16BHLTbits __attribute__((address(0x395))); +# 50457 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPS __attribute__((address(0x396))); + +__asm("TU16BPS equ 0396h"); + + +typedef union { + struct { + unsigned PS :8; + }; + struct { + unsigned PS0 :1; + unsigned PS1 :1; + unsigned PS2 :1; + unsigned PS3 :1; + unsigned PS4 :1; + unsigned PS5 :1; + unsigned PS6 :1; + unsigned PS7 :1; + }; + struct { + unsigned TU16BPS0 :1; + unsigned TU16BPS1 :1; + unsigned TU16BPS2 :1; + unsigned TU16BPS3 :1; + unsigned TU16BPS4 :1; + unsigned TU16BPS5 :1; + unsigned TU16BPS6 :1; + unsigned TU16BPS7 :1; + }; + struct { + unsigned TU16BPS :8; + }; +} TU16BPSbits_t; +extern volatile TU16BPSbits_t TU16BPSbits __attribute__((address(0x396))); +# 50585 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BTMR __attribute__((address(0x397))); + +__asm("TU16BTMR equ 0397h"); + + +extern volatile unsigned short TU16BCR __attribute__((address(0x397))); + +__asm("TU16BCR equ 0397h"); + + + + +extern volatile unsigned char TU16BTMRL __attribute__((address(0x397))); + +__asm("TU16BTMRL equ 0397h"); + + +typedef union { + struct { + unsigned TMRL :8; + }; + struct { + unsigned TMRL0 :1; + unsigned TMRL1 :1; + unsigned TMRL2 :1; + unsigned TMRL3 :1; + unsigned TMRL4 :1; + unsigned TMRL5 :1; + unsigned TMRL6 :1; + unsigned TMRL7 :1; + }; + struct { + unsigned TU16BTMRL0 :1; + unsigned TU16BTMRL1 :1; + unsigned TU16BTMRL2 :1; + unsigned TU16BTMRL3 :1; + unsigned TU16BTMRL4 :1; + unsigned TU16BTMRL5 :1; + unsigned TU16BTMRL6 :1; + unsigned TU16BTMRL7 :1; + }; + struct { + unsigned TU16BTMR0 :1; + unsigned TU16BTMR1 :1; + unsigned TU16BTMR2 :1; + unsigned TU16BTMR3 :1; + unsigned TU16BTMR4 :1; + unsigned TU16BTMR5 :1; + unsigned TU16BTMR6 :1; + unsigned TU16BTMR7 :1; + }; +} TU16BTMRLbits_t; +extern volatile TU16BTMRLbits_t TU16BTMRLbits __attribute__((address(0x397))); +# 50767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRL __attribute__((address(0x397))); + +__asm("TU16BCRL equ 0397h"); + + +typedef union { + struct { + unsigned CRL :8; + }; + struct { + unsigned CRL0 :1; + unsigned CRL1 :1; + unsigned CRL2 :1; + unsigned CRL3 :1; + unsigned CRL4 :1; + unsigned CRL5 :1; + unsigned CRL6 :1; + unsigned CRL7 :1; + }; + struct { + unsigned TU16BCRL0 :1; + unsigned TU16BCRL1 :1; + unsigned TU16BCRL2 :1; + unsigned TU16BCRL3 :1; + unsigned TU16BCRL4 :1; + unsigned TU16BCRL5 :1; + unsigned TU16BCRL6 :1; + unsigned TU16BCRL7 :1; + }; + struct { + unsigned TU16BCR0 :1; + unsigned TU16BCR1 :1; + unsigned TU16BCR2 :1; + unsigned TU16BCR3 :1; + unsigned TU16BCR4 :1; + unsigned TU16BCR5 :1; + unsigned TU16BCR6 :1; + unsigned TU16BCR7 :1; + }; +} TU16BCRLbits_t; +extern volatile TU16BCRLbits_t TU16BCRLbits __attribute__((address(0x397))); +# 50937 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BTMRH __attribute__((address(0x398))); + +__asm("TU16BTMRH equ 0398h"); + + +typedef union { + struct { + unsigned TMRH :8; + }; + struct { + unsigned TMRH0 :1; + unsigned TMRH1 :1; + unsigned TMRH2 :1; + unsigned TMRH3 :1; + unsigned TMRH4 :1; + unsigned TMRH5 :1; + unsigned TMRH6 :1; + unsigned TMRH7 :1; + }; + struct { + unsigned TU16BTMRH0 :1; + unsigned TU16BTMRH1 :1; + unsigned TU16BTMRH2 :1; + unsigned TU16BTMRH3 :1; + unsigned TU16BTMRH4 :1; + unsigned TU16BTMRH5 :1; + unsigned TU16BTMRH6 :1; + unsigned TU16BTMRH7 :1; + }; + struct { + unsigned TU16BTMR8 :1; + unsigned TU16BTMR9 :1; + unsigned TU16BTMR10 :1; + unsigned TU16BTMR11 :1; + unsigned TU16BTMR12 :1; + unsigned TU16BTMR13 :1; + unsigned TU16BTMR14 :1; + unsigned TU16BTMR15 :1; + }; +} TU16BTMRHbits_t; +extern volatile TU16BTMRHbits_t TU16BTMRHbits __attribute__((address(0x398))); +# 51107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCRH __attribute__((address(0x398))); + +__asm("TU16BCRH equ 0398h"); + + +typedef union { + struct { + unsigned CRH :8; + }; + struct { + unsigned CRH0 :1; + unsigned CRH1 :1; + unsigned CRH2 :1; + unsigned CRH3 :1; + unsigned CRH4 :1; + unsigned CRH5 :1; + unsigned CRH6 :1; + unsigned CRH7 :1; + }; + struct { + unsigned TU16BCRH0 :1; + unsigned TU16BCRH1 :1; + unsigned TU16BCRH2 :1; + unsigned TU16BCRH3 :1; + unsigned TU16BCRH4 :1; + unsigned TU16BCRH5 :1; + unsigned TU16BCRH6 :1; + unsigned TU16BCRH7 :1; + }; + struct { + unsigned TU16BCR8 :1; + unsigned TU16BCR9 :1; + unsigned TU16BCR10 :1; + unsigned TU16BCR11 :1; + unsigned TU16BCR12 :1; + unsigned TU16BCR13 :1; + unsigned TU16BCR14 :1; + unsigned TU16BCR15 :1; + }; +} TU16BCRHbits_t; +extern volatile TU16BCRHbits_t TU16BCRHbits __attribute__((address(0x398))); +# 51277 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short TU16BPR __attribute__((address(0x399))); + +__asm("TU16BPR equ 0399h"); + + + + +extern volatile unsigned char TU16BPRL __attribute__((address(0x399))); + +__asm("TU16BPRL equ 0399h"); + + +typedef union { + struct { + unsigned PRL :8; + }; + struct { + unsigned PRL0 :1; + unsigned PRL1 :1; + unsigned PRL2 :1; + unsigned PRL3 :1; + unsigned PRL4 :1; + unsigned PRL5 :1; + unsigned PRL6 :1; + unsigned PRL7 :1; + }; + struct { + unsigned TU16BPRL0 :1; + unsigned TU16BPRL1 :1; + unsigned TU16BPRL2 :1; + unsigned TU16BPRL3 :1; + unsigned TU16BPRL4 :1; + unsigned TU16BPRL5 :1; + unsigned TU16BPRL6 :1; + unsigned TU16BPRL7 :1; + }; + struct { + unsigned TU16BPR0 :1; + unsigned TU16BPR1 :1; + unsigned TU16BPR2 :1; + unsigned TU16BPR3 :1; + unsigned TU16BPR4 :1; + unsigned TU16BPR5 :1; + unsigned TU16BPR6 :1; + unsigned TU16BPR7 :1; + }; +} TU16BPRLbits_t; +extern volatile TU16BPRLbits_t TU16BPRLbits __attribute__((address(0x399))); +# 51454 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BPRH __attribute__((address(0x39A))); + +__asm("TU16BPRH equ 039Ah"); + + +typedef union { + struct { + unsigned PRH :8; + }; + struct { + unsigned PRH0 :1; + unsigned PRH1 :1; + unsigned PRH2 :1; + unsigned PRH3 :1; + unsigned PRH4 :1; + unsigned PRH5 :1; + unsigned PRH6 :1; + unsigned PRH7 :1; + }; + struct { + unsigned TU16BPRH0 :1; + unsigned TU16BPRH1 :1; + unsigned TU16BPRH2 :1; + unsigned TU16BPRH3 :1; + unsigned TU16BPRH4 :1; + unsigned TU16BPRH5 :1; + unsigned TU16BPRH6 :1; + unsigned TU16BPRH7 :1; + }; + struct { + unsigned TU16BPR8 :1; + unsigned TU16BPR9 :1; + unsigned TU16BPR10 :1; + unsigned TU16BPR11 :1; + unsigned TU16BPR12 :1; + unsigned TU16BPR13 :1; + unsigned TU16BPR14 :1; + unsigned TU16BPR15 :1; + }; +} TU16BPRHbits_t; +extern volatile TU16BPRHbits_t TU16BPRHbits __attribute__((address(0x39A))); +# 51624 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BCLK __attribute__((address(0x39B))); + +__asm("TU16BCLK equ 039Bh"); + + +typedef union { + struct { + unsigned CLK :8; + }; + struct { + unsigned CLK0 :1; + unsigned CLK1 :1; + unsigned CLK2 :1; + unsigned CLK3 :1; + unsigned CLK4 :1; + }; + struct { + unsigned TU16BCLK0 :1; + unsigned TU16BCLK1 :1; + unsigned TU16BCLK2 :1; + unsigned TU16BCLK3 :1; + unsigned TU16BCLK4 :1; + }; +} TU16BCLKbits_t; +extern volatile TU16BCLKbits_t TU16BCLKbits __attribute__((address(0x39B))); +# 51708 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TU16BERS __attribute__((address(0x39C))); + +__asm("TU16BERS equ 039Ch"); + + +typedef union { + struct { + unsigned ERS :8; + }; + struct { + unsigned ERS0 :1; + unsigned ERS1 :1; + unsigned ERS2 :1; + unsigned ERS3 :1; + unsigned ERS4 :1; + unsigned ERS5 :1; + }; + struct { + unsigned TU16BERS0 :1; + unsigned TU16BERS1 :1; + unsigned TU16BERS2 :1; + unsigned TU16BERS3 :1; + unsigned TU16BERS4 :1; + unsigned TU16BERS5 :1; + }; +} TU16BERSbits_t; +extern volatile TU16BERSbits_t TU16BERSbits __attribute__((address(0x39C))); +# 51804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TUCHAIN __attribute__((address(0x3BB))); + +__asm("TUCHAIN equ 03BBh"); + + +typedef union { + struct { + unsigned CH16AB :1; + }; +} TUCHAINbits_t; +extern volatile TUCHAINbits_t TUCHAINbits __attribute__((address(0x3BB))); +# 51824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CLK __attribute__((address(0x3BC))); + +__asm("CWG1CLK equ 03BCh"); + + +extern volatile unsigned char CWG1CLKCON __attribute__((address(0x3BC))); + +__asm("CWG1CLKCON equ 03BCh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKbits_t; +extern volatile CWG1CLKbits_t CWG1CLKbits __attribute__((address(0x3BC))); +# 51855 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG1CS :1; + }; +} CWG1CLKCONbits_t; +extern volatile CWG1CLKCONbits_t CWG1CLKCONbits __attribute__((address(0x3BC))); +# 51878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1ISM __attribute__((address(0x3BD))); + +__asm("CWG1ISM equ 03BDh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG1ISM0 :1; + unsigned CWG1ISM1 :1; + unsigned CWG1ISM2 :1; + unsigned CWG1ISM3 :1; + }; +} CWG1ISMbits_t; +extern volatile CWG1ISMbits_t CWG1ISMbits __attribute__((address(0x3BD))); +# 51924 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBR __attribute__((address(0x3BE))); + +__asm("CWG1DBR equ 03BEh"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG1DBR :6; + }; + struct { + unsigned CWG1DBR0 :1; + unsigned CWG1DBR1 :1; + unsigned CWG1DBR2 :1; + unsigned CWG1DBR3 :1; + unsigned CWG1DBR4 :1; + unsigned CWG1DBR5 :1; + }; +} CWG1DBRbits_t; +extern volatile CWG1DBRbits_t CWG1DBRbits __attribute__((address(0x3BE))); +# 52028 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1DBF __attribute__((address(0x3BF))); + +__asm("CWG1DBF equ 03BFh"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG1DBF :6; + }; + struct { + unsigned CWG1DBF0 :1; + unsigned CWG1DBF1 :1; + unsigned CWG1DBF2 :1; + unsigned CWG1DBF3 :1; + unsigned CWG1DBF4 :1; + unsigned CWG1DBF5 :1; + }; +} CWG1DBFbits_t; +extern volatile CWG1DBFbits_t CWG1DBFbits __attribute__((address(0x3BF))); +# 52132 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON0 __attribute__((address(0x3C0))); + +__asm("CWG1CON0 equ 03C0h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G1EN :1; + }; + struct { + unsigned CWG1MODE :3; + unsigned :3; + unsigned CWG1LD :1; + unsigned CWG1EN :1; + }; + struct { + unsigned CWG1MODE0 :1; + unsigned CWG1MODE1 :1; + unsigned CWG1MODE2 :1; + }; +} CWG1CON0bits_t; +extern volatile CWG1CON0bits_t CWG1CON0bits __attribute__((address(0x3C0))); +# 52233 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1CON1 __attribute__((address(0x3C1))); + +__asm("CWG1CON1 equ 03C1h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG1POLA :1; + unsigned CWG1POLB :1; + unsigned CWG1POLC :1; + unsigned CWG1POLD :1; + unsigned :1; + unsigned CWG1IN :1; + }; +} CWG1CON1bits_t; +extern volatile CWG1CON1bits_t CWG1CON1bits __attribute__((address(0x3C1))); +# 52311 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS0 __attribute__((address(0x3C2))); + +__asm("CWG1AS0 equ 03C2h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC :2; + unsigned CWG1LSBD :2; + unsigned CWG1REN :1; + unsigned CWG1SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG1LSAC0 :1; + unsigned CWG1LSAC1 :1; + unsigned CWG1LSBD0 :1; + unsigned CWG1LSBD1 :1; + }; +} CWG1AS0bits_t; +extern volatile CWG1AS0bits_t CWG1AS0bits __attribute__((address(0x3C2))); +# 52431 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1AS1 __attribute__((address(0x3C3))); + +__asm("CWG1AS1 equ 03C3h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG1AS1bits_t; +extern volatile CWG1AS1bits_t CWG1AS1bits __attribute__((address(0x3C3))); +# 52493 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG1STR __attribute__((address(0x3C4))); + +__asm("CWG1STR equ 03C4h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG1STRA :1; + unsigned CWG1STRB :1; + unsigned CWG1STRC :1; + unsigned CWG1STRD :1; + unsigned CWG1OVRA :1; + unsigned CWG1OVRB :1; + unsigned CWG1OVRC :1; + unsigned CWG1OVRD :1; + }; +} CWG1STRbits_t; +extern volatile CWG1STRbits_t CWG1STRbits __attribute__((address(0x3C4))); +# 52605 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CLK __attribute__((address(0x3C5))); + +__asm("CWG2CLK equ 03C5h"); + + +extern volatile unsigned char CWG2CLKCON __attribute__((address(0x3C5))); + +__asm("CWG2CLKCON equ 03C5h"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKbits_t; +extern volatile CWG2CLKbits_t CWG2CLKbits __attribute__((address(0x3C5))); +# 52636 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG2CS :1; + }; +} CWG2CLKCONbits_t; +extern volatile CWG2CLKCONbits_t CWG2CLKCONbits __attribute__((address(0x3C5))); +# 52659 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2ISM __attribute__((address(0x3C6))); + +__asm("CWG2ISM equ 03C6h"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG2ISM0 :1; + unsigned CWG2ISM1 :1; + unsigned CWG2ISM2 :1; + unsigned CWG2ISM3 :1; + }; +} CWG2ISMbits_t; +extern volatile CWG2ISMbits_t CWG2ISMbits __attribute__((address(0x3C6))); +# 52705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBR __attribute__((address(0x3C7))); + +__asm("CWG2DBR equ 03C7h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG2DBR :6; + }; + struct { + unsigned CWG2DBR0 :1; + unsigned CWG2DBR1 :1; + unsigned CWG2DBR2 :1; + unsigned CWG2DBR3 :1; + unsigned CWG2DBR4 :1; + unsigned CWG2DBR5 :1; + }; +} CWG2DBRbits_t; +extern volatile CWG2DBRbits_t CWG2DBRbits __attribute__((address(0x3C7))); +# 52809 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2DBF __attribute__((address(0x3C8))); + +__asm("CWG2DBF equ 03C8h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG2DBF :6; + }; + struct { + unsigned CWG2DBF0 :1; + unsigned CWG2DBF1 :1; + unsigned CWG2DBF2 :1; + unsigned CWG2DBF3 :1; + unsigned CWG2DBF4 :1; + unsigned CWG2DBF5 :1; + }; +} CWG2DBFbits_t; +extern volatile CWG2DBFbits_t CWG2DBFbits __attribute__((address(0x3C8))); +# 52913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON0 __attribute__((address(0x3C9))); + +__asm("CWG2CON0 equ 03C9h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G2EN :1; + }; + struct { + unsigned CWG2MODE :3; + unsigned :3; + unsigned CWG2LD :1; + unsigned CWG2EN :1; + }; + struct { + unsigned CWG2MODE0 :1; + unsigned CWG2MODE1 :1; + unsigned CWG2MODE2 :1; + }; +} CWG2CON0bits_t; +extern volatile CWG2CON0bits_t CWG2CON0bits __attribute__((address(0x3C9))); +# 53014 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2CON1 __attribute__((address(0x3CA))); + +__asm("CWG2CON1 equ 03CAh"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG2POLA :1; + unsigned CWG2POLB :1; + unsigned CWG2POLC :1; + unsigned CWG2POLD :1; + unsigned :1; + unsigned CWG2IN :1; + }; +} CWG2CON1bits_t; +extern volatile CWG2CON1bits_t CWG2CON1bits __attribute__((address(0x3CA))); +# 53092 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS0 __attribute__((address(0x3CB))); + +__asm("CWG2AS0 equ 03CBh"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC :2; + unsigned CWG2LSBD :2; + unsigned CWG2REN :1; + unsigned CWG2SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG2LSAC0 :1; + unsigned CWG2LSAC1 :1; + unsigned CWG2LSBD0 :1; + unsigned CWG2LSBD1 :1; + }; +} CWG2AS0bits_t; +extern volatile CWG2AS0bits_t CWG2AS0bits __attribute__((address(0x3CB))); +# 53212 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2AS1 __attribute__((address(0x3CC))); + +__asm("CWG2AS1 equ 03CCh"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG2AS1bits_t; +extern volatile CWG2AS1bits_t CWG2AS1bits __attribute__((address(0x3CC))); +# 53274 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG2STR __attribute__((address(0x3CD))); + +__asm("CWG2STR equ 03CDh"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG2STRA :1; + unsigned CWG2STRB :1; + unsigned CWG2STRC :1; + unsigned CWG2STRD :1; + unsigned CWG2OVRA :1; + unsigned CWG2OVRB :1; + unsigned CWG2OVRC :1; + unsigned CWG2OVRD :1; + }; +} CWG2STRbits_t; +extern volatile CWG2STRbits_t CWG2STRbits __attribute__((address(0x3CD))); +# 53386 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CLK __attribute__((address(0x3CE))); + +__asm("CWG3CLK equ 03CEh"); + + +extern volatile unsigned char CWG3CLKCON __attribute__((address(0x3CE))); + +__asm("CWG3CLKCON equ 03CEh"); + + +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKbits_t; +extern volatile CWG3CLKbits_t CWG3CLKbits __attribute__((address(0x3CE))); +# 53417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CS :1; + }; + struct { + unsigned CWG3CS :1; + }; +} CWG3CLKCONbits_t; +extern volatile CWG3CLKCONbits_t CWG3CLKCONbits __attribute__((address(0x3CE))); +# 53440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3ISM __attribute__((address(0x3CF))); + +__asm("CWG3ISM equ 03CFh"); + + +typedef union { + struct { + unsigned IS :4; + }; + struct { + unsigned CWG3ISM0 :1; + unsigned CWG3ISM1 :1; + unsigned CWG3ISM2 :1; + unsigned CWG3ISM3 :1; + }; +} CWG3ISMbits_t; +extern volatile CWG3ISMbits_t CWG3ISMbits __attribute__((address(0x3CF))); +# 53486 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBR __attribute__((address(0x3D0))); + +__asm("CWG3DBR equ 03D0h"); + + +typedef union { + struct { + unsigned DBR :6; + }; + struct { + unsigned DBR0 :1; + unsigned DBR1 :1; + unsigned DBR2 :1; + unsigned DBR3 :1; + unsigned DBR4 :1; + unsigned DBR5 :1; + }; + struct { + unsigned CWG3DBR :6; + }; + struct { + unsigned CWG3DBR0 :1; + unsigned CWG3DBR1 :1; + unsigned CWG3DBR2 :1; + unsigned CWG3DBR3 :1; + unsigned CWG3DBR4 :1; + unsigned CWG3DBR5 :1; + }; +} CWG3DBRbits_t; +extern volatile CWG3DBRbits_t CWG3DBRbits __attribute__((address(0x3D0))); +# 53590 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3DBF __attribute__((address(0x3D1))); + +__asm("CWG3DBF equ 03D1h"); + + +typedef union { + struct { + unsigned DBF :6; + }; + struct { + unsigned DBF0 :1; + unsigned DBF1 :1; + unsigned DBF2 :1; + unsigned DBF3 :1; + unsigned DBF4 :1; + unsigned DBF5 :1; + }; + struct { + unsigned CWG3DBF :6; + }; + struct { + unsigned CWG3DBF0 :1; + unsigned CWG3DBF1 :1; + unsigned CWG3DBF2 :1; + unsigned CWG3DBF3 :1; + unsigned CWG3DBF4 :1; + unsigned CWG3DBF5 :1; + }; +} CWG3DBFbits_t; +extern volatile CWG3DBFbits_t CWG3DBFbits __attribute__((address(0x3D1))); +# 53694 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON0 __attribute__((address(0x3D2))); + +__asm("CWG3CON0 equ 03D2h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned :3; + unsigned LD :1; + unsigned EN :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :4; + unsigned G3EN :1; + }; + struct { + unsigned CWG3MODE :3; + unsigned :3; + unsigned CWG3LD :1; + unsigned CWG3EN :1; + }; + struct { + unsigned CWG3MODE0 :1; + unsigned CWG3MODE1 :1; + unsigned CWG3MODE2 :1; + }; +} CWG3CON0bits_t; +extern volatile CWG3CON0bits_t CWG3CON0bits __attribute__((address(0x3D2))); +# 53795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3CON1 __attribute__((address(0x3D3))); + +__asm("CWG3CON1 equ 03D3h"); + + +typedef union { + struct { + unsigned POLA :1; + unsigned POLB :1; + unsigned POLC :1; + unsigned POLD :1; + unsigned :1; + unsigned IN :1; + }; + struct { + unsigned CWG3POLA :1; + unsigned CWG3POLB :1; + unsigned CWG3POLC :1; + unsigned CWG3POLD :1; + unsigned :1; + unsigned CWG3IN :1; + }; +} CWG3CON1bits_t; +extern volatile CWG3CON1bits_t CWG3CON1bits __attribute__((address(0x3D3))); +# 53873 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS0 __attribute__((address(0x3D4))); + +__asm("CWG3AS0 equ 03D4h"); + + +typedef union { + struct { + unsigned :2; + unsigned LSAC :2; + unsigned LSBD :2; + unsigned REN :1; + unsigned SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned LSAC0 :1; + unsigned LSAC1 :1; + unsigned LSBD0 :1; + unsigned LSBD1 :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC :2; + unsigned CWG3LSBD :2; + unsigned CWG3REN :1; + unsigned CWG3SHUTDOWN :1; + }; + struct { + unsigned :2; + unsigned CWG3LSAC0 :1; + unsigned CWG3LSAC1 :1; + unsigned CWG3LSBD0 :1; + unsigned CWG3LSBD1 :1; + }; +} CWG3AS0bits_t; +extern volatile CWG3AS0bits_t CWG3AS0bits __attribute__((address(0x3D4))); +# 53993 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3AS1 __attribute__((address(0x3D5))); + +__asm("CWG3AS1 equ 03D5h"); + + +typedef union { + struct { + unsigned AS0E :1; + unsigned AS1E :1; + unsigned AS2E :1; + unsigned AS3E :1; + unsigned AS4E :1; + unsigned AS5E :1; + unsigned AS6E :1; + unsigned AS7E :1; + }; +} CWG3AS1bits_t; +extern volatile CWG3AS1bits_t CWG3AS1bits __attribute__((address(0x3D5))); +# 54055 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CWG3STR __attribute__((address(0x3D6))); + +__asm("CWG3STR equ 03D6h"); + + +typedef union { + struct { + unsigned STRA :1; + unsigned STRB :1; + unsigned STRC :1; + unsigned STRD :1; + unsigned OVRA :1; + unsigned OVRB :1; + unsigned OVRC :1; + unsigned OVRD :1; + }; + struct { + unsigned CWG3STRA :1; + unsigned CWG3STRB :1; + unsigned CWG3STRC :1; + unsigned CWG3STRD :1; + unsigned CWG3OVRA :1; + unsigned CWG3OVRB :1; + unsigned CWG3OVRC :1; + unsigned CWG3OVRD :1; + }; +} CWG3STRbits_t; +extern volatile CWG3STRbits_t CWG3STRbits __attribute__((address(0x3D6))); +# 54167 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FVRCON __attribute__((address(0x3D7))); + +__asm("FVRCON equ 03D7h"); + + +typedef union { + struct { + unsigned ADFVR :2; + unsigned CDAFVR :2; + unsigned TSRNG :1; + unsigned TSEN :1; + unsigned RDY :1; + unsigned EN :1; + }; + struct { + unsigned ADFVR0 :1; + unsigned ADFVR1 :1; + unsigned CDAFVR0 :1; + unsigned CDAFVR1 :1; + unsigned :2; + unsigned FVRRDY :1; + unsigned FVREN :1; + }; +} FVRCONbits_t; +extern volatile FVRCONbits_t FVRCONbits __attribute__((address(0x3D7))); +# 54256 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCPCON __attribute__((address(0x3D8))); + +__asm("ADCPCON equ 03D8h"); + + +extern volatile unsigned char ADCP __attribute__((address(0x3D8))); + +__asm("ADCP equ 03D8h"); + + +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPCONbits_t; +extern volatile ADCPCONbits_t ADCPCONbits __attribute__((address(0x3D8))); +# 54310 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +typedef union { + struct { + unsigned CPRDY :1; + unsigned :6; + unsigned ON :1; + }; + struct { + unsigned ADCPRDY :1; + unsigned :6; + unsigned CPON :1; + }; + struct { + unsigned :7; + unsigned ADCPON :1; + }; +} ADCPbits_t; +extern volatile ADCPbits_t ADCPbits __attribute__((address(0x3D8))); +# 54356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADLTH __attribute__((address(0x3D9))); + +__asm("ADLTH equ 03D9h"); + + + + +extern volatile unsigned char ADLTHL __attribute__((address(0x3D9))); + +__asm("ADLTHL equ 03D9h"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH0 :1; + unsigned ADLTH1 :1; + unsigned ADLTH2 :1; + unsigned ADLTH3 :1; + unsigned ADLTH4 :1; + unsigned ADLTH5 :1; + unsigned ADLTH6 :1; + unsigned ADLTH7 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH0 :1; + unsigned LTH1 :1; + unsigned LTH2 :1; + unsigned LTH3 :1; + unsigned LTH4 :1; + unsigned LTH5 :1; + unsigned LTH6 :1; + unsigned LTH7 :1; + }; +} ADLTHLbits_t; +extern volatile ADLTHLbits_t ADLTHLbits __attribute__((address(0x3D9))); +# 54491 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADLTHH __attribute__((address(0x3DA))); + +__asm("ADLTHH equ 03DAh"); + + +typedef union { + struct { + unsigned LTH :8; + }; + struct { + unsigned ADLTH8 :1; + unsigned ADLTH9 :1; + unsigned ADLTH10 :1; + unsigned ADLTH11 :1; + unsigned ADLTH12 :1; + unsigned ADLTH13 :1; + unsigned ADLTH14 :1; + unsigned ADLTH15 :1; + }; + struct { + unsigned ADLTH :8; + }; + struct { + unsigned LTH8 :1; + unsigned LTH9 :1; + unsigned LTH10 :1; + unsigned LTH11 :1; + unsigned LTH12 :1; + unsigned LTH13 :1; + unsigned LTH14 :1; + unsigned LTH15 :1; + }; +} ADLTHHbits_t; +extern volatile ADLTHHbits_t ADLTHHbits __attribute__((address(0x3DA))); +# 54619 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADUTH __attribute__((address(0x3DB))); + +__asm("ADUTH equ 03DBh"); + + + + +extern volatile unsigned char ADUTHL __attribute__((address(0x3DB))); + +__asm("ADUTHL equ 03DBh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH0 :1; + unsigned ADUTH1 :1; + unsigned ADUTH2 :1; + unsigned ADUTH3 :1; + unsigned ADUTH4 :1; + unsigned ADUTH5 :1; + unsigned ADUTH6 :1; + unsigned ADUTH7 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH0 :1; + unsigned UTH1 :1; + unsigned UTH2 :1; + unsigned UTH3 :1; + unsigned UTH4 :1; + unsigned UTH5 :1; + unsigned UTH6 :1; + unsigned UTH7 :1; + }; +} ADUTHLbits_t; +extern volatile ADUTHLbits_t ADUTHLbits __attribute__((address(0x3DB))); +# 54754 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADUTHH __attribute__((address(0x3DC))); + +__asm("ADUTHH equ 03DCh"); + + +typedef union { + struct { + unsigned UTH :8; + }; + struct { + unsigned ADUTH8 :1; + unsigned ADUTH9 :1; + unsigned ADUTH10 :1; + unsigned ADUTH11 :1; + unsigned ADUTH12 :1; + unsigned ADUTH13 :1; + unsigned ADUTH14 :1; + unsigned ADUTH15 :1; + }; + struct { + unsigned ADUTH :8; + }; + struct { + unsigned UTH8 :1; + unsigned UTH9 :1; + unsigned UTH10 :1; + unsigned UTH11 :1; + unsigned UTH12 :1; + unsigned UTH13 :1; + unsigned UTH14 :1; + unsigned UTH15 :1; + }; +} ADUTHHbits_t; +extern volatile ADUTHHbits_t ADUTHHbits __attribute__((address(0x3DC))); +# 54882 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADERR __attribute__((address(0x3DD))); + +__asm("ADERR equ 03DDh"); + + + + +extern volatile unsigned char ADERRL __attribute__((address(0x3DD))); + +__asm("ADERRL equ 03DDh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR0 :1; + unsigned ADERR1 :1; + unsigned ADERR2 :1; + unsigned ADERR3 :1; + unsigned ADERR4 :1; + unsigned ADERR5 :1; + unsigned ADERR6 :1; + unsigned ADERR7 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR0 :1; + unsigned ERR1 :1; + unsigned ERR2 :1; + unsigned ERR3 :1; + unsigned ERR4 :1; + unsigned ERR5 :1; + unsigned ERR6 :1; + unsigned ERR7 :1; + }; +} ADERRLbits_t; +extern volatile ADERRLbits_t ADERRLbits __attribute__((address(0x3DD))); +# 55017 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADERRH __attribute__((address(0x3DE))); + +__asm("ADERRH equ 03DEh"); + + +typedef union { + struct { + unsigned ERR :8; + }; + struct { + unsigned ADERR8 :1; + unsigned ADERR9 :1; + unsigned ADERR10 :1; + unsigned ADERR11 :1; + unsigned ADERR12 :1; + unsigned ADERR13 :1; + unsigned ADERR14 :1; + unsigned ADERR15 :1; + }; + struct { + unsigned ADERR :8; + }; + struct { + unsigned ERR8 :1; + unsigned ERR9 :1; + unsigned ERR10 :1; + unsigned ERR11 :1; + unsigned ERR12 :1; + unsigned ERR13 :1; + unsigned ERR14 :1; + unsigned ERR15 :1; + }; +} ADERRHbits_t; +extern volatile ADERRHbits_t ADERRHbits __attribute__((address(0x3DE))); +# 55145 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADSTPT __attribute__((address(0x3DF))); + +__asm("ADSTPT equ 03DFh"); + + + + +extern volatile unsigned char ADSTPTL __attribute__((address(0x3DF))); + +__asm("ADSTPTL equ 03DFh"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT0 :1; + unsigned ADSTPT1 :1; + unsigned ADSTPT2 :1; + unsigned ADSTPT3 :1; + unsigned ADSTPT4 :1; + unsigned ADSTPT5 :1; + unsigned ADSTPT6 :1; + unsigned ADSTPT7 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT0 :1; + unsigned STPT1 :1; + unsigned STPT2 :1; + unsigned STPT3 :1; + unsigned STPT4 :1; + unsigned STPT5 :1; + unsigned STPT6 :1; + unsigned STPT7 :1; + }; +} ADSTPTLbits_t; +extern volatile ADSTPTLbits_t ADSTPTLbits __attribute__((address(0x3DF))); +# 55280 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTPTH __attribute__((address(0x3E0))); + +__asm("ADSTPTH equ 03E0h"); + + +typedef union { + struct { + unsigned STPT :8; + }; + struct { + unsigned ADSTPT8 :1; + unsigned ADSTPT9 :1; + unsigned ADSTPT10 :1; + unsigned ADSTPT11 :1; + unsigned ADSTPT12 :1; + unsigned ADSTPT13 :1; + unsigned ADSTPT14 :1; + unsigned ADSTPT15 :1; + }; + struct { + unsigned ADSTPT :8; + }; + struct { + unsigned STPT8 :1; + unsigned STPT9 :1; + unsigned STPT10 :1; + unsigned STPT11 :1; + unsigned STPT12 :1; + unsigned STPT13 :1; + unsigned STPT15 :1; + unsigned STPT16 :1; + }; +} ADSTPTHbits_t; +extern volatile ADSTPTHbits_t ADSTPTHbits __attribute__((address(0x3E0))); +# 55408 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADFLTR __attribute__((address(0x3E1))); + +__asm("ADFLTR equ 03E1h"); + + + + +extern volatile unsigned char ADFLTRL __attribute__((address(0x3E1))); + +__asm("ADFLTRL equ 03E1h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR0 :1; + unsigned ADFLTR1 :1; + unsigned ADFLTR2 :1; + unsigned ADFLTR3 :1; + unsigned ADFLTR4 :1; + unsigned ADFLTR5 :1; + unsigned ADFLTR6 :1; + unsigned ADFLTR7 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR0 :1; + unsigned FLTR1 :1; + unsigned FLTR2 :1; + unsigned FLTR3 :1; + unsigned FLTR4 :1; + unsigned FLTR5 :1; + unsigned FLTR6 :1; + unsigned FLTR7 :1; + }; +} ADFLTRLbits_t; +extern volatile ADFLTRLbits_t ADFLTRLbits __attribute__((address(0x3E1))); +# 55543 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADFLTRH __attribute__((address(0x3E2))); + +__asm("ADFLTRH equ 03E2h"); + + +typedef union { + struct { + unsigned FLTR :8; + }; + struct { + unsigned ADFLTR8 :1; + unsigned ADFLTR9 :1; + unsigned ADFLTR10 :1; + unsigned ADFLTR11 :1; + unsigned ADFLTR12 :1; + unsigned ADFLTR13 :1; + unsigned ADFLTR14 :1; + unsigned ADFLTR15 :1; + }; + struct { + unsigned ADFLTR :8; + }; + struct { + unsigned FLTR8 :1; + unsigned FLTR9 :1; + unsigned FLTR10 :1; + unsigned FLTR11 :1; + unsigned FLTR12 :1; + unsigned FLTR13 :1; + unsigned FLTR14 :1; + unsigned FLTR15 :1; + }; +} ADFLTRHbits_t; +extern volatile ADFLTRHbits_t ADFLTRHbits __attribute__((address(0x3E2))); +# 55672 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 ADACC __attribute__((address(0x3E3))); + + +__asm("ADACC equ 03E3h"); + + + + +extern volatile unsigned char ADACCL __attribute__((address(0x3E3))); + +__asm("ADACCL equ 03E3h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC0 :1; + unsigned ADACC1 :1; + unsigned ADACC2 :1; + unsigned ADACC3 :1; + unsigned ADACC4 :1; + unsigned ADACC5 :1; + unsigned ADACC6 :1; + unsigned ADACC7 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; +} ADACCLbits_t; +extern volatile ADACCLbits_t ADACCLbits __attribute__((address(0x3E3))); +# 55808 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCH __attribute__((address(0x3E4))); + +__asm("ADACCH equ 03E4h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC8 :1; + unsigned ADACC9 :1; + unsigned ADACC10 :1; + unsigned ADACC11 :1; + unsigned ADACC12 :1; + unsigned ADACC13 :1; + unsigned ADACC14 :1; + unsigned ADACC15 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; +} ADACCHbits_t; +extern volatile ADACCHbits_t ADACCHbits __attribute__((address(0x3E4))); +# 55936 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACCU __attribute__((address(0x3E5))); + +__asm("ADACCU equ 03E5h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned ADACC16 :1; + unsigned ADACC17 :1; + }; + struct { + unsigned ADACC :8; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + }; +} ADACCUbits_t; +extern volatile ADACCUbits_t ADACCUbits __attribute__((address(0x3E5))); +# 55992 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCNT __attribute__((address(0x3E6))); + +__asm("ADCNT equ 03E6h"); + + +typedef union { + struct { + unsigned CNT :8; + }; + struct { + unsigned ADCNT0 :1; + unsigned ADCNT1 :1; + unsigned ADCNT2 :1; + unsigned ADCNT3 :1; + unsigned ADCNT4 :1; + unsigned ADCNT5 :1; + unsigned ADCNT6 :1; + unsigned ADCNT7 :1; + }; + struct { + unsigned ADCNT :8; + }; + struct { + unsigned CNT0 :1; + unsigned CNT1 :1; + unsigned CNT2 :1; + unsigned CNT3 :1; + unsigned CNT4 :1; + unsigned CNT5 :1; + unsigned CNT6 :1; + unsigned CNT7 :1; + }; +} ADCNTbits_t; +extern volatile ADCNTbits_t ADCNTbits __attribute__((address(0x3E6))); +# 56120 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRPT __attribute__((address(0x3E7))); + +__asm("ADRPT equ 03E7h"); + + +typedef union { + struct { + unsigned RPT :8; + }; + struct { + unsigned ADRPT0 :1; + unsigned ADRPT1 :1; + unsigned ADRPT2 :1; + unsigned ADRPT3 :1; + unsigned ADRPT4 :1; + unsigned ADRPT5 :1; + unsigned ADRPT6 :1; + unsigned ADRPT7 :1; + }; + struct { + unsigned ADRPT :8; + }; + struct { + unsigned RPT0 :1; + unsigned RPT1 :1; + unsigned RPT2 :1; + unsigned RPT3 :1; + unsigned RPT4 :1; + unsigned RPT5 :1; + unsigned RPT6 :1; + unsigned RPT7 :1; + }; +} ADRPTbits_t; +extern volatile ADRPTbits_t ADRPTbits __attribute__((address(0x3E7))); +# 56248 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPREV __attribute__((address(0x3E8))); + +__asm("ADPREV equ 03E8h"); + + + + +extern volatile unsigned char ADPREVL __attribute__((address(0x3E8))); + +__asm("ADPREVL equ 03E8h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV0 :1; + unsigned ADPREV1 :1; + unsigned ADPREV2 :1; + unsigned ADPREV3 :1; + unsigned ADPREV4 :1; + unsigned ADPREV5 :1; + unsigned ADPREV6 :1; + unsigned ADPREV7 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV0 :1; + unsigned PREV1 :1; + unsigned PREV2 :1; + unsigned PREV3 :1; + unsigned PREV4 :1; + unsigned PREV5 :1; + unsigned PREV6 :1; + unsigned PREV7 :1; + }; +} ADPREVLbits_t; +extern volatile ADPREVLbits_t ADPREVLbits __attribute__((address(0x3E8))); +# 56383 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREVH __attribute__((address(0x3E9))); + +__asm("ADPREVH equ 03E9h"); + + +typedef union { + struct { + unsigned PREV :8; + }; + struct { + unsigned ADPREV8 :1; + unsigned ADPREV9 :1; + unsigned ADPREV10 :1; + unsigned ADPREV11 :1; + unsigned ADPREV12 :1; + unsigned ADPREV13 :1; + unsigned ADPREV14 :1; + unsigned ADPREV15 :1; + }; + struct { + unsigned ADPREV :8; + }; + struct { + unsigned PREV8 :1; + unsigned PREV9 :1; + unsigned PREV10 :1; + unsigned PREV11 :1; + unsigned PREV12 :1; + unsigned PREV13 :1; + unsigned PREV14 :1; + unsigned PREV15 :1; + }; +} ADPREVHbits_t; +extern volatile ADPREVHbits_t ADPREVHbits __attribute__((address(0x3E9))); +# 56511 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADRES __attribute__((address(0x3EA))); + +__asm("ADRES equ 03EAh"); + + + + +extern volatile unsigned char ADRESL __attribute__((address(0x3EA))); + +__asm("ADRESL equ 03EAh"); + + +typedef union { + struct { + unsigned RES :8; + }; + struct { + unsigned ADRES0 :1; + unsigned ADRES1 :1; + unsigned ADRES2 :1; + unsigned ADRES3 :1; + unsigned ADRES4 :1; + unsigned ADRES5 :1; + unsigned ADRES6 :1; + unsigned ADRES7 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES0 :1; + unsigned RES1 :1; + unsigned RES2 :1; + unsigned RES3 :1; + unsigned RES4 :1; + unsigned RES5 :1; + unsigned RES6 :1; + unsigned RES7 :1; + }; +} ADRESLbits_t; +extern volatile ADRESLbits_t ADRESLbits __attribute__((address(0x3EA))); +# 56646 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADRESH __attribute__((address(0x3EB))); + +__asm("ADRESH equ 03EBh"); + + +typedef union { + struct { + unsigned ADRES8 :1; + unsigned ADRES9 :1; + unsigned ADRES10 :1; + unsigned ADRES11 :1; + unsigned ADRES12 :1; + unsigned ADRES13 :1; + unsigned ADRES14 :1; + unsigned ADRES15 :1; + }; + struct { + unsigned ADRES :8; + }; + struct { + unsigned RES8 :1; + unsigned RES9 :1; + unsigned RES10 :1; + unsigned RES11 :1; + unsigned RES12 :1; + unsigned RES13 :1; + unsigned RES14 :1; + unsigned RES15 :1; + }; +} ADRESHbits_t; +extern volatile ADRESHbits_t ADRESHbits __attribute__((address(0x3EB))); +# 56766 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPCH __attribute__((address(0x3EC))); + +__asm("ADPCH equ 03ECh"); + + +typedef union { + struct { + unsigned ADPCH :6; + }; + struct { + unsigned ADPCH0 :1; + unsigned ADPCH1 :1; + unsigned ADPCH2 :1; + unsigned ADPCH3 :1; + unsigned ADPCH4 :1; + unsigned ADPCH5 :1; + }; +} ADPCHbits_t; +extern volatile ADPCHbits_t ADPCHbits __attribute__((address(0x3EC))); +# 56824 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADACQ __attribute__((address(0x3EE))); + +__asm("ADACQ equ 03EEh"); + + + + +extern volatile unsigned char ADACQL __attribute__((address(0x3EE))); + +__asm("ADACQL equ 03EEh"); + + +typedef union { + struct { + unsigned ACQ :8; + }; + struct { + unsigned ADACQ0 :1; + unsigned ADACQ1 :1; + unsigned ADACQ2 :1; + unsigned ADACQ3 :1; + unsigned ADACQ4 :1; + unsigned ADACQ5 :1; + unsigned ADACQ6 :1; + unsigned ADACQ7 :1; + }; + struct { + unsigned ADACQ :8; + }; + struct { + unsigned ACQ0 :1; + unsigned ACQ1 :1; + unsigned ACQ2 :1; + unsigned ACQ3 :1; + unsigned ACQ4 :1; + unsigned ACQ5 :1; + unsigned ACQ6 :1; + unsigned ACQ7 :1; + }; +} ADACQLbits_t; +extern volatile ADACQLbits_t ADACQLbits __attribute__((address(0x3EE))); +# 56959 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACQH __attribute__((address(0x3EF))); + +__asm("ADACQH equ 03EFh"); + + +typedef union { + struct { + unsigned ACQ :5; + }; + struct { + unsigned ADACQ8 :1; + unsigned ADACQ9 :1; + unsigned ADACQ10 :1; + unsigned ADACQ11 :1; + unsigned ADACQ12 :1; + }; + struct { + unsigned ADACQ :5; + }; + struct { + unsigned ACQ8 :1; + unsigned ACQ9 :1; + unsigned ACQ10 :1; + unsigned ACQ11 :1; + unsigned ACQ12 :1; + }; +} ADACQHbits_t; +extern volatile ADACQHbits_t ADACQHbits __attribute__((address(0x3EF))); +# 57051 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCAP __attribute__((address(0x3F0))); + +__asm("ADCAP equ 03F0h"); + + +typedef union { + struct { + unsigned ADCAP :5; + }; + struct { + unsigned ADCAP0 :1; + unsigned ADCAP1 :1; + unsigned ADCAP2 :1; + unsigned ADCAP3 :1; + unsigned ADCAP4 :1; + }; +} ADCAPbits_t; +extern volatile ADCAPbits_t ADCAPbits __attribute__((address(0x3F0))); +# 57103 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short ADPRE __attribute__((address(0x3F1))); + +__asm("ADPRE equ 03F1h"); + + + + +extern volatile unsigned char ADPREL __attribute__((address(0x3F1))); + +__asm("ADPREL equ 03F1h"); + + +typedef union { + struct { + unsigned PRE :8; + }; + struct { + unsigned PRE0 :1; + unsigned PRE1 :1; + unsigned PRE2 :1; + unsigned PRE3 :1; + unsigned PRE4 :1; + unsigned PRE5 :1; + unsigned PRE6 :1; + unsigned PRE7 :1; + }; + struct { + unsigned ADPRE :8; + }; + struct { + unsigned ADPRE0 :1; + unsigned ADPRE1 :1; + unsigned ADPRE2 :1; + unsigned ADPRE3 :1; + unsigned ADPRE4 :1; + unsigned ADPRE5 :1; + unsigned ADPRE6 :1; + unsigned ADPRE7 :1; + }; +} ADPRELbits_t; +extern volatile ADPRELbits_t ADPRELbits __attribute__((address(0x3F1))); +# 57238 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADPREH __attribute__((address(0x3F2))); + +__asm("ADPREH equ 03F2h"); + + +typedef union { + struct { + unsigned PRE :5; + }; + struct { + unsigned PRE8 :1; + unsigned PRE9 :1; + unsigned PRE10 :1; + unsigned PRE11 :1; + unsigned PRE12 :1; + }; + struct { + unsigned ADPRE :5; + }; + struct { + unsigned ADPRE8 :1; + unsigned ADPRE9 :1; + unsigned ADPRE10 :1; + unsigned ADPRE11 :1; + unsigned ADPRE12 :1; + }; +} ADPREHbits_t; +extern volatile ADPREHbits_t ADPREHbits __attribute__((address(0x3F2))); +# 57330 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON0 __attribute__((address(0x3F3))); + +__asm("ADCON0 equ 03F3h"); + + +typedef union { + struct { + unsigned GO :1; + unsigned :1; + unsigned FM :2; + unsigned CS :1; + unsigned CSEN :1; + unsigned CONT :1; + unsigned ON :1; + }; + struct { + unsigned ADGO :1; + unsigned :1; + unsigned ADFM :2; + unsigned ADCS :1; + unsigned ADCSEN :1; + unsigned ADCONT :1; + unsigned ADON :1; + }; + struct { + unsigned DONE :1; + unsigned :1; + unsigned FM0 :1; + }; + struct { + unsigned GO_NOT_DONE :1; + }; + struct { + unsigned GO_nDONE :1; + unsigned :1; + unsigned ADFM0 :1; + }; +} ADCON0bits_t; +extern volatile ADCON0bits_t ADCON0bits __attribute__((address(0x3F3))); +# 57458 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON1 __attribute__((address(0x3F4))); + +__asm("ADCON1 equ 03F4h"); + + +typedef union { + struct { + unsigned DSEN :1; + unsigned :4; + unsigned GPOL :1; + unsigned IPEN :1; + unsigned PPOL :1; + }; + struct { + unsigned ADDSEN :1; + unsigned :4; + unsigned ADGPOL :1; + unsigned ADIPEN :1; + unsigned ADPPOL :1; + }; +} ADCON1bits_t; +extern volatile ADCON1bits_t ADCON1bits __attribute__((address(0x3F4))); +# 57524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON2 __attribute__((address(0x3F5))); + +__asm("ADCON2 equ 03F5h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned ACLR :1; + unsigned CRS :3; + unsigned PSIS :1; + }; + struct { + unsigned ADMD0 :1; + unsigned ADMD1 :1; + unsigned ADMD2 :1; + unsigned ADACLR :1; + unsigned ADCRS0 :1; + unsigned ADCRS1 :1; + unsigned ADCRS2 :1; + unsigned ADPSIS :1; + }; + struct { + unsigned ADMD :3; + unsigned :1; + unsigned ADCRS :3; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + unsigned :1; + unsigned CRS0 :1; + unsigned CRS1 :1; + unsigned CRS2 :1; + }; + struct { + unsigned MD :3; + }; + struct { + unsigned MD0 :1; + unsigned MD1 :1; + unsigned MD2 :1; + }; + struct { + unsigned ADMODE :3; + }; +} ADCON2bits_t; +extern volatile ADCON2bits_t ADCON2bits __attribute__((address(0x3F5))); +# 57702 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCON3 __attribute__((address(0x3F6))); + +__asm("ADCON3 equ 03F6h"); + + +typedef union { + struct { + unsigned TMD :3; + unsigned SOI :1; + unsigned CALC :3; + }; + struct { + unsigned ADTMD0 :1; + unsigned ADTMD1 :1; + unsigned ADTMD2 :1; + unsigned ADSOI :1; + unsigned ADCALC0 :1; + unsigned ADCALC1 :1; + unsigned ADCALC2 :1; + }; + struct { + unsigned ADTMD :3; + unsigned :1; + unsigned ADCALC :3; + }; + struct { + unsigned TMD0 :1; + unsigned TMD1 :1; + unsigned TMD2 :1; + unsigned :1; + unsigned CALC0 :1; + unsigned CALC1 :1; + unsigned CALC2 :1; + }; +} ADCON3bits_t; +extern volatile ADCON3bits_t ADCON3bits __attribute__((address(0x3F6))); +# 57832 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADSTAT __attribute__((address(0x3F7))); + +__asm("ADSTAT equ 03F7h"); + + +typedef union { + struct { + unsigned STAT :3; + unsigned :1; + unsigned MATH :1; + unsigned LTHR :1; + unsigned UTHR :1; + unsigned OV :1; + }; + struct { + unsigned ADSTAT0 :1; + unsigned ADSTAT1 :1; + unsigned ADSTAT2 :1; + unsigned :1; + unsigned ADMATH :1; + unsigned ADLTHR :1; + unsigned ADUTHR :1; + unsigned ADAOV :1; + }; + struct { + unsigned ADSTAT :3; + unsigned :4; + unsigned ADOV :1; + }; + struct { + unsigned STAT0 :1; + unsigned STAT1 :1; + unsigned STAT2 :1; + }; +} ADSTATbits_t; +extern volatile ADSTATbits_t ADSTATbits __attribute__((address(0x3F7))); +# 57957 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADREF __attribute__((address(0x3F8))); + +__asm("ADREF equ 03F8h"); + + +typedef union { + struct { + unsigned PREF :4; + unsigned NREF :4; + }; + struct { + unsigned ADPREF :4; + unsigned ADNREF :4; + }; + struct { + unsigned PREF0 :1; + unsigned PREF1 :1; + unsigned :2; + unsigned NREF0 :1; + }; + struct { + unsigned ADPREF0 :1; + unsigned ADPREF1 :1; + unsigned :2; + unsigned ADNREF0 :1; + }; +} ADREFbits_t; +extern volatile ADREFbits_t ADREFbits __attribute__((address(0x3F8))); +# 58039 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADACT __attribute__((address(0x3F9))); + +__asm("ADACT equ 03F9h"); + + +typedef union { + struct { + unsigned ACT :6; + }; + struct { + unsigned ADACT0 :1; + unsigned ADACT1 :1; + unsigned ADACT2 :1; + unsigned ADACT3 :1; + unsigned ADACT4 :1; + unsigned ADACT5 :1; + }; + struct { + unsigned ADACT :6; + }; + struct { + unsigned ACT0 :1; + unsigned ACT1 :1; + unsigned ACT2 :1; + unsigned ACT3 :1; + unsigned ACT4 :1; + unsigned ACT5 :1; + }; +} ADACTbits_t; +extern volatile ADACTbits_t ADACTbits __attribute__((address(0x3F9))); +# 58143 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCLK __attribute__((address(0x3FA))); + +__asm("ADCLK equ 03FAh"); + + +typedef union { + struct { + unsigned CS :6; + }; + struct { + unsigned ADCS0 :1; + unsigned ADCS1 :1; + unsigned ADCS2 :1; + unsigned ADCS3 :1; + unsigned ADCS4 :1; + unsigned ADCS5 :1; + }; + struct { + unsigned ADCS :6; + }; + struct { + unsigned CS0 :1; + unsigned CS1 :1; + unsigned CS2 :1; + unsigned CS3 :1; + unsigned CS4 :1; + unsigned CS5 :1; + }; +} ADCLKbits_t; +extern volatile ADCLKbits_t ADCLKbits __attribute__((address(0x3FA))); +# 58247 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCTX __attribute__((address(0x3FB))); + +__asm("ADCTX equ 03FBh"); + + +typedef union { + struct { + unsigned CTX :2; + unsigned :5; + unsigned CTXSW :1; + }; + struct { + unsigned CTX0 :1; + unsigned CTX1 :1; + }; + struct { + unsigned ADCTX :2; + unsigned :5; + unsigned ADCTXSW :1; + }; + struct { + unsigned ADCTX0 :1; + unsigned ADCTX1 :1; + }; +} ADCTXbits_t; +extern volatile ADCTXbits_t ADCTXbits __attribute__((address(0x3FB))); +# 58317 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL1 __attribute__((address(0x3FC))); + +__asm("ADCSEL1 equ 03FCh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL1bits_t; +extern volatile ADCSEL1bits_t ADCSEL1bits __attribute__((address(0x3FC))); +# 58344 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL2 __attribute__((address(0x3FD))); + +__asm("ADCSEL2 equ 03FDh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL2bits_t; +extern volatile ADCSEL2bits_t ADCSEL2bits __attribute__((address(0x3FD))); +# 58371 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL3 __attribute__((address(0x3FE))); + +__asm("ADCSEL3 equ 03FEh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL3bits_t; +extern volatile ADCSEL3bits_t ADCSEL3bits __attribute__((address(0x3FE))); +# 58398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ADCSEL4 __attribute__((address(0x3FF))); + +__asm("ADCSEL4 equ 03FFh"); + + +typedef union { + struct { + unsigned :6; + unsigned SSI :1; + unsigned CHEN :1; + }; +} ADCSEL4bits_t; +extern volatile ADCSEL4bits_t ADCSEL4bits __attribute__((address(0x3FF))); +# 58425 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELA __attribute__((address(0x400))); + +__asm("ANSELA equ 0400h"); + + +typedef union { + struct { + unsigned ANSELA0 :1; + unsigned ANSELA1 :1; + unsigned ANSELA2 :1; + unsigned ANSELA3 :1; + unsigned ANSELA4 :1; + unsigned ANSELA5 :1; + unsigned ANSELA6 :1; + unsigned ANSELA7 :1; + }; +} ANSELAbits_t; +extern volatile ANSELAbits_t ANSELAbits __attribute__((address(0x400))); +# 58487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUA __attribute__((address(0x401))); + +__asm("WPUA equ 0401h"); + + +typedef union { + struct { + unsigned WPUA0 :1; + unsigned WPUA1 :1; + unsigned WPUA2 :1; + unsigned WPUA3 :1; + unsigned WPUA4 :1; + unsigned WPUA5 :1; + unsigned WPUA6 :1; + unsigned WPUA7 :1; + }; +} WPUAbits_t; +extern volatile WPUAbits_t WPUAbits __attribute__((address(0x401))); +# 58549 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONA __attribute__((address(0x402))); + +__asm("ODCONA equ 0402h"); + + +typedef union { + struct { + unsigned ODCA0 :1; + unsigned ODCA1 :1; + unsigned ODCA2 :1; + unsigned ODCA3 :1; + unsigned ODCA4 :1; + unsigned ODCA5 :1; + unsigned ODCA6 :1; + unsigned ODCA7 :1; + }; +} ODCONAbits_t; +extern volatile ODCONAbits_t ODCONAbits __attribute__((address(0x402))); +# 58611 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONA __attribute__((address(0x403))); + +__asm("SLRCONA equ 0403h"); + + +typedef union { + struct { + unsigned SLRA0 :1; + unsigned SLRA1 :1; + unsigned SLRA2 :1; + unsigned SLRA3 :1; + unsigned SLRA4 :1; + unsigned SLRA5 :1; + unsigned SLRA6 :1; + unsigned SLRA7 :1; + }; +} SLRCONAbits_t; +extern volatile SLRCONAbits_t SLRCONAbits __attribute__((address(0x403))); +# 58673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLA __attribute__((address(0x404))); + +__asm("INLVLA equ 0404h"); + + +typedef union { + struct { + unsigned INLVLA0 :1; + unsigned INLVLA1 :1; + unsigned INLVLA2 :1; + unsigned INLVLA3 :1; + unsigned INLVLA4 :1; + unsigned INLVLA5 :1; + unsigned INLVLA6 :1; + unsigned INLVLA7 :1; + }; +} INLVLAbits_t; +extern volatile INLVLAbits_t INLVLAbits __attribute__((address(0x404))); +# 58735 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAP __attribute__((address(0x405))); + +__asm("IOCAP equ 0405h"); + + +typedef union { + struct { + unsigned IOCAP0 :1; + unsigned IOCAP1 :1; + unsigned IOCAP2 :1; + unsigned IOCAP3 :1; + unsigned IOCAP4 :1; + unsigned IOCAP5 :1; + unsigned IOCAP6 :1; + unsigned IOCAP7 :1; + }; +} IOCAPbits_t; +extern volatile IOCAPbits_t IOCAPbits __attribute__((address(0x405))); +# 58797 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAN __attribute__((address(0x406))); + +__asm("IOCAN equ 0406h"); + + +typedef union { + struct { + unsigned IOCAN0 :1; + unsigned IOCAN1 :1; + unsigned IOCAN2 :1; + unsigned IOCAN3 :1; + unsigned IOCAN4 :1; + unsigned IOCAN5 :1; + unsigned IOCAN6 :1; + unsigned IOCAN7 :1; + }; +} IOCANbits_t; +extern volatile IOCANbits_t IOCANbits __attribute__((address(0x406))); +# 58859 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCAF __attribute__((address(0x407))); + +__asm("IOCAF equ 0407h"); + + +typedef union { + struct { + unsigned IOCAF0 :1; + unsigned IOCAF1 :1; + unsigned IOCAF2 :1; + unsigned IOCAF3 :1; + unsigned IOCAF4 :1; + unsigned IOCAF5 :1; + unsigned IOCAF6 :1; + unsigned IOCAF7 :1; + }; +} IOCAFbits_t; +extern volatile IOCAFbits_t IOCAFbits __attribute__((address(0x407))); +# 58921 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELB __attribute__((address(0x408))); + +__asm("ANSELB equ 0408h"); + + +typedef union { + struct { + unsigned ANSELB0 :1; + unsigned ANSELB1 :1; + unsigned ANSELB2 :1; + unsigned ANSELB3 :1; + unsigned ANSELB4 :1; + unsigned ANSELB5 :1; + unsigned ANSELB6 :1; + unsigned ANSELB7 :1; + }; +} ANSELBbits_t; +extern volatile ANSELBbits_t ANSELBbits __attribute__((address(0x408))); +# 58983 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUB __attribute__((address(0x409))); + +__asm("WPUB equ 0409h"); + + +typedef union { + struct { + unsigned WPUB0 :1; + unsigned WPUB1 :1; + unsigned WPUB2 :1; + unsigned WPUB3 :1; + unsigned WPUB4 :1; + unsigned WPUB5 :1; + unsigned WPUB6 :1; + unsigned WPUB7 :1; + }; +} WPUBbits_t; +extern volatile WPUBbits_t WPUBbits __attribute__((address(0x409))); +# 59045 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONB __attribute__((address(0x40A))); + +__asm("ODCONB equ 040Ah"); + + +typedef union { + struct { + unsigned ODCB0 :1; + unsigned ODCB1 :1; + unsigned ODCB2 :1; + unsigned ODCB3 :1; + unsigned ODCB4 :1; + unsigned ODCB5 :1; + unsigned ODCB6 :1; + unsigned ODCB7 :1; + }; +} ODCONBbits_t; +extern volatile ODCONBbits_t ODCONBbits __attribute__((address(0x40A))); +# 59107 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONB __attribute__((address(0x40B))); + +__asm("SLRCONB equ 040Bh"); + + +typedef union { + struct { + unsigned SLRB0 :1; + unsigned SLRB1 :1; + unsigned SLRB2 :1; + unsigned SLRB3 :1; + unsigned SLRB4 :1; + unsigned SLRB5 :1; + unsigned SLRB6 :1; + unsigned SLRB7 :1; + }; +} SLRCONBbits_t; +extern volatile SLRCONBbits_t SLRCONBbits __attribute__((address(0x40B))); +# 59169 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLB __attribute__((address(0x40C))); + +__asm("INLVLB equ 040Ch"); + + +typedef union { + struct { + unsigned INLVLB0 :1; + unsigned INLVLB1 :1; + unsigned INLVLB2 :1; + unsigned INLVLB3 :1; + unsigned INLVLB4 :1; + unsigned INLVLB5 :1; + unsigned INLVLB6 :1; + unsigned INLVLB7 :1; + }; +} INLVLBbits_t; +extern volatile INLVLBbits_t INLVLBbits __attribute__((address(0x40C))); +# 59231 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBP __attribute__((address(0x40D))); + +__asm("IOCBP equ 040Dh"); + + +typedef union { + struct { + unsigned IOCBP0 :1; + unsigned IOCBP1 :1; + unsigned IOCBP2 :1; + unsigned IOCBP3 :1; + unsigned IOCBP4 :1; + unsigned IOCBP5 :1; + unsigned IOCBP6 :1; + unsigned IOCBP7 :1; + }; +} IOCBPbits_t; +extern volatile IOCBPbits_t IOCBPbits __attribute__((address(0x40D))); +# 59293 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBN __attribute__((address(0x40E))); + +__asm("IOCBN equ 040Eh"); + + +typedef union { + struct { + unsigned IOCBN0 :1; + unsigned IOCBN1 :1; + unsigned IOCBN2 :1; + unsigned IOCBN3 :1; + unsigned IOCBN4 :1; + unsigned IOCBN5 :1; + unsigned IOCBN6 :1; + unsigned IOCBN7 :1; + }; +} IOCBNbits_t; +extern volatile IOCBNbits_t IOCBNbits __attribute__((address(0x40E))); +# 59355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCBF __attribute__((address(0x40F))); + +__asm("IOCBF equ 040Fh"); + + +typedef union { + struct { + unsigned IOCBF0 :1; + unsigned IOCBF1 :1; + unsigned IOCBF2 :1; + unsigned IOCBF3 :1; + unsigned IOCBF4 :1; + unsigned IOCBF5 :1; + unsigned IOCBF6 :1; + unsigned IOCBF7 :1; + }; +} IOCBFbits_t; +extern volatile IOCBFbits_t IOCBFbits __attribute__((address(0x40F))); +# 59417 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ANSELC __attribute__((address(0x410))); + +__asm("ANSELC equ 0410h"); + + +typedef union { + struct { + unsigned ANSELC0 :1; + unsigned ANSELC1 :1; + unsigned ANSELC2 :1; + unsigned ANSELC3 :1; + unsigned ANSELC4 :1; + unsigned ANSELC5 :1; + unsigned ANSELC6 :1; + unsigned ANSELC7 :1; + }; +} ANSELCbits_t; +extern volatile ANSELCbits_t ANSELCbits __attribute__((address(0x410))); +# 59479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUC __attribute__((address(0x411))); + +__asm("WPUC equ 0411h"); + + +typedef union { + struct { + unsigned WPUC0 :1; + unsigned WPUC1 :1; + unsigned WPUC2 :1; + unsigned WPUC3 :1; + unsigned WPUC4 :1; + unsigned WPUC5 :1; + unsigned WPUC6 :1; + unsigned WPUC7 :1; + }; +} WPUCbits_t; +extern volatile WPUCbits_t WPUCbits __attribute__((address(0x411))); +# 59541 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char ODCONC __attribute__((address(0x412))); + +__asm("ODCONC equ 0412h"); + + +typedef union { + struct { + unsigned ODCC0 :1; + unsigned ODCC1 :1; + unsigned ODCC2 :1; + unsigned ODCC3 :1; + unsigned ODCC4 :1; + unsigned ODCC5 :1; + unsigned ODCC6 :1; + unsigned ODCC7 :1; + }; +} ODCONCbits_t; +extern volatile ODCONCbits_t ODCONCbits __attribute__((address(0x412))); +# 59603 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char SLRCONC __attribute__((address(0x413))); + +__asm("SLRCONC equ 0413h"); + + +typedef union { + struct { + unsigned SLRC0 :1; + unsigned SLRC1 :1; + unsigned SLRC2 :1; + unsigned SLRC3 :1; + unsigned SLRC4 :1; + unsigned SLRC5 :1; + unsigned SLRC6 :1; + unsigned SLRC7 :1; + }; +} SLRCONCbits_t; +extern volatile SLRCONCbits_t SLRCONCbits __attribute__((address(0x413))); +# 59665 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLC __attribute__((address(0x414))); + +__asm("INLVLC equ 0414h"); + + +typedef union { + struct { + unsigned INLVLC0 :1; + unsigned INLVLC1 :1; + unsigned INLVLC2 :1; + unsigned INLVLC3 :1; + unsigned INLVLC4 :1; + unsigned INLVLC5 :1; + unsigned INLVLC6 :1; + unsigned INLVLC7 :1; + }; +} INLVLCbits_t; +extern volatile INLVLCbits_t INLVLCbits __attribute__((address(0x414))); +# 59727 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCP __attribute__((address(0x415))); + +__asm("IOCCP equ 0415h"); + + +typedef union { + struct { + unsigned IOCCP0 :1; + unsigned IOCCP1 :1; + unsigned IOCCP2 :1; + unsigned IOCCP3 :1; + unsigned IOCCP4 :1; + unsigned IOCCP5 :1; + unsigned IOCCP6 :1; + unsigned IOCCP7 :1; + }; +} IOCCPbits_t; +extern volatile IOCCPbits_t IOCCPbits __attribute__((address(0x415))); +# 59789 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCN __attribute__((address(0x416))); + +__asm("IOCCN equ 0416h"); + + +typedef union { + struct { + unsigned IOCCN0 :1; + unsigned IOCCN1 :1; + unsigned IOCCN2 :1; + unsigned IOCCN3 :1; + unsigned IOCCN4 :1; + unsigned IOCCN5 :1; + unsigned IOCCN6 :1; + unsigned IOCCN7 :1; + }; +} IOCCNbits_t; +extern volatile IOCCNbits_t IOCCNbits __attribute__((address(0x416))); +# 59851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCCF __attribute__((address(0x417))); + +__asm("IOCCF equ 0417h"); + + +typedef union { + struct { + unsigned IOCCF0 :1; + unsigned IOCCF1 :1; + unsigned IOCCF2 :1; + unsigned IOCCF3 :1; + unsigned IOCCF4 :1; + unsigned IOCCF5 :1; + unsigned IOCCF6 :1; + unsigned IOCCF7 :1; + }; +} IOCCFbits_t; +extern volatile IOCCFbits_t IOCCFbits __attribute__((address(0x417))); +# 59913 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WPUE __attribute__((address(0x421))); + +__asm("WPUE equ 0421h"); + + +typedef union { + struct { + unsigned :3; + unsigned WPUE3 :1; + }; +} WPUEbits_t; +extern volatile WPUEbits_t WPUEbits __attribute__((address(0x421))); +# 59934 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INLVLE __attribute__((address(0x424))); + +__asm("INLVLE equ 0424h"); + + +typedef union { + struct { + unsigned :3; + unsigned INLVLE3 :1; + }; +} INLVLEbits_t; +extern volatile INLVLEbits_t INLVLEbits __attribute__((address(0x424))); +# 59955 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEP __attribute__((address(0x425))); + +__asm("IOCEP equ 0425h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEP3 :1; + }; +} IOCEPbits_t; +extern volatile IOCEPbits_t IOCEPbits __attribute__((address(0x425))); +# 59976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEN __attribute__((address(0x426))); + +__asm("IOCEN equ 0426h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEN3 :1; + }; +} IOCENbits_t; +extern volatile IOCENbits_t IOCENbits __attribute__((address(0x426))); +# 59997 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IOCEF __attribute__((address(0x427))); + +__asm("IOCEF equ 0427h"); + + +typedef union { + struct { + unsigned :3; + unsigned IOCEF3 :1; + }; +} IOCEFbits_t; +extern volatile IOCEFbits_t IOCEFbits __attribute__((address(0x427))); +# 60019 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1ACC __attribute__((address(0x440))); + + +__asm("NCO1ACC equ 0440h"); + + + + +extern volatile unsigned char NCO1ACCL __attribute__((address(0x440))); + +__asm("NCO1ACCL equ 0440h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC0 :1; + unsigned NCO1ACC1 :1; + unsigned NCO1ACC2 :1; + unsigned NCO1ACC3 :1; + unsigned NCO1ACC4 :1; + unsigned NCO1ACC5 :1; + unsigned NCO1ACC6 :1; + unsigned NCO1ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCLbits_t; +extern volatile NCO1ACCLbits_t NCO1ACCLbits __attribute__((address(0x440))); +# 60155 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCH __attribute__((address(0x441))); + +__asm("NCO1ACCH equ 0441h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC8 :1; + unsigned NCO1ACC9 :1; + unsigned NCO1ACC10 :1; + unsigned NCO1ACC11 :1; + unsigned NCO1ACC12 :1; + unsigned NCO1ACC13 :1; + unsigned NCO1ACC14 :1; + unsigned NCO1ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCHbits_t; +extern volatile NCO1ACCHbits_t NCO1ACCHbits __attribute__((address(0x441))); +# 60283 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1ACCU __attribute__((address(0x442))); + +__asm("NCO1ACCU equ 0442h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO1ACC16 :1; + unsigned NCO1ACC17 :1; + unsigned NCO1ACC18 :1; + unsigned NCO1ACC19 :1; + unsigned NCO1ACC20 :1; + unsigned NCO1ACC21 :1; + unsigned NCO1ACC22 :1; + unsigned NCO1ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO1ACC :8; + }; +} NCO1ACCUbits_t; +extern volatile NCO1ACCUbits_t NCO1ACCUbits __attribute__((address(0x442))); +# 60412 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO1INC __attribute__((address(0x443))); + + +__asm("NCO1INC equ 0443h"); + + + + +extern volatile unsigned char NCO1INCL __attribute__((address(0x443))); + +__asm("NCO1INCL equ 0443h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC0 :1; + unsigned NCO1INC1 :1; + unsigned NCO1INC2 :1; + unsigned NCO1INC3 :1; + unsigned NCO1INC4 :1; + unsigned NCO1INC5 :1; + unsigned NCO1INC6 :1; + unsigned NCO1INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCLbits_t; +extern volatile NCO1INCLbits_t NCO1INCLbits __attribute__((address(0x443))); +# 60548 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCH __attribute__((address(0x444))); + +__asm("NCO1INCH equ 0444h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC8 :1; + unsigned NCO1INC9 :1; + unsigned NCO1INC10 :1; + unsigned NCO1INC11 :1; + unsigned NCO1INC12 :1; + unsigned NCO1INC13 :1; + unsigned NCO1INC14 :1; + unsigned NCO1INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCHbits_t; +extern volatile NCO1INCHbits_t NCO1INCHbits __attribute__((address(0x444))); +# 60676 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1INCU __attribute__((address(0x445))); + +__asm("NCO1INCU equ 0445h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO1INC16 :1; + unsigned NCO1INC17 :1; + unsigned NCO1INC18 :1; + unsigned NCO1INC19 :1; + unsigned NCO1INC20 :1; + unsigned NCO1INC21 :1; + unsigned NCO1INC22 :1; + unsigned NCO1INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO1INC :8; + }; +} NCO1INCUbits_t; +extern volatile NCO1INCUbits_t NCO1INCUbits __attribute__((address(0x445))); +# 60804 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CON __attribute__((address(0x446))); + +__asm("NCO1CON equ 0446h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO1PFM :1; + unsigned :3; + unsigned NCO1POL :1; + unsigned NCO1OUT :1; + unsigned :1; + unsigned NCO1EN :1; + }; +} NCO1CONbits_t; +extern volatile NCO1CONbits_t NCO1CONbits __attribute__((address(0x446))); +# 60872 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO1CLK __attribute__((address(0x447))); + +__asm("NCO1CLK equ 0447h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO1CKS :4; + unsigned :1; + unsigned NCO1PWS :3; + }; + struct { + unsigned NCO1CKS0 :1; + unsigned NCO1CKS1 :1; + unsigned NCO1CKS2 :1; + unsigned NCO1CKS3 :1; + unsigned :1; + unsigned NCO1PWS0 :1; + unsigned NCO1PWS1 :1; + unsigned NCO1PWS2 :1; + }; +} NCO1CLKbits_t; +extern volatile NCO1CLKbits_t NCO1CLKbits __attribute__((address(0x447))); +# 61005 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2ACC __attribute__((address(0x448))); + + +__asm("NCO2ACC equ 0448h"); + + + + +extern volatile unsigned char NCO2ACCL __attribute__((address(0x448))); + +__asm("NCO2ACCL equ 0448h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC0 :1; + unsigned NCO2ACC1 :1; + unsigned NCO2ACC2 :1; + unsigned NCO2ACC3 :1; + unsigned NCO2ACC4 :1; + unsigned NCO2ACC5 :1; + unsigned NCO2ACC6 :1; + unsigned NCO2ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCLbits_t; +extern volatile NCO2ACCLbits_t NCO2ACCLbits __attribute__((address(0x448))); +# 61141 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCH __attribute__((address(0x449))); + +__asm("NCO2ACCH equ 0449h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC8 :1; + unsigned NCO2ACC9 :1; + unsigned NCO2ACC10 :1; + unsigned NCO2ACC11 :1; + unsigned NCO2ACC12 :1; + unsigned NCO2ACC13 :1; + unsigned NCO2ACC14 :1; + unsigned NCO2ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCHbits_t; +extern volatile NCO2ACCHbits_t NCO2ACCHbits __attribute__((address(0x449))); +# 61269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2ACCU __attribute__((address(0x44A))); + +__asm("NCO2ACCU equ 044Ah"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO2ACC16 :1; + unsigned NCO2ACC17 :1; + unsigned NCO2ACC18 :1; + unsigned NCO2ACC19 :1; + unsigned NCO2ACC20 :1; + unsigned NCO2ACC21 :1; + unsigned NCO2ACC22 :1; + unsigned NCO2ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO2ACC :8; + }; +} NCO2ACCUbits_t; +extern volatile NCO2ACCUbits_t NCO2ACCUbits __attribute__((address(0x44A))); +# 61398 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO2INC __attribute__((address(0x44B))); + + +__asm("NCO2INC equ 044Bh"); + + + + +extern volatile unsigned char NCO2INCL __attribute__((address(0x44B))); + +__asm("NCO2INCL equ 044Bh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC0 :1; + unsigned NCO2INC1 :1; + unsigned NCO2INC2 :1; + unsigned NCO2INC3 :1; + unsigned NCO2INC4 :1; + unsigned NCO2INC5 :1; + unsigned NCO2INC6 :1; + unsigned NCO2INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCLbits_t; +extern volatile NCO2INCLbits_t NCO2INCLbits __attribute__((address(0x44B))); +# 61534 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCH __attribute__((address(0x44C))); + +__asm("NCO2INCH equ 044Ch"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC8 :1; + unsigned NCO2INC9 :1; + unsigned NCO2INC10 :1; + unsigned NCO2INC11 :1; + unsigned NCO2INC12 :1; + unsigned NCO2INC13 :1; + unsigned NCO2INC14 :1; + unsigned NCO2INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCHbits_t; +extern volatile NCO2INCHbits_t NCO2INCHbits __attribute__((address(0x44C))); +# 61662 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2INCU __attribute__((address(0x44D))); + +__asm("NCO2INCU equ 044Dh"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO2INC16 :1; + unsigned NCO2INC17 :1; + unsigned NCO2INC18 :1; + unsigned NCO2INC19 :1; + unsigned NCO2INC20 :1; + unsigned NCO2INC21 :1; + unsigned NCO2INC22 :1; + unsigned NCO2INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO2INC :8; + }; +} NCO2INCUbits_t; +extern volatile NCO2INCUbits_t NCO2INCUbits __attribute__((address(0x44D))); +# 61790 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CON __attribute__((address(0x44E))); + +__asm("NCO2CON equ 044Eh"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO2PFM :1; + unsigned :3; + unsigned NCO2POL :1; + unsigned NCO2OUT :1; + unsigned :1; + unsigned NCO2EN :1; + }; +} NCO2CONbits_t; +extern volatile NCO2CONbits_t NCO2CONbits __attribute__((address(0x44E))); +# 61858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO2CLK __attribute__((address(0x44F))); + +__asm("NCO2CLK equ 044Fh"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO2CKS :4; + unsigned :1; + unsigned NCO2PWS :3; + }; + struct { + unsigned NCO2CKS0 :1; + unsigned NCO2CKS1 :1; + unsigned NCO2CKS2 :1; + unsigned NCO2CKS3 :1; + unsigned :1; + unsigned NCO2PWS0 :1; + unsigned NCO2PWS1 :1; + unsigned NCO2PWS2 :1; + }; +} NCO2CLKbits_t; +extern volatile NCO2CLKbits_t NCO2CLKbits __attribute__((address(0x44F))); +# 61991 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3ACC __attribute__((address(0x450))); + + +__asm("NCO3ACC equ 0450h"); + + + + +extern volatile unsigned char NCO3ACCL __attribute__((address(0x450))); + +__asm("NCO3ACCL equ 0450h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC0 :1; + unsigned NCO3ACC1 :1; + unsigned NCO3ACC2 :1; + unsigned NCO3ACC3 :1; + unsigned NCO3ACC4 :1; + unsigned NCO3ACC5 :1; + unsigned NCO3ACC6 :1; + unsigned NCO3ACC7 :1; + }; + struct { + unsigned ACC0 :1; + unsigned ACC1 :1; + unsigned ACC2 :1; + unsigned ACC3 :1; + unsigned ACC4 :1; + unsigned ACC5 :1; + unsigned ACC6 :1; + unsigned ACC7 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCLbits_t; +extern volatile NCO3ACCLbits_t NCO3ACCLbits __attribute__((address(0x450))); +# 62127 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCH __attribute__((address(0x451))); + +__asm("NCO3ACCH equ 0451h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC8 :1; + unsigned NCO3ACC9 :1; + unsigned NCO3ACC10 :1; + unsigned NCO3ACC11 :1; + unsigned NCO3ACC12 :1; + unsigned NCO3ACC13 :1; + unsigned NCO3ACC14 :1; + unsigned NCO3ACC15 :1; + }; + struct { + unsigned ACC8 :1; + unsigned ACC9 :1; + unsigned ACC10 :1; + unsigned ACC11 :1; + unsigned ACC12 :1; + unsigned ACC13 :1; + unsigned ACC14 :1; + unsigned ACC15 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCHbits_t; +extern volatile NCO3ACCHbits_t NCO3ACCHbits __attribute__((address(0x451))); +# 62255 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3ACCU __attribute__((address(0x452))); + +__asm("NCO3ACCU equ 0452h"); + + +typedef union { + struct { + unsigned ACC :8; + }; + struct { + unsigned NCO3ACC16 :1; + unsigned NCO3ACC17 :1; + unsigned NCO3ACC18 :1; + unsigned NCO3ACC19 :1; + unsigned NCO3ACC20 :1; + unsigned NCO3ACC21 :1; + unsigned NCO3ACC22 :1; + unsigned NCO3ACC23 :1; + }; + struct { + unsigned ACC16 :1; + unsigned ACC17 :1; + unsigned ACC18 :1; + unsigned ACC19 :1; + unsigned ACC20 :1; + unsigned ACC21 :1; + unsigned ACC22 :1; + unsigned ACC23 :1; + }; + struct { + unsigned NCO3ACC :8; + }; +} NCO3ACCUbits_t; +extern volatile NCO3ACCUbits_t NCO3ACCUbits __attribute__((address(0x452))); +# 62384 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 NCO3INC __attribute__((address(0x453))); + + +__asm("NCO3INC equ 0453h"); + + + + +extern volatile unsigned char NCO3INCL __attribute__((address(0x453))); + +__asm("NCO3INCL equ 0453h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC0 :1; + unsigned NCO3INC1 :1; + unsigned NCO3INC2 :1; + unsigned NCO3INC3 :1; + unsigned NCO3INC4 :1; + unsigned NCO3INC5 :1; + unsigned NCO3INC6 :1; + unsigned NCO3INC7 :1; + }; + struct { + unsigned INC0 :1; + unsigned INC1 :1; + unsigned INC2 :1; + unsigned INC3 :1; + unsigned INC4 :1; + unsigned INC5 :1; + unsigned INC6 :1; + unsigned INC7 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCLbits_t; +extern volatile NCO3INCLbits_t NCO3INCLbits __attribute__((address(0x453))); +# 62520 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCH __attribute__((address(0x454))); + +__asm("NCO3INCH equ 0454h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC8 :1; + unsigned NCO3INC9 :1; + unsigned NCO3INC10 :1; + unsigned NCO3INC11 :1; + unsigned NCO3INC12 :1; + unsigned NCO3INC13 :1; + unsigned NCO3INC14 :1; + unsigned NCO3INC15 :1; + }; + struct { + unsigned INC8 :1; + unsigned INC9 :1; + unsigned INC10 :1; + unsigned INC11 :1; + unsigned INC12 :1; + unsigned INC13 :1; + unsigned INC14 :1; + unsigned INC15 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCHbits_t; +extern volatile NCO3INCHbits_t NCO3INCHbits __attribute__((address(0x454))); +# 62648 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3INCU __attribute__((address(0x455))); + +__asm("NCO3INCU equ 0455h"); + + +typedef union { + struct { + unsigned INC :8; + }; + struct { + unsigned NCO3INC16 :1; + unsigned NCO3INC17 :1; + unsigned NCO3INC18 :1; + unsigned NCO3INC19 :1; + unsigned NCO3INC20 :1; + unsigned NCO3INC21 :1; + unsigned NCO3INC22 :1; + unsigned NCO3INC23 :1; + }; + struct { + unsigned INC16 :1; + unsigned INC17 :1; + unsigned INC18 :1; + unsigned INC19 :1; + unsigned INC20 :1; + unsigned INC21 :1; + unsigned INC22 :1; + unsigned INC23 :1; + }; + struct { + unsigned NCO3INC :8; + }; +} NCO3INCUbits_t; +extern volatile NCO3INCUbits_t NCO3INCUbits __attribute__((address(0x455))); +# 62776 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CON __attribute__((address(0x456))); + +__asm("NCO3CON equ 0456h"); + + +typedef union { + struct { + unsigned PFM :1; + unsigned :3; + unsigned POL :1; + unsigned OUT :1; + unsigned :1; + unsigned EN :1; + }; + struct { + unsigned NCO3PFM :1; + unsigned :3; + unsigned NCO3POL :1; + unsigned NCO3OUT :1; + unsigned :1; + unsigned NCO3EN :1; + }; +} NCO3CONbits_t; +extern volatile NCO3CONbits_t NCO3CONbits __attribute__((address(0x456))); +# 62844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char NCO3CLK __attribute__((address(0x457))); + +__asm("NCO3CLK equ 0457h"); + + +typedef union { + struct { + unsigned CKS :4; + unsigned :1; + unsigned PWS :3; + }; + struct { + unsigned CKS0 :1; + unsigned CKS1 :1; + unsigned CKS2 :1; + unsigned CKS3 :1; + unsigned :1; + unsigned PWS0 :1; + unsigned PWS1 :1; + unsigned PWS2 :1; + }; + struct { + unsigned NCO3CKS :4; + unsigned :1; + unsigned NCO3PWS :3; + }; + struct { + unsigned NCO3CKS0 :1; + unsigned NCO3CKS1 :1; + unsigned NCO3CKS2 :1; + unsigned NCO3CKS3 :1; + unsigned :1; + unsigned NCO3PWS0 :1; + unsigned NCO3PWS1 :1; + unsigned NCO3PWS2 :1; + }; +} NCO3CLKbits_t; +extern volatile NCO3CLKbits_t NCO3CLKbits __attribute__((address(0x457))); +# 62976 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSCMCON __attribute__((address(0x458))); + +__asm("FSCMCON equ 0458h"); + + +typedef union { + struct { + unsigned FSCMFEV :1; + unsigned FSCMFFI :1; + unsigned FSCMPEV :1; + unsigned FSCMPFI :1; + unsigned FSCMSEV :1; + unsigned FSCMSFI :1; + }; +} FSCMCONbits_t; +extern volatile FSCMCONbits_t FSCMCONbits __attribute__((address(0x458))); +# 63026 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTLOCK __attribute__((address(0x459))); + +__asm("IVTLOCK equ 0459h"); + + +typedef union { + struct { + unsigned IVTLOCKED :1; + }; +} IVTLOCKbits_t; +extern volatile IVTLOCKbits_t IVTLOCKbits __attribute__((address(0x459))); +# 63047 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTAD __attribute__((address(0x45A))); + + +__asm("IVTAD equ 045Ah"); + + + + +extern volatile unsigned char IVTADL __attribute__((address(0x45A))); + +__asm("IVTADL equ 045Ah"); + + +typedef union { + struct { + unsigned AD0 :1; + unsigned AD1 :1; + unsigned AD2 :1; + unsigned AD3 :1; + unsigned AD4 :1; + unsigned AD5 :1; + unsigned AD6 :1; + unsigned AD7 :1; + }; +} IVTADLbits_t; +extern volatile IVTADLbits_t IVTADLbits __attribute__((address(0x45A))); +# 63117 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADH __attribute__((address(0x45B))); + +__asm("IVTADH equ 045Bh"); + + +typedef union { + struct { + unsigned AD8 :1; + unsigned AD9 :1; + unsigned AD10 :1; + unsigned AD11 :1; + unsigned AD12 :1; + unsigned AD13 :1; + unsigned AD14 :1; + unsigned AD15 :1; + }; +} IVTADHbits_t; +extern volatile IVTADHbits_t IVTADHbits __attribute__((address(0x45B))); +# 63179 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTADU __attribute__((address(0x45C))); + +__asm("IVTADU equ 045Ch"); + + +typedef union { + struct { + unsigned AD16 :1; + unsigned AD17 :1; + unsigned AD18 :1; + unsigned AD19 :1; + unsigned AD20 :1; + }; +} IVTADUbits_t; +extern volatile IVTADUbits_t IVTADUbits __attribute__((address(0x45C))); +# 63224 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 IVTBASE __attribute__((address(0x45D))); + + +__asm("IVTBASE equ 045Dh"); + + + + +extern volatile unsigned char IVTBASEL __attribute__((address(0x45D))); + +__asm("IVTBASEL equ 045Dh"); + + +typedef union { + struct { + unsigned BASE0 :1; + unsigned BASE1 :1; + unsigned BASE2 :1; + unsigned BASE3 :1; + unsigned BASE4 :1; + unsigned BASE5 :1; + unsigned BASE6 :1; + unsigned BASE7 :1; + }; +} IVTBASELbits_t; +extern volatile IVTBASELbits_t IVTBASELbits __attribute__((address(0x45D))); +# 63294 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEH __attribute__((address(0x45E))); + +__asm("IVTBASEH equ 045Eh"); + + +typedef union { + struct { + unsigned BASE8 :1; + unsigned BASE9 :1; + unsigned BASE10 :1; + unsigned BASE11 :1; + unsigned BASE12 :1; + unsigned BASE13 :1; + unsigned BASE14 :1; + unsigned BASE15 :1; + }; +} IVTBASEHbits_t; +extern volatile IVTBASEHbits_t IVTBASEHbits __attribute__((address(0x45E))); +# 63356 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char IVTBASEU __attribute__((address(0x45F))); + +__asm("IVTBASEU equ 045Fh"); + + +typedef union { + struct { + unsigned BASE16 :1; + unsigned BASE17 :1; + unsigned BASE18 :1; + unsigned BASE19 :1; + unsigned BASE20 :1; + }; +} IVTBASEUbits_t; +extern volatile IVTBASEUbits_t IVTBASEUbits __attribute__((address(0x45F))); +# 63400 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1ERS __attribute__((address(0x460))); + +__asm("PWM1ERS equ 0460h"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM1ERSbits_t; +extern volatile PWM1ERSbits_t PWM1ERSbits __attribute__((address(0x460))); +# 63420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CLK __attribute__((address(0x461))); + +__asm("PWM1CLK equ 0461h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM1CLKbits_t; +extern volatile PWM1CLKbits_t PWM1CLKbits __attribute__((address(0x461))); +# 63440 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1LDS __attribute__((address(0x462))); + +__asm("PWM1LDS equ 0462h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM1LDSbits_t; +extern volatile PWM1LDSbits_t PWM1LDSbits __attribute__((address(0x462))); +# 63460 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1PR __attribute__((address(0x463))); + +__asm("PWM1PR equ 0463h"); + + + + +extern volatile unsigned char PWM1PRL __attribute__((address(0x463))); + +__asm("PWM1PRL equ 0463h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM1PRLbits_t; +extern volatile PWM1PRLbits_t PWM1PRLbits __attribute__((address(0x463))); +# 63487 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PRH __attribute__((address(0x464))); + +__asm("PWM1PRH equ 0464h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM1PRHbits_t; +extern volatile PWM1PRHbits_t PWM1PRHbits __attribute__((address(0x464))); +# 63507 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CPRE __attribute__((address(0x465))); + +__asm("PWM1CPRE equ 0465h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM1CPREbits_t; +extern volatile PWM1CPREbits_t PWM1CPREbits __attribute__((address(0x465))); +# 63527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1PIPOS __attribute__((address(0x466))); + +__asm("PWM1PIPOS equ 0466h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM1PIPOSbits_t; +extern volatile PWM1PIPOSbits_t PWM1PIPOSbits __attribute__((address(0x466))); +# 63547 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIR __attribute__((address(0x467))); + +__asm("PWM1GIR equ 0467h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM1GIRbits_t; +extern volatile PWM1GIRbits_t PWM1GIRbits __attribute__((address(0x467))); +# 63573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1GIE __attribute__((address(0x468))); + +__asm("PWM1GIE equ 0468h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM1GIEbits_t; +extern volatile PWM1GIEbits_t PWM1GIEbits __attribute__((address(0x468))); +# 63599 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1CON __attribute__((address(0x469))); + +__asm("PWM1CON equ 0469h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM1CONbits_t; +extern volatile PWM1CONbits_t PWM1CONbits __attribute__((address(0x469))); +# 63638 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1CFG __attribute__((address(0x46A))); + +__asm("PWM1S1CFG equ 046Ah"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM1S1CFGbits_t; +extern volatile PWM1S1CFGbits_t PWM1S1CFGbits __attribute__((address(0x46A))); +# 63697 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P1 __attribute__((address(0x46B))); + +__asm("PWM1S1P1 equ 046Bh"); + + + + +extern volatile unsigned char PWM1S1P1L __attribute__((address(0x46B))); + +__asm("PWM1S1P1L equ 046Bh"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM1S1P1Lbits_t; +extern volatile PWM1S1P1Lbits_t PWM1S1P1Lbits __attribute__((address(0x46B))); +# 63724 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P1H __attribute__((address(0x46C))); + +__asm("PWM1S1P1H equ 046Ch"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM1S1P1Hbits_t; +extern volatile PWM1S1P1Hbits_t PWM1S1P1Hbits __attribute__((address(0x46C))); +# 63744 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM1S1P2 __attribute__((address(0x46D))); + +__asm("PWM1S1P2 equ 046Dh"); + + + + +extern volatile unsigned char PWM1S1P2L __attribute__((address(0x46D))); + +__asm("PWM1S1P2L equ 046Dh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM1S1P2Lbits_t; +extern volatile PWM1S1P2Lbits_t PWM1S1P2Lbits __attribute__((address(0x46D))); +# 63771 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM1S1P2H __attribute__((address(0x46E))); + +__asm("PWM1S1P2H equ 046Eh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM1S1P2Hbits_t; +extern volatile PWM1S1P2Hbits_t PWM1S1P2Hbits __attribute__((address(0x46E))); +# 63791 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2ERS __attribute__((address(0x46F))); + +__asm("PWM2ERS equ 046Fh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM2ERSbits_t; +extern volatile PWM2ERSbits_t PWM2ERSbits __attribute__((address(0x46F))); +# 63811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CLK __attribute__((address(0x470))); + +__asm("PWM2CLK equ 0470h"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM2CLKbits_t; +extern volatile PWM2CLKbits_t PWM2CLKbits __attribute__((address(0x470))); +# 63831 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2LDS __attribute__((address(0x471))); + +__asm("PWM2LDS equ 0471h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM2LDSbits_t; +extern volatile PWM2LDSbits_t PWM2LDSbits __attribute__((address(0x471))); +# 63851 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2PR __attribute__((address(0x472))); + +__asm("PWM2PR equ 0472h"); + + + + +extern volatile unsigned char PWM2PRL __attribute__((address(0x472))); + +__asm("PWM2PRL equ 0472h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM2PRLbits_t; +extern volatile PWM2PRLbits_t PWM2PRLbits __attribute__((address(0x472))); +# 63878 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PRH __attribute__((address(0x473))); + +__asm("PWM2PRH equ 0473h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM2PRHbits_t; +extern volatile PWM2PRHbits_t PWM2PRHbits __attribute__((address(0x473))); +# 63898 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CPRE __attribute__((address(0x474))); + +__asm("PWM2CPRE equ 0474h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM2CPREbits_t; +extern volatile PWM2CPREbits_t PWM2CPREbits __attribute__((address(0x474))); +# 63918 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2PIPOS __attribute__((address(0x475))); + +__asm("PWM2PIPOS equ 0475h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM2PIPOSbits_t; +extern volatile PWM2PIPOSbits_t PWM2PIPOSbits __attribute__((address(0x475))); +# 63938 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIR __attribute__((address(0x476))); + +__asm("PWM2GIR equ 0476h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM2GIRbits_t; +extern volatile PWM2GIRbits_t PWM2GIRbits __attribute__((address(0x476))); +# 63964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2GIE __attribute__((address(0x477))); + +__asm("PWM2GIE equ 0477h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM2GIEbits_t; +extern volatile PWM2GIEbits_t PWM2GIEbits __attribute__((address(0x477))); +# 63990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2CON __attribute__((address(0x478))); + +__asm("PWM2CON equ 0478h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM2CONbits_t; +extern volatile PWM2CONbits_t PWM2CONbits __attribute__((address(0x478))); +# 64029 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1CFG __attribute__((address(0x479))); + +__asm("PWM2S1CFG equ 0479h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM2S1CFGbits_t; +extern volatile PWM2S1CFGbits_t PWM2S1CFGbits __attribute__((address(0x479))); +# 64088 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P1 __attribute__((address(0x47A))); + +__asm("PWM2S1P1 equ 047Ah"); + + + + +extern volatile unsigned char PWM2S1P1L __attribute__((address(0x47A))); + +__asm("PWM2S1P1L equ 047Ah"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM2S1P1Lbits_t; +extern volatile PWM2S1P1Lbits_t PWM2S1P1Lbits __attribute__((address(0x47A))); +# 64115 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P1H __attribute__((address(0x47B))); + +__asm("PWM2S1P1H equ 047Bh"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM2S1P1Hbits_t; +extern volatile PWM2S1P1Hbits_t PWM2S1P1Hbits __attribute__((address(0x47B))); +# 64135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM2S1P2 __attribute__((address(0x47C))); + +__asm("PWM2S1P2 equ 047Ch"); + + + + +extern volatile unsigned char PWM2S1P2L __attribute__((address(0x47C))); + +__asm("PWM2S1P2L equ 047Ch"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM2S1P2Lbits_t; +extern volatile PWM2S1P2Lbits_t PWM2S1P2Lbits __attribute__((address(0x47C))); +# 64162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM2S1P2H __attribute__((address(0x47D))); + +__asm("PWM2S1P2H equ 047Dh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM2S1P2Hbits_t; +extern volatile PWM2S1P2Hbits_t PWM2S1P2Hbits __attribute__((address(0x47D))); +# 64182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3ERS __attribute__((address(0x47E))); + +__asm("PWM3ERS equ 047Eh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM3ERSbits_t; +extern volatile PWM3ERSbits_t PWM3ERSbits __attribute__((address(0x47E))); +# 64202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CLK __attribute__((address(0x47F))); + +__asm("PWM3CLK equ 047Fh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM3CLKbits_t; +extern volatile PWM3CLKbits_t PWM3CLKbits __attribute__((address(0x47F))); +# 64222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3LDS __attribute__((address(0x480))); + +__asm("PWM3LDS equ 0480h"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM3LDSbits_t; +extern volatile PWM3LDSbits_t PWM3LDSbits __attribute__((address(0x480))); +# 64242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3PR __attribute__((address(0x481))); + +__asm("PWM3PR equ 0481h"); + + + + +extern volatile unsigned char PWM3PRL __attribute__((address(0x481))); + +__asm("PWM3PRL equ 0481h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM3PRLbits_t; +extern volatile PWM3PRLbits_t PWM3PRLbits __attribute__((address(0x481))); +# 64269 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PRH __attribute__((address(0x482))); + +__asm("PWM3PRH equ 0482h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM3PRHbits_t; +extern volatile PWM3PRHbits_t PWM3PRHbits __attribute__((address(0x482))); +# 64289 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CPRE __attribute__((address(0x483))); + +__asm("PWM3CPRE equ 0483h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM3CPREbits_t; +extern volatile PWM3CPREbits_t PWM3CPREbits __attribute__((address(0x483))); +# 64309 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3PIPOS __attribute__((address(0x484))); + +__asm("PWM3PIPOS equ 0484h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM3PIPOSbits_t; +extern volatile PWM3PIPOSbits_t PWM3PIPOSbits __attribute__((address(0x484))); +# 64329 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIR __attribute__((address(0x485))); + +__asm("PWM3GIR equ 0485h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM3GIRbits_t; +extern volatile PWM3GIRbits_t PWM3GIRbits __attribute__((address(0x485))); +# 64355 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3GIE __attribute__((address(0x486))); + +__asm("PWM3GIE equ 0486h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM3GIEbits_t; +extern volatile PWM3GIEbits_t PWM3GIEbits __attribute__((address(0x486))); +# 64381 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3CON __attribute__((address(0x487))); + +__asm("PWM3CON equ 0487h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM3CONbits_t; +extern volatile PWM3CONbits_t PWM3CONbits __attribute__((address(0x487))); +# 64420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1CFG __attribute__((address(0x488))); + +__asm("PWM3S1CFG equ 0488h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM3S1CFGbits_t; +extern volatile PWM3S1CFGbits_t PWM3S1CFGbits __attribute__((address(0x488))); +# 64479 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P1 __attribute__((address(0x489))); + +__asm("PWM3S1P1 equ 0489h"); + + + + +extern volatile unsigned char PWM3S1P1L __attribute__((address(0x489))); + +__asm("PWM3S1P1L equ 0489h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM3S1P1Lbits_t; +extern volatile PWM3S1P1Lbits_t PWM3S1P1Lbits __attribute__((address(0x489))); +# 64506 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P1H __attribute__((address(0x48A))); + +__asm("PWM3S1P1H equ 048Ah"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM3S1P1Hbits_t; +extern volatile PWM3S1P1Hbits_t PWM3S1P1Hbits __attribute__((address(0x48A))); +# 64526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM3S1P2 __attribute__((address(0x48B))); + +__asm("PWM3S1P2 equ 048Bh"); + + + + +extern volatile unsigned char PWM3S1P2L __attribute__((address(0x48B))); + +__asm("PWM3S1P2L equ 048Bh"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM3S1P2Lbits_t; +extern volatile PWM3S1P2Lbits_t PWM3S1P2Lbits __attribute__((address(0x48B))); +# 64553 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM3S1P2H __attribute__((address(0x48C))); + +__asm("PWM3S1P2H equ 048Ch"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM3S1P2Hbits_t; +extern volatile PWM3S1P2Hbits_t PWM3S1P2Hbits __attribute__((address(0x48C))); +# 64573 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4ERS __attribute__((address(0x48D))); + +__asm("PWM4ERS equ 048Dh"); + + +typedef union { + struct { + unsigned ERS :8; + }; +} PWM4ERSbits_t; +extern volatile PWM4ERSbits_t PWM4ERSbits __attribute__((address(0x48D))); +# 64593 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CLK __attribute__((address(0x48E))); + +__asm("PWM4CLK equ 048Eh"); + + +typedef union { + struct { + unsigned CLK :8; + }; +} PWM4CLKbits_t; +extern volatile PWM4CLKbits_t PWM4CLKbits __attribute__((address(0x48E))); +# 64613 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4LDS __attribute__((address(0x48F))); + +__asm("PWM4LDS equ 048Fh"); + + +typedef union { + struct { + unsigned LDS :8; + }; +} PWM4LDSbits_t; +extern volatile PWM4LDSbits_t PWM4LDSbits __attribute__((address(0x48F))); +# 64633 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4PR __attribute__((address(0x490))); + +__asm("PWM4PR equ 0490h"); + + + + +extern volatile unsigned char PWM4PRL __attribute__((address(0x490))); + +__asm("PWM4PRL equ 0490h"); + + +typedef union { + struct { + unsigned PRL :8; + }; +} PWM4PRLbits_t; +extern volatile PWM4PRLbits_t PWM4PRLbits __attribute__((address(0x490))); +# 64660 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PRH __attribute__((address(0x491))); + +__asm("PWM4PRH equ 0491h"); + + +typedef union { + struct { + unsigned PRH :8; + }; +} PWM4PRHbits_t; +extern volatile PWM4PRHbits_t PWM4PRHbits __attribute__((address(0x491))); +# 64680 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CPRE __attribute__((address(0x492))); + +__asm("PWM4CPRE equ 0492h"); + + +typedef union { + struct { + unsigned CPRE :8; + }; +} PWM4CPREbits_t; +extern volatile PWM4CPREbits_t PWM4CPREbits __attribute__((address(0x492))); +# 64700 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4PIPOS __attribute__((address(0x493))); + +__asm("PWM4PIPOS equ 0493h"); + + +typedef union { + struct { + unsigned PIPOS :8; + }; +} PWM4PIPOSbits_t; +extern volatile PWM4PIPOSbits_t PWM4PIPOSbits __attribute__((address(0x493))); +# 64720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIR __attribute__((address(0x494))); + +__asm("PWM4GIR equ 0494h"); + + +typedef union { + struct { + unsigned S1P1IF :1; + unsigned S1P2IF :1; + }; +} PWM4GIRbits_t; +extern volatile PWM4GIRbits_t PWM4GIRbits __attribute__((address(0x494))); +# 64746 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4GIE __attribute__((address(0x495))); + +__asm("PWM4GIE equ 0495h"); + + +typedef union { + struct { + unsigned S1P1IE :1; + unsigned S1P2IE :1; + }; +} PWM4GIEbits_t; +extern volatile PWM4GIEbits_t PWM4GIEbits __attribute__((address(0x495))); +# 64772 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4CON __attribute__((address(0x496))); + +__asm("PWM4CON equ 0496h"); + + +typedef union { + struct { + unsigned ERSNOW :1; + unsigned ERSPOL :1; + unsigned LD :1; + unsigned :4; + unsigned EN :1; + }; +} PWM4CONbits_t; +extern volatile PWM4CONbits_t PWM4CONbits __attribute__((address(0x496))); +# 64811 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1CFG __attribute__((address(0x497))); + +__asm("PWM4S1CFG equ 0497h"); + + +typedef union { + struct { + unsigned MODE :3; + unsigned PPEN :1; + unsigned :2; + unsigned POL1 :1; + unsigned POL2 :1; + }; + struct { + unsigned MODE0 :1; + unsigned MODE1 :1; + unsigned MODE2 :1; + }; +} PWM4S1CFGbits_t; +extern volatile PWM4S1CFGbits_t PWM4S1CFGbits __attribute__((address(0x497))); +# 64870 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P1 __attribute__((address(0x498))); + +__asm("PWM4S1P1 equ 0498h"); + + + + +extern volatile unsigned char PWM4S1P1L __attribute__((address(0x498))); + +__asm("PWM4S1P1L equ 0498h"); + + +typedef union { + struct { + unsigned S1P1L :8; + }; +} PWM4S1P1Lbits_t; +extern volatile PWM4S1P1Lbits_t PWM4S1P1Lbits __attribute__((address(0x498))); +# 64897 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P1H __attribute__((address(0x499))); + +__asm("PWM4S1P1H equ 0499h"); + + +typedef union { + struct { + unsigned S1P1H :8; + }; +} PWM4S1P1Hbits_t; +extern volatile PWM4S1P1Hbits_t PWM4S1P1Hbits __attribute__((address(0x499))); +# 64917 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PWM4S1P2 __attribute__((address(0x49A))); + +__asm("PWM4S1P2 equ 049Ah"); + + + + +extern volatile unsigned char PWM4S1P2L __attribute__((address(0x49A))); + +__asm("PWM4S1P2L equ 049Ah"); + + +typedef union { + struct { + unsigned S1P2L :8; + }; +} PWM4S1P2Lbits_t; +extern volatile PWM4S1P2Lbits_t PWM4S1P2Lbits __attribute__((address(0x49A))); +# 64944 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWM4S1P2H __attribute__((address(0x49B))); + +__asm("PWM4S1P2H equ 049Bh"); + + +typedef union { + struct { + unsigned S1P2H :8; + }; +} PWM4S1P2Hbits_t; +extern volatile PWM4S1P2Hbits_t PWM4S1P2Hbits __attribute__((address(0x49B))); +# 64964 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMLOAD __attribute__((address(0x49C))); + +__asm("PWMLOAD equ 049Ch"); + + +typedef union { + struct { + unsigned PWM1LD :1; + unsigned PWM2LD :1; + unsigned PWM3LD :1; + unsigned PWM4LD :1; + }; +} PWMLOADbits_t; +extern volatile PWMLOADbits_t PWMLOADbits __attribute__((address(0x49C))); +# 65002 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PWMEN __attribute__((address(0x49D))); + +__asm("PWMEN equ 049Dh"); + + +typedef union { + struct { + unsigned PWM1EN :1; + unsigned PWM2EN :1; + unsigned PWM3EN :1; + unsigned PWM4EN :1; + }; +} PWMENbits_t; +extern volatile PWMENbits_t PWMENbits __attribute__((address(0x49D))); +# 65040 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE0 __attribute__((address(0x49E))); + +__asm("PIE0 equ 049Eh"); + + +typedef union { + struct { + unsigned SWIE :1; + unsigned HLVDIE :1; + unsigned OSFIE :1; + unsigned CSWIE :1; + unsigned TU16AIE :1; + unsigned CLC1IE :1; + unsigned CANIE :1; + unsigned IOCIE :1; + }; +} PIE0bits_t; +extern volatile PIE0bits_t PIE0bits __attribute__((address(0x49E))); +# 65102 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE1 __attribute__((address(0x49F))); + +__asm("PIE1 equ 049Fh"); + + +typedef union { + struct { + unsigned INT0IE :1; + unsigned ZCDIE :1; + unsigned ADIE :1; + unsigned ACTIE :1; + unsigned C1IE :1; + unsigned SMT1IE :1; + unsigned SMT1PRAIE :1; + unsigned SMT1PWAIE :1; + }; +} PIE1bits_t; +extern volatile PIE1bits_t PIE1bits __attribute__((address(0x49F))); +# 65164 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE2 __attribute__((address(0x4A0))); + +__asm("PIE2 equ 04A0h"); + + +typedef union { + struct { + unsigned ADTIE :1; + unsigned ADCH2IE :1; + unsigned ADCH3IE :1; + unsigned ADCH4IE :1; + unsigned DMA1SCNTIE :1; + unsigned DMA1DCNTIE :1; + unsigned DMA1ORIE :1; + unsigned DMA1AIE :1; + }; + struct { + unsigned ADCH1IE :1; + }; +} PIE2bits_t; +extern volatile PIE2bits_t PIE2bits __attribute__((address(0x4A0))); +# 65234 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE3 __attribute__((address(0x4A1))); + +__asm("PIE3 equ 04A1h"); + + +typedef union { + struct { + unsigned SPI1RXIE :1; + unsigned SPI1TXIE :1; + unsigned SPI1IE :1; + unsigned TMR2IE :1; + unsigned TMR1IE :1; + unsigned TMR1GIE :1; + unsigned CCP1IE :1; + unsigned TMR0IE :1; + }; +} PIE3bits_t; +extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +# 65296 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE4 __attribute__((address(0x4A2))); + +__asm("PIE4 equ 04A2h"); + + +typedef union { + struct { + unsigned U1RXIE :1; + unsigned U1TXIE :1; + unsigned U1EIE :1; + unsigned U1IE :1; + unsigned CANRXIE :1; + unsigned CANTXIE :1; + unsigned PWM1PIE :1; + unsigned PWM1IE :1; + }; +} PIE4bits_t; +extern volatile PIE4bits_t PIE4bits __attribute__((address(0x4A2))); +# 65358 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE5 __attribute__((address(0x4A3))); + +__asm("PIE5 equ 04A3h"); + + +typedef union { + struct { + unsigned SPI2RXIE :1; + unsigned SPI2TXIE :1; + unsigned SPI2IE :1; + unsigned TU16BIE :1; + unsigned TMR3IE :1; + unsigned TMR3GIE :1; + unsigned PWM2PIE :1; + unsigned PWM2IE :1; + }; +} PIE5bits_t; +extern volatile PIE5bits_t PIE5bits __attribute__((address(0x4A3))); +# 65420 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE6 __attribute__((address(0x4A4))); + +__asm("PIE6 equ 04A4h"); + + +typedef union { + struct { + unsigned INT1IE :1; + unsigned CLC2IE :1; + unsigned CWG1IE :1; + unsigned NCO1IE :1; + unsigned DMA2SCNTIE :1; + unsigned DMA2DCNTIE :1; + unsigned DMA2ORIE :1; + unsigned DMA2AIE :1; + }; +} PIE6bits_t; +extern volatile PIE6bits_t PIE6bits __attribute__((address(0x4A4))); +# 65482 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE7 __attribute__((address(0x4A5))); + +__asm("PIE7 equ 04A5h"); + + +typedef union { + struct { + unsigned I2C1RXIE :1; + unsigned I2C1TXIE :1; + unsigned I2C1IE :1; + unsigned I2C1EIE :1; + unsigned :1; + unsigned CLC3IE :1; + unsigned PWM3PIE :1; + unsigned PWM3IE :1; + }; +} PIE7bits_t; +extern volatile PIE7bits_t PIE7bits __attribute__((address(0x4A5))); +# 65539 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE8 __attribute__((address(0x4A6))); + +__asm("PIE8 equ 04A6h"); + + +typedef union { + struct { + unsigned U2RXIE :1; + unsigned U2TXIE :1; + unsigned U2EIE :1; + unsigned U2IE :1; + unsigned TMR5IE :1; + unsigned TMR5GIE :1; + unsigned CCP2IE :1; + unsigned SCANIE :1; + }; +} PIE8bits_t; +extern volatile PIE8bits_t PIE8bits __attribute__((address(0x4A6))); +# 65601 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE9 __attribute__((address(0x4A7))); + +__asm("PIE9 equ 04A7h"); + + +typedef union { + struct { + unsigned U3RXIE :1; + unsigned U3TXIE :1; + unsigned U3EIE :1; + unsigned U3IE :1; + unsigned :1; + unsigned CLC4IE :1; + unsigned PWM4PIE :1; + unsigned PWM4IE :1; + }; +} PIE9bits_t; +extern volatile PIE9bits_t PIE9bits __attribute__((address(0x4A7))); +# 65658 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE10 __attribute__((address(0x4A8))); + +__asm("PIE10 equ 04A8h"); + + +typedef union { + struct { + unsigned INT2IE :1; + unsigned CLC5IE :1; + unsigned CWG2IE :1; + unsigned NCO2IE :1; + unsigned DMA3SCNTIE :1; + unsigned DMA3DCNTIE :1; + unsigned DMA3ORIE :1; + unsigned DMA3AIE :1; + }; +} PIE10bits_t; +extern volatile PIE10bits_t PIE10bits __attribute__((address(0x4A8))); +# 65720 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE11 __attribute__((address(0x4A9))); + +__asm("PIE11 equ 04A9h"); + + +typedef union { + struct { + unsigned CCP3IE :1; + unsigned CLC6IE :1; + unsigned CWG3IE :1; + unsigned TMR4IE :1; + unsigned DMA4SCNTIE :1; + unsigned DMA4DCNTIE :1; + unsigned DMA4ORIE :1; + unsigned DMA4AIE :1; + }; +} PIE11bits_t; +extern volatile PIE11bits_t PIE11bits __attribute__((address(0x4A9))); +# 65782 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE12 __attribute__((address(0x4AA))); + +__asm("PIE12 equ 04AAh"); + + +typedef union { + struct { + unsigned U4RXIE :1; + unsigned U4TXIE :1; + unsigned U4EIE :1; + unsigned U4IE :1; + unsigned DMA5SCNTIE :1; + unsigned DMA5DCNTIE :1; + unsigned DMA5ORIE :1; + unsigned DMA5AIE :1; + }; +} PIE12bits_t; +extern volatile PIE12bits_t PIE12bits __attribute__((address(0x4AA))); +# 65844 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE13 __attribute__((address(0x4AB))); + +__asm("PIE13 equ 04ABh"); + + +typedef union { + struct { + unsigned U5RXIE :1; + unsigned U5TXIE :1; + unsigned U5EIE :1; + unsigned U5IE :1; + unsigned DMA6SCNTIE :1; + unsigned DMA6DCNTIE :1; + unsigned DMA6ORIE :1; + unsigned DMA6AIE :1; + }; +} PIE13bits_t; +extern volatile PIE13bits_t PIE13bits __attribute__((address(0x4AB))); +# 65906 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE14 __attribute__((address(0x4AC))); + +__asm("PIE14 equ 04ACh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IE :1; + unsigned C2IE :1; + unsigned NCO3IE :1; + unsigned DMA7SCNTIE :1; + unsigned DMA7DCNTIE :1; + unsigned DMA7ORIE :1; + unsigned DMA7AIE :1; + }; +} PIE14bits_t; +extern volatile PIE14bits_t PIE14bits __attribute__((address(0x4AC))); +# 65963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIE15 __attribute__((address(0x4AD))); + +__asm("PIE15 equ 04ADh"); + + +typedef union { + struct { + unsigned NVMIE :1; + unsigned CLC8IE :1; + unsigned CRCIE :1; + unsigned TMR6IE :1; + unsigned DMA8SCNTIE :1; + unsigned DMA8DCNTIE :1; + unsigned DMA8ORIE :1; + unsigned DMA8AIE :1; + }; +} PIE15bits_t; +extern volatile PIE15bits_t PIE15bits __attribute__((address(0x4AD))); +# 66025 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR0 __attribute__((address(0x4AE))); + +__asm("PIR0 equ 04AEh"); + + +typedef union { + struct { + unsigned SWIF :1; + unsigned HLVDIF :1; + unsigned OSFIF :1; + unsigned CSWIF :1; + unsigned TU16AIF :1; + unsigned CLC1IF :1; + unsigned CANIF :1; + unsigned IOCIF :1; + }; +} PIR0bits_t; +extern volatile PIR0bits_t PIR0bits __attribute__((address(0x4AE))); +# 66087 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR1 __attribute__((address(0x4AF))); + +__asm("PIR1 equ 04AFh"); + + +typedef union { + struct { + unsigned INT0IF :1; + unsigned ZCDIF :1; + unsigned ADIF :1; + unsigned ACTIF :1; + unsigned C1IF :1; + unsigned SMT1IF :1; + unsigned SMT1PRAIF :1; + unsigned SMT1PWAIF :1; + }; +} PIR1bits_t; +extern volatile PIR1bits_t PIR1bits __attribute__((address(0x4AF))); +# 66149 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR2 __attribute__((address(0x4B0))); + +__asm("PIR2 equ 04B0h"); + + +typedef union { + struct { + unsigned ADTIF :1; + unsigned ADCH2IF :1; + unsigned ADCH3IF :1; + unsigned ADCH4IF :1; + unsigned DMA1SCNTIF :1; + unsigned DMA1DCNTIF :1; + unsigned DMA1ORIF :1; + unsigned DMA1AIF :1; + }; + struct { + unsigned ADCH1IF :1; + }; +} PIR2bits_t; +extern volatile PIR2bits_t PIR2bits __attribute__((address(0x4B0))); +# 66219 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR3 __attribute__((address(0x4B1))); + +__asm("PIR3 equ 04B1h"); + + +typedef union { + struct { + unsigned SPI1RXIF :1; + unsigned SPI1TXIF :1; + unsigned SPI1IF :1; + unsigned TMR2IF :1; + unsigned TMR1IF :1; + unsigned TMR1GIF :1; + unsigned CCP1IF :1; + unsigned TMR0IF :1; + }; +} PIR3bits_t; +extern volatile PIR3bits_t PIR3bits __attribute__((address(0x4B1))); +# 66281 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR4 __attribute__((address(0x4B2))); + +__asm("PIR4 equ 04B2h"); + + +typedef union { + struct { + unsigned U1RXIF :1; + unsigned U1TXIF :1; + unsigned U1EIF :1; + unsigned U1IF :1; + unsigned CANRXIF :1; + unsigned CANTXIF :1; + unsigned PWM1PIF :1; + unsigned PWM1IF :1; + }; +} PIR4bits_t; +extern volatile PIR4bits_t PIR4bits __attribute__((address(0x4B2))); +# 66343 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR5 __attribute__((address(0x4B3))); + +__asm("PIR5 equ 04B3h"); + + +typedef union { + struct { + unsigned SPI2RXIF :1; + unsigned SPI2TXIF :1; + unsigned SPI2IF :1; + unsigned TU16BIF :1; + unsigned TMR3IF :1; + unsigned TMR3GIF :1; + unsigned PWM2PIF :1; + unsigned PWM2IF :1; + }; +} PIR5bits_t; +extern volatile PIR5bits_t PIR5bits __attribute__((address(0x4B3))); +# 66405 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR6 __attribute__((address(0x4B4))); + +__asm("PIR6 equ 04B4h"); + + +typedef union { + struct { + unsigned INT1IF :1; + unsigned CLC2IF :1; + unsigned CWG1IF :1; + unsigned NCO1IF :1; + unsigned DMA2SCNTIF :1; + unsigned DMA2DCNTIF :1; + unsigned DMA2ORIF :1; + unsigned DMA2AIF :1; + }; +} PIR6bits_t; +extern volatile PIR6bits_t PIR6bits __attribute__((address(0x4B4))); +# 66467 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR7 __attribute__((address(0x4B5))); + +__asm("PIR7 equ 04B5h"); + + +typedef union { + struct { + unsigned I2C1RXIF :1; + unsigned I2C1TXIF :1; + unsigned I2C1IF :1; + unsigned I2C1EIF :1; + unsigned :1; + unsigned CLC3IF :1; + unsigned PWM3PIF :1; + unsigned PWM3IF :1; + }; +} PIR7bits_t; +extern volatile PIR7bits_t PIR7bits __attribute__((address(0x4B5))); +# 66524 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR8 __attribute__((address(0x4B6))); + +__asm("PIR8 equ 04B6h"); + + +typedef union { + struct { + unsigned U2RXIF :1; + unsigned U2TXIF :1; + unsigned U2EIF :1; + unsigned U2IF :1; + unsigned TMR5IF :1; + unsigned TMR5GIF :1; + unsigned CCP2IF :1; + unsigned SCANIF :1; + }; +} PIR8bits_t; +extern volatile PIR8bits_t PIR8bits __attribute__((address(0x4B6))); +# 66586 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR9 __attribute__((address(0x4B7))); + +__asm("PIR9 equ 04B7h"); + + +typedef union { + struct { + unsigned U3RXIF :1; + unsigned U3TXIF :1; + unsigned U3EIF :1; + unsigned U3IF :1; + unsigned :1; + unsigned CLC4IF :1; + unsigned PWM4PIF :1; + unsigned PWM4IF :1; + }; +} PIR9bits_t; +extern volatile PIR9bits_t PIR9bits __attribute__((address(0x4B7))); +# 66643 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR10 __attribute__((address(0x4B8))); + +__asm("PIR10 equ 04B8h"); + + +typedef union { + struct { + unsigned INT2IF :1; + unsigned CLC5IF :1; + unsigned CWG2IF :1; + unsigned NCO2IF :1; + unsigned DMA3SCNTIF :1; + unsigned DMA3DCNTIF :1; + unsigned DMA3ORIF :1; + unsigned DMA3AIF :1; + }; +} PIR10bits_t; +extern volatile PIR10bits_t PIR10bits __attribute__((address(0x4B8))); +# 66705 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR11 __attribute__((address(0x4B9))); + +__asm("PIR11 equ 04B9h"); + + +typedef union { + struct { + unsigned CCP3IF :1; + unsigned CLC6IF :1; + unsigned CWG3IF :1; + unsigned TMR4IF :1; + unsigned DMA4SCNTIF :1; + unsigned DMA4DCNTIF :1; + unsigned DMA4ORIF :1; + unsigned DMA4AIF :1; + }; +} PIR11bits_t; +extern volatile PIR11bits_t PIR11bits __attribute__((address(0x4B9))); +# 66767 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR12 __attribute__((address(0x4BA))); + +__asm("PIR12 equ 04BAh"); + + +typedef union { + struct { + unsigned U4RXIF :1; + unsigned U4TXIF :1; + unsigned U4EIF :1; + unsigned U4IF :1; + unsigned DMA5SCNTIF :1; + unsigned DMA5DCNTIF :1; + unsigned DMA5ORIF :1; + unsigned DMA5AIF :1; + }; +} PIR12bits_t; +extern volatile PIR12bits_t PIR12bits __attribute__((address(0x4BA))); +# 66829 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR13 __attribute__((address(0x4BB))); + +__asm("PIR13 equ 04BBh"); + + +typedef union { + struct { + unsigned U5RXIF :1; + unsigned U5TXIF :1; + unsigned U5EIF :1; + unsigned U5IF :1; + unsigned DMA6SCNTIF :1; + unsigned DMA6DCNTIF :1; + unsigned DMA6ORIF :1; + unsigned DMA6AIF :1; + }; +} PIR13bits_t; +extern volatile PIR13bits_t PIR13bits __attribute__((address(0x4BB))); +# 66891 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR14 __attribute__((address(0x4BC))); + +__asm("PIR14 equ 04BCh"); + + +typedef union { + struct { + unsigned :1; + unsigned CLC7IF :1; + unsigned C2IF :1; + unsigned NCO3IF :1; + unsigned DMA7SCNTIF :1; + unsigned DMA7DCNTIF :1; + unsigned DMA7ORIF :1; + unsigned DMA7AIF :1; + }; +} PIR14bits_t; +extern volatile PIR14bits_t PIR14bits __attribute__((address(0x4BC))); +# 66948 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PIR15 __attribute__((address(0x4BD))); + +__asm("PIR15 equ 04BDh"); + + +typedef union { + struct { + unsigned NVMIF :1; + unsigned CLC8IF :1; + unsigned CRCIF :1; + unsigned TMR6IF :1; + unsigned DMA8SCNTIF :1; + unsigned DMA8DCNTIF :1; + unsigned DMA8ORIF :1; + unsigned DMA8AIF :1; + }; +} PIR15bits_t; +extern volatile PIR15bits_t PIR15bits __attribute__((address(0x4BD))); +# 67010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATA __attribute__((address(0x4BE))); + +__asm("LATA equ 04BEh"); + + +typedef union { + struct { + unsigned LATA0 :1; + unsigned LATA1 :1; + unsigned LATA2 :1; + unsigned LATA3 :1; + unsigned LATA4 :1; + unsigned LATA5 :1; + unsigned LATA6 :1; + unsigned LATA7 :1; + }; +} LATAbits_t; +extern volatile LATAbits_t LATAbits __attribute__((address(0x4BE))); +# 67072 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATB __attribute__((address(0x4BF))); + +__asm("LATB equ 04BFh"); + + +typedef union { + struct { + unsigned LATB0 :1; + unsigned LATB1 :1; + unsigned LATB2 :1; + unsigned LATB3 :1; + unsigned LATB4 :1; + unsigned LATB5 :1; + unsigned LATB6 :1; + unsigned LATB7 :1; + }; +} LATBbits_t; +extern volatile LATBbits_t LATBbits __attribute__((address(0x4BF))); +# 67134 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char LATC __attribute__((address(0x4C0))); + +__asm("LATC equ 04C0h"); + + +typedef union { + struct { + unsigned LATC0 :1; + unsigned LATC1 :1; + unsigned LATC2 :1; + unsigned LATC3 :1; + unsigned LATC4 :1; + unsigned LATC5 :1; + unsigned LATC6 :1; + unsigned LATC7 :1; + }; +} LATCbits_t; +extern volatile LATCbits_t LATCbits __attribute__((address(0x4C0))); +# 67196 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISA __attribute__((address(0x4C6))); + +__asm("TRISA equ 04C6h"); + + +typedef union { + struct { + unsigned TRISA0 :1; + unsigned TRISA1 :1; + unsigned TRISA2 :1; + unsigned TRISA3 :1; + unsigned TRISA4 :1; + unsigned TRISA5 :1; + unsigned TRISA6 :1; + unsigned TRISA7 :1; + }; +} TRISAbits_t; +extern volatile TRISAbits_t TRISAbits __attribute__((address(0x4C6))); +# 67258 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISB __attribute__((address(0x4C7))); + +__asm("TRISB equ 04C7h"); + + +typedef union { + struct { + unsigned TRISB0 :1; + unsigned TRISB1 :1; + unsigned TRISB2 :1; + unsigned TRISB3 :1; + unsigned TRISB4 :1; + unsigned TRISB5 :1; + unsigned TRISB6 :1; + unsigned TRISB7 :1; + }; +} TRISBbits_t; +extern volatile TRISBbits_t TRISBbits __attribute__((address(0x4C7))); +# 67320 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISC __attribute__((address(0x4C8))); + +__asm("TRISC equ 04C8h"); + + +typedef union { + struct { + unsigned TRISC0 :1; + unsigned TRISC1 :1; + unsigned TRISC2 :1; + unsigned TRISC3 :1; + unsigned TRISC4 :1; + unsigned TRISC5 :1; + unsigned TRISC6 :1; + unsigned TRISC7 :1; + }; +} TRISCbits_t; +extern volatile TRISCbits_t TRISCbits __attribute__((address(0x4C8))); +# 67382 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TRISE __attribute__((address(0x4CA))); + +__asm("TRISE equ 04CAh"); + + +typedef union { + struct { + unsigned :3; + unsigned TRISE3 :1; + }; +} TRISEbits_t; +extern volatile TRISEbits_t TRISEbits __attribute__((address(0x4CA))); +# 67403 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTA __attribute__((address(0x4CE))); + +__asm("PORTA equ 04CEh"); + + +typedef union { + struct { + unsigned RA0 :1; + unsigned RA1 :1; + unsigned RA2 :1; + unsigned RA3 :1; + unsigned RA4 :1; + unsigned RA5 :1; + unsigned RA6 :1; + unsigned RA7 :1; + }; +} PORTAbits_t; +extern volatile PORTAbits_t PORTAbits __attribute__((address(0x4CE))); +# 67465 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTB __attribute__((address(0x4CF))); + +__asm("PORTB equ 04CFh"); + + +typedef union { + struct { + unsigned RB0 :1; + unsigned RB1 :1; + unsigned RB2 :1; + unsigned RB3 :1; + unsigned RB4 :1; + unsigned RB5 :1; + unsigned RB6 :1; + unsigned RB7 :1; + }; +} PORTBbits_t; +extern volatile PORTBbits_t PORTBbits __attribute__((address(0x4CF))); +# 67527 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTC __attribute__((address(0x4D0))); + +__asm("PORTC equ 04D0h"); + + +typedef union { + struct { + unsigned RC0 :1; + unsigned RC1 :1; + unsigned RC2 :1; + unsigned RC3 :1; + unsigned RC4 :1; + unsigned RC5 :1; + unsigned RC6 :1; + unsigned RC7 :1; + }; +} PORTCbits_t; +extern volatile PORTCbits_t PORTCbits __attribute__((address(0x4D0))); +# 67589 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PORTE __attribute__((address(0x4D2))); + +__asm("PORTE equ 04D2h"); + + +typedef union { + struct { + unsigned :3; + unsigned RE3 :1; + }; +} PORTEbits_t; +extern volatile PORTEbits_t PORTEbits __attribute__((address(0x4D2))); +# 67610 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON0 __attribute__((address(0x4D6))); + +__asm("INTCON0 equ 04D6h"); + + +typedef union { + struct { + unsigned INT0EDG :1; + unsigned INT1EDG :1; + unsigned INT2EDG :1; + unsigned :2; + unsigned IPEN :1; + unsigned GIEL :1; + unsigned GIE :1; + }; + struct { + unsigned :7; + unsigned GIEH :1; + }; +} INTCON0bits_t; +extern volatile INTCON0bits_t INTCON0bits __attribute__((address(0x4D6))); +# 67670 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INTCON1 __attribute__((address(0x4D7))); + +__asm("INTCON1 equ 04D7h"); + + +typedef union { + struct { + unsigned :6; + unsigned STAT :2; + }; + struct { + unsigned :6; + unsigned STAT0 :1; + unsigned STAT1 :1; + }; +} INTCON1bits_t; +extern volatile INTCON1bits_t INTCON1bits __attribute__((address(0x4D7))); +# 67706 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STATUS __attribute__((address(0x4D8))); + +__asm("STATUS equ 04D8h"); + + +typedef union { + struct { + unsigned :5; + unsigned NOT_PD :1; + }; + struct { + unsigned :6; + unsigned NOT_TO :1; + }; + struct { + unsigned C :1; + unsigned DC :1; + unsigned Z :1; + unsigned OV :1; + unsigned N :1; + unsigned nPD :1; + unsigned nTO :1; + }; + struct { + unsigned :5; + unsigned PD :1; + unsigned TO :1; + }; +} STATUSbits_t; +extern volatile STATUSbits_t STATUSbits __attribute__((address(0x4D8))); +# 67795 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR2 __attribute__((address(0x4D9))); + +__asm("FSR2 equ 04D9h"); + + + + +extern volatile unsigned char FSR2L __attribute__((address(0x4D9))); + +__asm("FSR2L equ 04D9h"); + + +typedef union { + struct { + unsigned FSR2L :8; + }; +} FSR2Lbits_t; +extern volatile FSR2Lbits_t FSR2Lbits __attribute__((address(0x4D9))); +# 67822 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR2H __attribute__((address(0x4DA))); + +__asm("FSR2H equ 04DAh"); + + + + +extern volatile unsigned char PLUSW2 __attribute__((address(0x4DB))); + +__asm("PLUSW2 equ 04DBh"); + + +typedef union { + struct { + unsigned PLUSW2 :8; + }; +} PLUSW2bits_t; +extern volatile PLUSW2bits_t PLUSW2bits __attribute__((address(0x4DB))); +# 67849 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC2 __attribute__((address(0x4DC))); + +__asm("PREINC2 equ 04DCh"); + + +typedef union { + struct { + unsigned PREINC2 :8; + }; +} PREINC2bits_t; +extern volatile PREINC2bits_t PREINC2bits __attribute__((address(0x4DC))); +# 67869 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC2 __attribute__((address(0x4DD))); + +__asm("POSTDEC2 equ 04DDh"); + + +typedef union { + struct { + unsigned POSTDEC2 :8; + }; +} POSTDEC2bits_t; +extern volatile POSTDEC2bits_t POSTDEC2bits __attribute__((address(0x4DD))); +# 67889 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC2 __attribute__((address(0x4DE))); + +__asm("POSTINC2 equ 04DEh"); + + +typedef union { + struct { + unsigned POSTINC2 :8; + }; +} POSTINC2bits_t; +extern volatile POSTINC2bits_t POSTINC2bits __attribute__((address(0x4DE))); +# 67909 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF2 __attribute__((address(0x4DF))); + +__asm("INDF2 equ 04DFh"); + + +typedef union { + struct { + unsigned INDF2 :8; + }; +} INDF2bits_t; +extern volatile INDF2bits_t INDF2bits __attribute__((address(0x4DF))); +# 67929 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char BSR __attribute__((address(0x4E0))); + +__asm("BSR equ 04E0h"); + + + + +extern volatile unsigned short FSR1 __attribute__((address(0x4E1))); + +__asm("FSR1 equ 04E1h"); + + + + +extern volatile unsigned char FSR1L __attribute__((address(0x4E1))); + +__asm("FSR1L equ 04E1h"); + + +typedef union { + struct { + unsigned FSR1L :8; + }; +} FSR1Lbits_t; +extern volatile FSR1Lbits_t FSR1Lbits __attribute__((address(0x4E1))); +# 67963 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR1H __attribute__((address(0x4E2))); + +__asm("FSR1H equ 04E2h"); + + + + +extern volatile unsigned char PLUSW1 __attribute__((address(0x4E3))); + +__asm("PLUSW1 equ 04E3h"); + + +typedef union { + struct { + unsigned PLUSW1 :8; + }; +} PLUSW1bits_t; +extern volatile PLUSW1bits_t PLUSW1bits __attribute__((address(0x4E3))); +# 67990 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC1 __attribute__((address(0x4E4))); + +__asm("PREINC1 equ 04E4h"); + + +typedef union { + struct { + unsigned PREINC1 :8; + }; +} PREINC1bits_t; +extern volatile PREINC1bits_t PREINC1bits __attribute__((address(0x4E4))); +# 68010 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC1 __attribute__((address(0x4E5))); + +__asm("POSTDEC1 equ 04E5h"); + + +typedef union { + struct { + unsigned POSTDEC1 :8; + }; +} POSTDEC1bits_t; +extern volatile POSTDEC1bits_t POSTDEC1bits __attribute__((address(0x4E5))); +# 68030 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC1 __attribute__((address(0x4E6))); + +__asm("POSTINC1 equ 04E6h"); + + +typedef union { + struct { + unsigned POSTINC1 :8; + }; +} POSTINC1bits_t; +extern volatile POSTINC1bits_t POSTINC1bits __attribute__((address(0x4E6))); +# 68050 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF1 __attribute__((address(0x4E7))); + +__asm("INDF1 equ 04E7h"); + + +typedef union { + struct { + unsigned INDF1 :8; + }; +} INDF1bits_t; +extern volatile INDF1bits_t INDF1bits __attribute__((address(0x4E7))); +# 68070 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char WREG __attribute__((address(0x4E8))); + +__asm("WREG equ 04E8h"); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} WREGbits_t; +extern volatile WREGbits_t WREGbits __attribute__((address(0x4E8))); + + + + + + + +typedef union { + struct { + unsigned WREG :8; + }; +} Wbits_t; +extern volatile Wbits_t Wbits __attribute__((address(0x4E8))); +# 68108 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short FSR0 __attribute__((address(0x4E9))); + +__asm("FSR0 equ 04E9h"); + + + + +extern volatile unsigned char FSR0L __attribute__((address(0x4E9))); + +__asm("FSR0L equ 04E9h"); + + +typedef union { + struct { + unsigned FSR0L :8; + }; +} FSR0Lbits_t; +extern volatile FSR0Lbits_t FSR0Lbits __attribute__((address(0x4E9))); +# 68135 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char FSR0H __attribute__((address(0x4EA))); + +__asm("FSR0H equ 04EAh"); + + + + +extern volatile unsigned char PLUSW0 __attribute__((address(0x4EB))); + +__asm("PLUSW0 equ 04EBh"); + + +typedef union { + struct { + unsigned PLUSW0 :8; + }; +} PLUSW0bits_t; +extern volatile PLUSW0bits_t PLUSW0bits __attribute__((address(0x4EB))); +# 68162 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PREINC0 __attribute__((address(0x4EC))); + +__asm("PREINC0 equ 04ECh"); + + +typedef union { + struct { + unsigned PREINC0 :8; + }; +} PREINC0bits_t; +extern volatile PREINC0bits_t PREINC0bits __attribute__((address(0x4EC))); +# 68182 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTDEC0 __attribute__((address(0x4ED))); + +__asm("POSTDEC0 equ 04EDh"); + + +typedef union { + struct { + unsigned POSTDEC0 :8; + }; +} POSTDEC0bits_t; +extern volatile POSTDEC0bits_t POSTDEC0bits __attribute__((address(0x4ED))); +# 68202 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char POSTINC0 __attribute__((address(0x4EE))); + +__asm("POSTINC0 equ 04EEh"); + + +typedef union { + struct { + unsigned POSTINC0 :8; + }; +} POSTINC0bits_t; +extern volatile POSTINC0bits_t POSTINC0bits __attribute__((address(0x4EE))); +# 68222 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char INDF0 __attribute__((address(0x4EF))); + +__asm("INDF0 equ 04EFh"); + + +typedef union { + struct { + unsigned INDF0 :8; + }; +} INDF0bits_t; +extern volatile INDF0bits_t INDF0bits __attribute__((address(0x4EF))); +# 68242 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON0 __attribute__((address(0x4F0))); + +__asm("PCON0 equ 04F0h"); + + +typedef union { + struct { + unsigned NOT_BOR :1; + }; + struct { + unsigned :1; + unsigned NOT_POR :1; + }; + struct { + unsigned :2; + unsigned NOT_RI :1; + }; + struct { + unsigned :3; + unsigned NOT_RMCLR :1; + }; + struct { + unsigned :4; + unsigned NOT_RWDT :1; + }; + struct { + unsigned :5; + unsigned NOT_WDTWV :1; + }; + struct { + unsigned nBOR :1; + unsigned nPOR :1; + unsigned nRI :1; + unsigned nRMCLR :1; + unsigned nRWDT :1; + unsigned nWDTWV :1; + unsigned STKUNF :1; + unsigned STKOVF :1; + }; + struct { + unsigned BOR :1; + unsigned POR :1; + unsigned RI :1; + unsigned RMCLR :1; + unsigned RWDT :1; + unsigned WDTWV :1; + }; +} PCON0bits_t; +extern volatile PCON0bits_t PCON0bits __attribute__((address(0x4F0))); +# 68395 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCON1 __attribute__((address(0x4F1))); + +__asm("PCON1 equ 04F1h"); + + +typedef union { + struct { + unsigned :1; + unsigned NOT_MEMV :1; + }; + struct { + unsigned :1; + unsigned nMEMV :1; + }; + struct { + unsigned :1; + unsigned MEMV :1; + }; +} PCON1bits_t; +extern volatile PCON1bits_t PCON1bits __attribute__((address(0x4F1))); +# 68434 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char CPUDOZE __attribute__((address(0x4F2))); + +__asm("CPUDOZE equ 04F2h"); + + +typedef union { + struct { + unsigned DOZE :3; + unsigned :1; + unsigned DOE :1; + unsigned ROI :1; + unsigned DOZEN :1; + unsigned IDLEN :1; + }; + struct { + unsigned DOZE0 :1; + unsigned DOZE1 :1; + unsigned DOZE2 :1; + }; +} CPUDOZEbits_t; +extern volatile CPUDOZEbits_t CPUDOZEbits __attribute__((address(0x4F2))); +# 68499 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned short PROD __attribute__((address(0x4F3))); + +__asm("PROD equ 04F3h"); + + + + +extern volatile unsigned char PRODL __attribute__((address(0x4F3))); + +__asm("PRODL equ 04F3h"); + + +typedef union { + struct { + unsigned PRODL :8; + }; +} PRODLbits_t; +extern volatile PRODLbits_t PRODLbits __attribute__((address(0x4F3))); +# 68526 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PRODH __attribute__((address(0x4F4))); + +__asm("PRODH equ 04F4h"); + + +typedef union { + struct { + unsigned PRODH :8; + }; +} PRODHbits_t; +extern volatile PRODHbits_t PRODHbits __attribute__((address(0x4F4))); +# 68546 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TABLAT __attribute__((address(0x4F5))); + +__asm("TABLAT equ 04F5h"); + + +typedef union { + struct { + unsigned TABLAT :8; + }; +} TABLATbits_t; +extern volatile TABLATbits_t TABLATbits __attribute__((address(0x4F5))); +# 68567 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TBLPTR __attribute__((address(0x4F6))); + + +__asm("TBLPTR equ 04F6h"); + + + + +extern volatile unsigned char TBLPTRL __attribute__((address(0x4F6))); + +__asm("TBLPTRL equ 04F6h"); + + +typedef union { + struct { + unsigned TBLPTRL :8; + }; +} TBLPTRLbits_t; +extern volatile TBLPTRLbits_t TBLPTRLbits __attribute__((address(0x4F6))); +# 68595 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRH __attribute__((address(0x4F7))); + +__asm("TBLPTRH equ 04F7h"); + + +typedef union { + struct { + unsigned TBLPTRH :8; + }; +} TBLPTRHbits_t; +extern volatile TBLPTRHbits_t TBLPTRHbits __attribute__((address(0x4F7))); +# 68615 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TBLPTRU __attribute__((address(0x4F8))); + +__asm("TBLPTRU equ 04F8h"); + + +typedef union { + struct { + unsigned TBLPTRU :6; + }; + struct { + unsigned :5; + unsigned ACSS :1; + }; +} TBLPTRUbits_t; +extern volatile TBLPTRUbits_t TBLPTRUbits __attribute__((address(0x4F8))); +# 68645 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 PCLAT __attribute__((address(0x4F9))); + + +__asm("PCLAT equ 04F9h"); + + + + +extern volatile unsigned char PCL __attribute__((address(0x4F9))); + +__asm("PCL equ 04F9h"); + + +typedef union { + struct { + unsigned PCL :8; + }; +} PCLbits_t; +extern volatile PCLbits_t PCLbits __attribute__((address(0x4F9))); +# 68673 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATH __attribute__((address(0x4FA))); + +__asm("PCLATH equ 04FAh"); + + +typedef union { + struct { + unsigned PCH :8; + }; +} PCLATHbits_t; +extern volatile PCLATHbits_t PCLATHbits __attribute__((address(0x4FA))); +# 68693 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char PCLATU __attribute__((address(0x4FB))); + +__asm("PCLATU equ 04FBh"); + + +typedef union { + struct { + unsigned PCU :5; + }; +} PCLATUbits_t; +extern volatile PCLATUbits_t PCLATUbits __attribute__((address(0x4FB))); +# 68713 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char STKPTR __attribute__((address(0x4FC))); + +__asm("STKPTR equ 04FCh"); + + +typedef union { + struct { + unsigned STKPTR :6; + }; + struct { + unsigned STKPTR0 :1; + unsigned STKPTR1 :1; + unsigned STKPTR2 :1; + unsigned STKPTR3 :1; + unsigned STKPTR4 :1; + unsigned STKPTR5 :1; + }; + struct { + unsigned SP0 :1; + unsigned SP1 :1; + unsigned SP2 :1; + unsigned SP3 :1; + unsigned SP4 :1; + unsigned SP5 :1; + }; +} STKPTRbits_t; +extern volatile STKPTRbits_t STKPTRbits __attribute__((address(0x4FC))); +# 68810 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __uint24 TOS __attribute__((address(0x4FD))); + + +__asm("TOS equ 04FDh"); + + + + +extern volatile unsigned char TOSL __attribute__((address(0x4FD))); + +__asm("TOSL equ 04FDh"); + + +typedef union { + struct { + unsigned TOSL :8; + }; +} TOSLbits_t; +extern volatile TOSLbits_t TOSLbits __attribute__((address(0x4FD))); +# 68838 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSH __attribute__((address(0x4FE))); + +__asm("TOSH equ 04FEh"); + + +typedef union { + struct { + unsigned TOSH :8; + }; +} TOSHbits_t; +extern volatile TOSHbits_t TOSHbits __attribute__((address(0x4FE))); +# 68858 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile unsigned char TOSU __attribute__((address(0x4FF))); + +__asm("TOSU equ 04FFh"); +# 69695 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\proc\\pic18f26q84.h" 3 +extern volatile __bit ABAT __attribute__((address(0x81B))); + + +extern volatile __bit ABD __attribute__((address(0x14B4))); + + +extern volatile __bit ACCM __attribute__((address(0x1ABC))); + + +extern volatile __bit ACCMOD __attribute__((address(0x1ABC))); + + +extern volatile __bit ACKCNT __attribute__((address(0x14AF))); + + +extern volatile __bit ACKDT __attribute__((address(0x14AE))); + + +extern volatile __bit ACKSTAT __attribute__((address(0x14AD))); + + +extern volatile __bit ACKT __attribute__((address(0x14AC))); + + +extern volatile __bit ACKT1IE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKT1IF __attribute__((address(0x14D6))); + + +extern volatile __bit ACKTIE __attribute__((address(0x14DE))); + + +extern volatile __bit ACKTIF __attribute__((address(0x14D6))); + + +extern volatile __bit ACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ACNT __attribute__((address(0x14B7))); + + +extern volatile __bit ACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ACSS __attribute__((address(0x27C5))); + + +extern volatile __bit ACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ACTEN __attribute__((address(0x567))); + + +extern volatile __bit ACTIE __attribute__((address(0x24FB))); + + +extern volatile __bit ACTIF __attribute__((address(0x257B))); + + +extern volatile __bit ACTIP __attribute__((address(0x1B1B))); + + +extern volatile __bit ACTLOCK __attribute__((address(0x563))); + + +extern volatile __bit ACTMD __attribute__((address(0x31F))); + + +extern volatile __bit ACTORS __attribute__((address(0x561))); + + +extern volatile __bit ACTUD __attribute__((address(0x566))); + + +extern volatile __bit AD0 __attribute__((address(0x22D0))); + + +extern volatile __bit AD1 __attribute__((address(0x22D1))); + + +extern volatile __bit AD10 __attribute__((address(0x22DA))); + + +extern volatile __bit AD11 __attribute__((address(0x22DB))); + + +extern volatile __bit AD12 __attribute__((address(0x22DC))); + + +extern volatile __bit AD13 __attribute__((address(0x22DD))); + + +extern volatile __bit AD14 __attribute__((address(0x22DE))); + + +extern volatile __bit AD15 __attribute__((address(0x22DF))); + + +extern volatile __bit AD16 __attribute__((address(0x22E0))); + + +extern volatile __bit AD17 __attribute__((address(0x22E1))); + + +extern volatile __bit AD18 __attribute__((address(0x22E2))); + + +extern volatile __bit AD19 __attribute__((address(0x22E3))); + + +extern volatile __bit AD2 __attribute__((address(0x22D2))); + + +extern volatile __bit AD20 __attribute__((address(0x22E4))); + + +extern volatile __bit AD3 __attribute__((address(0x22D3))); + + +extern volatile __bit AD4 __attribute__((address(0x22D4))); + + +extern volatile __bit AD5 __attribute__((address(0x22D5))); + + +extern volatile __bit AD6 __attribute__((address(0x22D6))); + + +extern volatile __bit AD7 __attribute__((address(0x22D7))); + + +extern volatile __bit AD8 __attribute__((address(0x22D8))); + + +extern volatile __bit AD9 __attribute__((address(0x22D9))); + + +extern volatile __bit ADACC0 __attribute__((address(0x1F18))); + + +extern volatile __bit ADACC1 __attribute__((address(0x1F19))); + + +extern volatile __bit ADACC10 __attribute__((address(0x1F22))); + + +extern volatile __bit ADACC11 __attribute__((address(0x1F23))); + + +extern volatile __bit ADACC12 __attribute__((address(0x1F24))); + + +extern volatile __bit ADACC13 __attribute__((address(0x1F25))); + + +extern volatile __bit ADACC14 __attribute__((address(0x1F26))); + + +extern volatile __bit ADACC15 __attribute__((address(0x1F27))); + + +extern volatile __bit ADACC16 __attribute__((address(0x1F28))); + + +extern volatile __bit ADACC17 __attribute__((address(0x1F29))); + + +extern volatile __bit ADACC2 __attribute__((address(0x1F1A))); + + +extern volatile __bit ADACC3 __attribute__((address(0x1F1B))); + + +extern volatile __bit ADACC4 __attribute__((address(0x1F1C))); + + +extern volatile __bit ADACC5 __attribute__((address(0x1F1D))); + + +extern volatile __bit ADACC6 __attribute__((address(0x1F1E))); + + +extern volatile __bit ADACC7 __attribute__((address(0x1F1F))); + + +extern volatile __bit ADACC8 __attribute__((address(0x1F20))); + + +extern volatile __bit ADACC9 __attribute__((address(0x1F21))); + + +extern volatile __bit ADACLR __attribute__((address(0x1FAB))); + + +extern volatile __bit ADACQ0 __attribute__((address(0x1F70))); + + +extern volatile __bit ADACQ1 __attribute__((address(0x1F71))); + + +extern volatile __bit ADACQ10 __attribute__((address(0x1F7A))); + + +extern volatile __bit ADACQ11 __attribute__((address(0x1F7B))); + + +extern volatile __bit ADACQ12 __attribute__((address(0x1F7C))); + + +extern volatile __bit ADACQ2 __attribute__((address(0x1F72))); + + +extern volatile __bit ADACQ3 __attribute__((address(0x1F73))); + + +extern volatile __bit ADACQ4 __attribute__((address(0x1F74))); + + +extern volatile __bit ADACQ5 __attribute__((address(0x1F75))); + + +extern volatile __bit ADACQ6 __attribute__((address(0x1F76))); + + +extern volatile __bit ADACQ7 __attribute__((address(0x1F77))); + + +extern volatile __bit ADACQ8 __attribute__((address(0x1F78))); + + +extern volatile __bit ADACQ9 __attribute__((address(0x1F79))); + + +extern volatile __bit ADACT0 __attribute__((address(0x1FC8))); + + +extern volatile __bit ADACT1 __attribute__((address(0x1FC9))); + + +extern volatile __bit ADACT2 __attribute__((address(0x1FCA))); + + +extern volatile __bit ADACT3 __attribute__((address(0x1FCB))); + + +extern volatile __bit ADACT4 __attribute__((address(0x1FCC))); + + +extern volatile __bit ADACT5 __attribute__((address(0x1FCD))); + + +extern volatile __bit ADACTPPS0 __attribute__((address(0x1348))); + + +extern volatile __bit ADACTPPS1 __attribute__((address(0x1349))); + + +extern volatile __bit ADACTPPS2 __attribute__((address(0x134A))); + + +extern volatile __bit ADACTPPS3 __attribute__((address(0x134B))); + + +extern volatile __bit ADACTPPS4 __attribute__((address(0x134C))); + + +extern volatile __bit ADAOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADCALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit ADCALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit ADCALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit ADCAP0 __attribute__((address(0x1F80))); + + +extern volatile __bit ADCAP1 __attribute__((address(0x1F81))); + + +extern volatile __bit ADCAP2 __attribute__((address(0x1F82))); + + +extern volatile __bit ADCAP3 __attribute__((address(0x1F83))); + + +extern volatile __bit ADCAP4 __attribute__((address(0x1F84))); + + +extern volatile __bit ADCH1IE __attribute__((address(0x2500))); + + +extern volatile __bit ADCH1IF __attribute__((address(0x2580))); + + +extern volatile __bit ADCH1IP __attribute__((address(0x1B20))); + + +extern volatile __bit ADCH2IE __attribute__((address(0x2501))); + + +extern volatile __bit ADCH2IF __attribute__((address(0x2581))); + + +extern volatile __bit ADCH2IP __attribute__((address(0x1B21))); + + +extern volatile __bit ADCH3IE __attribute__((address(0x2502))); + + +extern volatile __bit ADCH3IF __attribute__((address(0x2582))); + + +extern volatile __bit ADCH3IP __attribute__((address(0x1B22))); + + +extern volatile __bit ADCH4IE __attribute__((address(0x2503))); + + +extern volatile __bit ADCH4IF __attribute__((address(0x2583))); + + +extern volatile __bit ADCH4IP __attribute__((address(0x1B23))); + + +extern volatile __bit ADCMD __attribute__((address(0x31D))); + + +extern volatile __bit ADCNT0 __attribute__((address(0x1F30))); + + +extern volatile __bit ADCNT1 __attribute__((address(0x1F31))); + + +extern volatile __bit ADCNT2 __attribute__((address(0x1F32))); + + +extern volatile __bit ADCNT3 __attribute__((address(0x1F33))); + + +extern volatile __bit ADCNT4 __attribute__((address(0x1F34))); + + +extern volatile __bit ADCNT5 __attribute__((address(0x1F35))); + + +extern volatile __bit ADCNT6 __attribute__((address(0x1F36))); + + +extern volatile __bit ADCNT7 __attribute__((address(0x1F37))); + + +extern volatile __bit ADCONT __attribute__((address(0x1F9E))); + + +extern volatile __bit ADCPON __attribute__((address(0x1EC7))); + + +extern volatile __bit ADCPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit ADCRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit ADCRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit ADCRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit ADCS __attribute__((address(0x1F9C))); + + +extern volatile __bit ADCS0 __attribute__((address(0x1FD0))); + + +extern volatile __bit ADCS1 __attribute__((address(0x1FD1))); + + +extern volatile __bit ADCS2 __attribute__((address(0x1FD2))); + + +extern volatile __bit ADCS3 __attribute__((address(0x1FD3))); + + +extern volatile __bit ADCS4 __attribute__((address(0x1FD4))); + + +extern volatile __bit ADCS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit ADCSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit ADCTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit ADCTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit ADCTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit ADDSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit ADERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ADERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ADERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ADERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ADERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ADERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ADERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ADERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ADERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ADERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ADERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ADERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ADERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ADERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ADERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ADERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ADFLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit ADFLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit ADFLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit ADFLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit ADFLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit ADFLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit ADFLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit ADFLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit ADFLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit ADFLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit ADFLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit ADFLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit ADFLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit ADFLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit ADFLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit ADFLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit ADFM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit ADFVR0 __attribute__((address(0x1EB8))); + + +extern volatile __bit ADFVR1 __attribute__((address(0x1EB9))); + + +extern volatile __bit ADGO __attribute__((address(0x1F98))); + + +extern volatile __bit ADGPOL __attribute__((address(0x1FA5))); + + +extern volatile __bit ADIE __attribute__((address(0x24FA))); + + +extern volatile __bit ADIF __attribute__((address(0x257A))); + + +extern volatile __bit ADIP __attribute__((address(0x1B1A))); + + +extern volatile __bit ADIPEN __attribute__((address(0x1FA6))); + + +extern volatile __bit ADLTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit ADLTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit ADLTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit ADLTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit ADLTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit ADLTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit ADLTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit ADLTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit ADLTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit ADLTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit ADLTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit ADLTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit ADLTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit ADLTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit ADLTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit ADLTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit ADLTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit ADMATH __attribute__((address(0x1FBC))); + + +extern volatile __bit ADMD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit ADMD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit ADMD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit ADNREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit ADOEN __attribute__((address(0x59A))); + + +extern volatile __bit ADON __attribute__((address(0x1F9F))); + + +extern volatile __bit ADOR __attribute__((address(0x592))); + + +extern volatile __bit ADOV __attribute__((address(0x1FBF))); + + +extern volatile __bit ADPCH0 __attribute__((address(0x1F60))); + + +extern volatile __bit ADPCH1 __attribute__((address(0x1F61))); + + +extern volatile __bit ADPCH2 __attribute__((address(0x1F62))); + + +extern volatile __bit ADPCH3 __attribute__((address(0x1F63))); + + +extern volatile __bit ADPCH4 __attribute__((address(0x1F64))); + + +extern volatile __bit ADPCH5 __attribute__((address(0x1F65))); + + +extern volatile __bit ADPPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit ADPRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit ADPRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit ADPRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit ADPRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit ADPRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit ADPRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit ADPRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit ADPRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit ADPRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit ADPRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit ADPRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit ADPRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit ADPRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit ADPREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit ADPREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit ADPREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit ADPREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit ADPREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit ADPREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit ADPREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit ADPREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit ADPREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit ADPREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit ADPREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit ADPREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit ADPREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit ADPREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit ADPREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit ADPREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit ADPREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit ADPREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit ADPSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit ADR1IE __attribute__((address(0x14DB))); + + +extern volatile __bit ADR1IF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRES0 __attribute__((address(0x1F50))); + + +extern volatile __bit ADRES1 __attribute__((address(0x1F51))); + + +extern volatile __bit ADRES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit ADRES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit ADRES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit ADRES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit ADRES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit ADRES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit ADRES2 __attribute__((address(0x1F52))); + + +extern volatile __bit ADRES3 __attribute__((address(0x1F53))); + + +extern volatile __bit ADRES4 __attribute__((address(0x1F54))); + + +extern volatile __bit ADRES5 __attribute__((address(0x1F55))); + + +extern volatile __bit ADRES6 __attribute__((address(0x1F56))); + + +extern volatile __bit ADRES7 __attribute__((address(0x1F57))); + + +extern volatile __bit ADRES8 __attribute__((address(0x1F58))); + + +extern volatile __bit ADRES9 __attribute__((address(0x1F59))); + + +extern volatile __bit ADRIE __attribute__((address(0x14DB))); + + +extern volatile __bit ADRIF __attribute__((address(0x14D3))); + + +extern volatile __bit ADRPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit ADRPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit ADRPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit ADRPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit ADRPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit ADRPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit ADRPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit ADRPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit ADSOI __attribute__((address(0x1FB3))); + + +extern volatile __bit ADSTAT0 __attribute__((address(0x1FB8))); + + +extern volatile __bit ADSTAT1 __attribute__((address(0x1FB9))); + + +extern volatile __bit ADSTAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit ADSTPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit ADSTPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit ADSTPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit ADSTPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit ADSTPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit ADSTPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit ADSTPT14 __attribute__((address(0x1F06))); + + +extern volatile __bit ADSTPT15 __attribute__((address(0x1F07))); + + +extern volatile __bit ADSTPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit ADSTPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit ADSTPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit ADSTPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit ADSTPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit ADSTPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit ADSTPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit ADSTPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit ADTIE __attribute__((address(0x2500))); + + +extern volatile __bit ADTIF __attribute__((address(0x2580))); + + +extern volatile __bit ADTIP __attribute__((address(0x1B20))); + + +extern volatile __bit ADTMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit ADTMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit ADTMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit ADUTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit ADUTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit ADUTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit ADUTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit ADUTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit ADUTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit ADUTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit ADUTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit ADUTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit ADUTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit ADUTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit ADUTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit ADUTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit ADUTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit ADUTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit ADUTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit ADUTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit AIRQ0 __attribute__((address(0x7F0))); + + +extern volatile __bit AIRQ1 __attribute__((address(0x7F1))); + + +extern volatile __bit AIRQ2 __attribute__((address(0x7F2))); + + +extern volatile __bit AIRQ3 __attribute__((address(0x7F3))); + + +extern volatile __bit AIRQ4 __attribute__((address(0x7F4))); + + +extern volatile __bit AIRQ5 __attribute__((address(0x7F5))); + + +extern volatile __bit AIRQ6 __attribute__((address(0x7F6))); + + +extern volatile __bit AIRQ7 __attribute__((address(0x7F7))); + + +extern volatile __bit AIRQEN __attribute__((address(0x7E2))); + + +extern volatile __bit ANSELA0 __attribute__((address(0x2000))); + + +extern volatile __bit ANSELA1 __attribute__((address(0x2001))); + + +extern volatile __bit ANSELA2 __attribute__((address(0x2002))); + + +extern volatile __bit ANSELA3 __attribute__((address(0x2003))); + + +extern volatile __bit ANSELA4 __attribute__((address(0x2004))); + + +extern volatile __bit ANSELA5 __attribute__((address(0x2005))); + + +extern volatile __bit ANSELA6 __attribute__((address(0x2006))); + + +extern volatile __bit ANSELA7 __attribute__((address(0x2007))); + + +extern volatile __bit ANSELB0 __attribute__((address(0x2040))); + + +extern volatile __bit ANSELB1 __attribute__((address(0x2041))); + + +extern volatile __bit ANSELB2 __attribute__((address(0x2042))); + + +extern volatile __bit ANSELB3 __attribute__((address(0x2043))); + + +extern volatile __bit ANSELB4 __attribute__((address(0x2044))); + + +extern volatile __bit ANSELB5 __attribute__((address(0x2045))); + + +extern volatile __bit ANSELB6 __attribute__((address(0x2046))); + + +extern volatile __bit ANSELB7 __attribute__((address(0x2047))); + + +extern volatile __bit ANSELC0 __attribute__((address(0x2080))); + + +extern volatile __bit ANSELC1 __attribute__((address(0x2081))); + + +extern volatile __bit ANSELC2 __attribute__((address(0x2082))); + + +extern volatile __bit ANSELC3 __attribute__((address(0x2083))); + + +extern volatile __bit ANSELC4 __attribute__((address(0x2084))); + + +extern volatile __bit ANSELC5 __attribute__((address(0x2085))); + + +extern volatile __bit ANSELC6 __attribute__((address(0x2086))); + + +extern volatile __bit ANSELC7 __attribute__((address(0x2087))); + + +extern volatile __bit AS __attribute__((address(0x1870))); + + +extern volatile __bit ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit BASE0 __attribute__((address(0x22E8))); + + +extern volatile __bit BASE1 __attribute__((address(0x22E9))); + + +extern volatile __bit BASE10 __attribute__((address(0x22F2))); + + +extern volatile __bit BASE11 __attribute__((address(0x22F3))); + + +extern volatile __bit BASE12 __attribute__((address(0x22F4))); + + +extern volatile __bit BASE13 __attribute__((address(0x22F5))); + + +extern volatile __bit BASE14 __attribute__((address(0x22F6))); + + +extern volatile __bit BASE15 __attribute__((address(0x22F7))); + + +extern volatile __bit BASE16 __attribute__((address(0x22F8))); + + +extern volatile __bit BASE17 __attribute__((address(0x22F9))); + + +extern volatile __bit BASE18 __attribute__((address(0x22FA))); + + +extern volatile __bit BASE19 __attribute__((address(0x22FB))); + + +extern volatile __bit BASE2 __attribute__((address(0x22EA))); + + +extern volatile __bit BASE20 __attribute__((address(0x22FC))); + + +extern volatile __bit BASE3 __attribute__((address(0x22EB))); + + +extern volatile __bit BASE4 __attribute__((address(0x22EC))); + + +extern volatile __bit BASE5 __attribute__((address(0x22ED))); + + +extern volatile __bit BASE6 __attribute__((address(0x22EE))); + + +extern volatile __bit BASE7 __attribute__((address(0x22EF))); + + +extern volatile __bit BASE8 __attribute__((address(0x22F0))); + + +extern volatile __bit BASE9 __attribute__((address(0x22F1))); + + +extern volatile __bit BCL1IE __attribute__((address(0x14B9))); + + +extern volatile __bit BCL1IF __attribute__((address(0x14BD))); + + +extern volatile __bit BCLIE __attribute__((address(0x14B9))); + + +extern volatile __bit BCLIF __attribute__((address(0x14BD))); + + +extern volatile __bit BFRE __attribute__((address(0x14C7))); + + +extern volatile __bit BFRET0 __attribute__((address(0x14B0))); + + +extern volatile __bit BFRET1 __attribute__((address(0x14B1))); + + +extern volatile __bit BIT __attribute__((address(0x350))); + + +extern volatile __bit BOOTDONE __attribute__((address(0x1C6))); + + +extern volatile __bit BOR __attribute__((address(0x2780))); + + +extern volatile __bit BORRDY __attribute__((address(0x248))); + + +extern volatile __bit BPOUT __attribute__((address(0x1C7))); + + +extern volatile __bit BRSDIS __attribute__((address(0x80C))); + + +extern volatile __bit BTO1IE __attribute__((address(0x14BA))); + + +extern volatile __bit BTO1IF __attribute__((address(0x14BE))); + + +extern volatile __bit BTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit BTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit BTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit BTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit BTOIE __attribute__((address(0x14BA))); + + +extern volatile __bit BTOIF __attribute__((address(0x14BE))); + + +extern volatile __bit BUF0 __attribute__((address(0x748))); + + +extern volatile __bit BUF1 __attribute__((address(0x749))); + + +extern volatile __bit BUF2 __attribute__((address(0x74A))); + + +extern volatile __bit BUF3 __attribute__((address(0x74B))); + + +extern volatile __bit BUF4 __attribute__((address(0x74C))); + + +extern volatile __bit BUF5 __attribute__((address(0x74D))); + + +extern volatile __bit BUF6 __attribute__((address(0x74E))); + + +extern volatile __bit BUF7 __attribute__((address(0x74F))); + + +extern volatile __bit BURSTMD __attribute__((address(0x1B01))); + + +extern volatile __bit C1EN __attribute__((address(0x387))); + + +extern volatile __bit C1HYS __attribute__((address(0x381))); + + +extern volatile __bit C1IE __attribute__((address(0x24FC))); + + +extern volatile __bit C1IF __attribute__((address(0x257C))); + + +extern volatile __bit C1INTN __attribute__((address(0x388))); + + +extern volatile __bit C1INTP __attribute__((address(0x389))); + + +extern volatile __bit C1IP __attribute__((address(0x1B1C))); + + +extern volatile __bit C1NCH0 __attribute__((address(0x390))); + + +extern volatile __bit C1NCH1 __attribute__((address(0x391))); + + +extern volatile __bit C1NCH2 __attribute__((address(0x392))); + + +extern volatile __bit C1OUT __attribute__((address(0x386))); + + +extern volatile __bit C1PCH0 __attribute__((address(0x398))); + + +extern volatile __bit C1PCH1 __attribute__((address(0x399))); + + +extern volatile __bit C1PCH2 __attribute__((address(0x39A))); + + +extern volatile __bit C1POL __attribute__((address(0x384))); + + +extern volatile __bit C1SYNC __attribute__((address(0x380))); + + +extern volatile __bit C1TSEL0 __attribute__((address(0x1A60))); + + +extern volatile __bit C1TSEL1 __attribute__((address(0x1A61))); + + +extern volatile __bit C2EN __attribute__((address(0x3A7))); + + +extern volatile __bit C2HYS __attribute__((address(0x3A1))); + + +extern volatile __bit C2IE __attribute__((address(0x2562))); + + +extern volatile __bit C2IF __attribute__((address(0x25E2))); + + +extern volatile __bit C2INTN __attribute__((address(0x3A8))); + + +extern volatile __bit C2INTP __attribute__((address(0x3A9))); + + +extern volatile __bit C2IP __attribute__((address(0x1B82))); + + +extern volatile __bit C2NCH0 __attribute__((address(0x3B0))); + + +extern volatile __bit C2NCH1 __attribute__((address(0x3B1))); + + +extern volatile __bit C2NCH2 __attribute__((address(0x3B2))); + + +extern volatile __bit C2OUT __attribute__((address(0x3A6))); + + +extern volatile __bit C2PCH0 __attribute__((address(0x3B8))); + + +extern volatile __bit C2PCH1 __attribute__((address(0x3B9))); + + +extern volatile __bit C2PCH2 __attribute__((address(0x3BA))); + + +extern volatile __bit C2POL __attribute__((address(0x3A4))); + + +extern volatile __bit C2SYNC __attribute__((address(0x3A0))); + + +extern volatile __bit C2TSEL0 __attribute__((address(0x1A62))); + + +extern volatile __bit C2TSEL1 __attribute__((address(0x1A63))); + + +extern volatile __bit C3TSEL0 __attribute__((address(0x1A64))); + + +extern volatile __bit C3TSEL1 __attribute__((address(0x1A65))); + + +extern volatile __bit CALC0 __attribute__((address(0x1FB4))); + + +extern volatile __bit CALC1 __attribute__((address(0x1FB5))); + + +extern volatile __bit CALC2 __attribute__((address(0x1FB6))); + + +extern volatile __bit CANIE __attribute__((address(0x24F6))); + + +extern volatile __bit CANIF __attribute__((address(0x2576))); + + +extern volatile __bit CANIP __attribute__((address(0x1B16))); + + +extern volatile __bit CANMD __attribute__((address(0x317))); + + +extern volatile __bit CANRXIE __attribute__((address(0x2514))); + + +extern volatile __bit CANRXIF __attribute__((address(0x2594))); + + +extern volatile __bit CANRXIP __attribute__((address(0x1B34))); + + +extern volatile __bit CANRXPPS0 __attribute__((address(0x11E8))); + + +extern volatile __bit CANRXPPS1 __attribute__((address(0x11E9))); + + +extern volatile __bit CANRXPPS2 __attribute__((address(0x11EA))); + + +extern volatile __bit CANRXPPS3 __attribute__((address(0x11EB))); + + +extern volatile __bit CANRXPPS4 __attribute__((address(0x11EC))); + + +extern volatile __bit CANTXIE __attribute__((address(0x2515))); + + +extern volatile __bit CANTXIF __attribute__((address(0x2595))); + + +extern volatile __bit CANTXIP __attribute__((address(0x1B35))); + + +extern volatile __bit CCP1CTS0 __attribute__((address(0x1A18))); + + +extern volatile __bit CCP1CTS1 __attribute__((address(0x1A19))); + + +extern volatile __bit CCP1CTS2 __attribute__((address(0x1A1A))); + + +extern volatile __bit CCP1CTS3 __attribute__((address(0x1A1B))); + + +extern volatile __bit CCP1EN __attribute__((address(0x1A17))); + + +extern volatile __bit CCP1FMT __attribute__((address(0x1A14))); + + +extern volatile __bit CCP1IE __attribute__((address(0x250E))); + + +extern volatile __bit CCP1IF __attribute__((address(0x258E))); + + +extern volatile __bit CCP1IP __attribute__((address(0x1B2E))); + + +extern volatile __bit CCP1MD __attribute__((address(0x328))); + + +extern volatile __bit CCP1MODE0 __attribute__((address(0x1A10))); + + +extern volatile __bit CCP1MODE1 __attribute__((address(0x1A11))); + + +extern volatile __bit CCP1MODE2 __attribute__((address(0x1A12))); + + +extern volatile __bit CCP1MODE3 __attribute__((address(0x1A13))); + + +extern volatile __bit CCP1OUT __attribute__((address(0x1A15))); + + +extern volatile __bit CCP1PPS0 __attribute__((address(0x1278))); + + +extern volatile __bit CCP1PPS1 __attribute__((address(0x1279))); + + +extern volatile __bit CCP1PPS2 __attribute__((address(0x127A))); + + +extern volatile __bit CCP1PPS3 __attribute__((address(0x127B))); + + +extern volatile __bit CCP1PPS4 __attribute__((address(0x127C))); + + +extern volatile __bit CCP1PPS5 __attribute__((address(0x127D))); + + +extern volatile __bit CCP2CTS0 __attribute__((address(0x1A38))); + + +extern volatile __bit CCP2CTS1 __attribute__((address(0x1A39))); + + +extern volatile __bit CCP2CTS2 __attribute__((address(0x1A3A))); + + +extern volatile __bit CCP2CTS3 __attribute__((address(0x1A3B))); + + +extern volatile __bit CCP2EN __attribute__((address(0x1A37))); + + +extern volatile __bit CCP2FMT __attribute__((address(0x1A34))); + + +extern volatile __bit CCP2IE __attribute__((address(0x2536))); + + +extern volatile __bit CCP2IF __attribute__((address(0x25B6))); + + +extern volatile __bit CCP2IP __attribute__((address(0x1B56))); + + +extern volatile __bit CCP2MD __attribute__((address(0x329))); + + +extern volatile __bit CCP2MODE0 __attribute__((address(0x1A30))); + + +extern volatile __bit CCP2MODE1 __attribute__((address(0x1A31))); + + +extern volatile __bit CCP2MODE2 __attribute__((address(0x1A32))); + + +extern volatile __bit CCP2MODE3 __attribute__((address(0x1A33))); + + +extern volatile __bit CCP2OUT __attribute__((address(0x1A35))); + + +extern volatile __bit CCP2PPS0 __attribute__((address(0x1280))); + + +extern volatile __bit CCP2PPS1 __attribute__((address(0x1281))); + + +extern volatile __bit CCP2PPS2 __attribute__((address(0x1282))); + + +extern volatile __bit CCP2PPS3 __attribute__((address(0x1283))); + + +extern volatile __bit CCP2PPS4 __attribute__((address(0x1284))); + + +extern volatile __bit CCP2PPS5 __attribute__((address(0x1285))); + + +extern volatile __bit CCP3CTS0 __attribute__((address(0x1A58))); + + +extern volatile __bit CCP3CTS1 __attribute__((address(0x1A59))); + + +extern volatile __bit CCP3CTS2 __attribute__((address(0x1A5A))); + + +extern volatile __bit CCP3CTS3 __attribute__((address(0x1A5B))); + + +extern volatile __bit CCP3EN __attribute__((address(0x1A57))); + + +extern volatile __bit CCP3FMT __attribute__((address(0x1A54))); + + +extern volatile __bit CCP3IE __attribute__((address(0x2548))); + + +extern volatile __bit CCP3IF __attribute__((address(0x25C8))); + + +extern volatile __bit CCP3IP __attribute__((address(0x1B68))); + + +extern volatile __bit CCP3MD __attribute__((address(0x32A))); + + +extern volatile __bit CCP3MODE0 __attribute__((address(0x1A50))); + + +extern volatile __bit CCP3MODE1 __attribute__((address(0x1A51))); + + +extern volatile __bit CCP3MODE2 __attribute__((address(0x1A52))); + + +extern volatile __bit CCP3MODE3 __attribute__((address(0x1A53))); + + +extern volatile __bit CCP3OUT __attribute__((address(0x1A55))); + + +extern volatile __bit CCP3PPS0 __attribute__((address(0x1288))); + + +extern volatile __bit CCP3PPS1 __attribute__((address(0x1289))); + + +extern volatile __bit CCP3PPS2 __attribute__((address(0x128A))); + + +extern volatile __bit CCP3PPS3 __attribute__((address(0x128B))); + + +extern volatile __bit CCP3PPS4 __attribute__((address(0x128C))); + + +extern volatile __bit CDAFVR0 __attribute__((address(0x1EBA))); + + +extern volatile __bit CDAFVR1 __attribute__((address(0x1EBB))); + + +extern volatile __bit CDIV0 __attribute__((address(0x570))); + + +extern volatile __bit CDIV1 __attribute__((address(0x571))); + + +extern volatile __bit CDIV2 __attribute__((address(0x572))); + + +extern volatile __bit CDIV3 __attribute__((address(0x573))); + + +extern volatile __bit CERRIE __attribute__((address(0x8FD))); + + +extern volatile __bit CERRIF __attribute__((address(0x8ED))); + + +extern volatile __bit CH0 __attribute__((address(0x370))); + + +extern volatile __bit CH1 __attribute__((address(0x371))); + + +extern volatile __bit CH16AB __attribute__((address(0x1DD8))); + + +extern volatile __bit CH2 __attribute__((address(0x372))); + + +extern volatile __bit CH3 __attribute__((address(0x373))); + + +extern volatile __bit CH4 __attribute__((address(0x374))); + + +extern volatile __bit CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit CL0 __attribute__((address(0x368))); + + +extern volatile __bit CL1 __attribute__((address(0x369))); + + +extern volatile __bit CL2 __attribute__((address(0x36A))); + + +extern volatile __bit CL3 __attribute__((address(0x36B))); + + +extern volatile __bit CL4 __attribute__((address(0x36C))); + + +extern volatile __bit CLC1IE __attribute__((address(0x24F5))); + + +extern volatile __bit CLC1IF __attribute__((address(0x2575))); + + +extern volatile __bit CLC1IP __attribute__((address(0x1B15))); + + +extern volatile __bit CLC1MD __attribute__((address(0x338))); + + +extern volatile __bit CLC1OUT __attribute__((address(0x6A0))); + + +extern volatile __bit CLC2IE __attribute__((address(0x2521))); + + +extern volatile __bit CLC2IF __attribute__((address(0x25A1))); + + +extern volatile __bit CLC2IP __attribute__((address(0x1B41))); + + +extern volatile __bit CLC2MD __attribute__((address(0x339))); + + +extern volatile __bit CLC2OUT __attribute__((address(0x6A1))); + + +extern volatile __bit CLC3IE __attribute__((address(0x252D))); + + +extern volatile __bit CLC3IF __attribute__((address(0x25AD))); + + +extern volatile __bit CLC3IP __attribute__((address(0x1B4D))); + + +extern volatile __bit CLC3MD __attribute__((address(0x33A))); + + +extern volatile __bit CLC3OUT __attribute__((address(0x6A2))); + + +extern volatile __bit CLC4IE __attribute__((address(0x253D))); + + +extern volatile __bit CLC4IF __attribute__((address(0x25BD))); + + +extern volatile __bit CLC4IP __attribute__((address(0x1B5D))); + + +extern volatile __bit CLC4MD __attribute__((address(0x33B))); + + +extern volatile __bit CLC4OUT __attribute__((address(0x6A3))); + + +extern volatile __bit CLC5IE __attribute__((address(0x2541))); + + +extern volatile __bit CLC5IF __attribute__((address(0x25C1))); + + +extern volatile __bit CLC5IP __attribute__((address(0x1B61))); + + +extern volatile __bit CLC5MD __attribute__((address(0x33C))); + + +extern volatile __bit CLC5OUT __attribute__((address(0x6A4))); + + +extern volatile __bit CLC6IE __attribute__((address(0x2549))); + + +extern volatile __bit CLC6IF __attribute__((address(0x25C9))); + + +extern volatile __bit CLC6IP __attribute__((address(0x1B69))); + + +extern volatile __bit CLC6MD __attribute__((address(0x33D))); + + +extern volatile __bit CLC6OUT __attribute__((address(0x6A5))); + + +extern volatile __bit CLC7IE __attribute__((address(0x2561))); + + +extern volatile __bit CLC7IF __attribute__((address(0x25E1))); + + +extern volatile __bit CLC7IP __attribute__((address(0x1B81))); + + +extern volatile __bit CLC7MD __attribute__((address(0x33E))); + + +extern volatile __bit CLC7OUT __attribute__((address(0x6A6))); + + +extern volatile __bit CLC8IE __attribute__((address(0x2569))); + + +extern volatile __bit CLC8IF __attribute__((address(0x25E9))); + + +extern volatile __bit CLC8IP __attribute__((address(0x1B89))); + + +extern volatile __bit CLC8MD __attribute__((address(0x33F))); + + +extern volatile __bit CLC8OUT __attribute__((address(0x6A7))); + + +extern volatile __bit CLCIN0PPS0 __attribute__((address(0x1308))); + + +extern volatile __bit CLCIN0PPS1 __attribute__((address(0x1309))); + + +extern volatile __bit CLCIN0PPS2 __attribute__((address(0x130A))); + + +extern volatile __bit CLCIN0PPS3 __attribute__((address(0x130B))); + + +extern volatile __bit CLCIN0PPS4 __attribute__((address(0x130C))); + + +extern volatile __bit CLCIN1PPS0 __attribute__((address(0x1310))); + + +extern volatile __bit CLCIN1PPS1 __attribute__((address(0x1311))); + + +extern volatile __bit CLCIN1PPS2 __attribute__((address(0x1312))); + + +extern volatile __bit CLCIN1PPS3 __attribute__((address(0x1313))); + + +extern volatile __bit CLCIN1PPS4 __attribute__((address(0x1314))); + + +extern volatile __bit CLCIN2PPS0 __attribute__((address(0x1318))); + + +extern volatile __bit CLCIN2PPS1 __attribute__((address(0x1319))); + + +extern volatile __bit CLCIN2PPS2 __attribute__((address(0x131A))); + + +extern volatile __bit CLCIN2PPS3 __attribute__((address(0x131B))); + + +extern volatile __bit CLCIN2PPS4 __attribute__((address(0x131C))); + + +extern volatile __bit CLCIN3PPS0 __attribute__((address(0x1320))); + + +extern volatile __bit CLCIN3PPS1 __attribute__((address(0x1321))); + + +extern volatile __bit CLCIN3PPS2 __attribute__((address(0x1322))); + + +extern volatile __bit CLCIN3PPS3 __attribute__((address(0x1323))); + + +extern volatile __bit CLCIN3PPS4 __attribute__((address(0x1324))); + + +extern volatile __bit CLCIN4PPS0 __attribute__((address(0x1328))); + + +extern volatile __bit CLCIN4PPS1 __attribute__((address(0x1329))); + + +extern volatile __bit CLCIN4PPS2 __attribute__((address(0x132A))); + + +extern volatile __bit CLCIN4PPS3 __attribute__((address(0x132B))); + + +extern volatile __bit CLCIN4PPS4 __attribute__((address(0x132C))); + + +extern volatile __bit CLCIN5PPS0 __attribute__((address(0x1330))); + + +extern volatile __bit CLCIN5PPS1 __attribute__((address(0x1331))); + + +extern volatile __bit CLCIN5PPS2 __attribute__((address(0x1332))); + + +extern volatile __bit CLCIN5PPS3 __attribute__((address(0x1333))); + + +extern volatile __bit CLCIN5PPS4 __attribute__((address(0x1334))); + + +extern volatile __bit CLCIN6PPS0 __attribute__((address(0x1338))); + + +extern volatile __bit CLCIN6PPS1 __attribute__((address(0x1339))); + + +extern volatile __bit CLCIN6PPS2 __attribute__((address(0x133A))); + + +extern volatile __bit CLCIN6PPS3 __attribute__((address(0x133B))); + + +extern volatile __bit CLCIN6PPS4 __attribute__((address(0x133C))); + + +extern volatile __bit CLCIN7PPS0 __attribute__((address(0x1340))); + + +extern volatile __bit CLCIN7PPS1 __attribute__((address(0x1341))); + + +extern volatile __bit CLCIN7PPS2 __attribute__((address(0x1342))); + + +extern volatile __bit CLCIN7PPS3 __attribute__((address(0x1343))); + + +extern volatile __bit CLCIN7PPS4 __attribute__((address(0x1344))); + + +extern volatile __bit CLKRCLK0 __attribute__((address(0x1D0))); + + +extern volatile __bit CLKRCLK1 __attribute__((address(0x1D1))); + + +extern volatile __bit CLKRCLK2 __attribute__((address(0x1D2))); + + +extern volatile __bit CLKRCLK3 __attribute__((address(0x1D3))); + + +extern volatile __bit CLKRCLK4 __attribute__((address(0x1D4))); + + +extern volatile __bit CLKRDC0 __attribute__((address(0x1CB))); + + +extern volatile __bit CLKRDC1 __attribute__((address(0x1CC))); + + +extern volatile __bit CLKRDIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit CLKRDIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit CLKRDIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit CLKREN __attribute__((address(0x1CF))); + + +extern volatile __bit CLKRMD __attribute__((address(0x301))); + + +extern volatile __bit CLPOL __attribute__((address(0x359))); + + +extern volatile __bit CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit CM1MD __attribute__((address(0x319))); + + +extern volatile __bit CM2MD __attribute__((address(0x31A))); + + +extern volatile __bit CNT10 __attribute__((address(0x146A))); + + +extern volatile __bit CNT11 __attribute__((address(0x146B))); + + +extern volatile __bit CNT12 __attribute__((address(0x146C))); + + +extern volatile __bit CNT13 __attribute__((address(0x146D))); + + +extern volatile __bit CNT14 __attribute__((address(0x146E))); + + +extern volatile __bit CNT15 __attribute__((address(0x146F))); + + +extern volatile __bit CNT1IE __attribute__((address(0x14DF))); + + +extern volatile __bit CNT1IF __attribute__((address(0x14D7))); + + +extern volatile __bit CNT8 __attribute__((address(0x1468))); + + +extern volatile __bit CNT9 __attribute__((address(0x1469))); + + +extern volatile __bit CNTIE __attribute__((address(0x14DF))); + + +extern volatile __bit CNTIF __attribute__((address(0x14D7))); + + +extern volatile __bit CONT __attribute__((address(0x1F9E))); + + +extern volatile __bit COSC0 __attribute__((address(0x574))); + + +extern volatile __bit COSC1 __attribute__((address(0x575))); + + +extern volatile __bit COSC2 __attribute__((address(0x576))); + + +extern volatile __bit CPON __attribute__((address(0x1EC7))); + + +extern volatile __bit CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit CPRDY __attribute__((address(0x1EC0))); + + +extern volatile __bit CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit CRCBUSY __attribute__((address(0x1ABD))); + + +extern volatile __bit CRCEN __attribute__((address(0x1ABF))); + + +extern volatile __bit CRCGO __attribute__((address(0x1ABE))); + + +extern volatile __bit CRCIE __attribute__((address(0x256A))); + + +extern volatile __bit CRCIF __attribute__((address(0x25EA))); + + +extern volatile __bit CRCIP __attribute__((address(0x1B8A))); + + +extern volatile __bit CRCMD __attribute__((address(0x304))); + + +extern volatile __bit CRS0 __attribute__((address(0x1FAC))); + + +extern volatile __bit CRS1 __attribute__((address(0x1FAD))); + + +extern volatile __bit CRS2 __attribute__((address(0x1FAE))); + + +extern volatile __bit CS5 __attribute__((address(0x1FD5))); + + +extern volatile __bit CSD __attribute__((address(0x14A8))); + + +extern volatile __bit CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit CSEN __attribute__((address(0x1F9D))); + + +extern volatile __bit CSTR __attribute__((address(0x14A4))); + + +extern volatile __bit CSWHOLD __attribute__((address(0x57F))); + + +extern volatile __bit CSWIE __attribute__((address(0x24F3))); + + +extern volatile __bit CSWIF __attribute__((address(0x2573))); + + +extern volatile __bit CSWIP __attribute__((address(0x1B13))); + + +extern volatile __bit CTX0 __attribute__((address(0x1FD8))); + + +extern volatile __bit CTX1 __attribute__((address(0x1FD9))); + + +extern volatile __bit CTXSW __attribute__((address(0x1FDF))); + + +extern volatile __bit CWG1CS __attribute__((address(0x1DE0))); + + +extern volatile __bit CWG1DBF0 __attribute__((address(0x1DF8))); + + +extern volatile __bit CWG1DBF1 __attribute__((address(0x1DF9))); + + +extern volatile __bit CWG1DBF2 __attribute__((address(0x1DFA))); + + +extern volatile __bit CWG1DBF3 __attribute__((address(0x1DFB))); + + +extern volatile __bit CWG1DBF4 __attribute__((address(0x1DFC))); + + +extern volatile __bit CWG1DBF5 __attribute__((address(0x1DFD))); + + +extern volatile __bit CWG1DBR0 __attribute__((address(0x1DF0))); + + +extern volatile __bit CWG1DBR1 __attribute__((address(0x1DF1))); + + +extern volatile __bit CWG1DBR2 __attribute__((address(0x1DF2))); + + +extern volatile __bit CWG1DBR3 __attribute__((address(0x1DF3))); + + +extern volatile __bit CWG1DBR4 __attribute__((address(0x1DF4))); + + +extern volatile __bit CWG1DBR5 __attribute__((address(0x1DF5))); + + +extern volatile __bit CWG1EN __attribute__((address(0x1E07))); + + +extern volatile __bit CWG1IE __attribute__((address(0x2522))); + + +extern volatile __bit CWG1IF __attribute__((address(0x25A2))); + + +extern volatile __bit CWG1IN __attribute__((address(0x1E0D))); + + +extern volatile __bit CWG1INPPS0 __attribute__((address(0x12D8))); + + +extern volatile __bit CWG1INPPS1 __attribute__((address(0x12D9))); + + +extern volatile __bit CWG1INPPS2 __attribute__((address(0x12DA))); + + +extern volatile __bit CWG1INPPS3 __attribute__((address(0x12DB))); + + +extern volatile __bit CWG1INPPS4 __attribute__((address(0x12DC))); + + +extern volatile __bit CWG1IP __attribute__((address(0x1B42))); + + +extern volatile __bit CWG1ISM0 __attribute__((address(0x1DE8))); + + +extern volatile __bit CWG1ISM1 __attribute__((address(0x1DE9))); + + +extern volatile __bit CWG1ISM2 __attribute__((address(0x1DEA))); + + +extern volatile __bit CWG1ISM3 __attribute__((address(0x1DEB))); + + +extern volatile __bit CWG1LD __attribute__((address(0x1E06))); + + +extern volatile __bit CWG1LSAC0 __attribute__((address(0x1E12))); + + +extern volatile __bit CWG1LSAC1 __attribute__((address(0x1E13))); + + +extern volatile __bit CWG1LSBD0 __attribute__((address(0x1E14))); + + +extern volatile __bit CWG1LSBD1 __attribute__((address(0x1E15))); + + +extern volatile __bit CWG1MD __attribute__((address(0x324))); + + +extern volatile __bit CWG1MODE0 __attribute__((address(0x1E00))); + + +extern volatile __bit CWG1MODE1 __attribute__((address(0x1E01))); + + +extern volatile __bit CWG1MODE2 __attribute__((address(0x1E02))); + + +extern volatile __bit CWG1OVRA __attribute__((address(0x1E24))); + + +extern volatile __bit CWG1OVRB __attribute__((address(0x1E25))); + + +extern volatile __bit CWG1OVRC __attribute__((address(0x1E26))); + + +extern volatile __bit CWG1OVRD __attribute__((address(0x1E27))); + + +extern volatile __bit CWG1POLA __attribute__((address(0x1E08))); + + +extern volatile __bit CWG1POLB __attribute__((address(0x1E09))); + + +extern volatile __bit CWG1POLC __attribute__((address(0x1E0A))); + + +extern volatile __bit CWG1POLD __attribute__((address(0x1E0B))); + + +extern volatile __bit CWG1REN __attribute__((address(0x1E16))); + + +extern volatile __bit CWG1SHUTDOWN __attribute__((address(0x1E17))); + + +extern volatile __bit CWG1STRA __attribute__((address(0x1E20))); + + +extern volatile __bit CWG1STRB __attribute__((address(0x1E21))); + + +extern volatile __bit CWG1STRC __attribute__((address(0x1E22))); + + +extern volatile __bit CWG1STRD __attribute__((address(0x1E23))); + + +extern volatile __bit CWG2CS __attribute__((address(0x1E28))); + + +extern volatile __bit CWG2DBF0 __attribute__((address(0x1E40))); + + +extern volatile __bit CWG2DBF1 __attribute__((address(0x1E41))); + + +extern volatile __bit CWG2DBF2 __attribute__((address(0x1E42))); + + +extern volatile __bit CWG2DBF3 __attribute__((address(0x1E43))); + + +extern volatile __bit CWG2DBF4 __attribute__((address(0x1E44))); + + +extern volatile __bit CWG2DBF5 __attribute__((address(0x1E45))); + + +extern volatile __bit CWG2DBR0 __attribute__((address(0x1E38))); + + +extern volatile __bit CWG2DBR1 __attribute__((address(0x1E39))); + + +extern volatile __bit CWG2DBR2 __attribute__((address(0x1E3A))); + + +extern volatile __bit CWG2DBR3 __attribute__((address(0x1E3B))); + + +extern volatile __bit CWG2DBR4 __attribute__((address(0x1E3C))); + + +extern volatile __bit CWG2DBR5 __attribute__((address(0x1E3D))); + + +extern volatile __bit CWG2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit CWG2IE __attribute__((address(0x2542))); + + +extern volatile __bit CWG2IF __attribute__((address(0x25C2))); + + +extern volatile __bit CWG2IN __attribute__((address(0x1E55))); + + +extern volatile __bit CWG2INPPS0 __attribute__((address(0x12E0))); + + +extern volatile __bit CWG2INPPS1 __attribute__((address(0x12E1))); + + +extern volatile __bit CWG2INPPS2 __attribute__((address(0x12E2))); + + +extern volatile __bit CWG2INPPS3 __attribute__((address(0x12E3))); + + +extern volatile __bit CWG2INPPS4 __attribute__((address(0x12E4))); + + +extern volatile __bit CWG2IP __attribute__((address(0x1B62))); + + +extern volatile __bit CWG2ISM0 __attribute__((address(0x1E30))); + + +extern volatile __bit CWG2ISM1 __attribute__((address(0x1E31))); + + +extern volatile __bit CWG2ISM2 __attribute__((address(0x1E32))); + + +extern volatile __bit CWG2ISM3 __attribute__((address(0x1E33))); + + +extern volatile __bit CWG2LD __attribute__((address(0x1E4E))); + + +extern volatile __bit CWG2LSAC0 __attribute__((address(0x1E5A))); + + +extern volatile __bit CWG2LSAC1 __attribute__((address(0x1E5B))); + + +extern volatile __bit CWG2LSBD0 __attribute__((address(0x1E5C))); + + +extern volatile __bit CWG2LSBD1 __attribute__((address(0x1E5D))); + + +extern volatile __bit CWG2MD __attribute__((address(0x325))); + + +extern volatile __bit CWG2MODE0 __attribute__((address(0x1E48))); + + +extern volatile __bit CWG2MODE1 __attribute__((address(0x1E49))); + + +extern volatile __bit CWG2MODE2 __attribute__((address(0x1E4A))); + + +extern volatile __bit CWG2OVRA __attribute__((address(0x1E6C))); + + +extern volatile __bit CWG2OVRB __attribute__((address(0x1E6D))); + + +extern volatile __bit CWG2OVRC __attribute__((address(0x1E6E))); + + +extern volatile __bit CWG2OVRD __attribute__((address(0x1E6F))); + + +extern volatile __bit CWG2POLA __attribute__((address(0x1E50))); + + +extern volatile __bit CWG2POLB __attribute__((address(0x1E51))); + + +extern volatile __bit CWG2POLC __attribute__((address(0x1E52))); + + +extern volatile __bit CWG2POLD __attribute__((address(0x1E53))); + + +extern volatile __bit CWG2REN __attribute__((address(0x1E5E))); + + +extern volatile __bit CWG2SHUTDOWN __attribute__((address(0x1E5F))); + + +extern volatile __bit CWG2STRA __attribute__((address(0x1E68))); + + +extern volatile __bit CWG2STRB __attribute__((address(0x1E69))); + + +extern volatile __bit CWG2STRC __attribute__((address(0x1E6A))); + + +extern volatile __bit CWG2STRD __attribute__((address(0x1E6B))); + + +extern volatile __bit CWG3CS __attribute__((address(0x1E70))); + + +extern volatile __bit CWG3DBF0 __attribute__((address(0x1E88))); + + +extern volatile __bit CWG3DBF1 __attribute__((address(0x1E89))); + + +extern volatile __bit CWG3DBF2 __attribute__((address(0x1E8A))); + + +extern volatile __bit CWG3DBF3 __attribute__((address(0x1E8B))); + + +extern volatile __bit CWG3DBF4 __attribute__((address(0x1E8C))); + + +extern volatile __bit CWG3DBF5 __attribute__((address(0x1E8D))); + + +extern volatile __bit CWG3DBR0 __attribute__((address(0x1E80))); + + +extern volatile __bit CWG3DBR1 __attribute__((address(0x1E81))); + + +extern volatile __bit CWG3DBR2 __attribute__((address(0x1E82))); + + +extern volatile __bit CWG3DBR3 __attribute__((address(0x1E83))); + + +extern volatile __bit CWG3DBR4 __attribute__((address(0x1E84))); + + +extern volatile __bit CWG3DBR5 __attribute__((address(0x1E85))); + + +extern volatile __bit CWG3EN __attribute__((address(0x1E97))); + + +extern volatile __bit CWG3IE __attribute__((address(0x254A))); + + +extern volatile __bit CWG3IF __attribute__((address(0x25CA))); + + +extern volatile __bit CWG3IN __attribute__((address(0x1E9D))); + + +extern volatile __bit CWG3INPPS0 __attribute__((address(0x12E8))); + + +extern volatile __bit CWG3INPPS1 __attribute__((address(0x12E9))); + + +extern volatile __bit CWG3INPPS2 __attribute__((address(0x12EA))); + + +extern volatile __bit CWG3INPPS3 __attribute__((address(0x12EB))); + + +extern volatile __bit CWG3INPPS4 __attribute__((address(0x12EC))); + + +extern volatile __bit CWG3IP __attribute__((address(0x1B6A))); + + +extern volatile __bit CWG3ISM0 __attribute__((address(0x1E78))); + + +extern volatile __bit CWG3ISM1 __attribute__((address(0x1E79))); + + +extern volatile __bit CWG3ISM2 __attribute__((address(0x1E7A))); + + +extern volatile __bit CWG3ISM3 __attribute__((address(0x1E7B))); + + +extern volatile __bit CWG3LD __attribute__((address(0x1E96))); + + +extern volatile __bit CWG3LSAC0 __attribute__((address(0x1EA2))); + + +extern volatile __bit CWG3LSAC1 __attribute__((address(0x1EA3))); + + +extern volatile __bit CWG3LSBD0 __attribute__((address(0x1EA4))); + + +extern volatile __bit CWG3LSBD1 __attribute__((address(0x1EA5))); + + +extern volatile __bit CWG3MD __attribute__((address(0x326))); + + +extern volatile __bit CWG3MODE0 __attribute__((address(0x1E90))); + + +extern volatile __bit CWG3MODE1 __attribute__((address(0x1E91))); + + +extern volatile __bit CWG3MODE2 __attribute__((address(0x1E92))); + + +extern volatile __bit CWG3OVRA __attribute__((address(0x1EB4))); + + +extern volatile __bit CWG3OVRB __attribute__((address(0x1EB5))); + + +extern volatile __bit CWG3OVRC __attribute__((address(0x1EB6))); + + +extern volatile __bit CWG3OVRD __attribute__((address(0x1EB7))); + + +extern volatile __bit CWG3POLA __attribute__((address(0x1E98))); + + +extern volatile __bit CWG3POLB __attribute__((address(0x1E99))); + + +extern volatile __bit CWG3POLC __attribute__((address(0x1E9A))); + + +extern volatile __bit CWG3POLD __attribute__((address(0x1E9B))); + + +extern volatile __bit CWG3REN __attribute__((address(0x1EA6))); + + +extern volatile __bit CWG3SHUTDOWN __attribute__((address(0x1EA7))); + + +extern volatile __bit CWG3STRA __attribute__((address(0x1EB0))); + + +extern volatile __bit CWG3STRB __attribute__((address(0x1EB1))); + + +extern volatile __bit CWG3STRC __attribute__((address(0x1EB2))); + + +extern volatile __bit CWG3STRD __attribute__((address(0x1EB3))); + + +extern volatile __bit D1S0 __attribute__((address(0x6C0))); + + +extern volatile __bit D1S1 __attribute__((address(0x6C1))); + + +extern volatile __bit D1S2 __attribute__((address(0x6C2))); + + +extern volatile __bit D1S3 __attribute__((address(0x6C3))); + + +extern volatile __bit D1S4 __attribute__((address(0x6C4))); + + +extern volatile __bit D1S5 __attribute__((address(0x6C5))); + + +extern volatile __bit D1S6 __attribute__((address(0x6C6))); + + +extern volatile __bit D1S7 __attribute__((address(0x6C7))); + + +extern volatile __bit D2S0 __attribute__((address(0x6C8))); + + +extern volatile __bit D2S1 __attribute__((address(0x6C9))); + + +extern volatile __bit D2S2 __attribute__((address(0x6CA))); + + +extern volatile __bit D2S3 __attribute__((address(0x6CB))); + + +extern volatile __bit D2S4 __attribute__((address(0x6CC))); + + +extern volatile __bit D2S5 __attribute__((address(0x6CD))); + + +extern volatile __bit D2S6 __attribute__((address(0x6CE))); + + +extern volatile __bit D2S7 __attribute__((address(0x6CF))); + + +extern volatile __bit D3S0 __attribute__((address(0x6D0))); + + +extern volatile __bit D3S1 __attribute__((address(0x6D1))); + + +extern volatile __bit D3S2 __attribute__((address(0x6D2))); + + +extern volatile __bit D3S3 __attribute__((address(0x6D3))); + + +extern volatile __bit D3S4 __attribute__((address(0x6D4))); + + +extern volatile __bit D3S5 __attribute__((address(0x6D5))); + + +extern volatile __bit D3S6 __attribute__((address(0x6D6))); + + +extern volatile __bit D3S7 __attribute__((address(0x6D7))); + + +extern volatile __bit D4S0 __attribute__((address(0x6D8))); + + +extern volatile __bit D4S1 __attribute__((address(0x6D9))); + + +extern volatile __bit D4S2 __attribute__((address(0x6DA))); + + +extern volatile __bit D4S3 __attribute__((address(0x6DB))); + + +extern volatile __bit D4S4 __attribute__((address(0x6DC))); + + +extern volatile __bit D4S5 __attribute__((address(0x6DD))); + + +extern volatile __bit D4S6 __attribute__((address(0x6DE))); + + +extern volatile __bit D4S7 __attribute__((address(0x6DF))); + + +extern volatile __bit DAC1EN __attribute__((address(0x3FF))); + + +extern volatile __bit DAC1PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit DAC1PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit DAC1R0 __attribute__((address(0x3E8))); + + +extern volatile __bit DAC1R1 __attribute__((address(0x3E9))); + + +extern volatile __bit DAC1R2 __attribute__((address(0x3EA))); + + +extern volatile __bit DAC1R3 __attribute__((address(0x3EB))); + + +extern volatile __bit DAC1R4 __attribute__((address(0x3EC))); + + +extern volatile __bit DAC1R5 __attribute__((address(0x3ED))); + + +extern volatile __bit DAC1R6 __attribute__((address(0x3EE))); + + +extern volatile __bit DAC1R7 __attribute__((address(0x3EF))); + + +extern volatile __bit DACMD __attribute__((address(0x31E))); + + +extern volatile __bit DATA __attribute__((address(0x14C3))); + + +extern volatile __bit DATA0 __attribute__((address(0x1A78))); + + +extern volatile __bit DATA1 __attribute__((address(0x1A79))); + + +extern volatile __bit DATA10 __attribute__((address(0x1A82))); + + +extern volatile __bit DATA11 __attribute__((address(0x1A83))); + + +extern volatile __bit DATA12 __attribute__((address(0x1A84))); + + +extern volatile __bit DATA13 __attribute__((address(0x1A85))); + + +extern volatile __bit DATA14 __attribute__((address(0x1A86))); + + +extern volatile __bit DATA15 __attribute__((address(0x1A87))); + + +extern volatile __bit DATA16 __attribute__((address(0x1A88))); + + +extern volatile __bit DATA17 __attribute__((address(0x1A89))); + + +extern volatile __bit DATA18 __attribute__((address(0x1A8A))); + + +extern volatile __bit DATA19 __attribute__((address(0x1A8B))); + + +extern volatile __bit DATA2 __attribute__((address(0x1A7A))); + + +extern volatile __bit DATA20 __attribute__((address(0x1A8C))); + + +extern volatile __bit DATA21 __attribute__((address(0x1A8D))); + + +extern volatile __bit DATA22 __attribute__((address(0x1A8E))); + + +extern volatile __bit DATA23 __attribute__((address(0x1A8F))); + + +extern volatile __bit DATA24 __attribute__((address(0x1A90))); + + +extern volatile __bit DATA25 __attribute__((address(0x1A91))); + + +extern volatile __bit DATA26 __attribute__((address(0x1A92))); + + +extern volatile __bit DATA27 __attribute__((address(0x1A93))); + + +extern volatile __bit DATA28 __attribute__((address(0x1A94))); + + +extern volatile __bit DATA29 __attribute__((address(0x1A95))); + + +extern volatile __bit DATA3 __attribute__((address(0x1A7B))); + + +extern volatile __bit DATA30 __attribute__((address(0x1A96))); + + +extern volatile __bit DATA31 __attribute__((address(0x1A97))); + + +extern volatile __bit DATA4 __attribute__((address(0x1A7C))); + + +extern volatile __bit DATA5 __attribute__((address(0x1A7D))); + + +extern volatile __bit DATA6 __attribute__((address(0x1A7E))); + + +extern volatile __bit DATA7 __attribute__((address(0x1A7F))); + + +extern volatile __bit DATA8 __attribute__((address(0x1A80))); + + +extern volatile __bit DATA9 __attribute__((address(0x1A81))); + + +extern volatile __bit DBIT0ERR __attribute__((address(0x9F8))); + + +extern volatile __bit DBIT1ERR __attribute__((address(0x9F9))); + + +extern volatile __bit DC0 __attribute__((address(0x1CB))); + + +extern volatile __bit DC1 __attribute__((address(0x1CC))); + + +extern volatile __bit DCNT0 __attribute__((address(0x750))); + + +extern volatile __bit DCNT1 __attribute__((address(0x751))); + + +extern volatile __bit DCNT10 __attribute__((address(0x75A))); + + +extern volatile __bit DCNT11 __attribute__((address(0x75B))); + + +extern volatile __bit DCNT2 __attribute__((address(0x752))); + + +extern volatile __bit DCNT3 __attribute__((address(0x753))); + + +extern volatile __bit DCNT4 __attribute__((address(0x754))); + + +extern volatile __bit DCNT5 __attribute__((address(0x755))); + + +extern volatile __bit DCNT6 __attribute__((address(0x756))); + + +extern volatile __bit DCNT7 __attribute__((address(0x757))); + + +extern volatile __bit DCNT8 __attribute__((address(0x758))); + + +extern volatile __bit DCNT9 __attribute__((address(0x759))); + + +extern volatile __bit DCRCERR __attribute__((address(0x9FD))); + + +extern volatile __bit DFORMERR __attribute__((address(0x9FB))); + + +extern volatile __bit DGO __attribute__((address(0x7E5))); + + +extern volatile __bit DIV0 __attribute__((address(0x1C8))); + + +extern volatile __bit DIV1 __attribute__((address(0x1C9))); + + +extern volatile __bit DIV2 __attribute__((address(0x1CA))); + + +extern volatile __bit DLCMM __attribute__((address(0x9FF))); + + +extern volatile __bit DLEN0 __attribute__((address(0x1AC8))); + + +extern volatile __bit DLEN1 __attribute__((address(0x1AC9))); + + +extern volatile __bit DLEN2 __attribute__((address(0x1ACA))); + + +extern volatile __bit DLEN3 __attribute__((address(0x1ACB))); + + +extern volatile __bit DLEN4 __attribute__((address(0x1ACC))); + + +extern volatile __bit DMA1AIE __attribute__((address(0x2507))); + + +extern volatile __bit DMA1AIF __attribute__((address(0x2587))); + + +extern volatile __bit DMA1AIP __attribute__((address(0x1B27))); + + +extern volatile __bit DMA1DCNTIE __attribute__((address(0x2505))); + + +extern volatile __bit DMA1DCNTIF __attribute__((address(0x2585))); + + +extern volatile __bit DMA1DCNTIP __attribute__((address(0x1B25))); + + +extern volatile __bit DMA1MD __attribute__((address(0x340))); + + +extern volatile __bit DMA1ORIE __attribute__((address(0x2506))); + + +extern volatile __bit DMA1ORIF __attribute__((address(0x2586))); + + +extern volatile __bit DMA1ORIP __attribute__((address(0x1B26))); + + +extern volatile __bit DMA1PR0 __attribute__((address(0x5B0))); + + +extern volatile __bit DMA1PR1 __attribute__((address(0x5B1))); + + +extern volatile __bit DMA1PR2 __attribute__((address(0x5B2))); + + +extern volatile __bit DMA1SCNTIE __attribute__((address(0x2504))); + + +extern volatile __bit DMA1SCNTIF __attribute__((address(0x2584))); + + +extern volatile __bit DMA1SCNTIP __attribute__((address(0x1B24))); + + +extern volatile __bit DMA2AIE __attribute__((address(0x2527))); + + +extern volatile __bit DMA2AIF __attribute__((address(0x25A7))); + + +extern volatile __bit DMA2AIP __attribute__((address(0x1B47))); + + +extern volatile __bit DMA2DCNTIE __attribute__((address(0x2525))); + + +extern volatile __bit DMA2DCNTIF __attribute__((address(0x25A5))); + + +extern volatile __bit DMA2DCNTIP __attribute__((address(0x1B45))); + + +extern volatile __bit DMA2MD __attribute__((address(0x341))); + + +extern volatile __bit DMA2ORIE __attribute__((address(0x2526))); + + +extern volatile __bit DMA2ORIF __attribute__((address(0x25A6))); + + +extern volatile __bit DMA2ORIP __attribute__((address(0x1B46))); + + +extern volatile __bit DMA2PR0 __attribute__((address(0x5B8))); + + +extern volatile __bit DMA2PR1 __attribute__((address(0x5B9))); + + +extern volatile __bit DMA2PR2 __attribute__((address(0x5BA))); + + +extern volatile __bit DMA2SCNTIE __attribute__((address(0x2524))); + + +extern volatile __bit DMA2SCNTIF __attribute__((address(0x25A4))); + + +extern volatile __bit DMA2SCNTIP __attribute__((address(0x1B44))); + + +extern volatile __bit DMA3AIE __attribute__((address(0x2547))); + + +extern volatile __bit DMA3AIF __attribute__((address(0x25C7))); + + +extern volatile __bit DMA3AIP __attribute__((address(0x1B67))); + + +extern volatile __bit DMA3DCNTIE __attribute__((address(0x2545))); + + +extern volatile __bit DMA3DCNTIF __attribute__((address(0x25C5))); + + +extern volatile __bit DMA3DCNTIP __attribute__((address(0x1B65))); + + +extern volatile __bit DMA3MD __attribute__((address(0x342))); + + +extern volatile __bit DMA3ORIE __attribute__((address(0x2546))); + + +extern volatile __bit DMA3ORIF __attribute__((address(0x25C6))); + + +extern volatile __bit DMA3ORIP __attribute__((address(0x1B66))); + + +extern volatile __bit DMA3PR0 __attribute__((address(0x5C0))); + + +extern volatile __bit DMA3PR1 __attribute__((address(0x5C1))); + + +extern volatile __bit DMA3PR2 __attribute__((address(0x5C2))); + + +extern volatile __bit DMA3SCNTIE __attribute__((address(0x2544))); + + +extern volatile __bit DMA3SCNTIF __attribute__((address(0x25C4))); + + +extern volatile __bit DMA3SCNTIP __attribute__((address(0x1B64))); + + +extern volatile __bit DMA4AIE __attribute__((address(0x254F))); + + +extern volatile __bit DMA4AIF __attribute__((address(0x25CF))); + + +extern volatile __bit DMA4AIP __attribute__((address(0x1B6F))); + + +extern volatile __bit DMA4DCNTIE __attribute__((address(0x254D))); + + +extern volatile __bit DMA4DCNTIF __attribute__((address(0x25CD))); + + +extern volatile __bit DMA4DCNTIP __attribute__((address(0x1B6D))); + + +extern volatile __bit DMA4MD __attribute__((address(0x343))); + + +extern volatile __bit DMA4ORIE __attribute__((address(0x254E))); + + +extern volatile __bit DMA4ORIF __attribute__((address(0x25CE))); + + +extern volatile __bit DMA4ORIP __attribute__((address(0x1B6E))); + + +extern volatile __bit DMA4PR0 __attribute__((address(0x5C8))); + + +extern volatile __bit DMA4PR1 __attribute__((address(0x5C9))); + + +extern volatile __bit DMA4PR2 __attribute__((address(0x5CA))); + + +extern volatile __bit DMA4SCNTIE __attribute__((address(0x254C))); + + +extern volatile __bit DMA4SCNTIF __attribute__((address(0x25CC))); + + +extern volatile __bit DMA4SCNTIP __attribute__((address(0x1B6C))); + + +extern volatile __bit DMA5AIE __attribute__((address(0x2557))); + + +extern volatile __bit DMA5AIF __attribute__((address(0x25D7))); + + +extern volatile __bit DMA5AIP __attribute__((address(0x1B77))); + + +extern volatile __bit DMA5DCNTIE __attribute__((address(0x2555))); + + +extern volatile __bit DMA5DCNTIF __attribute__((address(0x25D5))); + + +extern volatile __bit DMA5DCNTIP __attribute__((address(0x1B75))); + + +extern volatile __bit DMA5MD __attribute__((address(0x344))); + + +extern volatile __bit DMA5ORIE __attribute__((address(0x2556))); + + +extern volatile __bit DMA5ORIF __attribute__((address(0x25D6))); + + +extern volatile __bit DMA5ORIP __attribute__((address(0x1B76))); + + +extern volatile __bit DMA5PR0 __attribute__((address(0x5D0))); + + +extern volatile __bit DMA5PR1 __attribute__((address(0x5D1))); + + +extern volatile __bit DMA5PR2 __attribute__((address(0x5D2))); + + +extern volatile __bit DMA5SCNTIE __attribute__((address(0x2554))); + + +extern volatile __bit DMA5SCNTIF __attribute__((address(0x25D4))); + + +extern volatile __bit DMA5SCNTIP __attribute__((address(0x1B74))); + + +extern volatile __bit DMA6AIE __attribute__((address(0x255F))); + + +extern volatile __bit DMA6AIF __attribute__((address(0x25DF))); + + +extern volatile __bit DMA6AIP __attribute__((address(0x1B7F))); + + +extern volatile __bit DMA6DCNTIE __attribute__((address(0x255D))); + + +extern volatile __bit DMA6DCNTIF __attribute__((address(0x25DD))); + + +extern volatile __bit DMA6DCNTIP __attribute__((address(0x1B7D))); + + +extern volatile __bit DMA6MD __attribute__((address(0x345))); + + +extern volatile __bit DMA6ORIE __attribute__((address(0x255E))); + + +extern volatile __bit DMA6ORIF __attribute__((address(0x25DE))); + + +extern volatile __bit DMA6ORIP __attribute__((address(0x1B7E))); + + +extern volatile __bit DMA6PR0 __attribute__((address(0x5D8))); + + +extern volatile __bit DMA6PR1 __attribute__((address(0x5D9))); + + +extern volatile __bit DMA6PR2 __attribute__((address(0x5DA))); + + +extern volatile __bit DMA6SCNTIE __attribute__((address(0x255C))); + + +extern volatile __bit DMA6SCNTIF __attribute__((address(0x25DC))); + + +extern volatile __bit DMA6SCNTIP __attribute__((address(0x1B7C))); + + +extern volatile __bit DMA7AIE __attribute__((address(0x2567))); + + +extern volatile __bit DMA7AIF __attribute__((address(0x25E7))); + + +extern volatile __bit DMA7AIP __attribute__((address(0x1B87))); + + +extern volatile __bit DMA7DCNTIE __attribute__((address(0x2565))); + + +extern volatile __bit DMA7DCNTIF __attribute__((address(0x25E5))); + + +extern volatile __bit DMA7DCNTIP __attribute__((address(0x1B85))); + + +extern volatile __bit DMA7MD __attribute__((address(0x346))); + + +extern volatile __bit DMA7ORIE __attribute__((address(0x2566))); + + +extern volatile __bit DMA7ORIF __attribute__((address(0x25E6))); + + +extern volatile __bit DMA7ORIP __attribute__((address(0x1B86))); + + +extern volatile __bit DMA7PR0 __attribute__((address(0x5E0))); + + +extern volatile __bit DMA7PR1 __attribute__((address(0x5E1))); + + +extern volatile __bit DMA7PR2 __attribute__((address(0x5E2))); + + +extern volatile __bit DMA7SCNTIE __attribute__((address(0x2564))); + + +extern volatile __bit DMA7SCNTIF __attribute__((address(0x25E4))); + + +extern volatile __bit DMA7SCNTIP __attribute__((address(0x1B84))); + + +extern volatile __bit DMA8AIE __attribute__((address(0x256F))); + + +extern volatile __bit DMA8AIF __attribute__((address(0x25EF))); + + +extern volatile __bit DMA8AIP __attribute__((address(0x1B8F))); + + +extern volatile __bit DMA8DCNTIE __attribute__((address(0x256D))); + + +extern volatile __bit DMA8DCNTIF __attribute__((address(0x25ED))); + + +extern volatile __bit DMA8DCNTIP __attribute__((address(0x1B8D))); + + +extern volatile __bit DMA8MD __attribute__((address(0x347))); + + +extern volatile __bit DMA8ORIE __attribute__((address(0x256E))); + + +extern volatile __bit DMA8ORIF __attribute__((address(0x25EE))); + + +extern volatile __bit DMA8ORIP __attribute__((address(0x1B8E))); + + +extern volatile __bit DMA8PR0 __attribute__((address(0x5E8))); + + +extern volatile __bit DMA8PR1 __attribute__((address(0x5E9))); + + +extern volatile __bit DMA8PR2 __attribute__((address(0x5EA))); + + +extern volatile __bit DMA8SCNTIE __attribute__((address(0x256C))); + + +extern volatile __bit DMA8SCNTIF __attribute__((address(0x25EC))); + + +extern volatile __bit DMA8SCNTIP __attribute__((address(0x1B8C))); + + +extern volatile __bit DNCNT0 __attribute__((address(0x800))); + + +extern volatile __bit DNCNT1 __attribute__((address(0x801))); + + +extern volatile __bit DNCNT2 __attribute__((address(0x802))); + + +extern volatile __bit DNCNT3 __attribute__((address(0x803))); + + +extern volatile __bit DNCNT4 __attribute__((address(0x804))); + + +extern volatile __bit DOE __attribute__((address(0x2794))); + + +extern volatile __bit DONE __attribute__((address(0x1F98))); + + +extern volatile __bit DOZE0 __attribute__((address(0x2790))); + + +extern volatile __bit DOZE1 __attribute__((address(0x2791))); + + +extern volatile __bit DOZE2 __attribute__((address(0x2792))); + + +extern volatile __bit DOZEN __attribute__((address(0x2796))); + + +extern volatile __bit DPTR0 __attribute__((address(0x760))); + + +extern volatile __bit DPTR1 __attribute__((address(0x761))); + + +extern volatile __bit DPTR10 __attribute__((address(0x76A))); + + +extern volatile __bit DPTR11 __attribute__((address(0x76B))); + + +extern volatile __bit DPTR12 __attribute__((address(0x76C))); + + +extern volatile __bit DPTR13 __attribute__((address(0x76D))); + + +extern volatile __bit DPTR14 __attribute__((address(0x76E))); + + +extern volatile __bit DPTR15 __attribute__((address(0x76F))); + + +extern volatile __bit DPTR2 __attribute__((address(0x762))); + + +extern volatile __bit DPTR3 __attribute__((address(0x763))); + + +extern volatile __bit DPTR4 __attribute__((address(0x764))); + + +extern volatile __bit DPTR5 __attribute__((address(0x765))); + + +extern volatile __bit DPTR6 __attribute__((address(0x766))); + + +extern volatile __bit DPTR7 __attribute__((address(0x767))); + + +extern volatile __bit DPTR8 __attribute__((address(0x768))); + + +extern volatile __bit DPTR9 __attribute__((address(0x769))); + + +extern volatile __bit DRERRCNT0 __attribute__((address(0x9D0))); + + +extern volatile __bit DRERRCNT1 __attribute__((address(0x9D1))); + + +extern volatile __bit DRERRCNT2 __attribute__((address(0x9D2))); + + +extern volatile __bit DRERRCNT3 __attribute__((address(0x9D3))); + + +extern volatile __bit DRERRCNT4 __attribute__((address(0x9D4))); + + +extern volatile __bit DRERRCNT5 __attribute__((address(0x9D5))); + + +extern volatile __bit DRERRCNT6 __attribute__((address(0x9D6))); + + +extern volatile __bit DRERRCNT7 __attribute__((address(0x9D7))); + + +extern volatile __bit DSA0 __attribute__((address(0x780))); + + +extern volatile __bit DSA1 __attribute__((address(0x781))); + + +extern volatile __bit DSA10 __attribute__((address(0x78A))); + + +extern volatile __bit DSA11 __attribute__((address(0x78B))); + + +extern volatile __bit DSA12 __attribute__((address(0x78C))); + + +extern volatile __bit DSA13 __attribute__((address(0x78D))); + + +extern volatile __bit DSA14 __attribute__((address(0x78E))); + + +extern volatile __bit DSA15 __attribute__((address(0x78F))); + + +extern volatile __bit DSA2 __attribute__((address(0x782))); + + +extern volatile __bit DSA3 __attribute__((address(0x783))); + + +extern volatile __bit DSA4 __attribute__((address(0x784))); + + +extern volatile __bit DSA5 __attribute__((address(0x785))); + + +extern volatile __bit DSA6 __attribute__((address(0x786))); + + +extern volatile __bit DSA7 __attribute__((address(0x787))); + + +extern volatile __bit DSA8 __attribute__((address(0x788))); + + +extern volatile __bit DSA9 __attribute__((address(0x789))); + + +extern volatile __bit DSEN __attribute__((address(0x1FA0))); + + +extern volatile __bit DSM1MD __attribute__((address(0x323))); + + +extern volatile __bit DSTP __attribute__((address(0x7ED))); + + +extern volatile __bit DSTUFERR __attribute__((address(0x9FC))); + + +extern volatile __bit DSZ0 __attribute__((address(0x770))); + + +extern volatile __bit DSZ1 __attribute__((address(0x771))); + + +extern volatile __bit DSZ10 __attribute__((address(0x77A))); + + +extern volatile __bit DSZ11 __attribute__((address(0x77B))); + + +extern volatile __bit DSZ2 __attribute__((address(0x772))); + + +extern volatile __bit DSZ3 __attribute__((address(0x773))); + + +extern volatile __bit DSZ4 __attribute__((address(0x774))); + + +extern volatile __bit DSZ5 __attribute__((address(0x775))); + + +extern volatile __bit DSZ6 __attribute__((address(0x776))); + + +extern volatile __bit DSZ7 __attribute__((address(0x777))); + + +extern volatile __bit DSZ8 __attribute__((address(0x778))); + + +extern volatile __bit DSZ9 __attribute__((address(0x779))); + + +extern volatile __bit DTERRCNT0 __attribute__((address(0x9D8))); + + +extern volatile __bit DTERRCNT1 __attribute__((address(0x9D9))); + + +extern volatile __bit DTERRCNT2 __attribute__((address(0x9DA))); + + +extern volatile __bit DTERRCNT3 __attribute__((address(0x9DB))); + + +extern volatile __bit DTERRCNT4 __attribute__((address(0x9DC))); + + +extern volatile __bit DTERRCNT5 __attribute__((address(0x9DD))); + + +extern volatile __bit DTERRCNT6 __attribute__((address(0x9DE))); + + +extern volatile __bit DTERRCNT7 __attribute__((address(0x9DF))); + + +extern volatile __bit EDGFLTEN __attribute__((address(0x879))); + + +extern volatile __bit EFMSGCNT0 __attribute__((address(0x9E0))); + + +extern volatile __bit EFMSGCNT1 __attribute__((address(0x9E1))); + + +extern volatile __bit EFMSGCNT10 __attribute__((address(0x9EA))); + + +extern volatile __bit EFMSGCNT11 __attribute__((address(0x9EB))); + + +extern volatile __bit EFMSGCNT12 __attribute__((address(0x9EC))); + + +extern volatile __bit EFMSGCNT13 __attribute__((address(0x9ED))); + + +extern volatile __bit EFMSGCNT14 __attribute__((address(0x9EE))); + + +extern volatile __bit EFMSGCNT15 __attribute__((address(0x9EF))); + + +extern volatile __bit EFMSGCNT2 __attribute__((address(0x9E2))); + + +extern volatile __bit EFMSGCNT3 __attribute__((address(0x9E3))); + + +extern volatile __bit EFMSGCNT4 __attribute__((address(0x9E4))); + + +extern volatile __bit EFMSGCNT5 __attribute__((address(0x9E5))); + + +extern volatile __bit EFMSGCNT6 __attribute__((address(0x9E6))); + + +extern volatile __bit EFMSGCNT7 __attribute__((address(0x9E7))); + + +extern volatile __bit EFMSGCNT8 __attribute__((address(0x9E8))); + + +extern volatile __bit EFMSGCNT9 __attribute__((address(0x9E9))); + + +extern volatile __bit ERR0 __attribute__((address(0x1EE8))); + + +extern volatile __bit ERR1 __attribute__((address(0x1EE9))); + + +extern volatile __bit ERR10 __attribute__((address(0x1EF2))); + + +extern volatile __bit ERR11 __attribute__((address(0x1EF3))); + + +extern volatile __bit ERR12 __attribute__((address(0x1EF4))); + + +extern volatile __bit ERR13 __attribute__((address(0x1EF5))); + + +extern volatile __bit ERR14 __attribute__((address(0x1EF6))); + + +extern volatile __bit ERR15 __attribute__((address(0x1EF7))); + + +extern volatile __bit ERR2 __attribute__((address(0x1EEA))); + + +extern volatile __bit ERR3 __attribute__((address(0x1EEB))); + + +extern volatile __bit ERR4 __attribute__((address(0x1EEC))); + + +extern volatile __bit ERR5 __attribute__((address(0x1EED))); + + +extern volatile __bit ERR6 __attribute__((address(0x1EEE))); + + +extern volatile __bit ERR7 __attribute__((address(0x1EEF))); + + +extern volatile __bit ERR8 __attribute__((address(0x1EF0))); + + +extern volatile __bit ERR9 __attribute__((address(0x1EF1))); + + +extern volatile __bit ESI __attribute__((address(0x9FE))); + + +extern volatile __bit ESIGM __attribute__((address(0x811))); + + +extern volatile __bit EWARN __attribute__((address(0x9B0))); + + +extern volatile __bit EXTOEN __attribute__((address(0x59F))); + + +extern volatile __bit EXTOR __attribute__((address(0x597))); + + +extern volatile __bit F0BP0 __attribute__((address(0xC00))); + + +extern volatile __bit F0BP1 __attribute__((address(0xC01))); + + +extern volatile __bit F0BP2 __attribute__((address(0xC02))); + + +extern volatile __bit F0BP3 __attribute__((address(0xC03))); + + +extern volatile __bit F0BP4 __attribute__((address(0xC04))); + + +extern volatile __bit F10BP0 __attribute__((address(0xC50))); + + +extern volatile __bit F10BP1 __attribute__((address(0xC51))); + + +extern volatile __bit F10BP2 __attribute__((address(0xC52))); + + +extern volatile __bit F10BP3 __attribute__((address(0xC53))); + + +extern volatile __bit F10BP4 __attribute__((address(0xC54))); + + +extern volatile __bit F11BP0 __attribute__((address(0xC58))); + + +extern volatile __bit F11BP1 __attribute__((address(0xC59))); + + +extern volatile __bit F11BP2 __attribute__((address(0xC5A))); + + +extern volatile __bit F11BP3 __attribute__((address(0xC5B))); + + +extern volatile __bit F11BP4 __attribute__((address(0xC5C))); + + +extern volatile __bit F1BP0 __attribute__((address(0xC08))); + + +extern volatile __bit F1BP1 __attribute__((address(0xC09))); + + +extern volatile __bit F1BP2 __attribute__((address(0xC0A))); + + +extern volatile __bit F1BP3 __attribute__((address(0xC0B))); + + +extern volatile __bit F1BP4 __attribute__((address(0xC0C))); + + +extern volatile __bit F2BP0 __attribute__((address(0xC10))); + + +extern volatile __bit F2BP1 __attribute__((address(0xC11))); + + +extern volatile __bit F2BP2 __attribute__((address(0xC12))); + + +extern volatile __bit F2BP3 __attribute__((address(0xC13))); + + +extern volatile __bit F2BP4 __attribute__((address(0xC14))); + + +extern volatile __bit F3BP0 __attribute__((address(0xC18))); + + +extern volatile __bit F3BP1 __attribute__((address(0xC19))); + + +extern volatile __bit F3BP2 __attribute__((address(0xC1A))); + + +extern volatile __bit F3BP3 __attribute__((address(0xC1B))); + + +extern volatile __bit F3BP4 __attribute__((address(0xC1C))); + + +extern volatile __bit F4BP0 __attribute__((address(0xC20))); + + +extern volatile __bit F4BP1 __attribute__((address(0xC21))); + + +extern volatile __bit F4BP2 __attribute__((address(0xC22))); + + +extern volatile __bit F4BP3 __attribute__((address(0xC23))); + + +extern volatile __bit F4BP4 __attribute__((address(0xC24))); + + +extern volatile __bit F5BP0 __attribute__((address(0xC28))); + + +extern volatile __bit F5BP1 __attribute__((address(0xC29))); + + +extern volatile __bit F5BP2 __attribute__((address(0xC2A))); + + +extern volatile __bit F5BP3 __attribute__((address(0xC2B))); + + +extern volatile __bit F5BP4 __attribute__((address(0xC2C))); + + +extern volatile __bit F6BP0 __attribute__((address(0xC30))); + + +extern volatile __bit F6BP1 __attribute__((address(0xC31))); + + +extern volatile __bit F6BP2 __attribute__((address(0xC32))); + + +extern volatile __bit F6BP3 __attribute__((address(0xC33))); + + +extern volatile __bit F6BP4 __attribute__((address(0xC34))); + + +extern volatile __bit F7BP0 __attribute__((address(0xC38))); + + +extern volatile __bit F7BP1 __attribute__((address(0xC39))); + + +extern volatile __bit F7BP2 __attribute__((address(0xC3A))); + + +extern volatile __bit F7BP3 __attribute__((address(0xC3B))); + + +extern volatile __bit F7BP4 __attribute__((address(0xC3C))); + + +extern volatile __bit F8BP0 __attribute__((address(0xC40))); + + +extern volatile __bit F8BP1 __attribute__((address(0xC41))); + + +extern volatile __bit F8BP2 __attribute__((address(0xC42))); + + +extern volatile __bit F8BP3 __attribute__((address(0xC43))); + + +extern volatile __bit F8BP4 __attribute__((address(0xC44))); + + +extern volatile __bit F9BP0 __attribute__((address(0xC48))); + + +extern volatile __bit F9BP1 __attribute__((address(0xC49))); + + +extern volatile __bit F9BP2 __attribute__((address(0xC4A))); + + +extern volatile __bit F9BP3 __attribute__((address(0xC4B))); + + +extern volatile __bit F9BP4 __attribute__((address(0xC4C))); + + +extern volatile __bit FIFOBA0 __attribute__((address(0xA60))); + + +extern volatile __bit FIFOBA1 __attribute__((address(0xA61))); + + +extern volatile __bit FIFOBA10 __attribute__((address(0xA6A))); + + +extern volatile __bit FIFOBA11 __attribute__((address(0xA6B))); + + +extern volatile __bit FIFOBA12 __attribute__((address(0xA6C))); + + +extern volatile __bit FIFOBA13 __attribute__((address(0xA6D))); + + +extern volatile __bit FIFOBA14 __attribute__((address(0xA6E))); + + +extern volatile __bit FIFOBA15 __attribute__((address(0xA6F))); + + +extern volatile __bit FIFOBA16 __attribute__((address(0xA70))); + + +extern volatile __bit FIFOBA17 __attribute__((address(0xA71))); + + +extern volatile __bit FIFOBA18 __attribute__((address(0xA72))); + + +extern volatile __bit FIFOBA19 __attribute__((address(0xA73))); + + +extern volatile __bit FIFOBA2 __attribute__((address(0xA62))); + + +extern volatile __bit FIFOBA20 __attribute__((address(0xA74))); + + +extern volatile __bit FIFOBA21 __attribute__((address(0xA75))); + + +extern volatile __bit FIFOBA22 __attribute__((address(0xA76))); + + +extern volatile __bit FIFOBA23 __attribute__((address(0xA77))); + + +extern volatile __bit FIFOBA24 __attribute__((address(0xA78))); + + +extern volatile __bit FIFOBA25 __attribute__((address(0xA79))); + + +extern volatile __bit FIFOBA26 __attribute__((address(0xA7A))); + + +extern volatile __bit FIFOBA27 __attribute__((address(0xA7B))); + + +extern volatile __bit FIFOBA28 __attribute__((address(0xA7C))); + + +extern volatile __bit FIFOBA29 __attribute__((address(0xA7D))); + + +extern volatile __bit FIFOBA3 __attribute__((address(0xA63))); + + +extern volatile __bit FIFOBA30 __attribute__((address(0xA7E))); + + +extern volatile __bit FIFOBA31 __attribute__((address(0xA7F))); + + +extern volatile __bit FIFOBA4 __attribute__((address(0xA64))); + + +extern volatile __bit FIFOBA5 __attribute__((address(0xA65))); + + +extern volatile __bit FIFOBA6 __attribute__((address(0xA66))); + + +extern volatile __bit FIFOBA7 __attribute__((address(0xA67))); + + +extern volatile __bit FIFOBA8 __attribute__((address(0xA68))); + + +extern volatile __bit FIFOBA9 __attribute__((address(0xA69))); + + +extern volatile __bit FLTEN0 __attribute__((address(0xC07))); + + +extern volatile __bit FLTEN1 __attribute__((address(0xC0F))); + + +extern volatile __bit FLTEN10 __attribute__((address(0xC57))); + + +extern volatile __bit FLTEN11 __attribute__((address(0xC5F))); + + +extern volatile __bit FLTEN2 __attribute__((address(0xC17))); + + +extern volatile __bit FLTEN3 __attribute__((address(0xC1F))); + + +extern volatile __bit FLTEN4 __attribute__((address(0xC27))); + + +extern volatile __bit FLTEN5 __attribute__((address(0xC2F))); + + +extern volatile __bit FLTEN6 __attribute__((address(0xC37))); + + +extern volatile __bit FLTEN7 __attribute__((address(0xC3F))); + + +extern volatile __bit FLTEN8 __attribute__((address(0xC47))); + + +extern volatile __bit FLTEN9 __attribute__((address(0xC4F))); + + +extern volatile __bit FLTR0 __attribute__((address(0x1F08))); + + +extern volatile __bit FLTR1 __attribute__((address(0x1F09))); + + +extern volatile __bit FLTR10 __attribute__((address(0x1F12))); + + +extern volatile __bit FLTR11 __attribute__((address(0x1F13))); + + +extern volatile __bit FLTR12 __attribute__((address(0x1F14))); + + +extern volatile __bit FLTR13 __attribute__((address(0x1F15))); + + +extern volatile __bit FLTR14 __attribute__((address(0x1F16))); + + +extern volatile __bit FLTR15 __attribute__((address(0x1F17))); + + +extern volatile __bit FLTR2 __attribute__((address(0x1F0A))); + + +extern volatile __bit FLTR3 __attribute__((address(0x1F0B))); + + +extern volatile __bit FLTR4 __attribute__((address(0x1F0C))); + + +extern volatile __bit FLTR5 __attribute__((address(0x1F0D))); + + +extern volatile __bit FLTR6 __attribute__((address(0x1F0E))); + + +extern volatile __bit FLTR7 __attribute__((address(0x1F0F))); + + +extern volatile __bit FLTR8 __attribute__((address(0x1F10))); + + +extern volatile __bit FLTR9 __attribute__((address(0x1F11))); + + +extern volatile __bit FM0 __attribute__((address(0x1F9A))); + + +extern volatile __bit FME __attribute__((address(0x14B5))); + + +extern volatile __bit FRQ0 __attribute__((address(0x588))); + + +extern volatile __bit FRQ1 __attribute__((address(0x589))); + + +extern volatile __bit FRQ2 __attribute__((address(0x58A))); + + +extern volatile __bit FRQ3 __attribute__((address(0x58B))); + + +extern volatile __bit FRZ __attribute__((address(0x80E))); + + +extern volatile __bit FSCMFEV __attribute__((address(0x22C0))); + + +extern volatile __bit FSCMFFI __attribute__((address(0x22C1))); + + +extern volatile __bit FSCMPEV __attribute__((address(0x22C2))); + + +extern volatile __bit FSCMPFI __attribute__((address(0x22C3))); + + +extern volatile __bit FSCMSEV __attribute__((address(0x22C4))); + + +extern volatile __bit FSCMSFI __attribute__((address(0x22C5))); + + +extern volatile __bit FULL __attribute__((address(0x1AB8))); + + +extern volatile __bit FVREN __attribute__((address(0x1EBF))); + + +extern volatile __bit FVRMD __attribute__((address(0x306))); + + +extern volatile __bit FVRRDY __attribute__((address(0x1EBE))); + + +extern volatile __bit G1D1N __attribute__((address(0x6E0))); + + +extern volatile __bit G1D1T __attribute__((address(0x6E1))); + + +extern volatile __bit G1D2N __attribute__((address(0x6E2))); + + +extern volatile __bit G1D2T __attribute__((address(0x6E3))); + + +extern volatile __bit G1D3N __attribute__((address(0x6E4))); + + +extern volatile __bit G1D3T __attribute__((address(0x6E5))); + + +extern volatile __bit G1D4N __attribute__((address(0x6E6))); + + +extern volatile __bit G1D4T __attribute__((address(0x6E7))); + + +extern volatile __bit G1EN __attribute__((address(0x1E07))); + + +extern volatile __bit G1POL __attribute__((address(0x6B8))); + + +extern volatile __bit G2D1N __attribute__((address(0x6E8))); + + +extern volatile __bit G2D1T __attribute__((address(0x6E9))); + + +extern volatile __bit G2D2N __attribute__((address(0x6EA))); + + +extern volatile __bit G2D2T __attribute__((address(0x6EB))); + + +extern volatile __bit G2D3N __attribute__((address(0x6EC))); + + +extern volatile __bit G2D3T __attribute__((address(0x6ED))); + + +extern volatile __bit G2D4N __attribute__((address(0x6EE))); + + +extern volatile __bit G2D4T __attribute__((address(0x6EF))); + + +extern volatile __bit G2EN __attribute__((address(0x1E4F))); + + +extern volatile __bit G2POL __attribute__((address(0x6B9))); + + +extern volatile __bit G3D1N __attribute__((address(0x6F0))); + + +extern volatile __bit G3D1T __attribute__((address(0x6F1))); + + +extern volatile __bit G3D2N __attribute__((address(0x6F2))); + + +extern volatile __bit G3D2T __attribute__((address(0x6F3))); + + +extern volatile __bit G3D3N __attribute__((address(0x6F4))); + + +extern volatile __bit G3D3T __attribute__((address(0x6F5))); + + +extern volatile __bit G3D4N __attribute__((address(0x6F6))); + + +extern volatile __bit G3D4T __attribute__((address(0x6F7))); + + +extern volatile __bit G3EN __attribute__((address(0x1E97))); + + +extern volatile __bit G3POL __attribute__((address(0x6BA))); + + +extern volatile __bit G4D1N __attribute__((address(0x6F8))); + + +extern volatile __bit G4D1T __attribute__((address(0x6F9))); + + +extern volatile __bit G4D2N __attribute__((address(0x6FA))); + + +extern volatile __bit G4D2T __attribute__((address(0x6FB))); + + +extern volatile __bit G4D3N __attribute__((address(0x6FC))); + + +extern volatile __bit G4D3T __attribute__((address(0x6FD))); + + +extern volatile __bit G4D4N __attribute__((address(0x6FE))); + + +extern volatile __bit G4D4T __attribute__((address(0x6FF))); + + +extern volatile __bit G4POL __attribute__((address(0x6BB))); + + +extern volatile __bit GCEN __attribute__((address(0x14B6))); + + +extern volatile __bit GIE __attribute__((address(0x26B7))); + + +extern volatile __bit GIEH __attribute__((address(0x26B7))); + + +extern volatile __bit GIEL __attribute__((address(0x26B6))); + + +extern volatile __bit GO_NOT_DONE __attribute__((address(0x1F98))); + + +extern volatile __bit GO_nDONE __attribute__((address(0x1F98))); + + +extern volatile __bit HADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit HADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit HADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit HADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit HADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit HADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit HADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit HADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit HADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit HADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit HADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit HADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit HADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit HADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit HADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit HADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit HADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit HADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit HADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit HADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit HADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit HADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit HFOEN __attribute__((address(0x59E))); + + +extern volatile __bit HFOR __attribute__((address(0x596))); + + +extern volatile __bit HLVDEN __attribute__((address(0x257))); + + +extern volatile __bit HLVDIE __attribute__((address(0x24F1))); + + +extern volatile __bit HLVDIF __attribute__((address(0x2571))); + + +extern volatile __bit HLVDINTH __attribute__((address(0x251))); + + +extern volatile __bit HLVDINTL __attribute__((address(0x250))); + + +extern volatile __bit HLVDIP __attribute__((address(0x1B11))); + + +extern volatile __bit HLVDMD __attribute__((address(0x305))); + + +extern volatile __bit HLVDOUT __attribute__((address(0x255))); + + +extern volatile __bit HLVDRDY __attribute__((address(0x254))); + + +extern volatile __bit HLVDSEL0 __attribute__((address(0x258))); + + +extern volatile __bit HLVDSEL1 __attribute__((address(0x259))); + + +extern volatile __bit HLVDSEL2 __attribute__((address(0x25A))); + + +extern volatile __bit HLVDSEL3 __attribute__((address(0x25B))); + + +extern volatile __bit I2C1EIE __attribute__((address(0x252B))); + + +extern volatile __bit I2C1EIF __attribute__((address(0x25AB))); + + +extern volatile __bit I2C1EIP __attribute__((address(0x1B4B))); + + +extern volatile __bit I2C1IE __attribute__((address(0x252A))); + + +extern volatile __bit I2C1IF __attribute__((address(0x25AA))); + + +extern volatile __bit I2C1IP __attribute__((address(0x1B4A))); + + +extern volatile __bit I2C1MD __attribute__((address(0x330))); + + +extern volatile __bit I2C1RXIE __attribute__((address(0x2528))); + + +extern volatile __bit I2C1RXIF __attribute__((address(0x25A8))); + + +extern volatile __bit I2C1RXIP __attribute__((address(0x1B48))); + + +extern volatile __bit I2C1SCLPPS0 __attribute__((address(0x1388))); + + +extern volatile __bit I2C1SCLPPS1 __attribute__((address(0x1389))); + + +extern volatile __bit I2C1SCLPPS2 __attribute__((address(0x138A))); + + +extern volatile __bit I2C1SCLPPS3 __attribute__((address(0x138B))); + + +extern volatile __bit I2C1SCLPPS4 __attribute__((address(0x138C))); + + +extern volatile __bit I2C1SDAPPS0 __attribute__((address(0x1380))); + + +extern volatile __bit I2C1SDAPPS1 __attribute__((address(0x1381))); + + +extern volatile __bit I2C1SDAPPS2 __attribute__((address(0x1382))); + + +extern volatile __bit I2C1SDAPPS3 __attribute__((address(0x1383))); + + +extern volatile __bit I2C1SDAPPS4 __attribute__((address(0x1384))); + + +extern volatile __bit I2C1TXIE __attribute__((address(0x2529))); + + +extern volatile __bit I2C1TXIF __attribute__((address(0x25A9))); + + +extern volatile __bit I2C1TXIP __attribute__((address(0x1B49))); + + +extern volatile __bit I2CBTOC0 __attribute__((address(0x14F8))); + + +extern volatile __bit I2CBTOC1 __attribute__((address(0x14F9))); + + +extern volatile __bit I2CBTOC2 __attribute__((address(0x14FA))); + + +extern volatile __bit I2CBTOC3 __attribute__((address(0x14FB))); + + +extern volatile __bit I2CCLK0 __attribute__((address(0x14F0))); + + +extern volatile __bit I2CCLK1 __attribute__((address(0x14F1))); + + +extern volatile __bit I2CCLK2 __attribute__((address(0x14F2))); + + +extern volatile __bit I2CCLK3 __attribute__((address(0x14F3))); + + +extern volatile __bit I2CCLK4 __attribute__((address(0x14F4))); + + +extern volatile __bit I2CEN __attribute__((address(0x14A7))); + + +extern volatile __bit IDLEN __attribute__((address(0x2797))); + + +extern volatile __bit INLVLA0 __attribute__((address(0x2020))); + + +extern volatile __bit INLVLA1 __attribute__((address(0x2021))); + + +extern volatile __bit INLVLA2 __attribute__((address(0x2022))); + + +extern volatile __bit INLVLA3 __attribute__((address(0x2023))); + + +extern volatile __bit INLVLA4 __attribute__((address(0x2024))); + + +extern volatile __bit INLVLA5 __attribute__((address(0x2025))); + + +extern volatile __bit INLVLA6 __attribute__((address(0x2026))); + + +extern volatile __bit INLVLA7 __attribute__((address(0x2027))); + + +extern volatile __bit INLVLB0 __attribute__((address(0x2060))); + + +extern volatile __bit INLVLB1 __attribute__((address(0x2061))); + + +extern volatile __bit INLVLB2 __attribute__((address(0x2062))); + + +extern volatile __bit INLVLB3 __attribute__((address(0x2063))); + + +extern volatile __bit INLVLB4 __attribute__((address(0x2064))); + + +extern volatile __bit INLVLB5 __attribute__((address(0x2065))); + + +extern volatile __bit INLVLB6 __attribute__((address(0x2066))); + + +extern volatile __bit INLVLB7 __attribute__((address(0x2067))); + + +extern volatile __bit INLVLC0 __attribute__((address(0x20A0))); + + +extern volatile __bit INLVLC1 __attribute__((address(0x20A1))); + + +extern volatile __bit INLVLC2 __attribute__((address(0x20A2))); + + +extern volatile __bit INLVLC3 __attribute__((address(0x20A3))); + + +extern volatile __bit INLVLC4 __attribute__((address(0x20A4))); + + +extern volatile __bit INLVLC5 __attribute__((address(0x20A5))); + + +extern volatile __bit INLVLC6 __attribute__((address(0x20A6))); + + +extern volatile __bit INLVLC7 __attribute__((address(0x20A7))); + + +extern volatile __bit INLVLE3 __attribute__((address(0x2123))); + + +extern volatile __bit INT0EDG __attribute__((address(0x26B0))); + + +extern volatile __bit INT0IE __attribute__((address(0x24F8))); + + +extern volatile __bit INT0IF __attribute__((address(0x2578))); + + +extern volatile __bit INT0IP __attribute__((address(0x1B18))); + + +extern volatile __bit INT0PPS0 __attribute__((address(0x11F0))); + + +extern volatile __bit INT0PPS1 __attribute__((address(0x11F1))); + + +extern volatile __bit INT0PPS2 __attribute__((address(0x11F2))); + + +extern volatile __bit INT0PPS3 __attribute__((address(0x11F3))); + + +extern volatile __bit INT1EDG __attribute__((address(0x26B1))); + + +extern volatile __bit INT1IE __attribute__((address(0x2520))); + + +extern volatile __bit INT1IF __attribute__((address(0x25A0))); + + +extern volatile __bit INT1IP __attribute__((address(0x1B40))); + + +extern volatile __bit INT1PPS0 __attribute__((address(0x11F8))); + + +extern volatile __bit INT1PPS1 __attribute__((address(0x11F9))); + + +extern volatile __bit INT1PPS2 __attribute__((address(0x11FA))); + + +extern volatile __bit INT1PPS3 __attribute__((address(0x11FB))); + + +extern volatile __bit INT1PPS4 __attribute__((address(0x11FC))); + + +extern volatile __bit INT2EDG __attribute__((address(0x26B2))); + + +extern volatile __bit INT2IE __attribute__((address(0x2540))); + + +extern volatile __bit INT2IF __attribute__((address(0x25C0))); + + +extern volatile __bit INT2IP __attribute__((address(0x1B60))); + + +extern volatile __bit INT2PPS0 __attribute__((address(0x1200))); + + +extern volatile __bit INT2PPS1 __attribute__((address(0x1201))); + + +extern volatile __bit INT2PPS2 __attribute__((address(0x1202))); + + +extern volatile __bit INT2PPS3 __attribute__((address(0x1203))); + + +extern volatile __bit INT2PPS4 __attribute__((address(0x1204))); + + +extern volatile __bit INT2PPS5 __attribute__((address(0x1205))); + + +extern volatile __bit INTH __attribute__((address(0x251))); + + +extern volatile __bit INTL __attribute__((address(0x250))); + + +extern volatile __bit IOCAF0 __attribute__((address(0x2038))); + + +extern volatile __bit IOCAF1 __attribute__((address(0x2039))); + + +extern volatile __bit IOCAF2 __attribute__((address(0x203A))); + + +extern volatile __bit IOCAF3 __attribute__((address(0x203B))); + + +extern volatile __bit IOCAF4 __attribute__((address(0x203C))); + + +extern volatile __bit IOCAF5 __attribute__((address(0x203D))); + + +extern volatile __bit IOCAF6 __attribute__((address(0x203E))); + + +extern volatile __bit IOCAF7 __attribute__((address(0x203F))); + + +extern volatile __bit IOCAN0 __attribute__((address(0x2030))); + + +extern volatile __bit IOCAN1 __attribute__((address(0x2031))); + + +extern volatile __bit IOCAN2 __attribute__((address(0x2032))); + + +extern volatile __bit IOCAN3 __attribute__((address(0x2033))); + + +extern volatile __bit IOCAN4 __attribute__((address(0x2034))); + + +extern volatile __bit IOCAN5 __attribute__((address(0x2035))); + + +extern volatile __bit IOCAN6 __attribute__((address(0x2036))); + + +extern volatile __bit IOCAN7 __attribute__((address(0x2037))); + + +extern volatile __bit IOCAP0 __attribute__((address(0x2028))); + + +extern volatile __bit IOCAP1 __attribute__((address(0x2029))); + + +extern volatile __bit IOCAP2 __attribute__((address(0x202A))); + + +extern volatile __bit IOCAP3 __attribute__((address(0x202B))); + + +extern volatile __bit IOCAP4 __attribute__((address(0x202C))); + + +extern volatile __bit IOCAP5 __attribute__((address(0x202D))); + + +extern volatile __bit IOCAP6 __attribute__((address(0x202E))); + + +extern volatile __bit IOCAP7 __attribute__((address(0x202F))); + + +extern volatile __bit IOCBF0 __attribute__((address(0x2078))); + + +extern volatile __bit IOCBF1 __attribute__((address(0x2079))); + + +extern volatile __bit IOCBF2 __attribute__((address(0x207A))); + + +extern volatile __bit IOCBF3 __attribute__((address(0x207B))); + + +extern volatile __bit IOCBF4 __attribute__((address(0x207C))); + + +extern volatile __bit IOCBF5 __attribute__((address(0x207D))); + + +extern volatile __bit IOCBF6 __attribute__((address(0x207E))); + + +extern volatile __bit IOCBF7 __attribute__((address(0x207F))); + + +extern volatile __bit IOCBN0 __attribute__((address(0x2070))); + + +extern volatile __bit IOCBN1 __attribute__((address(0x2071))); + + +extern volatile __bit IOCBN2 __attribute__((address(0x2072))); + + +extern volatile __bit IOCBN3 __attribute__((address(0x2073))); + + +extern volatile __bit IOCBN4 __attribute__((address(0x2074))); + + +extern volatile __bit IOCBN5 __attribute__((address(0x2075))); + + +extern volatile __bit IOCBN6 __attribute__((address(0x2076))); + + +extern volatile __bit IOCBN7 __attribute__((address(0x2077))); + + +extern volatile __bit IOCBP0 __attribute__((address(0x2068))); + + +extern volatile __bit IOCBP1 __attribute__((address(0x2069))); + + +extern volatile __bit IOCBP2 __attribute__((address(0x206A))); + + +extern volatile __bit IOCBP3 __attribute__((address(0x206B))); + + +extern volatile __bit IOCBP4 __attribute__((address(0x206C))); + + +extern volatile __bit IOCBP5 __attribute__((address(0x206D))); + + +extern volatile __bit IOCBP6 __attribute__((address(0x206E))); + + +extern volatile __bit IOCBP7 __attribute__((address(0x206F))); + + +extern volatile __bit IOCCF0 __attribute__((address(0x20B8))); + + +extern volatile __bit IOCCF1 __attribute__((address(0x20B9))); + + +extern volatile __bit IOCCF2 __attribute__((address(0x20BA))); + + +extern volatile __bit IOCCF3 __attribute__((address(0x20BB))); + + +extern volatile __bit IOCCF4 __attribute__((address(0x20BC))); + + +extern volatile __bit IOCCF5 __attribute__((address(0x20BD))); + + +extern volatile __bit IOCCF6 __attribute__((address(0x20BE))); + + +extern volatile __bit IOCCF7 __attribute__((address(0x20BF))); + + +extern volatile __bit IOCCN0 __attribute__((address(0x20B0))); + + +extern volatile __bit IOCCN1 __attribute__((address(0x20B1))); + + +extern volatile __bit IOCCN2 __attribute__((address(0x20B2))); + + +extern volatile __bit IOCCN3 __attribute__((address(0x20B3))); + + +extern volatile __bit IOCCN4 __attribute__((address(0x20B4))); + + +extern volatile __bit IOCCN5 __attribute__((address(0x20B5))); + + +extern volatile __bit IOCCN6 __attribute__((address(0x20B6))); + + +extern volatile __bit IOCCN7 __attribute__((address(0x20B7))); + + +extern volatile __bit IOCCP0 __attribute__((address(0x20A8))); + + +extern volatile __bit IOCCP1 __attribute__((address(0x20A9))); + + +extern volatile __bit IOCCP2 __attribute__((address(0x20AA))); + + +extern volatile __bit IOCCP3 __attribute__((address(0x20AB))); + + +extern volatile __bit IOCCP4 __attribute__((address(0x20AC))); + + +extern volatile __bit IOCCP5 __attribute__((address(0x20AD))); + + +extern volatile __bit IOCCP6 __attribute__((address(0x20AE))); + + +extern volatile __bit IOCCP7 __attribute__((address(0x20AF))); + + +extern volatile __bit IOCEF3 __attribute__((address(0x213B))); + + +extern volatile __bit IOCEN3 __attribute__((address(0x2133))); + + +extern volatile __bit IOCEP3 __attribute__((address(0x212B))); + + +extern volatile __bit IOCIE __attribute__((address(0x24F7))); + + +extern volatile __bit IOCIF __attribute__((address(0x2577))); + + +extern volatile __bit IOCIP __attribute__((address(0x1B17))); + + +extern volatile __bit IOCMD __attribute__((address(0x300))); + + +extern volatile __bit ISOCRCEN __attribute__((address(0x805))); + + +extern volatile __bit ISRPR0 __attribute__((address(0x5F8))); + + +extern volatile __bit ISRPR1 __attribute__((address(0x5F9))); + + +extern volatile __bit ISRPR2 __attribute__((address(0x5FA))); + + +extern volatile __bit IVMIE __attribute__((address(0x8FF))); + + +extern volatile __bit IVMIF __attribute__((address(0x8EF))); + + +extern volatile __bit IVTLOCKED __attribute__((address(0x22C8))); + + +extern volatile __bit LADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit LADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit LADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit LADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit LADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit LADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit LADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit LADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit LADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit LADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit LADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit LADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit LADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit LADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit LADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit LADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit LADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit LADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit LADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit LADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit LADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit LADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit LATA0 __attribute__((address(0x25F0))); + + +extern volatile __bit LATA1 __attribute__((address(0x25F1))); + + +extern volatile __bit LATA2 __attribute__((address(0x25F2))); + + +extern volatile __bit LATA3 __attribute__((address(0x25F3))); + + +extern volatile __bit LATA4 __attribute__((address(0x25F4))); + + +extern volatile __bit LATA5 __attribute__((address(0x25F5))); + + +extern volatile __bit LATA6 __attribute__((address(0x25F6))); + + +extern volatile __bit LATA7 __attribute__((address(0x25F7))); + + +extern volatile __bit LATB0 __attribute__((address(0x25F8))); + + +extern volatile __bit LATB1 __attribute__((address(0x25F9))); + + +extern volatile __bit LATB2 __attribute__((address(0x25FA))); + + +extern volatile __bit LATB3 __attribute__((address(0x25FB))); + + +extern volatile __bit LATB4 __attribute__((address(0x25FC))); + + +extern volatile __bit LATB5 __attribute__((address(0x25FD))); + + +extern volatile __bit LATB6 __attribute__((address(0x25FE))); + + +extern volatile __bit LATB7 __attribute__((address(0x25FF))); + + +extern volatile __bit LATC0 __attribute__((address(0x2600))); + + +extern volatile __bit LATC1 __attribute__((address(0x2601))); + + +extern volatile __bit LATC2 __attribute__((address(0x2602))); + + +extern volatile __bit LATC3 __attribute__((address(0x2603))); + + +extern volatile __bit LATC4 __attribute__((address(0x2604))); + + +extern volatile __bit LATC5 __attribute__((address(0x2605))); + + +extern volatile __bit LATC6 __attribute__((address(0x2606))); + + +extern volatile __bit LATC7 __attribute__((address(0x2607))); + + +extern volatile __bit LENDIAN __attribute__((address(0x1AB9))); + + +extern volatile __bit LFOEN __attribute__((address(0x59C))); + + +extern volatile __bit LFOR __attribute__((address(0x594))); + + +extern volatile __bit LTH0 __attribute__((address(0x1EC8))); + + +extern volatile __bit LTH1 __attribute__((address(0x1EC9))); + + +extern volatile __bit LTH10 __attribute__((address(0x1ED2))); + + +extern volatile __bit LTH11 __attribute__((address(0x1ED3))); + + +extern volatile __bit LTH12 __attribute__((address(0x1ED4))); + + +extern volatile __bit LTH13 __attribute__((address(0x1ED5))); + + +extern volatile __bit LTH14 __attribute__((address(0x1ED6))); + + +extern volatile __bit LTH15 __attribute__((address(0x1ED7))); + + +extern volatile __bit LTH2 __attribute__((address(0x1ECA))); + + +extern volatile __bit LTH3 __attribute__((address(0x1ECB))); + + +extern volatile __bit LTH4 __attribute__((address(0x1ECC))); + + +extern volatile __bit LTH5 __attribute__((address(0x1ECD))); + + +extern volatile __bit LTH6 __attribute__((address(0x1ECE))); + + +extern volatile __bit LTH7 __attribute__((address(0x1ECF))); + + +extern volatile __bit LTH8 __attribute__((address(0x1ED0))); + + +extern volatile __bit LTH9 __attribute__((address(0x1ED1))); + + +extern volatile __bit LTHR __attribute__((address(0x1FBD))); + + +extern volatile __bit LVDMD __attribute__((address(0x305))); + + +extern volatile __bit MAINPR0 __attribute__((address(0x5F0))); + + +extern volatile __bit MAINPR1 __attribute__((address(0x5F1))); + + +extern volatile __bit MAINPR2 __attribute__((address(0x5F2))); + + +extern volatile __bit MATH __attribute__((address(0x1FBC))); + + +extern volatile __bit MC1OUT __attribute__((address(0x378))); + + +extern volatile __bit MC2OUT __attribute__((address(0x379))); + + +extern volatile __bit MCLC0 __attribute__((address(0x6A0))); + + +extern volatile __bit MCLC1 __attribute__((address(0x6A1))); + + +extern volatile __bit MCLC2 __attribute__((address(0x6A2))); + + +extern volatile __bit MCLC3 __attribute__((address(0x6A3))); + + +extern volatile __bit MCLC4 __attribute__((address(0x6A4))); + + +extern volatile __bit MCLC5 __attribute__((address(0x6A5))); + + +extern volatile __bit MCLC6 __attribute__((address(0x6A6))); + + +extern volatile __bit MCLC7 __attribute__((address(0x6A7))); + + +extern volatile __bit MD0 __attribute__((address(0x1FA8))); + + +extern volatile __bit MD1 __attribute__((address(0x1FA9))); + + +extern volatile __bit MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit MD1BIT __attribute__((address(0x350))); + + +extern volatile __bit MD1CH0 __attribute__((address(0x370))); + + +extern volatile __bit MD1CH1 __attribute__((address(0x371))); + + +extern volatile __bit MD1CH2 __attribute__((address(0x372))); + + +extern volatile __bit MD1CH3 __attribute__((address(0x373))); + + +extern volatile __bit MD1CH4 __attribute__((address(0x374))); + + +extern volatile __bit MD1CHPOL __attribute__((address(0x35D))); + + +extern volatile __bit MD1CHSYNC __attribute__((address(0x35C))); + + +extern volatile __bit MD1CL0 __attribute__((address(0x368))); + + +extern volatile __bit MD1CL1 __attribute__((address(0x369))); + + +extern volatile __bit MD1CL2 __attribute__((address(0x36A))); + + +extern volatile __bit MD1CL3 __attribute__((address(0x36B))); + + +extern volatile __bit MD1CL4 __attribute__((address(0x36C))); + + +extern volatile __bit MD1CLPOL __attribute__((address(0x359))); + + +extern volatile __bit MD1CLSYNC __attribute__((address(0x358))); + + +extern volatile __bit MD1EN __attribute__((address(0x357))); + + +extern volatile __bit MD1MS0 __attribute__((address(0x360))); + + +extern volatile __bit MD1MS1 __attribute__((address(0x361))); + + +extern volatile __bit MD1MS2 __attribute__((address(0x362))); + + +extern volatile __bit MD1MS3 __attribute__((address(0x363))); + + +extern volatile __bit MD1MS4 __attribute__((address(0x364))); + + +extern volatile __bit MD1MS5 __attribute__((address(0x365))); + + +extern volatile __bit MD1OPOL __attribute__((address(0x354))); + + +extern volatile __bit MD1OUT __attribute__((address(0x355))); + + +extern volatile __bit MD2 __attribute__((address(0x1FAA))); + + +extern volatile __bit MDCARHPPS0 __attribute__((address(0x12F8))); + + +extern volatile __bit MDCARHPPS1 __attribute__((address(0x12F9))); + + +extern volatile __bit MDCARHPPS2 __attribute__((address(0x12FA))); + + +extern volatile __bit MDCARHPPS3 __attribute__((address(0x12FB))); + + +extern volatile __bit MDCARHPPS4 __attribute__((address(0x12FC))); + + +extern volatile __bit MDCARLPPS0 __attribute__((address(0x12F0))); + + +extern volatile __bit MDCARLPPS1 __attribute__((address(0x12F1))); + + +extern volatile __bit MDCARLPPS2 __attribute__((address(0x12F2))); + + +extern volatile __bit MDCARLPPS3 __attribute__((address(0x12F3))); + + +extern volatile __bit MDCARLPPS4 __attribute__((address(0x12F4))); + + +extern volatile __bit MDR __attribute__((address(0x14A3))); + + +extern volatile __bit MDSRCPPS0 __attribute__((address(0x1300))); + + +extern volatile __bit MDSRCPPS1 __attribute__((address(0x1301))); + + +extern volatile __bit MDSRCPPS2 __attribute__((address(0x1302))); + + +extern volatile __bit MDSRCPPS3 __attribute__((address(0x1303))); + + +extern volatile __bit MDSRCPPS4 __attribute__((address(0x1304))); + + +extern volatile __bit MEMV __attribute__((address(0x2789))); + + +extern volatile __bit MFOEN __attribute__((address(0x59D))); + + +extern volatile __bit MFOR __attribute__((address(0x595))); + + +extern volatile __bit MMA __attribute__((address(0x14C5))); + + +extern volatile __bit MODIE __attribute__((address(0x8F3))); + + +extern volatile __bit MODIF __attribute__((address(0x8E3))); + + +extern volatile __bit MREG __attribute__((address(0x1B02))); + + +extern volatile __bit MS0 __attribute__((address(0x360))); + + +extern volatile __bit MS1 __attribute__((address(0x361))); + + +extern volatile __bit MS2 __attribute__((address(0x362))); + + +extern volatile __bit MS3 __attribute__((address(0x363))); + + +extern volatile __bit MS4 __attribute__((address(0x364))); + + +extern volatile __bit MS5 __attribute__((address(0x365))); + + +extern volatile __bit NACK1IE __attribute__((address(0x14B8))); + + +extern volatile __bit NACK1IF __attribute__((address(0x14BC))); + + +extern volatile __bit NACKERR __attribute__((address(0x9F2))); + + +extern volatile __bit NACKIE __attribute__((address(0x14B8))); + + +extern volatile __bit NACKIF __attribute__((address(0x14BC))); + + +extern volatile __bit NBIT0ERR __attribute__((address(0x9F0))); + + +extern volatile __bit NBIT1ERR __attribute__((address(0x9F1))); + + +extern volatile __bit NCO1ACC0 __attribute__((address(0x2200))); + + +extern volatile __bit NCO1ACC1 __attribute__((address(0x2201))); + + +extern volatile __bit NCO1ACC10 __attribute__((address(0x220A))); + + +extern volatile __bit NCO1ACC11 __attribute__((address(0x220B))); + + +extern volatile __bit NCO1ACC12 __attribute__((address(0x220C))); + + +extern volatile __bit NCO1ACC13 __attribute__((address(0x220D))); + + +extern volatile __bit NCO1ACC14 __attribute__((address(0x220E))); + + +extern volatile __bit NCO1ACC15 __attribute__((address(0x220F))); + + +extern volatile __bit NCO1ACC16 __attribute__((address(0x2210))); + + +extern volatile __bit NCO1ACC17 __attribute__((address(0x2211))); + + +extern volatile __bit NCO1ACC18 __attribute__((address(0x2212))); + + +extern volatile __bit NCO1ACC19 __attribute__((address(0x2213))); + + +extern volatile __bit NCO1ACC2 __attribute__((address(0x2202))); + + +extern volatile __bit NCO1ACC20 __attribute__((address(0x2214))); + + +extern volatile __bit NCO1ACC21 __attribute__((address(0x2215))); + + +extern volatile __bit NCO1ACC22 __attribute__((address(0x2216))); + + +extern volatile __bit NCO1ACC23 __attribute__((address(0x2217))); + + +extern volatile __bit NCO1ACC3 __attribute__((address(0x2203))); + + +extern volatile __bit NCO1ACC4 __attribute__((address(0x2204))); + + +extern volatile __bit NCO1ACC5 __attribute__((address(0x2205))); + + +extern volatile __bit NCO1ACC6 __attribute__((address(0x2206))); + + +extern volatile __bit NCO1ACC7 __attribute__((address(0x2207))); + + +extern volatile __bit NCO1ACC8 __attribute__((address(0x2208))); + + +extern volatile __bit NCO1ACC9 __attribute__((address(0x2209))); + + +extern volatile __bit NCO1CKS0 __attribute__((address(0x2238))); + + +extern volatile __bit NCO1CKS1 __attribute__((address(0x2239))); + + +extern volatile __bit NCO1CKS2 __attribute__((address(0x223A))); + + +extern volatile __bit NCO1CKS3 __attribute__((address(0x223B))); + + +extern volatile __bit NCO1EN __attribute__((address(0x2237))); + + +extern volatile __bit NCO1IE __attribute__((address(0x2523))); + + +extern volatile __bit NCO1IF __attribute__((address(0x25A3))); + + +extern volatile __bit NCO1INC0 __attribute__((address(0x2218))); + + +extern volatile __bit NCO1INC1 __attribute__((address(0x2219))); + + +extern volatile __bit NCO1INC10 __attribute__((address(0x2222))); + + +extern volatile __bit NCO1INC11 __attribute__((address(0x2223))); + + +extern volatile __bit NCO1INC12 __attribute__((address(0x2224))); + + +extern volatile __bit NCO1INC13 __attribute__((address(0x2225))); + + +extern volatile __bit NCO1INC14 __attribute__((address(0x2226))); + + +extern volatile __bit NCO1INC15 __attribute__((address(0x2227))); + + +extern volatile __bit NCO1INC16 __attribute__((address(0x2228))); + + +extern volatile __bit NCO1INC17 __attribute__((address(0x2229))); + + +extern volatile __bit NCO1INC18 __attribute__((address(0x222A))); + + +extern volatile __bit NCO1INC19 __attribute__((address(0x222B))); + + +extern volatile __bit NCO1INC2 __attribute__((address(0x221A))); + + +extern volatile __bit NCO1INC20 __attribute__((address(0x222C))); + + +extern volatile __bit NCO1INC21 __attribute__((address(0x222D))); + + +extern volatile __bit NCO1INC22 __attribute__((address(0x222E))); + + +extern volatile __bit NCO1INC23 __attribute__((address(0x222F))); + + +extern volatile __bit NCO1INC3 __attribute__((address(0x221B))); + + +extern volatile __bit NCO1INC4 __attribute__((address(0x221C))); + + +extern volatile __bit NCO1INC5 __attribute__((address(0x221D))); + + +extern volatile __bit NCO1INC6 __attribute__((address(0x221E))); + + +extern volatile __bit NCO1INC7 __attribute__((address(0x221F))); + + +extern volatile __bit NCO1INC8 __attribute__((address(0x2220))); + + +extern volatile __bit NCO1INC9 __attribute__((address(0x2221))); + + +extern volatile __bit NCO1IP __attribute__((address(0x1B43))); + + +extern volatile __bit NCO1MD __attribute__((address(0x320))); + + +extern volatile __bit NCO1OUT __attribute__((address(0x2235))); + + +extern volatile __bit NCO1PFM __attribute__((address(0x2230))); + + +extern volatile __bit NCO1POL __attribute__((address(0x2234))); + + +extern volatile __bit NCO1PWS0 __attribute__((address(0x223D))); + + +extern volatile __bit NCO1PWS1 __attribute__((address(0x223E))); + + +extern volatile __bit NCO1PWS2 __attribute__((address(0x223F))); + + +extern volatile __bit NCO2ACC0 __attribute__((address(0x2240))); + + +extern volatile __bit NCO2ACC1 __attribute__((address(0x2241))); + + +extern volatile __bit NCO2ACC10 __attribute__((address(0x224A))); + + +extern volatile __bit NCO2ACC11 __attribute__((address(0x224B))); + + +extern volatile __bit NCO2ACC12 __attribute__((address(0x224C))); + + +extern volatile __bit NCO2ACC13 __attribute__((address(0x224D))); + + +extern volatile __bit NCO2ACC14 __attribute__((address(0x224E))); + + +extern volatile __bit NCO2ACC15 __attribute__((address(0x224F))); + + +extern volatile __bit NCO2ACC16 __attribute__((address(0x2250))); + + +extern volatile __bit NCO2ACC17 __attribute__((address(0x2251))); + + +extern volatile __bit NCO2ACC18 __attribute__((address(0x2252))); + + +extern volatile __bit NCO2ACC19 __attribute__((address(0x2253))); + + +extern volatile __bit NCO2ACC2 __attribute__((address(0x2242))); + + +extern volatile __bit NCO2ACC20 __attribute__((address(0x2254))); + + +extern volatile __bit NCO2ACC21 __attribute__((address(0x2255))); + + +extern volatile __bit NCO2ACC22 __attribute__((address(0x2256))); + + +extern volatile __bit NCO2ACC23 __attribute__((address(0x2257))); + + +extern volatile __bit NCO2ACC3 __attribute__((address(0x2243))); + + +extern volatile __bit NCO2ACC4 __attribute__((address(0x2244))); + + +extern volatile __bit NCO2ACC5 __attribute__((address(0x2245))); + + +extern volatile __bit NCO2ACC6 __attribute__((address(0x2246))); + + +extern volatile __bit NCO2ACC7 __attribute__((address(0x2247))); + + +extern volatile __bit NCO2ACC8 __attribute__((address(0x2248))); + + +extern volatile __bit NCO2ACC9 __attribute__((address(0x2249))); + + +extern volatile __bit NCO2CKS0 __attribute__((address(0x2278))); + + +extern volatile __bit NCO2CKS1 __attribute__((address(0x2279))); + + +extern volatile __bit NCO2CKS2 __attribute__((address(0x227A))); + + +extern volatile __bit NCO2CKS3 __attribute__((address(0x227B))); + + +extern volatile __bit NCO2EN __attribute__((address(0x2277))); + + +extern volatile __bit NCO2IE __attribute__((address(0x2543))); + + +extern volatile __bit NCO2IF __attribute__((address(0x25C3))); + + +extern volatile __bit NCO2INC0 __attribute__((address(0x2258))); + + +extern volatile __bit NCO2INC1 __attribute__((address(0x2259))); + + +extern volatile __bit NCO2INC10 __attribute__((address(0x2262))); + + +extern volatile __bit NCO2INC11 __attribute__((address(0x2263))); + + +extern volatile __bit NCO2INC12 __attribute__((address(0x2264))); + + +extern volatile __bit NCO2INC13 __attribute__((address(0x2265))); + + +extern volatile __bit NCO2INC14 __attribute__((address(0x2266))); + + +extern volatile __bit NCO2INC15 __attribute__((address(0x2267))); + + +extern volatile __bit NCO2INC16 __attribute__((address(0x2268))); + + +extern volatile __bit NCO2INC17 __attribute__((address(0x2269))); + + +extern volatile __bit NCO2INC18 __attribute__((address(0x226A))); + + +extern volatile __bit NCO2INC19 __attribute__((address(0x226B))); + + +extern volatile __bit NCO2INC2 __attribute__((address(0x225A))); + + +extern volatile __bit NCO2INC20 __attribute__((address(0x226C))); + + +extern volatile __bit NCO2INC21 __attribute__((address(0x226D))); + + +extern volatile __bit NCO2INC22 __attribute__((address(0x226E))); + + +extern volatile __bit NCO2INC23 __attribute__((address(0x226F))); + + +extern volatile __bit NCO2INC3 __attribute__((address(0x225B))); + + +extern volatile __bit NCO2INC4 __attribute__((address(0x225C))); + + +extern volatile __bit NCO2INC5 __attribute__((address(0x225D))); + + +extern volatile __bit NCO2INC6 __attribute__((address(0x225E))); + + +extern volatile __bit NCO2INC7 __attribute__((address(0x225F))); + + +extern volatile __bit NCO2INC8 __attribute__((address(0x2260))); + + +extern volatile __bit NCO2INC9 __attribute__((address(0x2261))); + + +extern volatile __bit NCO2IP __attribute__((address(0x1B63))); + + +extern volatile __bit NCO2MD __attribute__((address(0x321))); + + +extern volatile __bit NCO2OUT __attribute__((address(0x2275))); + + +extern volatile __bit NCO2PFM __attribute__((address(0x2270))); + + +extern volatile __bit NCO2POL __attribute__((address(0x2274))); + + +extern volatile __bit NCO2PWS0 __attribute__((address(0x227D))); + + +extern volatile __bit NCO2PWS1 __attribute__((address(0x227E))); + + +extern volatile __bit NCO2PWS2 __attribute__((address(0x227F))); + + +extern volatile __bit NCO3ACC0 __attribute__((address(0x2280))); + + +extern volatile __bit NCO3ACC1 __attribute__((address(0x2281))); + + +extern volatile __bit NCO3ACC10 __attribute__((address(0x228A))); + + +extern volatile __bit NCO3ACC11 __attribute__((address(0x228B))); + + +extern volatile __bit NCO3ACC12 __attribute__((address(0x228C))); + + +extern volatile __bit NCO3ACC13 __attribute__((address(0x228D))); + + +extern volatile __bit NCO3ACC14 __attribute__((address(0x228E))); + + +extern volatile __bit NCO3ACC15 __attribute__((address(0x228F))); + + +extern volatile __bit NCO3ACC16 __attribute__((address(0x2290))); + + +extern volatile __bit NCO3ACC17 __attribute__((address(0x2291))); + + +extern volatile __bit NCO3ACC18 __attribute__((address(0x2292))); + + +extern volatile __bit NCO3ACC19 __attribute__((address(0x2293))); + + +extern volatile __bit NCO3ACC2 __attribute__((address(0x2282))); + + +extern volatile __bit NCO3ACC20 __attribute__((address(0x2294))); + + +extern volatile __bit NCO3ACC21 __attribute__((address(0x2295))); + + +extern volatile __bit NCO3ACC22 __attribute__((address(0x2296))); + + +extern volatile __bit NCO3ACC23 __attribute__((address(0x2297))); + + +extern volatile __bit NCO3ACC3 __attribute__((address(0x2283))); + + +extern volatile __bit NCO3ACC4 __attribute__((address(0x2284))); + + +extern volatile __bit NCO3ACC5 __attribute__((address(0x2285))); + + +extern volatile __bit NCO3ACC6 __attribute__((address(0x2286))); + + +extern volatile __bit NCO3ACC7 __attribute__((address(0x2287))); + + +extern volatile __bit NCO3ACC8 __attribute__((address(0x2288))); + + +extern volatile __bit NCO3ACC9 __attribute__((address(0x2289))); + + +extern volatile __bit NCO3CKS0 __attribute__((address(0x22B8))); + + +extern volatile __bit NCO3CKS1 __attribute__((address(0x22B9))); + + +extern volatile __bit NCO3CKS2 __attribute__((address(0x22BA))); + + +extern volatile __bit NCO3CKS3 __attribute__((address(0x22BB))); + + +extern volatile __bit NCO3EN __attribute__((address(0x22B7))); + + +extern volatile __bit NCO3IE __attribute__((address(0x2563))); + + +extern volatile __bit NCO3IF __attribute__((address(0x25E3))); + + +extern volatile __bit NCO3INC0 __attribute__((address(0x2298))); + + +extern volatile __bit NCO3INC1 __attribute__((address(0x2299))); + + +extern volatile __bit NCO3INC10 __attribute__((address(0x22A2))); + + +extern volatile __bit NCO3INC11 __attribute__((address(0x22A3))); + + +extern volatile __bit NCO3INC12 __attribute__((address(0x22A4))); + + +extern volatile __bit NCO3INC13 __attribute__((address(0x22A5))); + + +extern volatile __bit NCO3INC14 __attribute__((address(0x22A6))); + + +extern volatile __bit NCO3INC15 __attribute__((address(0x22A7))); + + +extern volatile __bit NCO3INC16 __attribute__((address(0x22A8))); + + +extern volatile __bit NCO3INC17 __attribute__((address(0x22A9))); + + +extern volatile __bit NCO3INC18 __attribute__((address(0x22AA))); + + +extern volatile __bit NCO3INC19 __attribute__((address(0x22AB))); + + +extern volatile __bit NCO3INC2 __attribute__((address(0x229A))); + + +extern volatile __bit NCO3INC20 __attribute__((address(0x22AC))); + + +extern volatile __bit NCO3INC21 __attribute__((address(0x22AD))); + + +extern volatile __bit NCO3INC22 __attribute__((address(0x22AE))); + + +extern volatile __bit NCO3INC23 __attribute__((address(0x22AF))); + + +extern volatile __bit NCO3INC3 __attribute__((address(0x229B))); + + +extern volatile __bit NCO3INC4 __attribute__((address(0x229C))); + + +extern volatile __bit NCO3INC5 __attribute__((address(0x229D))); + + +extern volatile __bit NCO3INC6 __attribute__((address(0x229E))); + + +extern volatile __bit NCO3INC7 __attribute__((address(0x229F))); + + +extern volatile __bit NCO3INC8 __attribute__((address(0x22A0))); + + +extern volatile __bit NCO3INC9 __attribute__((address(0x22A1))); + + +extern volatile __bit NCO3IP __attribute__((address(0x1B83))); + + +extern volatile __bit NCO3MD __attribute__((address(0x322))); + + +extern volatile __bit NCO3OUT __attribute__((address(0x22B5))); + + +extern volatile __bit NCO3PFM __attribute__((address(0x22B0))); + + +extern volatile __bit NCO3POL __attribute__((address(0x22B4))); + + +extern volatile __bit NCO3PWS0 __attribute__((address(0x22BD))); + + +extern volatile __bit NCO3PWS1 __attribute__((address(0x22BE))); + + +extern volatile __bit NCO3PWS2 __attribute__((address(0x22BF))); + + +extern volatile __bit NCRCERR __attribute__((address(0x9F5))); + + +extern volatile __bit NDIV0 __attribute__((address(0x568))); + + +extern volatile __bit NDIV1 __attribute__((address(0x569))); + + +extern volatile __bit NDIV2 __attribute__((address(0x56A))); + + +extern volatile __bit NDIV3 __attribute__((address(0x56B))); + + +extern volatile __bit NFORMERR __attribute__((address(0x9F3))); + + +extern volatile __bit NOSC0 __attribute__((address(0x56C))); + + +extern volatile __bit NOSC1 __attribute__((address(0x56D))); + + +extern volatile __bit NOSC2 __attribute__((address(0x56E))); + + +extern volatile __bit NOSCR __attribute__((address(0x57B))); + + +extern volatile __bit NOT_A __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_ADDRESS __attribute__((address(0x14C3))); + + +extern volatile __bit NOT_BOR __attribute__((address(0x2780))); + + +extern volatile __bit NOT_MEMV __attribute__((address(0x2789))); + + +extern volatile __bit NOT_POR __attribute__((address(0x2781))); + + +extern volatile __bit NOT_RI __attribute__((address(0x2782))); + + +extern volatile __bit NOT_RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit NOT_RWDT __attribute__((address(0x2784))); + + +extern volatile __bit NOT_T1DONE __attribute__((address(0x18FB))); + + +extern volatile __bit NOT_T1SYNC __attribute__((address(0x18F2))); + + +extern volatile __bit NOT_T3DONE __attribute__((address(0x195B))); + + +extern volatile __bit NOT_T3SYNC __attribute__((address(0x1952))); + + +extern volatile __bit NOT_T5DONE __attribute__((address(0x19BB))); + + +extern volatile __bit NOT_T5SYNC __attribute__((address(0x19B2))); + + +extern volatile __bit NOT_W __attribute__((address(0x14C4))); + + +extern volatile __bit NOT_WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit NOT_WRITE __attribute__((address(0x14C4))); + + +extern volatile __bit NREF0 __attribute__((address(0x1FC4))); + + +extern volatile __bit NRERRCNT0 __attribute__((address(0x9C0))); + + +extern volatile __bit NRERRCNT1 __attribute__((address(0x9C1))); + + +extern volatile __bit NRERRCNT2 __attribute__((address(0x9C2))); + + +extern volatile __bit NRERRCNT3 __attribute__((address(0x9C3))); + + +extern volatile __bit NRERRCNT4 __attribute__((address(0x9C4))); + + +extern volatile __bit NRERRCNT5 __attribute__((address(0x9C5))); + + +extern volatile __bit NRERRCNT6 __attribute__((address(0x9C6))); + + +extern volatile __bit NRERRCNT7 __attribute__((address(0x9C7))); + + +extern volatile __bit NSS0 __attribute__((address(0x3F8))); + + +extern volatile __bit NSTUFERR __attribute__((address(0x9F4))); + + +extern volatile __bit NTERRCNT0 __attribute__((address(0x9C8))); + + +extern volatile __bit NTERRCNT1 __attribute__((address(0x9C9))); + + +extern volatile __bit NTERRCNT2 __attribute__((address(0x9CA))); + + +extern volatile __bit NTERRCNT3 __attribute__((address(0x9CB))); + + +extern volatile __bit NTERRCNT4 __attribute__((address(0x9CC))); + + +extern volatile __bit NTERRCNT5 __attribute__((address(0x9CD))); + + +extern volatile __bit NTERRCNT6 __attribute__((address(0x9CE))); + + +extern volatile __bit NTERRCNT7 __attribute__((address(0x9CF))); + + +extern volatile __bit NVMADR0 __attribute__((address(0x218))); + + +extern volatile __bit NVMADR1 __attribute__((address(0x219))); + + +extern volatile __bit NVMADR10 __attribute__((address(0x222))); + + +extern volatile __bit NVMADR11 __attribute__((address(0x223))); + + +extern volatile __bit NVMADR12 __attribute__((address(0x224))); + + +extern volatile __bit NVMADR13 __attribute__((address(0x225))); + + +extern volatile __bit NVMADR14 __attribute__((address(0x226))); + + +extern volatile __bit NVMADR15 __attribute__((address(0x227))); + + +extern volatile __bit NVMADR16 __attribute__((address(0x228))); + + +extern volatile __bit NVMADR17 __attribute__((address(0x229))); + + +extern volatile __bit NVMADR18 __attribute__((address(0x22A))); + + +extern volatile __bit NVMADR19 __attribute__((address(0x22B))); + + +extern volatile __bit NVMADR2 __attribute__((address(0x21A))); + + +extern volatile __bit NVMADR20 __attribute__((address(0x22C))); + + +extern volatile __bit NVMADR21 __attribute__((address(0x22D))); + + +extern volatile __bit NVMADR3 __attribute__((address(0x21B))); + + +extern volatile __bit NVMADR4 __attribute__((address(0x21C))); + + +extern volatile __bit NVMADR5 __attribute__((address(0x21D))); + + +extern volatile __bit NVMADR6 __attribute__((address(0x21E))); + + +extern volatile __bit NVMADR7 __attribute__((address(0x21F))); + + +extern volatile __bit NVMADR8 __attribute__((address(0x220))); + + +extern volatile __bit NVMADR9 __attribute__((address(0x221))); + + +extern volatile __bit NVMDAT0 __attribute__((address(0x230))); + + +extern volatile __bit NVMDAT1 __attribute__((address(0x231))); + + +extern volatile __bit NVMDAT10 __attribute__((address(0x23A))); + + +extern volatile __bit NVMDAT11 __attribute__((address(0x23B))); + + +extern volatile __bit NVMDAT12 __attribute__((address(0x23C))); + + +extern volatile __bit NVMDAT13 __attribute__((address(0x23D))); + + +extern volatile __bit NVMDAT14 __attribute__((address(0x23E))); + + +extern volatile __bit NVMDAT15 __attribute__((address(0x23F))); + + +extern volatile __bit NVMDAT2 __attribute__((address(0x232))); + + +extern volatile __bit NVMDAT3 __attribute__((address(0x233))); + + +extern volatile __bit NVMDAT4 __attribute__((address(0x234))); + + +extern volatile __bit NVMDAT5 __attribute__((address(0x235))); + + +extern volatile __bit NVMDAT6 __attribute__((address(0x236))); + + +extern volatile __bit NVMDAT7 __attribute__((address(0x237))); + + +extern volatile __bit NVMDAT8 __attribute__((address(0x238))); + + +extern volatile __bit NVMDAT9 __attribute__((address(0x239))); + + +extern volatile __bit NVMIE __attribute__((address(0x2568))); + + +extern volatile __bit NVMIF __attribute__((address(0x25E8))); + + +extern volatile __bit NVMIP __attribute__((address(0x1B88))); + + +extern volatile __bit ODCA0 __attribute__((address(0x2010))); + + +extern volatile __bit ODCA1 __attribute__((address(0x2011))); + + +extern volatile __bit ODCA2 __attribute__((address(0x2012))); + + +extern volatile __bit ODCA3 __attribute__((address(0x2013))); + + +extern volatile __bit ODCA4 __attribute__((address(0x2014))); + + +extern volatile __bit ODCA5 __attribute__((address(0x2015))); + + +extern volatile __bit ODCA6 __attribute__((address(0x2016))); + + +extern volatile __bit ODCA7 __attribute__((address(0x2017))); + + +extern volatile __bit ODCB0 __attribute__((address(0x2050))); + + +extern volatile __bit ODCB1 __attribute__((address(0x2051))); + + +extern volatile __bit ODCB2 __attribute__((address(0x2052))); + + +extern volatile __bit ODCB3 __attribute__((address(0x2053))); + + +extern volatile __bit ODCB4 __attribute__((address(0x2054))); + + +extern volatile __bit ODCB5 __attribute__((address(0x2055))); + + +extern volatile __bit ODCB6 __attribute__((address(0x2056))); + + +extern volatile __bit ODCB7 __attribute__((address(0x2057))); + + +extern volatile __bit ODCC0 __attribute__((address(0x2090))); + + +extern volatile __bit ODCC1 __attribute__((address(0x2091))); + + +extern volatile __bit ODCC2 __attribute__((address(0x2092))); + + +extern volatile __bit ODCC3 __attribute__((address(0x2093))); + + +extern volatile __bit ODCC4 __attribute__((address(0x2094))); + + +extern volatile __bit ODCC5 __attribute__((address(0x2095))); + + +extern volatile __bit ODCC6 __attribute__((address(0x2096))); + + +extern volatile __bit ODCC7 __attribute__((address(0x2097))); + + +extern volatile __bit OE __attribute__((address(0x6B6))); + + +extern volatile __bit OE0 __attribute__((address(0x3FC))); + + +extern volatile __bit OE1 __attribute__((address(0x3FD))); + + +extern volatile __bit OPMOD0 __attribute__((address(0x815))); + + +extern volatile __bit OPMOD1 __attribute__((address(0x816))); + + +extern volatile __bit OPMOD2 __attribute__((address(0x817))); + + +extern volatile __bit ORDY __attribute__((address(0x57C))); + + +extern volatile __bit OSFIE __attribute__((address(0x24F2))); + + +extern volatile __bit OSFIF __attribute__((address(0x2572))); + + +extern volatile __bit OSFIP __attribute__((address(0x1B12))); + + +extern volatile __bit OUT0 __attribute__((address(0x1A98))); + + +extern volatile __bit OUT1 __attribute__((address(0x1A99))); + + +extern volatile __bit OUT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit OUT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit OUT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit OUT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit OUT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit OUT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit OUT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit OUT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit OUT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit OUT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit OUT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit OUT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit OUT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit OUT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit OUT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit OUT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit OUT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit OUT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit OUT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit OUT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit OUT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit OUT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit OUT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit OUT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit OUT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit OUT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit OUT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit OUT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit OUT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit OUT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit PC1IE __attribute__((address(0x14DA))); + + +extern volatile __bit PC1IF __attribute__((address(0x14D2))); + + +extern volatile __bit PCIE __attribute__((address(0x14DA))); + + +extern volatile __bit PCIF __attribute__((address(0x14D2))); + + +extern volatile __bit PLEN0 __attribute__((address(0x1AC0))); + + +extern volatile __bit PLEN1 __attribute__((address(0x1AC1))); + + +extern volatile __bit PLEN2 __attribute__((address(0x1AC2))); + + +extern volatile __bit PLEN3 __attribute__((address(0x1AC3))); + + +extern volatile __bit PLEN4 __attribute__((address(0x1AC4))); + + +extern volatile __bit PLLEN __attribute__((address(0x598))); + + +extern volatile __bit PLLR __attribute__((address(0x590))); + + +extern volatile __bit PMSYS0 __attribute__((address(0x244))); + + +extern volatile __bit PMSYS1 __attribute__((address(0x245))); + + +extern volatile __bit POR __attribute__((address(0x2781))); + + +extern volatile __bit PORT __attribute__((address(0x11F3))); + + +extern volatile __bit PPOL __attribute__((address(0x1FA7))); + + +extern volatile __bit PPSLOCKED __attribute__((address(0x1000))); + + +extern volatile __bit PR10 __attribute__((address(0x1852))); + + +extern volatile __bit PR11 __attribute__((address(0x1853))); + + +extern volatile __bit PR12 __attribute__((address(0x1854))); + + +extern volatile __bit PR13 __attribute__((address(0x1855))); + + +extern volatile __bit PR14 __attribute__((address(0x1856))); + + +extern volatile __bit PR15 __attribute__((address(0x1857))); + + +extern volatile __bit PR16 __attribute__((address(0x1858))); + + +extern volatile __bit PR17 __attribute__((address(0x1859))); + + +extern volatile __bit PR18 __attribute__((address(0x185A))); + + +extern volatile __bit PR19 __attribute__((address(0x185B))); + + +extern volatile __bit PR20 __attribute__((address(0x185C))); + + +extern volatile __bit PR21 __attribute__((address(0x185D))); + + +extern volatile __bit PR22 __attribute__((address(0x185E))); + + +extern volatile __bit PR23 __attribute__((address(0x185F))); + + +extern volatile __bit PR3 __attribute__((address(0x184B))); + + +extern volatile __bit PR5 __attribute__((address(0x184D))); + + +extern volatile __bit PR7 __attribute__((address(0x184F))); + + +extern volatile __bit PR8 __attribute__((address(0x1850))); + + +extern volatile __bit PR9 __attribute__((address(0x1851))); + + +extern volatile __bit PRE0 __attribute__((address(0x1F88))); + + +extern volatile __bit PRE1 __attribute__((address(0x1F89))); + + +extern volatile __bit PRE10 __attribute__((address(0x1F92))); + + +extern volatile __bit PRE11 __attribute__((address(0x1F93))); + + +extern volatile __bit PRE12 __attribute__((address(0x1F94))); + + +extern volatile __bit PRE2 __attribute__((address(0x1F8A))); + + +extern volatile __bit PRE3 __attribute__((address(0x1F8B))); + + +extern volatile __bit PRE4 __attribute__((address(0x1F8C))); + + +extern volatile __bit PRE5 __attribute__((address(0x1F8D))); + + +extern volatile __bit PRE6 __attribute__((address(0x1F8E))); + + +extern volatile __bit PRE7 __attribute__((address(0x1F8F))); + + +extern volatile __bit PRE8 __attribute__((address(0x1F90))); + + +extern volatile __bit PRE9 __attribute__((address(0x1F91))); + + +extern volatile __bit PREF0 __attribute__((address(0x1FC0))); + + +extern volatile __bit PREF1 __attribute__((address(0x1FC1))); + + +extern volatile __bit PREV0 __attribute__((address(0x1F40))); + + +extern volatile __bit PREV1 __attribute__((address(0x1F41))); + + +extern volatile __bit PREV10 __attribute__((address(0x1F4A))); + + +extern volatile __bit PREV11 __attribute__((address(0x1F4B))); + + +extern volatile __bit PREV12 __attribute__((address(0x1F4C))); + + +extern volatile __bit PREV13 __attribute__((address(0x1F4D))); + + +extern volatile __bit PREV14 __attribute__((address(0x1F4E))); + + +extern volatile __bit PREV15 __attribute__((address(0x1F4F))); + + +extern volatile __bit PREV2 __attribute__((address(0x1F42))); + + +extern volatile __bit PREV3 __attribute__((address(0x1F43))); + + +extern volatile __bit PREV4 __attribute__((address(0x1F44))); + + +extern volatile __bit PREV5 __attribute__((address(0x1F45))); + + +extern volatile __bit PREV6 __attribute__((address(0x1F46))); + + +extern volatile __bit PREV7 __attribute__((address(0x1F47))); + + +extern volatile __bit PREV8 __attribute__((address(0x1F48))); + + +extern volatile __bit PREV9 __attribute__((address(0x1F49))); + + +extern volatile __bit PRLOCKED __attribute__((address(0x5A0))); + + +extern volatile __bit PSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit PSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit PSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit PSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit PSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit PSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit PSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit PSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit PSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit PSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit PSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit PSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit PSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit PSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit PSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit PSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit PSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit PSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit PSIS __attribute__((address(0x1FAF))); + + +extern volatile __bit PSS0 __attribute__((address(0x3FA))); + + +extern volatile __bit PSS1 __attribute__((address(0x3FB))); + + +extern volatile __bit PWM1EN __attribute__((address(0x24E8))); + + +extern volatile __bit PWM1ERSPPS0 __attribute__((address(0x1298))); + + +extern volatile __bit PWM1ERSPPS1 __attribute__((address(0x1299))); + + +extern volatile __bit PWM1ERSPPS2 __attribute__((address(0x129A))); + + +extern volatile __bit PWM1ERSPPS3 __attribute__((address(0x129B))); + + +extern volatile __bit PWM1ERSPPS4 __attribute__((address(0x129C))); + + +extern volatile __bit PWM1IE __attribute__((address(0x2517))); + + +extern volatile __bit PWM1IF __attribute__((address(0x2597))); + + +extern volatile __bit PWM1IP __attribute__((address(0x1B37))); + + +extern volatile __bit PWM1LD __attribute__((address(0x24E0))); + + +extern volatile __bit PWM1MD __attribute__((address(0x32C))); + + +extern volatile __bit PWM1PIE __attribute__((address(0x2516))); + + +extern volatile __bit PWM1PIF __attribute__((address(0x2596))); + + +extern volatile __bit PWM1PIP __attribute__((address(0x1B36))); + + +extern volatile __bit PWM2EN __attribute__((address(0x24E9))); + + +extern volatile __bit PWM2ERSPPS0 __attribute__((address(0x12A0))); + + +extern volatile __bit PWM2ERSPPS1 __attribute__((address(0x12A1))); + + +extern volatile __bit PWM2ERSPPS2 __attribute__((address(0x12A2))); + + +extern volatile __bit PWM2ERSPPS3 __attribute__((address(0x12A3))); + + +extern volatile __bit PWM2ERSPPS4 __attribute__((address(0x12A4))); + + +extern volatile __bit PWM2ERSPPS5 __attribute__((address(0x12A5))); + + +extern volatile __bit PWM2IE __attribute__((address(0x251F))); + + +extern volatile __bit PWM2IF __attribute__((address(0x259F))); + + +extern volatile __bit PWM2IP __attribute__((address(0x1B3F))); + + +extern volatile __bit PWM2LD __attribute__((address(0x24E1))); + + +extern volatile __bit PWM2MD __attribute__((address(0x32D))); + + +extern volatile __bit PWM2PIE __attribute__((address(0x251E))); + + +extern volatile __bit PWM2PIF __attribute__((address(0x259E))); + + +extern volatile __bit PWM2PIP __attribute__((address(0x1B3E))); + + +extern volatile __bit PWM3EN __attribute__((address(0x24EA))); + + +extern volatile __bit PWM3ERSPPS0 __attribute__((address(0x12A8))); + + +extern volatile __bit PWM3ERSPPS1 __attribute__((address(0x12A9))); + + +extern volatile __bit PWM3ERSPPS2 __attribute__((address(0x12AA))); + + +extern volatile __bit PWM3ERSPPS3 __attribute__((address(0x12AB))); + + +extern volatile __bit PWM3ERSPPS4 __attribute__((address(0x12AC))); + + +extern volatile __bit PWM3IE __attribute__((address(0x252F))); + + +extern volatile __bit PWM3IF __attribute__((address(0x25AF))); + + +extern volatile __bit PWM3IP __attribute__((address(0x1B4F))); + + +extern volatile __bit PWM3LD __attribute__((address(0x24E2))); + + +extern volatile __bit PWM3MD __attribute__((address(0x32E))); + + +extern volatile __bit PWM3PIE __attribute__((address(0x252E))); + + +extern volatile __bit PWM3PIF __attribute__((address(0x25AE))); + + +extern volatile __bit PWM3PIP __attribute__((address(0x1B4E))); + + +extern volatile __bit PWM4EN __attribute__((address(0x24EB))); + + +extern volatile __bit PWM4IE __attribute__((address(0x253F))); + + +extern volatile __bit PWM4IF __attribute__((address(0x25BF))); + + +extern volatile __bit PWM4IP __attribute__((address(0x1B5F))); + + +extern volatile __bit PWM4LD __attribute__((address(0x24E3))); + + +extern volatile __bit PWM4MD __attribute__((address(0x32F))); + + +extern volatile __bit PWM4PIE __attribute__((address(0x253E))); + + +extern volatile __bit PWM4PIF __attribute__((address(0x25BE))); + + +extern volatile __bit PWM4PIP __attribute__((address(0x1B5E))); + + +extern volatile __bit PWMIN0PPS0 __attribute__((address(0x12B8))); + + +extern volatile __bit PWMIN0PPS1 __attribute__((address(0x12B9))); + + +extern volatile __bit PWMIN0PPS2 __attribute__((address(0x12BA))); + + +extern volatile __bit PWMIN0PPS3 __attribute__((address(0x12BB))); + + +extern volatile __bit PWMIN0PPS4 __attribute__((address(0x12BC))); + + +extern volatile __bit PWMIN0PPS5 __attribute__((address(0x12BD))); + + +extern volatile __bit PWMIN1PPS0 __attribute__((address(0x12C0))); + + +extern volatile __bit PWMIN1PPS1 __attribute__((address(0x12C1))); + + +extern volatile __bit PWMIN1PPS2 __attribute__((address(0x12C2))); + + +extern volatile __bit PWMIN1PPS3 __attribute__((address(0x12C3))); + + +extern volatile __bit PWMIN1PPS4 __attribute__((address(0x12C4))); + + +extern volatile __bit PWMIN1PPS5 __attribute__((address(0x12C5))); + + +extern volatile __bit PXEDIS __attribute__((address(0x806))); + + +extern volatile __bit RA0 __attribute__((address(0x2670))); + + +extern volatile __bit RA0PPS0 __attribute__((address(0x1008))); + + +extern volatile __bit RA0PPS1 __attribute__((address(0x1009))); + + +extern volatile __bit RA0PPS2 __attribute__((address(0x100A))); + + +extern volatile __bit RA0PPS3 __attribute__((address(0x100B))); + + +extern volatile __bit RA0PPS4 __attribute__((address(0x100C))); + + +extern volatile __bit RA0PPS5 __attribute__((address(0x100D))); + + +extern volatile __bit RA1 __attribute__((address(0x2671))); + + +extern volatile __bit RA1PPS0 __attribute__((address(0x1010))); + + +extern volatile __bit RA1PPS1 __attribute__((address(0x1011))); + + +extern volatile __bit RA1PPS2 __attribute__((address(0x1012))); + + +extern volatile __bit RA1PPS3 __attribute__((address(0x1013))); + + +extern volatile __bit RA1PPS4 __attribute__((address(0x1014))); + + +extern volatile __bit RA1PPS5 __attribute__((address(0x1015))); + + +extern volatile __bit RA2 __attribute__((address(0x2672))); + + +extern volatile __bit RA2PPS0 __attribute__((address(0x1018))); + + +extern volatile __bit RA2PPS1 __attribute__((address(0x1019))); + + +extern volatile __bit RA2PPS2 __attribute__((address(0x101A))); + + +extern volatile __bit RA2PPS3 __attribute__((address(0x101B))); + + +extern volatile __bit RA2PPS4 __attribute__((address(0x101C))); + + +extern volatile __bit RA2PPS5 __attribute__((address(0x101D))); + + +extern volatile __bit RA3 __attribute__((address(0x2673))); + + +extern volatile __bit RA3PPS0 __attribute__((address(0x1020))); + + +extern volatile __bit RA3PPS1 __attribute__((address(0x1021))); + + +extern volatile __bit RA3PPS2 __attribute__((address(0x1022))); + + +extern volatile __bit RA3PPS3 __attribute__((address(0x1023))); + + +extern volatile __bit RA3PPS4 __attribute__((address(0x1024))); + + +extern volatile __bit RA3PPS5 __attribute__((address(0x1025))); + + +extern volatile __bit RA4 __attribute__((address(0x2674))); + + +extern volatile __bit RA4PPS0 __attribute__((address(0x1028))); + + +extern volatile __bit RA4PPS1 __attribute__((address(0x1029))); + + +extern volatile __bit RA4PPS2 __attribute__((address(0x102A))); + + +extern volatile __bit RA4PPS3 __attribute__((address(0x102B))); + + +extern volatile __bit RA4PPS4 __attribute__((address(0x102C))); + + +extern volatile __bit RA4PPS5 __attribute__((address(0x102D))); + + +extern volatile __bit RA5 __attribute__((address(0x2675))); + + +extern volatile __bit RA5PPS0 __attribute__((address(0x1030))); + + +extern volatile __bit RA5PPS1 __attribute__((address(0x1031))); + + +extern volatile __bit RA5PPS2 __attribute__((address(0x1032))); + + +extern volatile __bit RA5PPS3 __attribute__((address(0x1033))); + + +extern volatile __bit RA5PPS4 __attribute__((address(0x1034))); + + +extern volatile __bit RA5PPS5 __attribute__((address(0x1035))); + + +extern volatile __bit RA6 __attribute__((address(0x2676))); + + +extern volatile __bit RA6PPS0 __attribute__((address(0x1038))); + + +extern volatile __bit RA6PPS1 __attribute__((address(0x1039))); + + +extern volatile __bit RA6PPS2 __attribute__((address(0x103A))); + + +extern volatile __bit RA6PPS3 __attribute__((address(0x103B))); + + +extern volatile __bit RA6PPS4 __attribute__((address(0x103C))); + + +extern volatile __bit RA6PPS5 __attribute__((address(0x103D))); + + +extern volatile __bit RA7 __attribute__((address(0x2677))); + + +extern volatile __bit RA7PPS0 __attribute__((address(0x1040))); + + +extern volatile __bit RA7PPS1 __attribute__((address(0x1041))); + + +extern volatile __bit RA7PPS2 __attribute__((address(0x1042))); + + +extern volatile __bit RA7PPS3 __attribute__((address(0x1043))); + + +extern volatile __bit RA7PPS4 __attribute__((address(0x1044))); + + +extern volatile __bit RA7PPS5 __attribute__((address(0x1045))); + + +extern volatile __bit RB0 __attribute__((address(0x2678))); + + +extern volatile __bit RB0PPS0 __attribute__((address(0x1048))); + + +extern volatile __bit RB0PPS1 __attribute__((address(0x1049))); + + +extern volatile __bit RB0PPS2 __attribute__((address(0x104A))); + + +extern volatile __bit RB0PPS3 __attribute__((address(0x104B))); + + +extern volatile __bit RB0PPS4 __attribute__((address(0x104C))); + + +extern volatile __bit RB0PPS5 __attribute__((address(0x104D))); + + +extern volatile __bit RB1 __attribute__((address(0x2679))); + + +extern volatile __bit RB1PPS0 __attribute__((address(0x1050))); + + +extern volatile __bit RB1PPS1 __attribute__((address(0x1051))); + + +extern volatile __bit RB1PPS2 __attribute__((address(0x1052))); + + +extern volatile __bit RB1PPS3 __attribute__((address(0x1053))); + + +extern volatile __bit RB1PPS4 __attribute__((address(0x1054))); + + +extern volatile __bit RB1PPS5 __attribute__((address(0x1055))); + + +extern volatile __bit RB2 __attribute__((address(0x267A))); + + +extern volatile __bit RB2PPS0 __attribute__((address(0x1058))); + + +extern volatile __bit RB2PPS1 __attribute__((address(0x1059))); + + +extern volatile __bit RB2PPS2 __attribute__((address(0x105A))); + + +extern volatile __bit RB2PPS3 __attribute__((address(0x105B))); + + +extern volatile __bit RB2PPS4 __attribute__((address(0x105C))); + + +extern volatile __bit RB2PPS5 __attribute__((address(0x105D))); + + +extern volatile __bit RB3 __attribute__((address(0x267B))); + + +extern volatile __bit RB3PPS0 __attribute__((address(0x1060))); + + +extern volatile __bit RB3PPS1 __attribute__((address(0x1061))); + + +extern volatile __bit RB3PPS2 __attribute__((address(0x1062))); + + +extern volatile __bit RB3PPS3 __attribute__((address(0x1063))); + + +extern volatile __bit RB3PPS4 __attribute__((address(0x1064))); + + +extern volatile __bit RB3PPS5 __attribute__((address(0x1065))); + + +extern volatile __bit RB4 __attribute__((address(0x267C))); + + +extern volatile __bit RB4PPS0 __attribute__((address(0x1068))); + + +extern volatile __bit RB4PPS1 __attribute__((address(0x1069))); + + +extern volatile __bit RB4PPS2 __attribute__((address(0x106A))); + + +extern volatile __bit RB4PPS3 __attribute__((address(0x106B))); + + +extern volatile __bit RB4PPS4 __attribute__((address(0x106C))); + + +extern volatile __bit RB4PPS5 __attribute__((address(0x106D))); + + +extern volatile __bit RB5 __attribute__((address(0x267D))); + + +extern volatile __bit RB5PPS0 __attribute__((address(0x1070))); + + +extern volatile __bit RB5PPS1 __attribute__((address(0x1071))); + + +extern volatile __bit RB5PPS2 __attribute__((address(0x1072))); + + +extern volatile __bit RB5PPS3 __attribute__((address(0x1073))); + + +extern volatile __bit RB5PPS4 __attribute__((address(0x1074))); + + +extern volatile __bit RB5PPS5 __attribute__((address(0x1075))); + + +extern volatile __bit RB6 __attribute__((address(0x267E))); + + +extern volatile __bit RB6PPS0 __attribute__((address(0x1078))); + + +extern volatile __bit RB6PPS1 __attribute__((address(0x1079))); + + +extern volatile __bit RB6PPS2 __attribute__((address(0x107A))); + + +extern volatile __bit RB6PPS3 __attribute__((address(0x107B))); + + +extern volatile __bit RB6PPS4 __attribute__((address(0x107C))); + + +extern volatile __bit RB6PPS5 __attribute__((address(0x107D))); + + +extern volatile __bit RB7 __attribute__((address(0x267F))); + + +extern volatile __bit RB7PPS0 __attribute__((address(0x1080))); + + +extern volatile __bit RB7PPS1 __attribute__((address(0x1081))); + + +extern volatile __bit RB7PPS2 __attribute__((address(0x1082))); + + +extern volatile __bit RB7PPS3 __attribute__((address(0x1083))); + + +extern volatile __bit RB7PPS4 __attribute__((address(0x1084))); + + +extern volatile __bit RB7PPS5 __attribute__((address(0x1085))); + + +extern volatile __bit RC0 __attribute__((address(0x2680))); + + +extern volatile __bit RC0PPS0 __attribute__((address(0x1088))); + + +extern volatile __bit RC0PPS1 __attribute__((address(0x1089))); + + +extern volatile __bit RC0PPS2 __attribute__((address(0x108A))); + + +extern volatile __bit RC0PPS3 __attribute__((address(0x108B))); + + +extern volatile __bit RC0PPS4 __attribute__((address(0x108C))); + + +extern volatile __bit RC0PPS5 __attribute__((address(0x108D))); + + +extern volatile __bit RC1 __attribute__((address(0x2681))); + + +extern volatile __bit RC1PPS0 __attribute__((address(0x1090))); + + +extern volatile __bit RC1PPS1 __attribute__((address(0x1091))); + + +extern volatile __bit RC1PPS2 __attribute__((address(0x1092))); + + +extern volatile __bit RC1PPS3 __attribute__((address(0x1093))); + + +extern volatile __bit RC1PPS4 __attribute__((address(0x1094))); + + +extern volatile __bit RC1PPS5 __attribute__((address(0x1095))); + + +extern volatile __bit RC2 __attribute__((address(0x2682))); + + +extern volatile __bit RC2PPS0 __attribute__((address(0x1098))); + + +extern volatile __bit RC2PPS1 __attribute__((address(0x1099))); + + +extern volatile __bit RC2PPS2 __attribute__((address(0x109A))); + + +extern volatile __bit RC2PPS3 __attribute__((address(0x109B))); + + +extern volatile __bit RC2PPS4 __attribute__((address(0x109C))); + + +extern volatile __bit RC2PPS5 __attribute__((address(0x109D))); + + +extern volatile __bit RC3 __attribute__((address(0x2683))); + + +extern volatile __bit RC3PPS0 __attribute__((address(0x10A0))); + + +extern volatile __bit RC3PPS1 __attribute__((address(0x10A1))); + + +extern volatile __bit RC3PPS2 __attribute__((address(0x10A2))); + + +extern volatile __bit RC3PPS3 __attribute__((address(0x10A3))); + + +extern volatile __bit RC3PPS4 __attribute__((address(0x10A4))); + + +extern volatile __bit RC3PPS5 __attribute__((address(0x10A5))); + + +extern volatile __bit RC4 __attribute__((address(0x2684))); + + +extern volatile __bit RC4PPS0 __attribute__((address(0x10A8))); + + +extern volatile __bit RC4PPS1 __attribute__((address(0x10A9))); + + +extern volatile __bit RC4PPS2 __attribute__((address(0x10AA))); + + +extern volatile __bit RC4PPS3 __attribute__((address(0x10AB))); + + +extern volatile __bit RC4PPS4 __attribute__((address(0x10AC))); + + +extern volatile __bit RC4PPS5 __attribute__((address(0x10AD))); + + +extern volatile __bit RC5 __attribute__((address(0x2685))); + + +extern volatile __bit RC5PPS0 __attribute__((address(0x10B0))); + + +extern volatile __bit RC5PPS1 __attribute__((address(0x10B1))); + + +extern volatile __bit RC5PPS2 __attribute__((address(0x10B2))); + + +extern volatile __bit RC5PPS3 __attribute__((address(0x10B3))); + + +extern volatile __bit RC5PPS4 __attribute__((address(0x10B4))); + + +extern volatile __bit RC5PPS5 __attribute__((address(0x10B5))); + + +extern volatile __bit RC6 __attribute__((address(0x2686))); + + +extern volatile __bit RC6PPS0 __attribute__((address(0x10B8))); + + +extern volatile __bit RC6PPS1 __attribute__((address(0x10B9))); + + +extern volatile __bit RC6PPS2 __attribute__((address(0x10BA))); + + +extern volatile __bit RC6PPS3 __attribute__((address(0x10BB))); + + +extern volatile __bit RC6PPS4 __attribute__((address(0x10BC))); + + +extern volatile __bit RC6PPS5 __attribute__((address(0x10BD))); + + +extern volatile __bit RC7 __attribute__((address(0x2687))); + + +extern volatile __bit RC7PPS0 __attribute__((address(0x10C0))); + + +extern volatile __bit RC7PPS1 __attribute__((address(0x10C1))); + + +extern volatile __bit RC7PPS2 __attribute__((address(0x10C2))); + + +extern volatile __bit RC7PPS3 __attribute__((address(0x10C3))); + + +extern volatile __bit RC7PPS4 __attribute__((address(0x10C4))); + + +extern volatile __bit RC7PPS5 __attribute__((address(0x10C5))); + + +extern volatile __bit RD161 __attribute__((address(0x18F1))); + + +extern volatile __bit RD163 __attribute__((address(0x1951))); + + +extern volatile __bit RD165 __attribute__((address(0x19B1))); + + +extern volatile __bit RE3 __attribute__((address(0x2693))); + + +extern volatile __bit READ __attribute__((address(0x14C4))); + + +extern volatile __bit REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit REQOP0 __attribute__((address(0x818))); + + +extern volatile __bit REQOP1 __attribute__((address(0x819))); + + +extern volatile __bit REQOP2 __attribute__((address(0x81A))); + + +extern volatile __bit RERRCNT0 __attribute__((address(0x9A0))); + + +extern volatile __bit RERRCNT1 __attribute__((address(0x9A1))); + + +extern volatile __bit RERRCNT2 __attribute__((address(0x9A2))); + + +extern volatile __bit RERRCNT3 __attribute__((address(0x9A3))); + + +extern volatile __bit RERRCNT4 __attribute__((address(0x9A4))); + + +extern volatile __bit RERRCNT5 __attribute__((address(0x9A5))); + + +extern volatile __bit RERRCNT6 __attribute__((address(0x9A6))); + + +extern volatile __bit RERRCNT7 __attribute__((address(0x9A7))); + + +extern volatile __bit RES0 __attribute__((address(0x1F50))); + + +extern volatile __bit RES1 __attribute__((address(0x1F51))); + + +extern volatile __bit RES10 __attribute__((address(0x1F5A))); + + +extern volatile __bit RES11 __attribute__((address(0x1F5B))); + + +extern volatile __bit RES12 __attribute__((address(0x1F5C))); + + +extern volatile __bit RES13 __attribute__((address(0x1F5D))); + + +extern volatile __bit RES14 __attribute__((address(0x1F5E))); + + +extern volatile __bit RES15 __attribute__((address(0x1F5F))); + + +extern volatile __bit RES2 __attribute__((address(0x1F52))); + + +extern volatile __bit RES3 __attribute__((address(0x1F53))); + + +extern volatile __bit RES4 __attribute__((address(0x1F54))); + + +extern volatile __bit RES5 __attribute__((address(0x1F55))); + + +extern volatile __bit RES6 __attribute__((address(0x1F56))); + + +extern volatile __bit RES7 __attribute__((address(0x1F57))); + + +extern volatile __bit RES8 __attribute__((address(0x1F58))); + + +extern volatile __bit RES9 __attribute__((address(0x1F59))); + + +extern volatile __bit RFIF1 __attribute__((address(0x901))); + + +extern volatile __bit RFIF10 __attribute__((address(0x90A))); + + +extern volatile __bit RFIF11 __attribute__((address(0x90B))); + + +extern volatile __bit RFIF12 __attribute__((address(0x90C))); + + +extern volatile __bit RFIF13 __attribute__((address(0x90D))); + + +extern volatile __bit RFIF14 __attribute__((address(0x90E))); + + +extern volatile __bit RFIF15 __attribute__((address(0x90F))); + + +extern volatile __bit RFIF16 __attribute__((address(0x910))); + + +extern volatile __bit RFIF17 __attribute__((address(0x911))); + + +extern volatile __bit RFIF18 __attribute__((address(0x912))); + + +extern volatile __bit RFIF19 __attribute__((address(0x913))); + + +extern volatile __bit RFIF2 __attribute__((address(0x902))); + + +extern volatile __bit RFIF20 __attribute__((address(0x914))); + + +extern volatile __bit RFIF21 __attribute__((address(0x915))); + + +extern volatile __bit RFIF22 __attribute__((address(0x916))); + + +extern volatile __bit RFIF23 __attribute__((address(0x917))); + + +extern volatile __bit RFIF24 __attribute__((address(0x918))); + + +extern volatile __bit RFIF25 __attribute__((address(0x919))); + + +extern volatile __bit RFIF26 __attribute__((address(0x91A))); + + +extern volatile __bit RFIF27 __attribute__((address(0x91B))); + + +extern volatile __bit RFIF28 __attribute__((address(0x91C))); + + +extern volatile __bit RFIF29 __attribute__((address(0x91D))); + + +extern volatile __bit RFIF3 __attribute__((address(0x903))); + + +extern volatile __bit RFIF30 __attribute__((address(0x91E))); + + +extern volatile __bit RFIF31 __attribute__((address(0x91F))); + + +extern volatile __bit RFIF4 __attribute__((address(0x904))); + + +extern volatile __bit RFIF5 __attribute__((address(0x905))); + + +extern volatile __bit RFIF6 __attribute__((address(0x906))); + + +extern volatile __bit RFIF7 __attribute__((address(0x907))); + + +extern volatile __bit RFIF8 __attribute__((address(0x908))); + + +extern volatile __bit RFIF9 __attribute__((address(0x909))); + + +extern volatile __bit RFOVIF1 __attribute__((address(0x941))); + + +extern volatile __bit RFOVIF10 __attribute__((address(0x94A))); + + +extern volatile __bit RFOVIF11 __attribute__((address(0x94B))); + + +extern volatile __bit RFOVIF12 __attribute__((address(0x94C))); + + +extern volatile __bit RFOVIF13 __attribute__((address(0x94D))); + + +extern volatile __bit RFOVIF14 __attribute__((address(0x94E))); + + +extern volatile __bit RFOVIF15 __attribute__((address(0x94F))); + + +extern volatile __bit RFOVIF16 __attribute__((address(0x950))); + + +extern volatile __bit RFOVIF17 __attribute__((address(0x951))); + + +extern volatile __bit RFOVIF18 __attribute__((address(0x952))); + + +extern volatile __bit RFOVIF19 __attribute__((address(0x953))); + + +extern volatile __bit RFOVIF2 __attribute__((address(0x942))); + + +extern volatile __bit RFOVIF20 __attribute__((address(0x954))); + + +extern volatile __bit RFOVIF21 __attribute__((address(0x955))); + + +extern volatile __bit RFOVIF22 __attribute__((address(0x956))); + + +extern volatile __bit RFOVIF23 __attribute__((address(0x957))); + + +extern volatile __bit RFOVIF24 __attribute__((address(0x958))); + + +extern volatile __bit RFOVIF25 __attribute__((address(0x959))); + + +extern volatile __bit RFOVIF26 __attribute__((address(0x95A))); + + +extern volatile __bit RFOVIF27 __attribute__((address(0x95B))); + + +extern volatile __bit RFOVIF28 __attribute__((address(0x95C))); + + +extern volatile __bit RFOVIF29 __attribute__((address(0x95D))); + + +extern volatile __bit RFOVIF3 __attribute__((address(0x943))); + + +extern volatile __bit RFOVIF30 __attribute__((address(0x95E))); + + +extern volatile __bit RFOVIF31 __attribute__((address(0x95F))); + + +extern volatile __bit RFOVIF4 __attribute__((address(0x944))); + + +extern volatile __bit RFOVIF5 __attribute__((address(0x945))); + + +extern volatile __bit RFOVIF6 __attribute__((address(0x946))); + + +extern volatile __bit RFOVIF7 __attribute__((address(0x947))); + + +extern volatile __bit RFOVIF8 __attribute__((address(0x948))); + + +extern volatile __bit RFOVIF9 __attribute__((address(0x949))); + + +extern volatile __bit RI __attribute__((address(0x2782))); + + +extern volatile __bit RMCLR __attribute__((address(0x2783))); + + +extern volatile __bit ROI __attribute__((address(0x2795))); + + +extern volatile __bit RPT0 __attribute__((address(0x1F38))); + + +extern volatile __bit RPT1 __attribute__((address(0x1F39))); + + +extern volatile __bit RPT2 __attribute__((address(0x1F3A))); + + +extern volatile __bit RPT3 __attribute__((address(0x1F3B))); + + +extern volatile __bit RPT4 __attribute__((address(0x1F3C))); + + +extern volatile __bit RPT5 __attribute__((address(0x1F3D))); + + +extern volatile __bit RPT6 __attribute__((address(0x1F3E))); + + +extern volatile __bit RPT7 __attribute__((address(0x1F3F))); + + +extern volatile __bit RSC1IE __attribute__((address(0x14D9))); + + +extern volatile __bit RSC1IF __attribute__((address(0x14D1))); + + +extern volatile __bit RSCIE __attribute__((address(0x14D9))); + + +extern volatile __bit RSCIF __attribute__((address(0x14D1))); + + +extern volatile __bit RSEN __attribute__((address(0x14A6))); + + +extern volatile __bit RST __attribute__((address(0x1875))); + + +extern volatile __bit RTXAT __attribute__((address(0x810))); + + +extern volatile __bit RWDT __attribute__((address(0x2784))); + + +extern volatile __bit RXBP __attribute__((address(0x9B3))); + + +extern volatile __bit RXIE __attribute__((address(0x8F1))); + + +extern volatile __bit RXIF __attribute__((address(0x8E1))); + + +extern volatile __bit RXO __attribute__((address(0x14AA))); + + +extern volatile __bit RXWARN __attribute__((address(0x9B1))); + + +extern volatile __bit SBOREN __attribute__((address(0x24F))); + + +extern volatile __bit SC1IE __attribute__((address(0x14D8))); + + +extern volatile __bit SC1IF __attribute__((address(0x14D0))); + + +extern volatile __bit SCANEN __attribute__((address(0x1B07))); + + +extern volatile __bit SCANHADR0 __attribute__((address(0x1AE8))); + + +extern volatile __bit SCANHADR1 __attribute__((address(0x1AE9))); + + +extern volatile __bit SCANHADR10 __attribute__((address(0x1AF2))); + + +extern volatile __bit SCANHADR11 __attribute__((address(0x1AF3))); + + +extern volatile __bit SCANHADR12 __attribute__((address(0x1AF4))); + + +extern volatile __bit SCANHADR13 __attribute__((address(0x1AF5))); + + +extern volatile __bit SCANHADR14 __attribute__((address(0x1AF6))); + + +extern volatile __bit SCANHADR15 __attribute__((address(0x1AF7))); + + +extern volatile __bit SCANHADR16 __attribute__((address(0x1AF8))); + + +extern volatile __bit SCANHADR17 __attribute__((address(0x1AF9))); + + +extern volatile __bit SCANHADR18 __attribute__((address(0x1AFA))); + + +extern volatile __bit SCANHADR19 __attribute__((address(0x1AFB))); + + +extern volatile __bit SCANHADR2 __attribute__((address(0x1AEA))); + + +extern volatile __bit SCANHADR20 __attribute__((address(0x1AFC))); + + +extern volatile __bit SCANHADR21 __attribute__((address(0x1AFD))); + + +extern volatile __bit SCANHADR3 __attribute__((address(0x1AEB))); + + +extern volatile __bit SCANHADR4 __attribute__((address(0x1AEC))); + + +extern volatile __bit SCANHADR5 __attribute__((address(0x1AED))); + + +extern volatile __bit SCANHADR6 __attribute__((address(0x1AEE))); + + +extern volatile __bit SCANHADR7 __attribute__((address(0x1AEF))); + + +extern volatile __bit SCANHADR8 __attribute__((address(0x1AF0))); + + +extern volatile __bit SCANHADR9 __attribute__((address(0x1AF1))); + + +extern volatile __bit SCANIE __attribute__((address(0x2537))); + + +extern volatile __bit SCANIF __attribute__((address(0x25B7))); + + +extern volatile __bit SCANIP __attribute__((address(0x1B57))); + + +extern volatile __bit SCANLADR0 __attribute__((address(0x1AD0))); + + +extern volatile __bit SCANLADR1 __attribute__((address(0x1AD1))); + + +extern volatile __bit SCANLADR10 __attribute__((address(0x1ADA))); + + +extern volatile __bit SCANLADR11 __attribute__((address(0x1ADB))); + + +extern volatile __bit SCANLADR12 __attribute__((address(0x1ADC))); + + +extern volatile __bit SCANLADR13 __attribute__((address(0x1ADD))); + + +extern volatile __bit SCANLADR14 __attribute__((address(0x1ADE))); + + +extern volatile __bit SCANLADR15 __attribute__((address(0x1ADF))); + + +extern volatile __bit SCANLADR16 __attribute__((address(0x1AE0))); + + +extern volatile __bit SCANLADR17 __attribute__((address(0x1AE1))); + + +extern volatile __bit SCANLADR18 __attribute__((address(0x1AE2))); + + +extern volatile __bit SCANLADR19 __attribute__((address(0x1AE3))); + + +extern volatile __bit SCANLADR2 __attribute__((address(0x1AD2))); + + +extern volatile __bit SCANLADR20 __attribute__((address(0x1AE4))); + + +extern volatile __bit SCANLADR21 __attribute__((address(0x1AE5))); + + +extern volatile __bit SCANLADR3 __attribute__((address(0x1AD3))); + + +extern volatile __bit SCANLADR4 __attribute__((address(0x1AD4))); + + +extern volatile __bit SCANLADR5 __attribute__((address(0x1AD5))); + + +extern volatile __bit SCANLADR6 __attribute__((address(0x1AD6))); + + +extern volatile __bit SCANLADR7 __attribute__((address(0x1AD7))); + + +extern volatile __bit SCANLADR8 __attribute__((address(0x1AD8))); + + +extern volatile __bit SCANLADR9 __attribute__((address(0x1AD9))); + + +extern volatile __bit SCANMD __attribute__((address(0x303))); + + +extern volatile __bit SCANPR0 __attribute__((address(0x5A8))); + + +extern volatile __bit SCANPR1 __attribute__((address(0x5A9))); + + +extern volatile __bit SCANPR2 __attribute__((address(0x5AA))); + + +extern volatile __bit SCIE __attribute__((address(0x14D8))); + + +extern volatile __bit SCIF __attribute__((address(0x14D0))); + + +extern volatile __bit SCNT0 __attribute__((address(0x790))); + + +extern volatile __bit SCNT1 __attribute__((address(0x791))); + + +extern volatile __bit SCNT10 __attribute__((address(0x79A))); + + +extern volatile __bit SCNT11 __attribute__((address(0x79B))); + + +extern volatile __bit SCNT2 __attribute__((address(0x792))); + + +extern volatile __bit SCNT3 __attribute__((address(0x793))); + + +extern volatile __bit SCNT4 __attribute__((address(0x794))); + + +extern volatile __bit SCNT5 __attribute__((address(0x795))); + + +extern volatile __bit SCNT6 __attribute__((address(0x796))); + + +extern volatile __bit SCNT7 __attribute__((address(0x797))); + + +extern volatile __bit SCNT8 __attribute__((address(0x798))); + + +extern volatile __bit SCNT9 __attribute__((address(0x799))); + + +extern volatile __bit SDAHT0 __attribute__((address(0x14B2))); + + +extern volatile __bit SDAHT1 __attribute__((address(0x14B3))); + + +extern volatile __bit SEL0 __attribute__((address(0x258))); + + +extern volatile __bit SEL1 __attribute__((address(0x259))); + + +extern volatile __bit SEL2 __attribute__((address(0x25A))); + + +extern volatile __bit SEL3 __attribute__((address(0x25B))); + + +extern volatile __bit SERR2LOM __attribute__((address(0x812))); + + +extern volatile __bit SERRIE __attribute__((address(0x8FC))); + + +extern volatile __bit SERRIF __attribute__((address(0x8EC))); + + +extern volatile __bit SETUP0 __attribute__((address(0x1ABA))); + + +extern volatile __bit SETUP1 __attribute__((address(0x1ABB))); + + +extern volatile __bit SGO __attribute__((address(0x1B05))); + + +extern volatile __bit SHADLO __attribute__((address(0x1BB0))); + + +extern volatile __bit SHIFT0 __attribute__((address(0x1A98))); + + +extern volatile __bit SHIFT1 __attribute__((address(0x1A99))); + + +extern volatile __bit SHIFT10 __attribute__((address(0x1AA2))); + + +extern volatile __bit SHIFT11 __attribute__((address(0x1AA3))); + + +extern volatile __bit SHIFT12 __attribute__((address(0x1AA4))); + + +extern volatile __bit SHIFT13 __attribute__((address(0x1AA5))); + + +extern volatile __bit SHIFT14 __attribute__((address(0x1AA6))); + + +extern volatile __bit SHIFT15 __attribute__((address(0x1AA7))); + + +extern volatile __bit SHIFT16 __attribute__((address(0x1AA8))); + + +extern volatile __bit SHIFT17 __attribute__((address(0x1AA9))); + + +extern volatile __bit SHIFT18 __attribute__((address(0x1AAA))); + + +extern volatile __bit SHIFT19 __attribute__((address(0x1AAB))); + + +extern volatile __bit SHIFT2 __attribute__((address(0x1A9A))); + + +extern volatile __bit SHIFT20 __attribute__((address(0x1AAC))); + + +extern volatile __bit SHIFT21 __attribute__((address(0x1AAD))); + + +extern volatile __bit SHIFT22 __attribute__((address(0x1AAE))); + + +extern volatile __bit SHIFT23 __attribute__((address(0x1AAF))); + + +extern volatile __bit SHIFT24 __attribute__((address(0x1AB0))); + + +extern volatile __bit SHIFT25 __attribute__((address(0x1AB1))); + + +extern volatile __bit SHIFT26 __attribute__((address(0x1AB2))); + + +extern volatile __bit SHIFT27 __attribute__((address(0x1AB3))); + + +extern volatile __bit SHIFT28 __attribute__((address(0x1AB4))); + + +extern volatile __bit SHIFT29 __attribute__((address(0x1AB5))); + + +extern volatile __bit SHIFT3 __attribute__((address(0x1A9B))); + + +extern volatile __bit SHIFT30 __attribute__((address(0x1AB6))); + + +extern volatile __bit SHIFT31 __attribute__((address(0x1AB7))); + + +extern volatile __bit SHIFT4 __attribute__((address(0x1A9C))); + + +extern volatile __bit SHIFT5 __attribute__((address(0x1A9D))); + + +extern volatile __bit SHIFT6 __attribute__((address(0x1A9E))); + + +extern volatile __bit SHIFT7 __attribute__((address(0x1A9F))); + + +extern volatile __bit SHIFT8 __attribute__((address(0x1AA0))); + + +extern volatile __bit SHIFT9 __attribute__((address(0x1AA1))); + + +extern volatile __bit SHIFTM __attribute__((address(0x1AB9))); + + +extern volatile __bit SID11EN __attribute__((address(0x878))); + + +extern volatile __bit SIDL __attribute__((address(0x80D))); + + +extern volatile __bit SIRQ0 __attribute__((address(0x7F8))); + + +extern volatile __bit SIRQ1 __attribute__((address(0x7F9))); + + +extern volatile __bit SIRQ2 __attribute__((address(0x7FA))); + + +extern volatile __bit SIRQ3 __attribute__((address(0x7FB))); + + +extern volatile __bit SIRQ4 __attribute__((address(0x7FC))); + + +extern volatile __bit SIRQ5 __attribute__((address(0x7FD))); + + +extern volatile __bit SIRQ6 __attribute__((address(0x7FE))); + + +extern volatile __bit SIRQ7 __attribute__((address(0x7FF))); + + +extern volatile __bit SIRQEN __attribute__((address(0x7E6))); + + +extern volatile __bit SJW4 __attribute__((address(0x824))); + + +extern volatile __bit SJW5 __attribute__((address(0x825))); + + +extern volatile __bit SJW6 __attribute__((address(0x826))); + + +extern volatile __bit SLRA0 __attribute__((address(0x2018))); + + +extern volatile __bit SLRA1 __attribute__((address(0x2019))); + + +extern volatile __bit SLRA2 __attribute__((address(0x201A))); + + +extern volatile __bit SLRA3 __attribute__((address(0x201B))); + + +extern volatile __bit SLRA4 __attribute__((address(0x201C))); + + +extern volatile __bit SLRA5 __attribute__((address(0x201D))); + + +extern volatile __bit SLRA6 __attribute__((address(0x201E))); + + +extern volatile __bit SLRA7 __attribute__((address(0x201F))); + + +extern volatile __bit SLRB0 __attribute__((address(0x2058))); + + +extern volatile __bit SLRB1 __attribute__((address(0x2059))); + + +extern volatile __bit SLRB2 __attribute__((address(0x205A))); + + +extern volatile __bit SLRB3 __attribute__((address(0x205B))); + + +extern volatile __bit SLRB4 __attribute__((address(0x205C))); + + +extern volatile __bit SLRB5 __attribute__((address(0x205D))); + + +extern volatile __bit SLRB6 __attribute__((address(0x205E))); + + +extern volatile __bit SLRB7 __attribute__((address(0x205F))); + + +extern volatile __bit SLRC0 __attribute__((address(0x2098))); + + +extern volatile __bit SLRC1 __attribute__((address(0x2099))); + + +extern volatile __bit SLRC2 __attribute__((address(0x209A))); + + +extern volatile __bit SLRC3 __attribute__((address(0x209B))); + + +extern volatile __bit SLRC4 __attribute__((address(0x209C))); + + +extern volatile __bit SLRC5 __attribute__((address(0x209D))); + + +extern volatile __bit SLRC6 __attribute__((address(0x209E))); + + +extern volatile __bit SLRC7 __attribute__((address(0x209F))); + + +extern volatile __bit SMA __attribute__((address(0x14C6))); + + +extern volatile __bit SMT1AS __attribute__((address(0x1870))); + + +extern volatile __bit SMT1CPOL __attribute__((address(0x1862))); + + +extern volatile __bit SMT1CPR0 __attribute__((address(0x1818))); + + +extern volatile __bit SMT1CPR1 __attribute__((address(0x1819))); + + +extern volatile __bit SMT1CPR10 __attribute__((address(0x1822))); + + +extern volatile __bit SMT1CPR11 __attribute__((address(0x1823))); + + +extern volatile __bit SMT1CPR12 __attribute__((address(0x1824))); + + +extern volatile __bit SMT1CPR13 __attribute__((address(0x1825))); + + +extern volatile __bit SMT1CPR14 __attribute__((address(0x1826))); + + +extern volatile __bit SMT1CPR15 __attribute__((address(0x1827))); + + +extern volatile __bit SMT1CPR16 __attribute__((address(0x1828))); + + +extern volatile __bit SMT1CPR17 __attribute__((address(0x1829))); + + +extern volatile __bit SMT1CPR18 __attribute__((address(0x182A))); + + +extern volatile __bit SMT1CPR19 __attribute__((address(0x182B))); + + +extern volatile __bit SMT1CPR2 __attribute__((address(0x181A))); + + +extern volatile __bit SMT1CPR20 __attribute__((address(0x182C))); + + +extern volatile __bit SMT1CPR21 __attribute__((address(0x182D))); + + +extern volatile __bit SMT1CPR22 __attribute__((address(0x182E))); + + +extern volatile __bit SMT1CPR23 __attribute__((address(0x182F))); + + +extern volatile __bit SMT1CPR3 __attribute__((address(0x181B))); + + +extern volatile __bit SMT1CPR4 __attribute__((address(0x181C))); + + +extern volatile __bit SMT1CPR5 __attribute__((address(0x181D))); + + +extern volatile __bit SMT1CPR6 __attribute__((address(0x181E))); + + +extern volatile __bit SMT1CPR7 __attribute__((address(0x181F))); + + +extern volatile __bit SMT1CPR8 __attribute__((address(0x1820))); + + +extern volatile __bit SMT1CPR9 __attribute__((address(0x1821))); + + +extern volatile __bit SMT1CPRUP __attribute__((address(0x1877))); + + +extern volatile __bit SMT1CPW0 __attribute__((address(0x1830))); + + +extern volatile __bit SMT1CPW1 __attribute__((address(0x1831))); + + +extern volatile __bit SMT1CPW10 __attribute__((address(0x183A))); + + +extern volatile __bit SMT1CPW11 __attribute__((address(0x183B))); + + +extern volatile __bit SMT1CPW12 __attribute__((address(0x183C))); + + +extern volatile __bit SMT1CPW13 __attribute__((address(0x183D))); + + +extern volatile __bit SMT1CPW14 __attribute__((address(0x183E))); + + +extern volatile __bit SMT1CPW15 __attribute__((address(0x183F))); + + +extern volatile __bit SMT1CPW16 __attribute__((address(0x1840))); + + +extern volatile __bit SMT1CPW17 __attribute__((address(0x1841))); + + +extern volatile __bit SMT1CPW18 __attribute__((address(0x1842))); + + +extern volatile __bit SMT1CPW19 __attribute__((address(0x1843))); + + +extern volatile __bit SMT1CPW2 __attribute__((address(0x1832))); + + +extern volatile __bit SMT1CPW20 __attribute__((address(0x1844))); + + +extern volatile __bit SMT1CPW21 __attribute__((address(0x1845))); + + +extern volatile __bit SMT1CPW22 __attribute__((address(0x1846))); + + +extern volatile __bit SMT1CPW23 __attribute__((address(0x1847))); + + +extern volatile __bit SMT1CPW3 __attribute__((address(0x1833))); + + +extern volatile __bit SMT1CPW4 __attribute__((address(0x1834))); + + +extern volatile __bit SMT1CPW5 __attribute__((address(0x1835))); + + +extern volatile __bit SMT1CPW6 __attribute__((address(0x1836))); + + +extern volatile __bit SMT1CPW7 __attribute__((address(0x1837))); + + +extern volatile __bit SMT1CPW8 __attribute__((address(0x1838))); + + +extern volatile __bit SMT1CPW9 __attribute__((address(0x1839))); + + +extern volatile __bit SMT1CPWUP __attribute__((address(0x1876))); + + +extern volatile __bit SMT1CSEL0 __attribute__((address(0x1878))); + + +extern volatile __bit SMT1CSEL1 __attribute__((address(0x1879))); + + +extern volatile __bit SMT1CSEL2 __attribute__((address(0x187A))); + + +extern volatile __bit SMT1EN __attribute__((address(0x1867))); + + +extern volatile __bit SMT1GO __attribute__((address(0x186F))); + + +extern volatile __bit SMT1IE __attribute__((address(0x24FD))); + + +extern volatile __bit SMT1IF __attribute__((address(0x257D))); + + +extern volatile __bit SMT1IP __attribute__((address(0x1B1D))); + + +extern volatile __bit SMT1MD __attribute__((address(0x30F))); + + +extern volatile __bit SMT1PR0 __attribute__((address(0x1848))); + + +extern volatile __bit SMT1PR1 __attribute__((address(0x1849))); + + +extern volatile __bit SMT1PR10 __attribute__((address(0x1852))); + + +extern volatile __bit SMT1PR11 __attribute__((address(0x1853))); + + +extern volatile __bit SMT1PR12 __attribute__((address(0x1854))); + + +extern volatile __bit SMT1PR13 __attribute__((address(0x1855))); + + +extern volatile __bit SMT1PR14 __attribute__((address(0x1856))); + + +extern volatile __bit SMT1PR15 __attribute__((address(0x1857))); + + +extern volatile __bit SMT1PR16 __attribute__((address(0x1858))); + + +extern volatile __bit SMT1PR17 __attribute__((address(0x1859))); + + +extern volatile __bit SMT1PR18 __attribute__((address(0x185A))); + + +extern volatile __bit SMT1PR19 __attribute__((address(0x185B))); + + +extern volatile __bit SMT1PR2 __attribute__((address(0x184A))); + + +extern volatile __bit SMT1PR20 __attribute__((address(0x185C))); + + +extern volatile __bit SMT1PR21 __attribute__((address(0x185D))); + + +extern volatile __bit SMT1PR22 __attribute__((address(0x185E))); + + +extern volatile __bit SMT1PR23 __attribute__((address(0x185F))); + + +extern volatile __bit SMT1PR3 __attribute__((address(0x184B))); + + +extern volatile __bit SMT1PR4 __attribute__((address(0x184C))); + + +extern volatile __bit SMT1PR5 __attribute__((address(0x184D))); + + +extern volatile __bit SMT1PR6 __attribute__((address(0x184E))); + + +extern volatile __bit SMT1PR7 __attribute__((address(0x184F))); + + +extern volatile __bit SMT1PR8 __attribute__((address(0x1850))); + + +extern volatile __bit SMT1PR9 __attribute__((address(0x1851))); + + +extern volatile __bit SMT1PRAIE __attribute__((address(0x24FE))); + + +extern volatile __bit SMT1PRAIF __attribute__((address(0x257E))); + + +extern volatile __bit SMT1PRAIP __attribute__((address(0x1B1E))); + + +extern volatile __bit SMT1PS0 __attribute__((address(0x1860))); + + +extern volatile __bit SMT1PS1 __attribute__((address(0x1861))); + + +extern volatile __bit SMT1PWAIE __attribute__((address(0x24FF))); + + +extern volatile __bit SMT1PWAIF __attribute__((address(0x257F))); + + +extern volatile __bit SMT1PWAIP __attribute__((address(0x1B1F))); + + +extern volatile __bit SMT1REPEAT __attribute__((address(0x186E))); + + +extern volatile __bit SMT1RESET __attribute__((address(0x1875))); + + +extern volatile __bit SMT1RST __attribute__((address(0x1875))); + + +extern volatile __bit SMT1SIGPPS0 __attribute__((address(0x12D0))); + + +extern volatile __bit SMT1SIGPPS1 __attribute__((address(0x12D1))); + + +extern volatile __bit SMT1SIGPPS2 __attribute__((address(0x12D2))); + + +extern volatile __bit SMT1SIGPPS3 __attribute__((address(0x12D3))); + + +extern volatile __bit SMT1SIGPPS4 __attribute__((address(0x12D4))); + + +extern volatile __bit SMT1SIGPPS5 __attribute__((address(0x12D5))); + + +extern volatile __bit SMT1SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SMT1SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SMT1SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SMT1SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SMT1SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SMT1SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SMT1STP __attribute__((address(0x1865))); + + +extern volatile __bit SMT1TMR0 __attribute__((address(0x1800))); + + +extern volatile __bit SMT1TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit SMT1TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit SMT1TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit SMT1TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit SMT1TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit SMT1TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit SMT1TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit SMT1TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit SMT1TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit SMT1TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit SMT1TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit SMT1TMR2 __attribute__((address(0x1802))); + + +extern volatile __bit SMT1TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit SMT1TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit SMT1TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit SMT1TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit SMT1TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit SMT1TMR4 __attribute__((address(0x1804))); + + +extern volatile __bit SMT1TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit SMT1TMR6 __attribute__((address(0x1806))); + + +extern volatile __bit SMT1TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit SMT1TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit SMT1TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit SMT1TS __attribute__((address(0x1872))); + + +extern volatile __bit SMT1WINPPS0 __attribute__((address(0x12C8))); + + +extern volatile __bit SMT1WINPPS1 __attribute__((address(0x12C9))); + + +extern volatile __bit SMT1WINPPS2 __attribute__((address(0x12CA))); + + +extern volatile __bit SMT1WINPPS3 __attribute__((address(0x12CB))); + + +extern volatile __bit SMT1WINPPS4 __attribute__((address(0x12CC))); + + +extern volatile __bit SMT1WINPPS5 __attribute__((address(0x12CD))); + + +extern volatile __bit SMT1WOL __attribute__((address(0x1864))); + + +extern volatile __bit SMT1WS __attribute__((address(0x1871))); + + +extern volatile __bit SMT1WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit SMT1WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit SMT1WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit SMT1WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit SMT1WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit SOI __attribute__((address(0x1FB3))); + + +extern volatile __bit SOR __attribute__((address(0x593))); + + +extern volatile __bit SOSCEN __attribute__((address(0x59B))); + + +extern volatile __bit SOSCPWR __attribute__((address(0x57E))); + + +extern volatile __bit SP0 __attribute__((address(0x27E0))); + + +extern volatile __bit SP1 __attribute__((address(0x27E1))); + + +extern volatile __bit SP2 __attribute__((address(0x27E2))); + + +extern volatile __bit SP3 __attribute__((address(0x27E3))); + + +extern volatile __bit SP4 __attribute__((address(0x27E4))); + + +extern volatile __bit SP5 __attribute__((address(0x27E5))); + + +extern volatile __bit SPI1BMODE __attribute__((address(0x420))); + + +extern volatile __bit SPI1BUSY __attribute__((address(0x437))); + + +extern volatile __bit SPI1CKE __attribute__((address(0x42E))); + + +extern volatile __bit SPI1CKP __attribute__((address(0x42D))); + + +extern volatile __bit SPI1CLKSEL0 __attribute__((address(0x460))); + + +extern volatile __bit SPI1CLKSEL1 __attribute__((address(0x461))); + + +extern volatile __bit SPI1CLKSEL2 __attribute__((address(0x462))); + + +extern volatile __bit SPI1CLKSEL3 __attribute__((address(0x463))); + + +extern volatile __bit SPI1CLKSEL4 __attribute__((address(0x464))); + + +extern volatile __bit SPI1CLRBF __attribute__((address(0x43A))); + + +extern volatile __bit SPI1EOSIE __attribute__((address(0x45C))); + + +extern volatile __bit SPI1EOSIF __attribute__((address(0x454))); + + +extern volatile __bit SPI1FST __attribute__((address(0x42C))); + + +extern volatile __bit SPI1IE __attribute__((address(0x250A))); + + +extern volatile __bit SPI1IF __attribute__((address(0x258A))); + + +extern volatile __bit SPI1IP __attribute__((address(0x1B2A))); + + +extern volatile __bit SPI1LSBF __attribute__((address(0x422))); + + +extern volatile __bit SPI1MD __attribute__((address(0x331))); + + +extern volatile __bit SPI1MST __attribute__((address(0x421))); + + +extern volatile __bit SPI1RXBF __attribute__((address(0x438))); + + +extern volatile __bit SPI1RXIE __attribute__((address(0x2508))); + + +extern volatile __bit SPI1RXIF __attribute__((address(0x2588))); + + +extern volatile __bit SPI1RXIP __attribute__((address(0x1B28))); + + +extern volatile __bit SPI1RXOIE __attribute__((address(0x45A))); + + +extern volatile __bit SPI1RXOIF __attribute__((address(0x452))); + + +extern volatile __bit SPI1RXR __attribute__((address(0x430))); + + +extern volatile __bit SPI1RXRE __attribute__((address(0x43B))); + + +extern volatile __bit SPI1SCKPPS0 __attribute__((address(0x1350))); + + +extern volatile __bit SPI1SCKPPS1 __attribute__((address(0x1351))); + + +extern volatile __bit SPI1SCKPPS2 __attribute__((address(0x1352))); + + +extern volatile __bit SPI1SCKPPS3 __attribute__((address(0x1353))); + + +extern volatile __bit SPI1SCKPPS4 __attribute__((address(0x1354))); + + +extern volatile __bit SPI1SDIP __attribute__((address(0x429))); + + +extern volatile __bit SPI1SDIPPS0 __attribute__((address(0x1358))); + + +extern volatile __bit SPI1SDIPPS1 __attribute__((address(0x1359))); + + +extern volatile __bit SPI1SDIPPS2 __attribute__((address(0x135A))); + + +extern volatile __bit SPI1SDIPPS3 __attribute__((address(0x135B))); + + +extern volatile __bit SPI1SDIPPS4 __attribute__((address(0x135C))); + + +extern volatile __bit SPI1SDOP __attribute__((address(0x428))); + + +extern volatile __bit SPI1SMP __attribute__((address(0x42F))); + + +extern volatile __bit SPI1SOSIE __attribute__((address(0x45D))); + + +extern volatile __bit SPI1SOSIF __attribute__((address(0x455))); + + +extern volatile __bit SPI1SPIEN __attribute__((address(0x427))); + + +extern volatile __bit SPI1SRMTIE __attribute__((address(0x45F))); + + +extern volatile __bit SPI1SRMTIF __attribute__((address(0x457))); + + +extern volatile __bit SPI1SSET __attribute__((address(0x432))); + + +extern volatile __bit SPI1SSFLT __attribute__((address(0x436))); + + +extern volatile __bit SPI1SSP __attribute__((address(0x42A))); + + +extern volatile __bit SPI1SSPPS0 __attribute__((address(0x1360))); + + +extern volatile __bit SPI1SSPPS1 __attribute__((address(0x1361))); + + +extern volatile __bit SPI1SSPPS2 __attribute__((address(0x1362))); + + +extern volatile __bit SPI1SSPPS3 __attribute__((address(0x1363))); + + +extern volatile __bit SPI1SSPPS4 __attribute__((address(0x1364))); + + +extern volatile __bit SPI1TCZIE __attribute__((address(0x45E))); + + +extern volatile __bit SPI1TCZIF __attribute__((address(0x456))); + + +extern volatile __bit SPI1TXBE __attribute__((address(0x43D))); + + +extern volatile __bit SPI1TXIE __attribute__((address(0x2509))); + + +extern volatile __bit SPI1TXIF __attribute__((address(0x2589))); + + +extern volatile __bit SPI1TXIP __attribute__((address(0x1B29))); + + +extern volatile __bit SPI1TXR __attribute__((address(0x431))); + + +extern volatile __bit SPI1TXUIE __attribute__((address(0x459))); + + +extern volatile __bit SPI1TXUIF __attribute__((address(0x451))); + + +extern volatile __bit SPI1TXWE __attribute__((address(0x43F))); + + +extern volatile __bit SPI2BMODE __attribute__((address(0x488))); + + +extern volatile __bit SPI2BUSY __attribute__((address(0x49F))); + + +extern volatile __bit SPI2CKE __attribute__((address(0x496))); + + +extern volatile __bit SPI2CKP __attribute__((address(0x495))); + + +extern volatile __bit SPI2CLKSEL0 __attribute__((address(0x4C8))); + + +extern volatile __bit SPI2CLKSEL1 __attribute__((address(0x4C9))); + + +extern volatile __bit SPI2CLKSEL2 __attribute__((address(0x4CA))); + + +extern volatile __bit SPI2CLKSEL3 __attribute__((address(0x4CB))); + + +extern volatile __bit SPI2CLKSEL4 __attribute__((address(0x4CC))); + + +extern volatile __bit SPI2CLRBF __attribute__((address(0x4A2))); + + +extern volatile __bit SPI2EOSIE __attribute__((address(0x4C4))); + + +extern volatile __bit SPI2EOSIF __attribute__((address(0x4BC))); + + +extern volatile __bit SPI2FST __attribute__((address(0x494))); + + +extern volatile __bit SPI2IE __attribute__((address(0x251A))); + + +extern volatile __bit SPI2IF __attribute__((address(0x259A))); + + +extern volatile __bit SPI2IP __attribute__((address(0x1B3A))); + + +extern volatile __bit SPI2LSBF __attribute__((address(0x48A))); + + +extern volatile __bit SPI2MD __attribute__((address(0x332))); + + +extern volatile __bit SPI2MST __attribute__((address(0x489))); + + +extern volatile __bit SPI2RXBF __attribute__((address(0x4A0))); + + +extern volatile __bit SPI2RXIE __attribute__((address(0x2518))); + + +extern volatile __bit SPI2RXIF __attribute__((address(0x2598))); + + +extern volatile __bit SPI2RXIP __attribute__((address(0x1B38))); + + +extern volatile __bit SPI2RXOIE __attribute__((address(0x4C2))); + + +extern volatile __bit SPI2RXOIF __attribute__((address(0x4BA))); + + +extern volatile __bit SPI2RXR __attribute__((address(0x498))); + + +extern volatile __bit SPI2RXRE __attribute__((address(0x4A3))); + + +extern volatile __bit SPI2SCKPPS0 __attribute__((address(0x1368))); + + +extern volatile __bit SPI2SCKPPS1 __attribute__((address(0x1369))); + + +extern volatile __bit SPI2SCKPPS2 __attribute__((address(0x136A))); + + +extern volatile __bit SPI2SCKPPS3 __attribute__((address(0x136B))); + + +extern volatile __bit SPI2SCKPPS4 __attribute__((address(0x136C))); + + +extern volatile __bit SPI2SDIP __attribute__((address(0x491))); + + +extern volatile __bit SPI2SDIPPS0 __attribute__((address(0x1370))); + + +extern volatile __bit SPI2SDIPPS1 __attribute__((address(0x1371))); + + +extern volatile __bit SPI2SDIPPS2 __attribute__((address(0x1372))); + + +extern volatile __bit SPI2SDIPPS3 __attribute__((address(0x1373))); + + +extern volatile __bit SPI2SDIPPS4 __attribute__((address(0x1374))); + + +extern volatile __bit SPI2SDOP __attribute__((address(0x490))); + + +extern volatile __bit SPI2SMP __attribute__((address(0x497))); + + +extern volatile __bit SPI2SOSIE __attribute__((address(0x4C5))); + + +extern volatile __bit SPI2SOSIF __attribute__((address(0x4BD))); + + +extern volatile __bit SPI2SPIEN __attribute__((address(0x48F))); + + +extern volatile __bit SPI2SRMTIE __attribute__((address(0x4C7))); + + +extern volatile __bit SPI2SRMTIF __attribute__((address(0x4BF))); + + +extern volatile __bit SPI2SSET __attribute__((address(0x49A))); + + +extern volatile __bit SPI2SSFLT __attribute__((address(0x49E))); + + +extern volatile __bit SPI2SSP __attribute__((address(0x492))); + + +extern volatile __bit SPI2SSPPS0 __attribute__((address(0x1378))); + + +extern volatile __bit SPI2SSPPS1 __attribute__((address(0x1379))); + + +extern volatile __bit SPI2SSPPS2 __attribute__((address(0x137A))); + + +extern volatile __bit SPI2SSPPS3 __attribute__((address(0x137B))); + + +extern volatile __bit SPI2SSPPS4 __attribute__((address(0x137C))); + + +extern volatile __bit SPI2TCZIE __attribute__((address(0x4C6))); + + +extern volatile __bit SPI2TCZIF __attribute__((address(0x4BE))); + + +extern volatile __bit SPI2TXBE __attribute__((address(0x4A5))); + + +extern volatile __bit SPI2TXIE __attribute__((address(0x2519))); + + +extern volatile __bit SPI2TXIF __attribute__((address(0x2599))); + + +extern volatile __bit SPI2TXIP __attribute__((address(0x1B39))); + + +extern volatile __bit SPI2TXR __attribute__((address(0x499))); + + +extern volatile __bit SPI2TXUIE __attribute__((address(0x4C1))); + + +extern volatile __bit SPI2TXUIF __attribute__((address(0x4B9))); + + +extern volatile __bit SPI2TXWE __attribute__((address(0x4A7))); + + +extern volatile __bit SPOL __attribute__((address(0x1863))); + + +extern volatile __bit SPTR0 __attribute__((address(0x7A0))); + + +extern volatile __bit SPTR1 __attribute__((address(0x7A1))); + + +extern volatile __bit SPTR10 __attribute__((address(0x7AA))); + + +extern volatile __bit SPTR11 __attribute__((address(0x7AB))); + + +extern volatile __bit SPTR12 __attribute__((address(0x7AC))); + + +extern volatile __bit SPTR13 __attribute__((address(0x7AD))); + + +extern volatile __bit SPTR14 __attribute__((address(0x7AE))); + + +extern volatile __bit SPTR15 __attribute__((address(0x7AF))); + + +extern volatile __bit SPTR16 __attribute__((address(0x7B0))); + + +extern volatile __bit SPTR17 __attribute__((address(0x7B1))); + + +extern volatile __bit SPTR18 __attribute__((address(0x7B2))); + + +extern volatile __bit SPTR19 __attribute__((address(0x7B3))); + + +extern volatile __bit SPTR2 __attribute__((address(0x7A2))); + + +extern volatile __bit SPTR20 __attribute__((address(0x7B4))); + + +extern volatile __bit SPTR21 __attribute__((address(0x7B5))); + + +extern volatile __bit SPTR3 __attribute__((address(0x7A3))); + + +extern volatile __bit SPTR4 __attribute__((address(0x7A4))); + + +extern volatile __bit SPTR5 __attribute__((address(0x7A5))); + + +extern volatile __bit SPTR6 __attribute__((address(0x7A6))); + + +extern volatile __bit SPTR7 __attribute__((address(0x7A7))); + + +extern volatile __bit SPTR8 __attribute__((address(0x7A8))); + + +extern volatile __bit SPTR9 __attribute__((address(0x7A9))); + + +extern volatile __bit SSA0 __attribute__((address(0x7C8))); + + +extern volatile __bit SSA1 __attribute__((address(0x7C9))); + + +extern volatile __bit SSA10 __attribute__((address(0x7D2))); + + +extern volatile __bit SSA11 __attribute__((address(0x7D3))); + + +extern volatile __bit SSA12 __attribute__((address(0x7D4))); + + +extern volatile __bit SSA13 __attribute__((address(0x7D5))); + + +extern volatile __bit SSA14 __attribute__((address(0x7D6))); + + +extern volatile __bit SSA15 __attribute__((address(0x7D7))); + + +extern volatile __bit SSA16 __attribute__((address(0x7D8))); + + +extern volatile __bit SSA17 __attribute__((address(0x7D9))); + + +extern volatile __bit SSA18 __attribute__((address(0x7DA))); + + +extern volatile __bit SSA19 __attribute__((address(0x7DB))); + + +extern volatile __bit SSA2 __attribute__((address(0x7CA))); + + +extern volatile __bit SSA20 __attribute__((address(0x7DC))); + + +extern volatile __bit SSA21 __attribute__((address(0x7DD))); + + +extern volatile __bit SSA3 __attribute__((address(0x7CB))); + + +extern volatile __bit SSA4 __attribute__((address(0x7CC))); + + +extern volatile __bit SSA5 __attribute__((address(0x7CD))); + + +extern volatile __bit SSA6 __attribute__((address(0x7CE))); + + +extern volatile __bit SSA7 __attribute__((address(0x7CF))); + + +extern volatile __bit SSA8 __attribute__((address(0x7D0))); + + +extern volatile __bit SSA9 __attribute__((address(0x7D1))); + + +extern volatile __bit SSEL0 __attribute__((address(0x1880))); + + +extern volatile __bit SSEL1 __attribute__((address(0x1881))); + + +extern volatile __bit SSEL2 __attribute__((address(0x1882))); + + +extern volatile __bit SSEL3 __attribute__((address(0x1883))); + + +extern volatile __bit SSEL4 __attribute__((address(0x1884))); + + +extern volatile __bit SSTP __attribute__((address(0x7E8))); + + +extern volatile __bit SSZ0 __attribute__((address(0x7B8))); + + +extern volatile __bit SSZ1 __attribute__((address(0x7B9))); + + +extern volatile __bit SSZ10 __attribute__((address(0x7C2))); + + +extern volatile __bit SSZ11 __attribute__((address(0x7C3))); + + +extern volatile __bit SSZ2 __attribute__((address(0x7BA))); + + +extern volatile __bit SSZ3 __attribute__((address(0x7BB))); + + +extern volatile __bit SSZ4 __attribute__((address(0x7BC))); + + +extern volatile __bit SSZ5 __attribute__((address(0x7BD))); + + +extern volatile __bit SSZ6 __attribute__((address(0x7BE))); + + +extern volatile __bit SSZ7 __attribute__((address(0x7BF))); + + +extern volatile __bit SSZ8 __attribute__((address(0x7C0))); + + +extern volatile __bit SSZ9 __attribute__((address(0x7C1))); + + +extern volatile __bit STAT2 __attribute__((address(0x1FBA))); + + +extern volatile __bit STATE __attribute__((address(0x3E2))); + + +extern volatile __bit STEF __attribute__((address(0x813))); + + +extern volatile __bit STKOVF __attribute__((address(0x2787))); + + +extern volatile __bit STKPTR0 __attribute__((address(0x27E0))); + + +extern volatile __bit STKPTR1 __attribute__((address(0x27E1))); + + +extern volatile __bit STKPTR2 __attribute__((address(0x27E2))); + + +extern volatile __bit STKPTR3 __attribute__((address(0x27E3))); + + +extern volatile __bit STKPTR4 __attribute__((address(0x27E4))); + + +extern volatile __bit STKPTR5 __attribute__((address(0x27E5))); + + +extern volatile __bit STKUNF __attribute__((address(0x2786))); + + +extern volatile __bit STP __attribute__((address(0x1865))); + + +extern volatile __bit STPT0 __attribute__((address(0x1EF8))); + + +extern volatile __bit STPT1 __attribute__((address(0x1EF9))); + + +extern volatile __bit STPT10 __attribute__((address(0x1F02))); + + +extern volatile __bit STPT11 __attribute__((address(0x1F03))); + + +extern volatile __bit STPT12 __attribute__((address(0x1F04))); + + +extern volatile __bit STPT13 __attribute__((address(0x1F05))); + + +extern volatile __bit STPT15 __attribute__((address(0x1F06))); + + +extern volatile __bit STPT16 __attribute__((address(0x1F07))); + + +extern volatile __bit STPT2 __attribute__((address(0x1EFA))); + + +extern volatile __bit STPT3 __attribute__((address(0x1EFB))); + + +extern volatile __bit STPT4 __attribute__((address(0x1EFC))); + + +extern volatile __bit STPT5 __attribute__((address(0x1EFD))); + + +extern volatile __bit STPT6 __attribute__((address(0x1EFE))); + + +extern volatile __bit STPT7 __attribute__((address(0x1EFF))); + + +extern volatile __bit STPT8 __attribute__((address(0x1F00))); + + +extern volatile __bit STPT9 __attribute__((address(0x1F01))); + + +extern volatile __bit SWDTEN __attribute__((address(0x3C0))); + + +extern volatile __bit SWIE __attribute__((address(0x24F0))); + + +extern volatile __bit SWIF __attribute__((address(0x2570))); + + +extern volatile __bit SWIP __attribute__((address(0x1B10))); + + +extern volatile __bit SYSCMD __attribute__((address(0x307))); + + +extern volatile __bit T016BIT __attribute__((address(0x18D4))); + + +extern volatile __bit T0ASYNC __attribute__((address(0x18DC))); + + +extern volatile __bit T0CKIPPS0 __attribute__((address(0x1208))); + + +extern volatile __bit T0CKIPPS1 __attribute__((address(0x1209))); + + +extern volatile __bit T0CKIPPS2 __attribute__((address(0x120A))); + + +extern volatile __bit T0CKIPPS3 __attribute__((address(0x120B))); + + +extern volatile __bit T0CKIPPS4 __attribute__((address(0x120C))); + + +extern volatile __bit T0CKIPPS5 __attribute__((address(0x120D))); + + +extern volatile __bit T0CKPS0 __attribute__((address(0x18D8))); + + +extern volatile __bit T0CKPS1 __attribute__((address(0x18D9))); + + +extern volatile __bit T0CKPS2 __attribute__((address(0x18DA))); + + +extern volatile __bit T0CKPS3 __attribute__((address(0x18DB))); + + +extern volatile __bit T0CS0 __attribute__((address(0x18DD))); + + +extern volatile __bit T0CS1 __attribute__((address(0x18DE))); + + +extern volatile __bit T0CS2 __attribute__((address(0x18DF))); + + +extern volatile __bit T0EN __attribute__((address(0x18D7))); + + +extern volatile __bit T0MD16 __attribute__((address(0x18D4))); + + +extern volatile __bit T0OUT __attribute__((address(0x18D5))); + + +extern volatile __bit T0PR0 __attribute__((address(0x18C8))); + + +extern volatile __bit T0PR1 __attribute__((address(0x18C9))); + + +extern volatile __bit T0PR2 __attribute__((address(0x18CA))); + + +extern volatile __bit T0PR3 __attribute__((address(0x18CB))); + + +extern volatile __bit T0PR4 __attribute__((address(0x18CC))); + + +extern volatile __bit T0PR5 __attribute__((address(0x18CD))); + + +extern volatile __bit T0PR6 __attribute__((address(0x18CE))); + + +extern volatile __bit T0PR7 __attribute__((address(0x18CF))); + + +extern volatile __bit T1CKIPPS0 __attribute__((address(0x1210))); + + +extern volatile __bit T1CKIPPS1 __attribute__((address(0x1211))); + + +extern volatile __bit T1CKIPPS2 __attribute__((address(0x1212))); + + +extern volatile __bit T1CKIPPS3 __attribute__((address(0x1213))); + + +extern volatile __bit T1CKIPPS4 __attribute__((address(0x1214))); + + +extern volatile __bit T1CKIPPS5 __attribute__((address(0x1215))); + + +extern volatile __bit T1CKPS0 __attribute__((address(0x18F4))); + + +extern volatile __bit T1CKPS1 __attribute__((address(0x18F5))); + + +extern volatile __bit T1CS0 __attribute__((address(0x1908))); + + +extern volatile __bit T1CS1 __attribute__((address(0x1909))); + + +extern volatile __bit T1CS2 __attribute__((address(0x190A))); + + +extern volatile __bit T1CS3 __attribute__((address(0x190B))); + + +extern volatile __bit T1CS4 __attribute__((address(0x190C))); + + +extern volatile __bit T1GE __attribute__((address(0x18FF))); + + +extern volatile __bit T1GGO __attribute__((address(0x18FB))); + + +extern volatile __bit T1GPOL __attribute__((address(0x18FE))); + + +extern volatile __bit T1GPPS0 __attribute__((address(0x1218))); + + +extern volatile __bit T1GPPS1 __attribute__((address(0x1219))); + + +extern volatile __bit T1GPPS2 __attribute__((address(0x121A))); + + +extern volatile __bit T1GPPS3 __attribute__((address(0x121B))); + + +extern volatile __bit T1GPPS4 __attribute__((address(0x121C))); + + +extern volatile __bit T1GSPM __attribute__((address(0x18FC))); + + +extern volatile __bit T1GSS0 __attribute__((address(0x1900))); + + +extern volatile __bit T1GSS1 __attribute__((address(0x1901))); + + +extern volatile __bit T1GSS2 __attribute__((address(0x1902))); + + +extern volatile __bit T1GSS3 __attribute__((address(0x1903))); + + +extern volatile __bit T1GSS4 __attribute__((address(0x1904))); + + +extern volatile __bit T1GTM __attribute__((address(0x18FD))); + + +extern volatile __bit T1GVAL __attribute__((address(0x18FA))); + + +extern volatile __bit T1RD16 __attribute__((address(0x18F1))); + + +extern volatile __bit T2CKPOL __attribute__((address(0x192E))); + + +extern volatile __bit T2CKPS0 __attribute__((address(0x1924))); + + +extern volatile __bit T2CKPS1 __attribute__((address(0x1925))); + + +extern volatile __bit T2CKPS2 __attribute__((address(0x1926))); + + +extern volatile __bit T2CKSYNC __attribute__((address(0x192D))); + + +extern volatile __bit T2CS0 __attribute__((address(0x1930))); + + +extern volatile __bit T2CS1 __attribute__((address(0x1931))); + + +extern volatile __bit T2CS2 __attribute__((address(0x1932))); + + +extern volatile __bit T2CS3 __attribute__((address(0x1933))); + + +extern volatile __bit T2INPPS0 __attribute__((address(0x1240))); + + +extern volatile __bit T2INPPS1 __attribute__((address(0x1241))); + + +extern volatile __bit T2INPPS2 __attribute__((address(0x1242))); + + +extern volatile __bit T2INPPS3 __attribute__((address(0x1243))); + + +extern volatile __bit T2INPPS4 __attribute__((address(0x1244))); + + +extern volatile __bit T2MODE0 __attribute__((address(0x1928))); + + +extern volatile __bit T2MODE1 __attribute__((address(0x1929))); + + +extern volatile __bit T2MODE2 __attribute__((address(0x192A))); + + +extern volatile __bit T2MODE3 __attribute__((address(0x192B))); + + +extern volatile __bit T2MODE4 __attribute__((address(0x192C))); + + +extern volatile __bit T2ON __attribute__((address(0x1927))); + + +extern volatile __bit T2OUTPS0 __attribute__((address(0x1920))); + + +extern volatile __bit T2OUTPS1 __attribute__((address(0x1921))); + + +extern volatile __bit T2OUTPS2 __attribute__((address(0x1922))); + + +extern volatile __bit T2OUTPS3 __attribute__((address(0x1923))); + + +extern volatile __bit T2PSYNC __attribute__((address(0x192F))); + + +extern volatile __bit T2RSEL0 __attribute__((address(0x1938))); + + +extern volatile __bit T2RSEL1 __attribute__((address(0x1939))); + + +extern volatile __bit T2RSEL2 __attribute__((address(0x193A))); + + +extern volatile __bit T2RSEL3 __attribute__((address(0x193B))); + + +extern volatile __bit T2RSEL4 __attribute__((address(0x193C))); + + +extern volatile __bit T3CKIPPS0 __attribute__((address(0x1220))); + + +extern volatile __bit T3CKIPPS1 __attribute__((address(0x1221))); + + +extern volatile __bit T3CKIPPS2 __attribute__((address(0x1222))); + + +extern volatile __bit T3CKIPPS3 __attribute__((address(0x1223))); + + +extern volatile __bit T3CKIPPS4 __attribute__((address(0x1224))); + + +extern volatile __bit T3CKIPPS5 __attribute__((address(0x1225))); + + +extern volatile __bit T3CKPS0 __attribute__((address(0x1954))); + + +extern volatile __bit T3CKPS1 __attribute__((address(0x1955))); + + +extern volatile __bit T3CS0 __attribute__((address(0x1968))); + + +extern volatile __bit T3CS1 __attribute__((address(0x1969))); + + +extern volatile __bit T3CS2 __attribute__((address(0x196A))); + + +extern volatile __bit T3CS3 __attribute__((address(0x196B))); + + +extern volatile __bit T3CS4 __attribute__((address(0x196C))); + + +extern volatile __bit T3GE __attribute__((address(0x195F))); + + +extern volatile __bit T3GGO __attribute__((address(0x195B))); + + +extern volatile __bit T3GPOL __attribute__((address(0x195E))); + + +extern volatile __bit T3GPPS0 __attribute__((address(0x1228))); + + +extern volatile __bit T3GPPS1 __attribute__((address(0x1229))); + + +extern volatile __bit T3GPPS2 __attribute__((address(0x122A))); + + +extern volatile __bit T3GPPS3 __attribute__((address(0x122B))); + + +extern volatile __bit T3GPPS4 __attribute__((address(0x122C))); + + +extern volatile __bit T3GSPM __attribute__((address(0x195C))); + + +extern volatile __bit T3GSS0 __attribute__((address(0x1960))); + + +extern volatile __bit T3GSS1 __attribute__((address(0x1961))); + + +extern volatile __bit T3GSS2 __attribute__((address(0x1962))); + + +extern volatile __bit T3GSS3 __attribute__((address(0x1963))); + + +extern volatile __bit T3GSS4 __attribute__((address(0x1964))); + + +extern volatile __bit T3GTM __attribute__((address(0x195D))); + + +extern volatile __bit T3GVAL __attribute__((address(0x195A))); + + +extern volatile __bit T3RD16 __attribute__((address(0x1951))); + + +extern volatile __bit T4CKPOL __attribute__((address(0x198E))); + + +extern volatile __bit T4CKPS0 __attribute__((address(0x1984))); + + +extern volatile __bit T4CKPS1 __attribute__((address(0x1985))); + + +extern volatile __bit T4CKPS2 __attribute__((address(0x1986))); + + +extern volatile __bit T4CKSYNC __attribute__((address(0x198D))); + + +extern volatile __bit T4CS0 __attribute__((address(0x1990))); + + +extern volatile __bit T4CS1 __attribute__((address(0x1991))); + + +extern volatile __bit T4CS2 __attribute__((address(0x1992))); + + +extern volatile __bit T4CS3 __attribute__((address(0x1993))); + + +extern volatile __bit T4INPPS0 __attribute__((address(0x1248))); + + +extern volatile __bit T4INPPS1 __attribute__((address(0x1249))); + + +extern volatile __bit T4INPPS2 __attribute__((address(0x124A))); + + +extern volatile __bit T4INPPS3 __attribute__((address(0x124B))); + + +extern volatile __bit T4INPPS4 __attribute__((address(0x124C))); + + +extern volatile __bit T4MODE0 __attribute__((address(0x1988))); + + +extern volatile __bit T4MODE1 __attribute__((address(0x1989))); + + +extern volatile __bit T4MODE2 __attribute__((address(0x198A))); + + +extern volatile __bit T4MODE3 __attribute__((address(0x198B))); + + +extern volatile __bit T4MODE4 __attribute__((address(0x198C))); + + +extern volatile __bit T4ON __attribute__((address(0x1987))); + + +extern volatile __bit T4OUTPS0 __attribute__((address(0x1980))); + + +extern volatile __bit T4OUTPS1 __attribute__((address(0x1981))); + + +extern volatile __bit T4OUTPS2 __attribute__((address(0x1982))); + + +extern volatile __bit T4OUTPS3 __attribute__((address(0x1983))); + + +extern volatile __bit T4PSYNC __attribute__((address(0x198F))); + + +extern volatile __bit T4RSEL0 __attribute__((address(0x1998))); + + +extern volatile __bit T4RSEL1 __attribute__((address(0x1999))); + + +extern volatile __bit T4RSEL2 __attribute__((address(0x199A))); + + +extern volatile __bit T4RSEL3 __attribute__((address(0x199B))); + + +extern volatile __bit T4RSEL4 __attribute__((address(0x199C))); + + +extern volatile __bit T5CKIPPS0 __attribute__((address(0x1230))); + + +extern volatile __bit T5CKIPPS1 __attribute__((address(0x1231))); + + +extern volatile __bit T5CKIPPS2 __attribute__((address(0x1232))); + + +extern volatile __bit T5CKIPPS3 __attribute__((address(0x1233))); + + +extern volatile __bit T5CKIPPS4 __attribute__((address(0x1234))); + + +extern volatile __bit T5CKIPPS5 __attribute__((address(0x1235))); + + +extern volatile __bit T5CKPS0 __attribute__((address(0x19B4))); + + +extern volatile __bit T5CKPS1 __attribute__((address(0x19B5))); + + +extern volatile __bit T5CS0 __attribute__((address(0x19C8))); + + +extern volatile __bit T5CS1 __attribute__((address(0x19C9))); + + +extern volatile __bit T5CS2 __attribute__((address(0x19CA))); + + +extern volatile __bit T5CS3 __attribute__((address(0x19CB))); + + +extern volatile __bit T5CS4 __attribute__((address(0x19CC))); + + +extern volatile __bit T5GE __attribute__((address(0x19BF))); + + +extern volatile __bit T5GGO __attribute__((address(0x19BB))); + + +extern volatile __bit T5GPOL __attribute__((address(0x19BE))); + + +extern volatile __bit T5GPPS0 __attribute__((address(0x1238))); + + +extern volatile __bit T5GPPS1 __attribute__((address(0x1239))); + + +extern volatile __bit T5GPPS2 __attribute__((address(0x123A))); + + +extern volatile __bit T5GPPS3 __attribute__((address(0x123B))); + + +extern volatile __bit T5GPPS4 __attribute__((address(0x123C))); + + +extern volatile __bit T5GSPM __attribute__((address(0x19BC))); + + +extern volatile __bit T5GSS0 __attribute__((address(0x19C0))); + + +extern volatile __bit T5GSS1 __attribute__((address(0x19C1))); + + +extern volatile __bit T5GSS2 __attribute__((address(0x19C2))); + + +extern volatile __bit T5GSS3 __attribute__((address(0x19C3))); + + +extern volatile __bit T5GSS4 __attribute__((address(0x19C4))); + + +extern volatile __bit T5GTM __attribute__((address(0x19BD))); + + +extern volatile __bit T5GVAL __attribute__((address(0x19BA))); + + +extern volatile __bit T5RD16 __attribute__((address(0x19B1))); + + +extern volatile __bit T6CKPOL __attribute__((address(0x19EE))); + + +extern volatile __bit T6CKPS0 __attribute__((address(0x19E4))); + + +extern volatile __bit T6CKPS1 __attribute__((address(0x19E5))); + + +extern volatile __bit T6CKPS2 __attribute__((address(0x19E6))); + + +extern volatile __bit T6CKSYNC __attribute__((address(0x19ED))); + + +extern volatile __bit T6CS0 __attribute__((address(0x19F0))); + + +extern volatile __bit T6CS1 __attribute__((address(0x19F1))); + + +extern volatile __bit T6CS2 __attribute__((address(0x19F2))); + + +extern volatile __bit T6CS3 __attribute__((address(0x19F3))); + + +extern volatile __bit T6INPPS0 __attribute__((address(0x1250))); + + +extern volatile __bit T6INPPS1 __attribute__((address(0x1251))); + + +extern volatile __bit T6INPPS2 __attribute__((address(0x1252))); + + +extern volatile __bit T6INPPS3 __attribute__((address(0x1253))); + + +extern volatile __bit T6INPPS4 __attribute__((address(0x1254))); + + +extern volatile __bit T6MODE0 __attribute__((address(0x19E8))); + + +extern volatile __bit T6MODE1 __attribute__((address(0x19E9))); + + +extern volatile __bit T6MODE2 __attribute__((address(0x19EA))); + + +extern volatile __bit T6MODE3 __attribute__((address(0x19EB))); + + +extern volatile __bit T6MODE4 __attribute__((address(0x19EC))); + + +extern volatile __bit T6ON __attribute__((address(0x19E7))); + + +extern volatile __bit T6OUTPS0 __attribute__((address(0x19E0))); + + +extern volatile __bit T6OUTPS1 __attribute__((address(0x19E1))); + + +extern volatile __bit T6OUTPS2 __attribute__((address(0x19E2))); + + +extern volatile __bit T6OUTPS3 __attribute__((address(0x19E3))); + + +extern volatile __bit T6PSYNC __attribute__((address(0x19EF))); + + +extern volatile __bit T6RSEL0 __attribute__((address(0x19F8))); + + +extern volatile __bit T6RSEL1 __attribute__((address(0x19F9))); + + +extern volatile __bit T6RSEL2 __attribute__((address(0x19FA))); + + +extern volatile __bit T6RSEL3 __attribute__((address(0x19FB))); + + +extern volatile __bit T6RSEL4 __attribute__((address(0x19FC))); + + +extern volatile __bit TBC0 __attribute__((address(0x880))); + + +extern volatile __bit TBC1 __attribute__((address(0x881))); + + +extern volatile __bit TBC10 __attribute__((address(0x88A))); + + +extern volatile __bit TBC11 __attribute__((address(0x88B))); + + +extern volatile __bit TBC12 __attribute__((address(0x88C))); + + +extern volatile __bit TBC13 __attribute__((address(0x88D))); + + +extern volatile __bit TBC14 __attribute__((address(0x88E))); + + +extern volatile __bit TBC15 __attribute__((address(0x88F))); + + +extern volatile __bit TBC16 __attribute__((address(0x890))); + + +extern volatile __bit TBC17 __attribute__((address(0x891))); + + +extern volatile __bit TBC18 __attribute__((address(0x892))); + + +extern volatile __bit TBC19 __attribute__((address(0x893))); + + +extern volatile __bit TBC2 __attribute__((address(0x882))); + + +extern volatile __bit TBC20 __attribute__((address(0x894))); + + +extern volatile __bit TBC21 __attribute__((address(0x895))); + + +extern volatile __bit TBC22 __attribute__((address(0x896))); + + +extern volatile __bit TBC23 __attribute__((address(0x897))); + + +extern volatile __bit TBC24 __attribute__((address(0x898))); + + +extern volatile __bit TBC25 __attribute__((address(0x899))); + + +extern volatile __bit TBC26 __attribute__((address(0x89A))); + + +extern volatile __bit TBC27 __attribute__((address(0x89B))); + + +extern volatile __bit TBC28 __attribute__((address(0x89C))); + + +extern volatile __bit TBC29 __attribute__((address(0x89D))); + + +extern volatile __bit TBC3 __attribute__((address(0x883))); + + +extern volatile __bit TBC30 __attribute__((address(0x89E))); + + +extern volatile __bit TBC31 __attribute__((address(0x89F))); + + +extern volatile __bit TBC4 __attribute__((address(0x884))); + + +extern volatile __bit TBC5 __attribute__((address(0x885))); + + +extern volatile __bit TBC6 __attribute__((address(0x886))); + + +extern volatile __bit TBC7 __attribute__((address(0x887))); + + +extern volatile __bit TBC8 __attribute__((address(0x888))); + + +extern volatile __bit TBC9 __attribute__((address(0x889))); + + +extern volatile __bit TBCEN __attribute__((address(0x8B0))); + + +extern volatile __bit TBCIE __attribute__((address(0x8F2))); + + +extern volatile __bit TBCIF __attribute__((address(0x8E2))); + + +extern volatile __bit TBCPRE0 __attribute__((address(0x8A0))); + + +extern volatile __bit TBCPRE1 __attribute__((address(0x8A1))); + + +extern volatile __bit TBCPRE2 __attribute__((address(0x8A2))); + + +extern volatile __bit TBCPRE3 __attribute__((address(0x8A3))); + + +extern volatile __bit TBCPRE4 __attribute__((address(0x8A4))); + + +extern volatile __bit TBCPRE5 __attribute__((address(0x8A5))); + + +extern volatile __bit TBCPRE6 __attribute__((address(0x8A6))); + + +extern volatile __bit TBCPRE7 __attribute__((address(0x8A7))); + + +extern volatile __bit TBCPRE8 __attribute__((address(0x8A8))); + + +extern volatile __bit TBCPRE9 __attribute__((address(0x8A9))); + + +extern volatile __bit TDCMOD0 __attribute__((address(0x870))); + + +extern volatile __bit TDCMOD1 __attribute__((address(0x871))); + + +extern volatile __bit TDCO0 __attribute__((address(0x868))); + + +extern volatile __bit TDCO1 __attribute__((address(0x869))); + + +extern volatile __bit TDCO2 __attribute__((address(0x86A))); + + +extern volatile __bit TDCO3 __attribute__((address(0x86B))); + + +extern volatile __bit TDCO4 __attribute__((address(0x86C))); + + +extern volatile __bit TDCO5 __attribute__((address(0x86D))); + + +extern volatile __bit TDCO6 __attribute__((address(0x86E))); + + +extern volatile __bit TDCV0 __attribute__((address(0x860))); + + +extern volatile __bit TDCV1 __attribute__((address(0x861))); + + +extern volatile __bit TDCV2 __attribute__((address(0x862))); + + +extern volatile __bit TDCV3 __attribute__((address(0x863))); + + +extern volatile __bit TDCV4 __attribute__((address(0x864))); + + +extern volatile __bit TDCV5 __attribute__((address(0x865))); + + +extern volatile __bit TEFFIE __attribute__((address(0xA02))); + + +extern volatile __bit TEFFIF __attribute__((address(0xA22))); + + +extern volatile __bit TEFHIE __attribute__((address(0xA01))); + + +extern volatile __bit TEFHIF __attribute__((address(0xA21))); + + +extern volatile __bit TEFIE __attribute__((address(0x8F4))); + + +extern volatile __bit TEFIF __attribute__((address(0x8E4))); + + +extern volatile __bit TEFNEIE __attribute__((address(0xA00))); + + +extern volatile __bit TEFNEIF __attribute__((address(0xA20))); + + +extern volatile __bit TEFOVIE __attribute__((address(0xA03))); + + +extern volatile __bit TEFOVIF __attribute__((address(0xA23))); + + +extern volatile __bit TEFTSEN __attribute__((address(0xA05))); + + +extern volatile __bit TEFUA0 __attribute__((address(0xA40))); + + +extern volatile __bit TEFUA1 __attribute__((address(0xA41))); + + +extern volatile __bit TEFUA10 __attribute__((address(0xA4A))); + + +extern volatile __bit TEFUA11 __attribute__((address(0xA4B))); + + +extern volatile __bit TEFUA12 __attribute__((address(0xA4C))); + + +extern volatile __bit TEFUA13 __attribute__((address(0xA4D))); + + +extern volatile __bit TEFUA14 __attribute__((address(0xA4E))); + + +extern volatile __bit TEFUA15 __attribute__((address(0xA4F))); + + +extern volatile __bit TEFUA16 __attribute__((address(0xA50))); + + +extern volatile __bit TEFUA17 __attribute__((address(0xA51))); + + +extern volatile __bit TEFUA18 __attribute__((address(0xA52))); + + +extern volatile __bit TEFUA19 __attribute__((address(0xA53))); + + +extern volatile __bit TEFUA2 __attribute__((address(0xA42))); + + +extern volatile __bit TEFUA20 __attribute__((address(0xA54))); + + +extern volatile __bit TEFUA21 __attribute__((address(0xA55))); + + +extern volatile __bit TEFUA22 __attribute__((address(0xA56))); + + +extern volatile __bit TEFUA23 __attribute__((address(0xA57))); + + +extern volatile __bit TEFUA24 __attribute__((address(0xA58))); + + +extern volatile __bit TEFUA25 __attribute__((address(0xA59))); + + +extern volatile __bit TEFUA26 __attribute__((address(0xA5A))); + + +extern volatile __bit TEFUA27 __attribute__((address(0xA5B))); + + +extern volatile __bit TEFUA28 __attribute__((address(0xA5C))); + + +extern volatile __bit TEFUA29 __attribute__((address(0xA5D))); + + +extern volatile __bit TEFUA3 __attribute__((address(0xA43))); + + +extern volatile __bit TEFUA30 __attribute__((address(0xA5E))); + + +extern volatile __bit TEFUA31 __attribute__((address(0xA5F))); + + +extern volatile __bit TEFUA4 __attribute__((address(0xA44))); + + +extern volatile __bit TEFUA5 __attribute__((address(0xA45))); + + +extern volatile __bit TEFUA6 __attribute__((address(0xA46))); + + +extern volatile __bit TEFUA7 __attribute__((address(0xA47))); + + +extern volatile __bit TEFUA8 __attribute__((address(0xA48))); + + +extern volatile __bit TEFUA9 __attribute__((address(0xA49))); + + +extern volatile __bit TERRCNT0 __attribute__((address(0x9A8))); + + +extern volatile __bit TERRCNT1 __attribute__((address(0x9A9))); + + +extern volatile __bit TERRCNT2 __attribute__((address(0x9AA))); + + +extern volatile __bit TERRCNT3 __attribute__((address(0x9AB))); + + +extern volatile __bit TERRCNT4 __attribute__((address(0x9AC))); + + +extern volatile __bit TERRCNT5 __attribute__((address(0x9AD))); + + +extern volatile __bit TERRCNT6 __attribute__((address(0x9AE))); + + +extern volatile __bit TERRCNT7 __attribute__((address(0x9AF))); + + +extern volatile __bit TFATIF0 __attribute__((address(0x960))); + + +extern volatile __bit TFATIF1 __attribute__((address(0x961))); + + +extern volatile __bit TFATIF10 __attribute__((address(0x96A))); + + +extern volatile __bit TFATIF11 __attribute__((address(0x96B))); + + +extern volatile __bit TFATIF12 __attribute__((address(0x96C))); + + +extern volatile __bit TFATIF13 __attribute__((address(0x96D))); + + +extern volatile __bit TFATIF14 __attribute__((address(0x96E))); + + +extern volatile __bit TFATIF15 __attribute__((address(0x96F))); + + +extern volatile __bit TFATIF16 __attribute__((address(0x970))); + + +extern volatile __bit TFATIF17 __attribute__((address(0x971))); + + +extern volatile __bit TFATIF18 __attribute__((address(0x972))); + + +extern volatile __bit TFATIF19 __attribute__((address(0x973))); + + +extern volatile __bit TFATIF2 __attribute__((address(0x962))); + + +extern volatile __bit TFATIF20 __attribute__((address(0x974))); + + +extern volatile __bit TFATIF21 __attribute__((address(0x975))); + + +extern volatile __bit TFATIF22 __attribute__((address(0x976))); + + +extern volatile __bit TFATIF23 __attribute__((address(0x977))); + + +extern volatile __bit TFATIF24 __attribute__((address(0x978))); + + +extern volatile __bit TFATIF25 __attribute__((address(0x979))); + + +extern volatile __bit TFATIF26 __attribute__((address(0x97A))); + + +extern volatile __bit TFATIF27 __attribute__((address(0x97B))); + + +extern volatile __bit TFATIF28 __attribute__((address(0x97C))); + + +extern volatile __bit TFATIF29 __attribute__((address(0x97D))); + + +extern volatile __bit TFATIF3 __attribute__((address(0x963))); + + +extern volatile __bit TFATIF30 __attribute__((address(0x97E))); + + +extern volatile __bit TFATIF31 __attribute__((address(0x97F))); + + +extern volatile __bit TFATIF4 __attribute__((address(0x964))); + + +extern volatile __bit TFATIF5 __attribute__((address(0x965))); + + +extern volatile __bit TFATIF6 __attribute__((address(0x966))); + + +extern volatile __bit TFATIF7 __attribute__((address(0x967))); + + +extern volatile __bit TFATIF8 __attribute__((address(0x968))); + + +extern volatile __bit TFATIF9 __attribute__((address(0x969))); + + +extern volatile __bit TFIF0 __attribute__((address(0x920))); + + +extern volatile __bit TFIF1 __attribute__((address(0x921))); + + +extern volatile __bit TFIF10 __attribute__((address(0x92A))); + + +extern volatile __bit TFIF11 __attribute__((address(0x92B))); + + +extern volatile __bit TFIF12 __attribute__((address(0x92C))); + + +extern volatile __bit TFIF13 __attribute__((address(0x92D))); + + +extern volatile __bit TFIF14 __attribute__((address(0x92E))); + + +extern volatile __bit TFIF15 __attribute__((address(0x92F))); + + +extern volatile __bit TFIF16 __attribute__((address(0x930))); + + +extern volatile __bit TFIF17 __attribute__((address(0x931))); + + +extern volatile __bit TFIF18 __attribute__((address(0x932))); + + +extern volatile __bit TFIF19 __attribute__((address(0x933))); + + +extern volatile __bit TFIF2 __attribute__((address(0x922))); + + +extern volatile __bit TFIF20 __attribute__((address(0x934))); + + +extern volatile __bit TFIF21 __attribute__((address(0x935))); + + +extern volatile __bit TFIF22 __attribute__((address(0x936))); + + +extern volatile __bit TFIF23 __attribute__((address(0x937))); + + +extern volatile __bit TFIF24 __attribute__((address(0x938))); + + +extern volatile __bit TFIF25 __attribute__((address(0x939))); + + +extern volatile __bit TFIF26 __attribute__((address(0x93A))); + + +extern volatile __bit TFIF27 __attribute__((address(0x93B))); + + +extern volatile __bit TFIF28 __attribute__((address(0x93C))); + + +extern volatile __bit TFIF29 __attribute__((address(0x93D))); + + +extern volatile __bit TFIF3 __attribute__((address(0x923))); + + +extern volatile __bit TFIF30 __attribute__((address(0x93E))); + + +extern volatile __bit TFIF31 __attribute__((address(0x93F))); + + +extern volatile __bit TFIF4 __attribute__((address(0x924))); + + +extern volatile __bit TFIF5 __attribute__((address(0x925))); + + +extern volatile __bit TFIF6 __attribute__((address(0x926))); + + +extern volatile __bit TFIF7 __attribute__((address(0x927))); + + +extern volatile __bit TFIF8 __attribute__((address(0x928))); + + +extern volatile __bit TFIF9 __attribute__((address(0x929))); + + +extern volatile __bit TMD0 __attribute__((address(0x1FB0))); + + +extern volatile __bit TMD1 __attribute__((address(0x1FB1))); + + +extern volatile __bit TMD2 __attribute__((address(0x1FB2))); + + +extern volatile __bit TMR0H0 __attribute__((address(0x18C8))); + + +extern volatile __bit TMR0H1 __attribute__((address(0x18C9))); + + +extern volatile __bit TMR0H2 __attribute__((address(0x18CA))); + + +extern volatile __bit TMR0H3 __attribute__((address(0x18CB))); + + +extern volatile __bit TMR0H4 __attribute__((address(0x18CC))); + + +extern volatile __bit TMR0H5 __attribute__((address(0x18CD))); + + +extern volatile __bit TMR0H6 __attribute__((address(0x18CE))); + + +extern volatile __bit TMR0H7 __attribute__((address(0x18CF))); + + +extern volatile __bit TMR0IE __attribute__((address(0x250F))); + + +extern volatile __bit TMR0IF __attribute__((address(0x258F))); + + +extern volatile __bit TMR0IP __attribute__((address(0x1B2F))); + + +extern volatile __bit TMR0L0 __attribute__((address(0x18C0))); + + +extern volatile __bit TMR0L1 __attribute__((address(0x18C1))); + + +extern volatile __bit TMR0L2 __attribute__((address(0x18C2))); + + +extern volatile __bit TMR0L3 __attribute__((address(0x18C3))); + + +extern volatile __bit TMR0L4 __attribute__((address(0x18C4))); + + +extern volatile __bit TMR0L5 __attribute__((address(0x18C5))); + + +extern volatile __bit TMR0L6 __attribute__((address(0x18C6))); + + +extern volatile __bit TMR0L7 __attribute__((address(0x18C7))); + + +extern volatile __bit TMR0MD __attribute__((address(0x308))); + + +extern volatile __bit TMR1 __attribute__((address(0x1801))); + + +extern volatile __bit TMR10 __attribute__((address(0x180A))); + + +extern volatile __bit TMR11 __attribute__((address(0x180B))); + + +extern volatile __bit TMR12 __attribute__((address(0x180C))); + + +extern volatile __bit TMR13 __attribute__((address(0x180D))); + + +extern volatile __bit TMR14 __attribute__((address(0x180E))); + + +extern volatile __bit TMR15 __attribute__((address(0x180F))); + + +extern volatile __bit TMR16 __attribute__((address(0x1810))); + + +extern volatile __bit TMR17 __attribute__((address(0x1811))); + + +extern volatile __bit TMR18 __attribute__((address(0x1812))); + + +extern volatile __bit TMR19 __attribute__((address(0x1813))); + + +extern volatile __bit TMR1GIE __attribute__((address(0x250D))); + + +extern volatile __bit TMR1GIF __attribute__((address(0x258D))); + + +extern volatile __bit TMR1GIP __attribute__((address(0x1B2D))); + + +extern volatile __bit TMR1H0 __attribute__((address(0x18E8))); + + +extern volatile __bit TMR1H1 __attribute__((address(0x18E9))); + + +extern volatile __bit TMR1H2 __attribute__((address(0x18EA))); + + +extern volatile __bit TMR1H3 __attribute__((address(0x18EB))); + + +extern volatile __bit TMR1H4 __attribute__((address(0x18EC))); + + +extern volatile __bit TMR1H5 __attribute__((address(0x18ED))); + + +extern volatile __bit TMR1H6 __attribute__((address(0x18EE))); + + +extern volatile __bit TMR1H7 __attribute__((address(0x18EF))); + + +extern volatile __bit TMR1IE __attribute__((address(0x250C))); + + +extern volatile __bit TMR1IF __attribute__((address(0x258C))); + + +extern volatile __bit TMR1IP __attribute__((address(0x1B2C))); + + +extern volatile __bit TMR1L0 __attribute__((address(0x18E0))); + + +extern volatile __bit TMR1L1 __attribute__((address(0x18E1))); + + +extern volatile __bit TMR1L2 __attribute__((address(0x18E2))); + + +extern volatile __bit TMR1L3 __attribute__((address(0x18E3))); + + +extern volatile __bit TMR1L4 __attribute__((address(0x18E4))); + + +extern volatile __bit TMR1L5 __attribute__((address(0x18E5))); + + +extern volatile __bit TMR1L6 __attribute__((address(0x18E6))); + + +extern volatile __bit TMR1L7 __attribute__((address(0x18E7))); + + +extern volatile __bit TMR1MD __attribute__((address(0x309))); + + +extern volatile __bit TMR1ON __attribute__((address(0x18F0))); + + +extern volatile __bit TMR20 __attribute__((address(0x1814))); + + +extern volatile __bit TMR21 __attribute__((address(0x1815))); + + +extern volatile __bit TMR22 __attribute__((address(0x1816))); + + +extern volatile __bit TMR23 __attribute__((address(0x1817))); + + +extern volatile __bit TMR2IE __attribute__((address(0x250B))); + + +extern volatile __bit TMR2IF __attribute__((address(0x258B))); + + +extern volatile __bit TMR2IP __attribute__((address(0x1B2B))); + + +extern volatile __bit TMR2MD __attribute__((address(0x30A))); + + +extern volatile __bit TMR2ON __attribute__((address(0x1927))); + + +extern volatile __bit TMR3 __attribute__((address(0x1803))); + + +extern volatile __bit TMR3GIE __attribute__((address(0x251D))); + + +extern volatile __bit TMR3GIF __attribute__((address(0x259D))); + + +extern volatile __bit TMR3GIP __attribute__((address(0x1B3D))); + + +extern volatile __bit TMR3H0 __attribute__((address(0x1948))); + + +extern volatile __bit TMR3H1 __attribute__((address(0x1949))); + + +extern volatile __bit TMR3H2 __attribute__((address(0x194A))); + + +extern volatile __bit TMR3H3 __attribute__((address(0x194B))); + + +extern volatile __bit TMR3H4 __attribute__((address(0x194C))); + + +extern volatile __bit TMR3H5 __attribute__((address(0x194D))); + + +extern volatile __bit TMR3H6 __attribute__((address(0x194E))); + + +extern volatile __bit TMR3H7 __attribute__((address(0x194F))); + + +extern volatile __bit TMR3IE __attribute__((address(0x251C))); + + +extern volatile __bit TMR3IF __attribute__((address(0x259C))); + + +extern volatile __bit TMR3IP __attribute__((address(0x1B3C))); + + +extern volatile __bit TMR3L0 __attribute__((address(0x1940))); + + +extern volatile __bit TMR3L1 __attribute__((address(0x1941))); + + +extern volatile __bit TMR3L2 __attribute__((address(0x1942))); + + +extern volatile __bit TMR3L3 __attribute__((address(0x1943))); + + +extern volatile __bit TMR3L4 __attribute__((address(0x1944))); + + +extern volatile __bit TMR3L5 __attribute__((address(0x1945))); + + +extern volatile __bit TMR3L6 __attribute__((address(0x1946))); + + +extern volatile __bit TMR3L7 __attribute__((address(0x1947))); + + +extern volatile __bit TMR3MD __attribute__((address(0x30B))); + + +extern volatile __bit TMR3ON __attribute__((address(0x1950))); + + +extern volatile __bit TMR4IE __attribute__((address(0x254B))); + + +extern volatile __bit TMR4IF __attribute__((address(0x25CB))); + + +extern volatile __bit TMR4IP __attribute__((address(0x1B6B))); + + +extern volatile __bit TMR4MD __attribute__((address(0x30C))); + + +extern volatile __bit TMR4ON __attribute__((address(0x1987))); + + +extern volatile __bit TMR5 __attribute__((address(0x1805))); + + +extern volatile __bit TMR5GIE __attribute__((address(0x2535))); + + +extern volatile __bit TMR5GIF __attribute__((address(0x25B5))); + + +extern volatile __bit TMR5GIP __attribute__((address(0x1B55))); + + +extern volatile __bit TMR5H0 __attribute__((address(0x19A8))); + + +extern volatile __bit TMR5H1 __attribute__((address(0x19A9))); + + +extern volatile __bit TMR5H2 __attribute__((address(0x19AA))); + + +extern volatile __bit TMR5H3 __attribute__((address(0x19AB))); + + +extern volatile __bit TMR5H4 __attribute__((address(0x19AC))); + + +extern volatile __bit TMR5H5 __attribute__((address(0x19AD))); + + +extern volatile __bit TMR5H6 __attribute__((address(0x19AE))); + + +extern volatile __bit TMR5H7 __attribute__((address(0x19AF))); + + +extern volatile __bit TMR5IE __attribute__((address(0x2534))); + + +extern volatile __bit TMR5IF __attribute__((address(0x25B4))); + + +extern volatile __bit TMR5IP __attribute__((address(0x1B54))); + + +extern volatile __bit TMR5L0 __attribute__((address(0x19A0))); + + +extern volatile __bit TMR5L1 __attribute__((address(0x19A1))); + + +extern volatile __bit TMR5L2 __attribute__((address(0x19A2))); + + +extern volatile __bit TMR5L3 __attribute__((address(0x19A3))); + + +extern volatile __bit TMR5L4 __attribute__((address(0x19A4))); + + +extern volatile __bit TMR5L5 __attribute__((address(0x19A5))); + + +extern volatile __bit TMR5L6 __attribute__((address(0x19A6))); + + +extern volatile __bit TMR5L7 __attribute__((address(0x19A7))); + + +extern volatile __bit TMR5MD __attribute__((address(0x30D))); + + +extern volatile __bit TMR5ON __attribute__((address(0x19B0))); + + +extern volatile __bit TMR6IE __attribute__((address(0x256B))); + + +extern volatile __bit TMR6IF __attribute__((address(0x25EB))); + + +extern volatile __bit TMR6IP __attribute__((address(0x1B8B))); + + +extern volatile __bit TMR6MD __attribute__((address(0x30E))); + + +extern volatile __bit TMR6ON __attribute__((address(0x19E7))); + + +extern volatile __bit TMR7 __attribute__((address(0x1807))); + + +extern volatile __bit TMR8 __attribute__((address(0x1808))); + + +extern volatile __bit TMR9 __attribute__((address(0x1809))); + + +extern volatile __bit TMRAOSEN __attribute__((address(0x1C46))); + + +extern volatile __bit TMRBOSEN __attribute__((address(0x1CA6))); + + +extern volatile __bit TOBY32 __attribute__((address(0x14E6))); + + +extern volatile __bit TOREC __attribute__((address(0x14E7))); + + +extern volatile __bit TOTIME0 __attribute__((address(0x14E0))); + + +extern volatile __bit TOTIME1 __attribute__((address(0x14E1))); + + +extern volatile __bit TOTIME2 __attribute__((address(0x14E2))); + + +extern volatile __bit TOTIME3 __attribute__((address(0x14E3))); + + +extern volatile __bit TOTIME4 __attribute__((address(0x14E4))); + + +extern volatile __bit TOTIME5 __attribute__((address(0x14E5))); + + +extern volatile __bit TRIGEN __attribute__((address(0x1B06))); + + +extern volatile __bit TRISA0 __attribute__((address(0x2630))); + + +extern volatile __bit TRISA1 __attribute__((address(0x2631))); + + +extern volatile __bit TRISA2 __attribute__((address(0x2632))); + + +extern volatile __bit TRISA3 __attribute__((address(0x2633))); + + +extern volatile __bit TRISA4 __attribute__((address(0x2634))); + + +extern volatile __bit TRISA5 __attribute__((address(0x2635))); + + +extern volatile __bit TRISA6 __attribute__((address(0x2636))); + + +extern volatile __bit TRISA7 __attribute__((address(0x2637))); + + +extern volatile __bit TRISB0 __attribute__((address(0x2638))); + + +extern volatile __bit TRISB1 __attribute__((address(0x2639))); + + +extern volatile __bit TRISB2 __attribute__((address(0x263A))); + + +extern volatile __bit TRISB3 __attribute__((address(0x263B))); + + +extern volatile __bit TRISB4 __attribute__((address(0x263C))); + + +extern volatile __bit TRISB5 __attribute__((address(0x263D))); + + +extern volatile __bit TRISB6 __attribute__((address(0x263E))); + + +extern volatile __bit TRISB7 __attribute__((address(0x263F))); + + +extern volatile __bit TRISC0 __attribute__((address(0x2640))); + + +extern volatile __bit TRISC1 __attribute__((address(0x2641))); + + +extern volatile __bit TRISC2 __attribute__((address(0x2642))); + + +extern volatile __bit TRISC3 __attribute__((address(0x2643))); + + +extern volatile __bit TRISC4 __attribute__((address(0x2644))); + + +extern volatile __bit TRISC5 __attribute__((address(0x2645))); + + +extern volatile __bit TRISC6 __attribute__((address(0x2646))); + + +extern volatile __bit TRISC7 __attribute__((address(0x2647))); + + +extern volatile __bit TRISE3 __attribute__((address(0x2653))); + + +extern volatile __bit TS __attribute__((address(0x1872))); + + +extern volatile __bit TSEG15 __attribute__((address(0x835))); + + +extern volatile __bit TSEG16 __attribute__((address(0x836))); + + +extern volatile __bit TSEG17 __attribute__((address(0x837))); + + +extern volatile __bit TSEG24 __attribute__((address(0x82C))); + + +extern volatile __bit TSEG25 __attribute__((address(0x82D))); + + +extern volatile __bit TSEG26 __attribute__((address(0x82E))); + + +extern volatile __bit TSEL0 __attribute__((address(0x1B08))); + + +extern volatile __bit TSEL1 __attribute__((address(0x1B09))); + + +extern volatile __bit TSEL2 __attribute__((address(0x1B0A))); + + +extern volatile __bit TSEL3 __attribute__((address(0x1B0B))); + + +extern volatile __bit TSEL4 __attribute__((address(0x1B0C))); + + +extern volatile __bit TSEN __attribute__((address(0x1EBD))); + + +extern volatile __bit TSEOF __attribute__((address(0x8B1))); + + +extern volatile __bit TSRES __attribute__((address(0x8B2))); + + +extern volatile __bit TSRNG __attribute__((address(0x1EBC))); + + +extern volatile __bit TU16ACAPT __attribute__((address(0x1C43))); + + +extern volatile __bit TU16ACIE __attribute__((address(0x1C38))); + + +extern volatile __bit TU16ACIF __attribute__((address(0x1C40))); + + +extern volatile __bit TU16ACLK0 __attribute__((address(0x1C78))); + + +extern volatile __bit TU16ACLK1 __attribute__((address(0x1C79))); + + +extern volatile __bit TU16ACLK2 __attribute__((address(0x1C7A))); + + +extern volatile __bit TU16ACLK3 __attribute__((address(0x1C7B))); + + +extern volatile __bit TU16ACLK4 __attribute__((address(0x1C7C))); + + +extern volatile __bit TU16ACLR __attribute__((address(0x1C45))); + + +extern volatile __bit TU16ACPOL __attribute__((address(0x1C3E))); + + +extern volatile __bit TU16ACR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ACRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ACRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ACRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ACRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ACRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ACRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ACRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ACRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ACRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ACRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ACRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ACRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ACRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ACRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ACRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ACSYNC __attribute__((address(0x1C4E))); + + +extern volatile __bit TU16AEPOL __attribute__((address(0x1C4F))); + + +extern volatile __bit TU16AERS0 __attribute__((address(0x1C80))); + + +extern volatile __bit TU16AERS1 __attribute__((address(0x1C81))); + + +extern volatile __bit TU16AERS2 __attribute__((address(0x1C82))); + + +extern volatile __bit TU16AERS3 __attribute__((address(0x1C83))); + + +extern volatile __bit TU16AERS4 __attribute__((address(0x1C84))); + + +extern volatile __bit TU16AERS5 __attribute__((address(0x1C85))); + + +extern volatile __bit TU16AIE __attribute__((address(0x24F4))); + + +extern volatile __bit TU16AIF __attribute__((address(0x2574))); + + +extern volatile __bit TU16AIP __attribute__((address(0x1B14))); + + +extern volatile __bit TU16ALIMIT __attribute__((address(0x1C44))); + + +extern volatile __bit TU16AMD __attribute__((address(0x310))); + + +extern volatile __bit TU16AOM __attribute__((address(0x1C3D))); + + +extern volatile __bit TU16AON __attribute__((address(0x1C3F))); + + +extern volatile __bit TU16AOPOL __attribute__((address(0x1C3C))); + + +extern volatile __bit TU16APR0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APR1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APR10 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APR11 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APR12 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APR13 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APR14 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APR15 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APR2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APR3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APR4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APR5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APR6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APR7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APR8 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APR9 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH0 __attribute__((address(0x1C70))); + + +extern volatile __bit TU16APRH1 __attribute__((address(0x1C71))); + + +extern volatile __bit TU16APRH2 __attribute__((address(0x1C72))); + + +extern volatile __bit TU16APRH3 __attribute__((address(0x1C73))); + + +extern volatile __bit TU16APRH4 __attribute__((address(0x1C74))); + + +extern volatile __bit TU16APRH5 __attribute__((address(0x1C75))); + + +extern volatile __bit TU16APRH6 __attribute__((address(0x1C76))); + + +extern volatile __bit TU16APRH7 __attribute__((address(0x1C77))); + + +extern volatile __bit TU16APRIE __attribute__((address(0x1C3A))); + + +extern volatile __bit TU16APRIF __attribute__((address(0x1C42))); + + +extern volatile __bit TU16APRL0 __attribute__((address(0x1C68))); + + +extern volatile __bit TU16APRL1 __attribute__((address(0x1C69))); + + +extern volatile __bit TU16APRL2 __attribute__((address(0x1C6A))); + + +extern volatile __bit TU16APRL3 __attribute__((address(0x1C6B))); + + +extern volatile __bit TU16APRL4 __attribute__((address(0x1C6C))); + + +extern volatile __bit TU16APRL5 __attribute__((address(0x1C6D))); + + +extern volatile __bit TU16APRL6 __attribute__((address(0x1C6E))); + + +extern volatile __bit TU16APRL7 __attribute__((address(0x1C6F))); + + +extern volatile __bit TU16APS0 __attribute__((address(0x1C50))); + + +extern volatile __bit TU16APS1 __attribute__((address(0x1C51))); + + +extern volatile __bit TU16APS2 __attribute__((address(0x1C52))); + + +extern volatile __bit TU16APS3 __attribute__((address(0x1C53))); + + +extern volatile __bit TU16APS4 __attribute__((address(0x1C54))); + + +extern volatile __bit TU16APS5 __attribute__((address(0x1C55))); + + +extern volatile __bit TU16APS6 __attribute__((address(0x1C56))); + + +extern volatile __bit TU16APS7 __attribute__((address(0x1C57))); + + +extern volatile __bit TU16ARDSEL __attribute__((address(0x1C3B))); + + +extern volatile __bit TU16ARESET0 __attribute__((address(0x1C4A))); + + +extern volatile __bit TU16ARESET1 __attribute__((address(0x1C4B))); + + +extern volatile __bit TU16ARUN __attribute__((address(0x1C47))); + + +extern volatile __bit TU16ASTART0 __attribute__((address(0x1C4C))); + + +extern volatile __bit TU16ASTART1 __attribute__((address(0x1C4D))); + + +extern volatile __bit TU16ASTOP0 __attribute__((address(0x1C48))); + + +extern volatile __bit TU16ASTOP1 __attribute__((address(0x1C49))); + + +extern volatile __bit TU16ATMR0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMR1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMR10 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMR11 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMR12 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMR13 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMR14 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMR15 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMR2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMR3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMR4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMR5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMR6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMR7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16ATMR8 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMR9 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH0 __attribute__((address(0x1C60))); + + +extern volatile __bit TU16ATMRH1 __attribute__((address(0x1C61))); + + +extern volatile __bit TU16ATMRH2 __attribute__((address(0x1C62))); + + +extern volatile __bit TU16ATMRH3 __attribute__((address(0x1C63))); + + +extern volatile __bit TU16ATMRH4 __attribute__((address(0x1C64))); + + +extern volatile __bit TU16ATMRH5 __attribute__((address(0x1C65))); + + +extern volatile __bit TU16ATMRH6 __attribute__((address(0x1C66))); + + +extern volatile __bit TU16ATMRH7 __attribute__((address(0x1C67))); + + +extern volatile __bit TU16ATMRL0 __attribute__((address(0x1C58))); + + +extern volatile __bit TU16ATMRL1 __attribute__((address(0x1C59))); + + +extern volatile __bit TU16ATMRL2 __attribute__((address(0x1C5A))); + + +extern volatile __bit TU16ATMRL3 __attribute__((address(0x1C5B))); + + +extern volatile __bit TU16ATMRL4 __attribute__((address(0x1C5C))); + + +extern volatile __bit TU16ATMRL5 __attribute__((address(0x1C5D))); + + +extern volatile __bit TU16ATMRL6 __attribute__((address(0x1C5E))); + + +extern volatile __bit TU16ATMRL7 __attribute__((address(0x1C5F))); + + +extern volatile __bit TU16AZIE __attribute__((address(0x1C39))); + + +extern volatile __bit TU16AZIF __attribute__((address(0x1C41))); + + +extern volatile __bit TU16BCAPT __attribute__((address(0x1CA3))); + + +extern volatile __bit TU16BCIE __attribute__((address(0x1C98))); + + +extern volatile __bit TU16BCIF __attribute__((address(0x1CA0))); + + +extern volatile __bit TU16BCLK0 __attribute__((address(0x1CD8))); + + +extern volatile __bit TU16BCLK1 __attribute__((address(0x1CD9))); + + +extern volatile __bit TU16BCLK2 __attribute__((address(0x1CDA))); + + +extern volatile __bit TU16BCLK3 __attribute__((address(0x1CDB))); + + +extern volatile __bit TU16BCLK4 __attribute__((address(0x1CDC))); + + +extern volatile __bit TU16BCLR __attribute__((address(0x1CA5))); + + +extern volatile __bit TU16BCPOL __attribute__((address(0x1C9E))); + + +extern volatile __bit TU16BCR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BCRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BCRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BCRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BCRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BCRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BCRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BCRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BCRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BCRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BCRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BCRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BCRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BCRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BCRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BCRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BCSYNC __attribute__((address(0x1CAE))); + + +extern volatile __bit TU16BEPOL __attribute__((address(0x1CAF))); + + +extern volatile __bit TU16BERS0 __attribute__((address(0x1CE0))); + + +extern volatile __bit TU16BERS1 __attribute__((address(0x1CE1))); + + +extern volatile __bit TU16BERS2 __attribute__((address(0x1CE2))); + + +extern volatile __bit TU16BERS3 __attribute__((address(0x1CE3))); + + +extern volatile __bit TU16BERS4 __attribute__((address(0x1CE4))); + + +extern volatile __bit TU16BERS5 __attribute__((address(0x1CE5))); + + +extern volatile __bit TU16BIE __attribute__((address(0x251B))); + + +extern volatile __bit TU16BIF __attribute__((address(0x259B))); + + +extern volatile __bit TU16BIP __attribute__((address(0x1B3B))); + + +extern volatile __bit TU16BLIMIT __attribute__((address(0x1CA4))); + + +extern volatile __bit TU16BMD __attribute__((address(0x311))); + + +extern volatile __bit TU16BOM __attribute__((address(0x1C9D))); + + +extern volatile __bit TU16BON __attribute__((address(0x1C9F))); + + +extern volatile __bit TU16BOPOL __attribute__((address(0x1C9C))); + + +extern volatile __bit TU16BPR0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPR1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPR10 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPR11 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPR12 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPR13 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPR14 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPR15 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPR2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPR3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPR4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPR5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPR6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPR7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPR8 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPR9 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH0 __attribute__((address(0x1CD0))); + + +extern volatile __bit TU16BPRH1 __attribute__((address(0x1CD1))); + + +extern volatile __bit TU16BPRH2 __attribute__((address(0x1CD2))); + + +extern volatile __bit TU16BPRH3 __attribute__((address(0x1CD3))); + + +extern volatile __bit TU16BPRH4 __attribute__((address(0x1CD4))); + + +extern volatile __bit TU16BPRH5 __attribute__((address(0x1CD5))); + + +extern volatile __bit TU16BPRH6 __attribute__((address(0x1CD6))); + + +extern volatile __bit TU16BPRH7 __attribute__((address(0x1CD7))); + + +extern volatile __bit TU16BPRIE __attribute__((address(0x1C9A))); + + +extern volatile __bit TU16BPRIF __attribute__((address(0x1CA2))); + + +extern volatile __bit TU16BPRL0 __attribute__((address(0x1CC8))); + + +extern volatile __bit TU16BPRL1 __attribute__((address(0x1CC9))); + + +extern volatile __bit TU16BPRL2 __attribute__((address(0x1CCA))); + + +extern volatile __bit TU16BPRL3 __attribute__((address(0x1CCB))); + + +extern volatile __bit TU16BPRL4 __attribute__((address(0x1CCC))); + + +extern volatile __bit TU16BPRL5 __attribute__((address(0x1CCD))); + + +extern volatile __bit TU16BPRL6 __attribute__((address(0x1CCE))); + + +extern volatile __bit TU16BPRL7 __attribute__((address(0x1CCF))); + + +extern volatile __bit TU16BPS0 __attribute__((address(0x1CB0))); + + +extern volatile __bit TU16BPS1 __attribute__((address(0x1CB1))); + + +extern volatile __bit TU16BPS2 __attribute__((address(0x1CB2))); + + +extern volatile __bit TU16BPS3 __attribute__((address(0x1CB3))); + + +extern volatile __bit TU16BPS4 __attribute__((address(0x1CB4))); + + +extern volatile __bit TU16BPS5 __attribute__((address(0x1CB5))); + + +extern volatile __bit TU16BPS6 __attribute__((address(0x1CB6))); + + +extern volatile __bit TU16BPS7 __attribute__((address(0x1CB7))); + + +extern volatile __bit TU16BRDSEL __attribute__((address(0x1C9B))); + + +extern volatile __bit TU16BRESET0 __attribute__((address(0x1CAA))); + + +extern volatile __bit TU16BRESET1 __attribute__((address(0x1CAB))); + + +extern volatile __bit TU16BRUN __attribute__((address(0x1CA7))); + + +extern volatile __bit TU16BSTART0 __attribute__((address(0x1CAC))); + + +extern volatile __bit TU16BSTART1 __attribute__((address(0x1CAD))); + + +extern volatile __bit TU16BSTOP0 __attribute__((address(0x1CA8))); + + +extern volatile __bit TU16BSTOP1 __attribute__((address(0x1CA9))); + + +extern volatile __bit TU16BTMR0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMR1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMR10 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMR11 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMR12 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMR13 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMR14 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMR15 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMR2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMR3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMR4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMR5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMR6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMR7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BTMR8 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMR9 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH0 __attribute__((address(0x1CC0))); + + +extern volatile __bit TU16BTMRH1 __attribute__((address(0x1CC1))); + + +extern volatile __bit TU16BTMRH2 __attribute__((address(0x1CC2))); + + +extern volatile __bit TU16BTMRH3 __attribute__((address(0x1CC3))); + + +extern volatile __bit TU16BTMRH4 __attribute__((address(0x1CC4))); + + +extern volatile __bit TU16BTMRH5 __attribute__((address(0x1CC5))); + + +extern volatile __bit TU16BTMRH6 __attribute__((address(0x1CC6))); + + +extern volatile __bit TU16BTMRH7 __attribute__((address(0x1CC7))); + + +extern volatile __bit TU16BTMRL0 __attribute__((address(0x1CB8))); + + +extern volatile __bit TU16BTMRL1 __attribute__((address(0x1CB9))); + + +extern volatile __bit TU16BTMRL2 __attribute__((address(0x1CBA))); + + +extern volatile __bit TU16BTMRL3 __attribute__((address(0x1CBB))); + + +extern volatile __bit TU16BTMRL4 __attribute__((address(0x1CBC))); + + +extern volatile __bit TU16BTMRL5 __attribute__((address(0x1CBD))); + + +extern volatile __bit TU16BTMRL6 __attribute__((address(0x1CBE))); + + +extern volatile __bit TU16BTMRL7 __attribute__((address(0x1CBF))); + + +extern volatile __bit TU16BZIE __attribute__((address(0x1C99))); + + +extern volatile __bit TU16BZIF __attribute__((address(0x1CA1))); + + +extern volatile __bit TU1MD __attribute__((address(0x310))); + + +extern volatile __bit TU2MD __attribute__((address(0x311))); + + +extern volatile __bit TUIN0PPS0 __attribute__((address(0x1258))); + + +extern volatile __bit TUIN0PPS1 __attribute__((address(0x1259))); + + +extern volatile __bit TUIN0PPS2 __attribute__((address(0x125A))); + + +extern volatile __bit TUIN0PPS3 __attribute__((address(0x125B))); + + +extern volatile __bit TUIN0PPS4 __attribute__((address(0x125C))); + + +extern volatile __bit TUIN0PPS5 __attribute__((address(0x125D))); + + +extern volatile __bit TUIN1PPS0 __attribute__((address(0x1260))); + + +extern volatile __bit TUIN1PPS1 __attribute__((address(0x1261))); + + +extern volatile __bit TUIN1PPS2 __attribute__((address(0x1262))); + + +extern volatile __bit TUIN1PPS3 __attribute__((address(0x1263))); + + +extern volatile __bit TUIN1PPS4 __attribute__((address(0x1264))); + + +extern volatile __bit TUIN1PPS5 __attribute__((address(0x1265))); + + +extern volatile __bit TUIN2PPS0 __attribute__((address(0x1268))); + + +extern volatile __bit TUIN2PPS1 __attribute__((address(0x1269))); + + +extern volatile __bit TUIN2PPS2 __attribute__((address(0x126A))); + + +extern volatile __bit TUIN2PPS3 __attribute__((address(0x126B))); + + +extern volatile __bit TUIN2PPS4 __attribute__((address(0x126C))); + + +extern volatile __bit TUIN3PPS0 __attribute__((address(0x1270))); + + +extern volatile __bit TUIN3PPS1 __attribute__((address(0x1271))); + + +extern volatile __bit TUIN3PPS2 __attribute__((address(0x1272))); + + +extern volatile __bit TUIN3PPS3 __attribute__((address(0x1273))); + + +extern volatile __bit TUIN3PPS4 __attribute__((address(0x1274))); + + +extern volatile __bit TUN0 __attribute__((address(0x580))); + + +extern volatile __bit TUN1 __attribute__((address(0x581))); + + +extern volatile __bit TUN2 __attribute__((address(0x582))); + + +extern volatile __bit TUN3 __attribute__((address(0x583))); + + +extern volatile __bit TUN4 __attribute__((address(0x584))); + + +extern volatile __bit TUN5 __attribute__((address(0x585))); + + +extern volatile __bit TXBO __attribute__((address(0x9B5))); + + +extern volatile __bit TXBOERR __attribute__((address(0x9F7))); + + +extern volatile __bit TXBP __attribute__((address(0x9B4))); + + +extern volatile __bit TXBWS0 __attribute__((address(0x81C))); + + +extern volatile __bit TXBWS1 __attribute__((address(0x81D))); + + +extern volatile __bit TXBWS2 __attribute__((address(0x81E))); + + +extern volatile __bit TXBWS3 __attribute__((address(0x81F))); + + +extern volatile __bit TXIE __attribute__((address(0x8F0))); + + +extern volatile __bit TXIF __attribute__((address(0x8E0))); + + +extern volatile __bit TXQCI0 __attribute__((address(0xAA8))); + + +extern volatile __bit TXQCI1 __attribute__((address(0xAA9))); + + +extern volatile __bit TXQCI2 __attribute__((address(0xAAA))); + + +extern volatile __bit TXQCI3 __attribute__((address(0xAAB))); + + +extern volatile __bit TXQCI4 __attribute__((address(0xAAC))); + + +extern volatile __bit TXQEIE __attribute__((address(0xA82))); + + +extern volatile __bit TXQEIF __attribute__((address(0xAA2))); + + +extern volatile __bit TXQEN __attribute__((address(0x814))); + + +extern volatile __bit TXQNIE __attribute__((address(0xA80))); + + +extern volatile __bit TXQNIF __attribute__((address(0xAA0))); + + +extern volatile __bit TXQUA0 __attribute__((address(0xAC0))); + + +extern volatile __bit TXQUA1 __attribute__((address(0xAC1))); + + +extern volatile __bit TXQUA10 __attribute__((address(0xACA))); + + +extern volatile __bit TXQUA11 __attribute__((address(0xACB))); + + +extern volatile __bit TXQUA12 __attribute__((address(0xACC))); + + +extern volatile __bit TXQUA13 __attribute__((address(0xACD))); + + +extern volatile __bit TXQUA14 __attribute__((address(0xACE))); + + +extern volatile __bit TXQUA15 __attribute__((address(0xACF))); + + +extern volatile __bit TXQUA16 __attribute__((address(0xAD0))); + + +extern volatile __bit TXQUA17 __attribute__((address(0xAD1))); + + +extern volatile __bit TXQUA18 __attribute__((address(0xAD2))); + + +extern volatile __bit TXQUA19 __attribute__((address(0xAD3))); + + +extern volatile __bit TXQUA2 __attribute__((address(0xAC2))); + + +extern volatile __bit TXQUA20 __attribute__((address(0xAD4))); + + +extern volatile __bit TXQUA21 __attribute__((address(0xAD5))); + + +extern volatile __bit TXQUA22 __attribute__((address(0xAD6))); + + +extern volatile __bit TXQUA23 __attribute__((address(0xAD7))); + + +extern volatile __bit TXQUA24 __attribute__((address(0xAD8))); + + +extern volatile __bit TXQUA25 __attribute__((address(0xAD9))); + + +extern volatile __bit TXQUA26 __attribute__((address(0xADA))); + + +extern volatile __bit TXQUA27 __attribute__((address(0xADB))); + + +extern volatile __bit TXQUA28 __attribute__((address(0xADC))); + + +extern volatile __bit TXQUA29 __attribute__((address(0xADD))); + + +extern volatile __bit TXQUA3 __attribute__((address(0xAC3))); + + +extern volatile __bit TXQUA30 __attribute__((address(0xADE))); + + +extern volatile __bit TXQUA31 __attribute__((address(0xADF))); + + +extern volatile __bit TXQUA4 __attribute__((address(0xAC4))); + + +extern volatile __bit TXQUA5 __attribute__((address(0xAC5))); + + +extern volatile __bit TXQUA6 __attribute__((address(0xAC6))); + + +extern volatile __bit TXQUA7 __attribute__((address(0xAC7))); + + +extern volatile __bit TXQUA8 __attribute__((address(0xAC8))); + + +extern volatile __bit TXQUA9 __attribute__((address(0xAC9))); + + +extern volatile __bit TXREQ0 __attribute__((address(0x980))); + + +extern volatile __bit TXREQ1 __attribute__((address(0x981))); + + +extern volatile __bit TXREQ10 __attribute__((address(0x98A))); + + +extern volatile __bit TXREQ11 __attribute__((address(0x98B))); + + +extern volatile __bit TXREQ12 __attribute__((address(0x98C))); + + +extern volatile __bit TXREQ13 __attribute__((address(0x98D))); + + +extern volatile __bit TXREQ14 __attribute__((address(0x98E))); + + +extern volatile __bit TXREQ15 __attribute__((address(0x98F))); + + +extern volatile __bit TXREQ16 __attribute__((address(0x990))); + + +extern volatile __bit TXREQ17 __attribute__((address(0x991))); + + +extern volatile __bit TXREQ18 __attribute__((address(0x992))); + + +extern volatile __bit TXREQ19 __attribute__((address(0x993))); + + +extern volatile __bit TXREQ2 __attribute__((address(0x982))); + + +extern volatile __bit TXREQ20 __attribute__((address(0x994))); + + +extern volatile __bit TXREQ21 __attribute__((address(0x995))); + + +extern volatile __bit TXREQ22 __attribute__((address(0x996))); + + +extern volatile __bit TXREQ23 __attribute__((address(0x997))); + + +extern volatile __bit TXREQ24 __attribute__((address(0x998))); + + +extern volatile __bit TXREQ25 __attribute__((address(0x999))); + + +extern volatile __bit TXREQ26 __attribute__((address(0x99A))); + + +extern volatile __bit TXREQ27 __attribute__((address(0x99B))); + + +extern volatile __bit TXREQ28 __attribute__((address(0x99C))); + + +extern volatile __bit TXREQ29 __attribute__((address(0x99D))); + + +extern volatile __bit TXREQ3 __attribute__((address(0x983))); + + +extern volatile __bit TXREQ30 __attribute__((address(0x99E))); + + +extern volatile __bit TXREQ31 __attribute__((address(0x99F))); + + +extern volatile __bit TXREQ4 __attribute__((address(0x984))); + + +extern volatile __bit TXREQ5 __attribute__((address(0x985))); + + +extern volatile __bit TXREQ6 __attribute__((address(0x986))); + + +extern volatile __bit TXREQ7 __attribute__((address(0x987))); + + +extern volatile __bit TXREQ8 __attribute__((address(0x988))); + + +extern volatile __bit TXREQ9 __attribute__((address(0x989))); + + +extern volatile __bit TXU __attribute__((address(0x14A9))); + + +extern volatile __bit TXWARN __attribute__((address(0x9B2))); + + +extern volatile __bit U1ABDEN __attribute__((address(0x155E))); + + +extern volatile __bit U1ABDIE __attribute__((address(0x158A))); + + +extern volatile __bit U1ABDIF __attribute__((address(0x158E))); + + +extern volatile __bit U1ABDOVE __attribute__((address(0x159D))); + + +extern volatile __bit U1ABDOVF __attribute__((address(0x1595))); + + +extern volatile __bit U1BRGS __attribute__((address(0x155F))); + + +extern volatile __bit U1BRKOVR __attribute__((address(0x1561))); + + +extern volatile __bit U1C0EN __attribute__((address(0x156B))); + + +extern volatile __bit U1CERIE __attribute__((address(0x159C))); + + +extern volatile __bit U1CERIF __attribute__((address(0x1594))); + + +extern volatile __bit U1CTSPPS0 __attribute__((address(0x1398))); + + +extern volatile __bit U1CTSPPS1 __attribute__((address(0x1399))); + + +extern volatile __bit U1CTSPPS2 __attribute__((address(0x139A))); + + +extern volatile __bit U1CTSPPS3 __attribute__((address(0x139B))); + + +extern volatile __bit U1CTSPPS4 __attribute__((address(0x139C))); + + +extern volatile __bit U1CTSPPS5 __attribute__((address(0x139D))); + + +extern volatile __bit U1EIE __attribute__((address(0x2512))); + + +extern volatile __bit U1EIF __attribute__((address(0x2592))); + + +extern volatile __bit U1EIP __attribute__((address(0x1B32))); + + +extern volatile __bit U1FERIE __attribute__((address(0x159B))); + + +extern volatile __bit U1FERIF __attribute__((address(0x1593))); + + +extern volatile __bit U1FLO0 __attribute__((address(0x1568))); + + +extern volatile __bit U1FLO1 __attribute__((address(0x1569))); + + +extern volatile __bit U1IE __attribute__((address(0x2513))); + + +extern volatile __bit U1IF __attribute__((address(0x2593))); + + +extern volatile __bit U1IP __attribute__((address(0x1B33))); + + +extern volatile __bit U1MD __attribute__((address(0x333))); + + +extern volatile __bit U1MODE0 __attribute__((address(0x1558))); + + +extern volatile __bit U1MODE1 __attribute__((address(0x1559))); + + +extern volatile __bit U1MODE2 __attribute__((address(0x155A))); + + +extern volatile __bit U1MODE3 __attribute__((address(0x155B))); + + +extern volatile __bit U1ON __attribute__((address(0x1567))); + + +extern volatile __bit U1PERIE __attribute__((address(0x159E))); + + +extern volatile __bit U1PERIF __attribute__((address(0x1596))); + + +extern volatile __bit U1RCIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RUNOVF __attribute__((address(0x156F))); + + +extern volatile __bit U1RXBE __attribute__((address(0x1581))); + + +extern volatile __bit U1RXBF __attribute__((address(0x1580))); + + +extern volatile __bit U1RXBIMD __attribute__((address(0x1563))); + + +extern volatile __bit U1RXBKIE __attribute__((address(0x159A))); + + +extern volatile __bit U1RXBKIF __attribute__((address(0x1592))); + + +extern volatile __bit U1RXEN __attribute__((address(0x155C))); + + +extern volatile __bit U1RXFOIE __attribute__((address(0x1599))); + + +extern volatile __bit U1RXFOIF __attribute__((address(0x1591))); + + +extern volatile __bit U1RXIDL __attribute__((address(0x1583))); + + +extern volatile __bit U1RXIE __attribute__((address(0x2510))); + + +extern volatile __bit U1RXIF __attribute__((address(0x2590))); + + +extern volatile __bit U1RXIP __attribute__((address(0x1B30))); + + +extern volatile __bit U1RXPOL __attribute__((address(0x156E))); + + +extern volatile __bit U1RXPPS0 __attribute__((address(0x1390))); + + +extern volatile __bit U1RXPPS1 __attribute__((address(0x1391))); + + +extern volatile __bit U1RXPPS2 __attribute__((address(0x1392))); + + +extern volatile __bit U1RXPPS3 __attribute__((address(0x1393))); + + +extern volatile __bit U1RXPPS4 __attribute__((address(0x1394))); + + +extern volatile __bit U1RXPPS5 __attribute__((address(0x1395))); + + +extern volatile __bit U1SENDB __attribute__((address(0x1560))); + + +extern volatile __bit U1STP0 __attribute__((address(0x156C))); + + +extern volatile __bit U1STP1 __attribute__((address(0x156D))); + + +extern volatile __bit U1STPMD __attribute__((address(0x1586))); + + +extern volatile __bit U1TXBE __attribute__((address(0x1585))); + + +extern volatile __bit U1TXBF __attribute__((address(0x1584))); + + +extern volatile __bit U1TXCIE __attribute__((address(0x1598))); + + +extern volatile __bit U1TXCIF __attribute__((address(0x1590))); + + +extern volatile __bit U1TXEN __attribute__((address(0x155D))); + + +extern volatile __bit U1TXIE __attribute__((address(0x2511))); + + +extern volatile __bit U1TXIF __attribute__((address(0x2591))); + + +extern volatile __bit U1TXIP __attribute__((address(0x1B31))); + + +extern volatile __bit U1TXMTIE __attribute__((address(0x159F))); + + +extern volatile __bit U1TXMTIF __attribute__((address(0x1597))); + + +extern volatile __bit U1TXPOL __attribute__((address(0x156A))); + + +extern volatile __bit U1TXWRE __attribute__((address(0x1587))); + + +extern volatile __bit U1WUE __attribute__((address(0x1564))); + + +extern volatile __bit U1WUIF __attribute__((address(0x158F))); + + +extern volatile __bit U1XON __attribute__((address(0x1582))); + + +extern volatile __bit U2ABDEN __attribute__((address(0x15F6))); + + +extern volatile __bit U2ABDIE __attribute__((address(0x1622))); + + +extern volatile __bit U2ABDIF __attribute__((address(0x1626))); + + +extern volatile __bit U2ABDOVE __attribute__((address(0x1635))); + + +extern volatile __bit U2ABDOVF __attribute__((address(0x162D))); + + +extern volatile __bit U2BRGS __attribute__((address(0x15F7))); + + +extern volatile __bit U2BRKOVR __attribute__((address(0x15F9))); + + +extern volatile __bit U2C0EN __attribute__((address(0x1603))); + + +extern volatile __bit U2CERIE __attribute__((address(0x1634))); + + +extern volatile __bit U2CERIF __attribute__((address(0x162C))); + + +extern volatile __bit U2CTSPPS0 __attribute__((address(0x13A8))); + + +extern volatile __bit U2CTSPPS1 __attribute__((address(0x13A9))); + + +extern volatile __bit U2CTSPPS2 __attribute__((address(0x13AA))); + + +extern volatile __bit U2CTSPPS3 __attribute__((address(0x13AB))); + + +extern volatile __bit U2CTSPPS4 __attribute__((address(0x13AC))); + + +extern volatile __bit U2EIE __attribute__((address(0x2532))); + + +extern volatile __bit U2EIF __attribute__((address(0x25B2))); + + +extern volatile __bit U2EIP __attribute__((address(0x1B52))); + + +extern volatile __bit U2FERIE __attribute__((address(0x1633))); + + +extern volatile __bit U2FERIF __attribute__((address(0x162B))); + + +extern volatile __bit U2FLO0 __attribute__((address(0x1600))); + + +extern volatile __bit U2FLO1 __attribute__((address(0x1601))); + + +extern volatile __bit U2IE __attribute__((address(0x2533))); + + +extern volatile __bit U2IF __attribute__((address(0x25B3))); + + +extern volatile __bit U2IP __attribute__((address(0x1B53))); + + +extern volatile __bit U2MD __attribute__((address(0x334))); + + +extern volatile __bit U2MODE0 __attribute__((address(0x15F0))); + + +extern volatile __bit U2MODE1 __attribute__((address(0x15F1))); + + +extern volatile __bit U2MODE2 __attribute__((address(0x15F2))); + + +extern volatile __bit U2MODE3 __attribute__((address(0x15F3))); + + +extern volatile __bit U2ON __attribute__((address(0x15FF))); + + +extern volatile __bit U2PERIE __attribute__((address(0x1636))); + + +extern volatile __bit U2PERIF __attribute__((address(0x162E))); + + +extern volatile __bit U2RCIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RUNOVF __attribute__((address(0x1607))); + + +extern volatile __bit U2RXBE __attribute__((address(0x1619))); + + +extern volatile __bit U2RXBF __attribute__((address(0x1618))); + + +extern volatile __bit U2RXBIMD __attribute__((address(0x15FB))); + + +extern volatile __bit U2RXBKIE __attribute__((address(0x1632))); + + +extern volatile __bit U2RXBKIF __attribute__((address(0x162A))); + + +extern volatile __bit U2RXEN __attribute__((address(0x15F4))); + + +extern volatile __bit U2RXFOIE __attribute__((address(0x1631))); + + +extern volatile __bit U2RXFOIF __attribute__((address(0x1629))); + + +extern volatile __bit U2RXIDL __attribute__((address(0x161B))); + + +extern volatile __bit U2RXIE __attribute__((address(0x2530))); + + +extern volatile __bit U2RXIF __attribute__((address(0x25B0))); + + +extern volatile __bit U2RXIP __attribute__((address(0x1B50))); + + +extern volatile __bit U2RXPOL __attribute__((address(0x1606))); + + +extern volatile __bit U2RXPPS0 __attribute__((address(0x13A0))); + + +extern volatile __bit U2RXPPS1 __attribute__((address(0x13A1))); + + +extern volatile __bit U2RXPPS2 __attribute__((address(0x13A2))); + + +extern volatile __bit U2RXPPS3 __attribute__((address(0x13A3))); + + +extern volatile __bit U2RXPPS4 __attribute__((address(0x13A4))); + + +extern volatile __bit U2SENDB __attribute__((address(0x15F8))); + + +extern volatile __bit U2STP0 __attribute__((address(0x1604))); + + +extern volatile __bit U2STP1 __attribute__((address(0x1605))); + + +extern volatile __bit U2STPMD __attribute__((address(0x161E))); + + +extern volatile __bit U2TXBE __attribute__((address(0x161D))); + + +extern volatile __bit U2TXBF __attribute__((address(0x161C))); + + +extern volatile __bit U2TXCIE __attribute__((address(0x1630))); + + +extern volatile __bit U2TXCIF __attribute__((address(0x1628))); + + +extern volatile __bit U2TXEN __attribute__((address(0x15F5))); + + +extern volatile __bit U2TXIE __attribute__((address(0x2531))); + + +extern volatile __bit U2TXIF __attribute__((address(0x25B1))); + + +extern volatile __bit U2TXIP __attribute__((address(0x1B51))); + + +extern volatile __bit U2TXMTIE __attribute__((address(0x1637))); + + +extern volatile __bit U2TXMTIF __attribute__((address(0x162F))); + + +extern volatile __bit U2TXPOL __attribute__((address(0x1602))); + + +extern volatile __bit U2TXWRE __attribute__((address(0x161F))); + + +extern volatile __bit U2WUE __attribute__((address(0x15FC))); + + +extern volatile __bit U2WUIF __attribute__((address(0x1627))); + + +extern volatile __bit U2XON __attribute__((address(0x161A))); + + +extern volatile __bit U3ABDEN __attribute__((address(0x168E))); + + +extern volatile __bit U3ABDIE __attribute__((address(0x16BA))); + + +extern volatile __bit U3ABDIF __attribute__((address(0x16BE))); + + +extern volatile __bit U3ABDOVE __attribute__((address(0x16CD))); + + +extern volatile __bit U3ABDOVF __attribute__((address(0x16C5))); + + +extern volatile __bit U3BRGS __attribute__((address(0x168F))); + + +extern volatile __bit U3BRKOVR __attribute__((address(0x1691))); + + +extern volatile __bit U3CERIE __attribute__((address(0x16CC))); + + +extern volatile __bit U3CERIF __attribute__((address(0x16C4))); + + +extern volatile __bit U3CTSPPS0 __attribute__((address(0x13B8))); + + +extern volatile __bit U3CTSPPS1 __attribute__((address(0x13B9))); + + +extern volatile __bit U3CTSPPS2 __attribute__((address(0x13BA))); + + +extern volatile __bit U3CTSPPS3 __attribute__((address(0x13BB))); + + +extern volatile __bit U3CTSPPS4 __attribute__((address(0x13BC))); + + +extern volatile __bit U3CTSPPS5 __attribute__((address(0x13BD))); + + +extern volatile __bit U3EIE __attribute__((address(0x253A))); + + +extern volatile __bit U3EIF __attribute__((address(0x25BA))); + + +extern volatile __bit U3EIP __attribute__((address(0x1B5A))); + + +extern volatile __bit U3FERIE __attribute__((address(0x16CB))); + + +extern volatile __bit U3FERIF __attribute__((address(0x16C3))); + + +extern volatile __bit U3FLO0 __attribute__((address(0x1698))); + + +extern volatile __bit U3FLO1 __attribute__((address(0x1699))); + + +extern volatile __bit U3IE __attribute__((address(0x253B))); + + +extern volatile __bit U3IF __attribute__((address(0x25BB))); + + +extern volatile __bit U3IP __attribute__((address(0x1B5B))); + + +extern volatile __bit U3MD __attribute__((address(0x335))); + + +extern volatile __bit U3MODE0 __attribute__((address(0x1688))); + + +extern volatile __bit U3MODE1 __attribute__((address(0x1689))); + + +extern volatile __bit U3MODE2 __attribute__((address(0x168A))); + + +extern volatile __bit U3ON __attribute__((address(0x1697))); + + +extern volatile __bit U3PERIE __attribute__((address(0x16CE))); + + +extern volatile __bit U3PERIF __attribute__((address(0x16C6))); + + +extern volatile __bit U3RCIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RUNOVF __attribute__((address(0x169F))); + + +extern volatile __bit U3RXBE __attribute__((address(0x16B1))); + + +extern volatile __bit U3RXBF __attribute__((address(0x16B0))); + + +extern volatile __bit U3RXBIMD __attribute__((address(0x1693))); + + +extern volatile __bit U3RXBKIE __attribute__((address(0x16CA))); + + +extern volatile __bit U3RXBKIF __attribute__((address(0x16C2))); + + +extern volatile __bit U3RXEN __attribute__((address(0x168C))); + + +extern volatile __bit U3RXFOIE __attribute__((address(0x16C9))); + + +extern volatile __bit U3RXFOIF __attribute__((address(0x16C1))); + + +extern volatile __bit U3RXIDL __attribute__((address(0x16B3))); + + +extern volatile __bit U3RXIE __attribute__((address(0x2538))); + + +extern volatile __bit U3RXIF __attribute__((address(0x25B8))); + + +extern volatile __bit U3RXIP __attribute__((address(0x1B58))); + + +extern volatile __bit U3RXPOL __attribute__((address(0x169E))); + + +extern volatile __bit U3RXPPS0 __attribute__((address(0x13B0))); + + +extern volatile __bit U3RXPPS1 __attribute__((address(0x13B1))); + + +extern volatile __bit U3RXPPS2 __attribute__((address(0x13B2))); + + +extern volatile __bit U3RXPPS3 __attribute__((address(0x13B3))); + + +extern volatile __bit U3RXPPS4 __attribute__((address(0x13B4))); + + +extern volatile __bit U3RXPPS5 __attribute__((address(0x13B5))); + + +extern volatile __bit U3SENDB __attribute__((address(0x1690))); + + +extern volatile __bit U3STP0 __attribute__((address(0x169C))); + + +extern volatile __bit U3STP1 __attribute__((address(0x169D))); + + +extern volatile __bit U3STPMD __attribute__((address(0x16B6))); + + +extern volatile __bit U3TXBE __attribute__((address(0x16B5))); + + +extern volatile __bit U3TXBF __attribute__((address(0x16B4))); + + +extern volatile __bit U3TXCIE __attribute__((address(0x16C8))); + + +extern volatile __bit U3TXCIF __attribute__((address(0x16C0))); + + +extern volatile __bit U3TXEN __attribute__((address(0x168D))); + + +extern volatile __bit U3TXIE __attribute__((address(0x2539))); + + +extern volatile __bit U3TXIF __attribute__((address(0x25B9))); + + +extern volatile __bit U3TXIP __attribute__((address(0x1B59))); + + +extern volatile __bit U3TXMTIE __attribute__((address(0x16CF))); + + +extern volatile __bit U3TXMTIF __attribute__((address(0x16C7))); + + +extern volatile __bit U3TXPOL __attribute__((address(0x169A))); + + +extern volatile __bit U3TXWRE __attribute__((address(0x16B7))); + + +extern volatile __bit U3WUE __attribute__((address(0x1694))); + + +extern volatile __bit U3WUIF __attribute__((address(0x16BF))); + + +extern volatile __bit U3XON __attribute__((address(0x16B2))); + + +extern volatile __bit U4ABDEN __attribute__((address(0x1726))); + + +extern volatile __bit U4ABDIE __attribute__((address(0x1752))); + + +extern volatile __bit U4ABDIF __attribute__((address(0x1756))); + + +extern volatile __bit U4ABDOVE __attribute__((address(0x1765))); + + +extern volatile __bit U4ABDOVF __attribute__((address(0x175D))); + + +extern volatile __bit U4BRGS __attribute__((address(0x1727))); + + +extern volatile __bit U4BRKOVR __attribute__((address(0x1729))); + + +extern volatile __bit U4CERIE __attribute__((address(0x1764))); + + +extern volatile __bit U4CERIF __attribute__((address(0x175C))); + + +extern volatile __bit U4CTSPPS0 __attribute__((address(0x13C8))); + + +extern volatile __bit U4CTSPPS1 __attribute__((address(0x13C9))); + + +extern volatile __bit U4CTSPPS2 __attribute__((address(0x13CA))); + + +extern volatile __bit U4CTSPPS3 __attribute__((address(0x13CB))); + + +extern volatile __bit U4CTSPPS4 __attribute__((address(0x13CC))); + + +extern volatile __bit U4EIE __attribute__((address(0x2552))); + + +extern volatile __bit U4EIF __attribute__((address(0x25D2))); + + +extern volatile __bit U4EIP __attribute__((address(0x1B72))); + + +extern volatile __bit U4FERIE __attribute__((address(0x1763))); + + +extern volatile __bit U4FERIF __attribute__((address(0x175B))); + + +extern volatile __bit U4FLO0 __attribute__((address(0x1730))); + + +extern volatile __bit U4FLO1 __attribute__((address(0x1731))); + + +extern volatile __bit U4IE __attribute__((address(0x2553))); + + +extern volatile __bit U4IF __attribute__((address(0x25D3))); + + +extern volatile __bit U4IP __attribute__((address(0x1B73))); + + +extern volatile __bit U4MD __attribute__((address(0x336))); + + +extern volatile __bit U4MODE0 __attribute__((address(0x1720))); + + +extern volatile __bit U4MODE1 __attribute__((address(0x1721))); + + +extern volatile __bit U4MODE2 __attribute__((address(0x1722))); + + +extern volatile __bit U4ON __attribute__((address(0x172F))); + + +extern volatile __bit U4PERIE __attribute__((address(0x1766))); + + +extern volatile __bit U4PERIF __attribute__((address(0x175E))); + + +extern volatile __bit U4RCIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RUNOVF __attribute__((address(0x1737))); + + +extern volatile __bit U4RXBE __attribute__((address(0x1749))); + + +extern volatile __bit U4RXBF __attribute__((address(0x1748))); + + +extern volatile __bit U4RXBIMD __attribute__((address(0x172B))); + + +extern volatile __bit U4RXBKIE __attribute__((address(0x1762))); + + +extern volatile __bit U4RXBKIF __attribute__((address(0x175A))); + + +extern volatile __bit U4RXEN __attribute__((address(0x1724))); + + +extern volatile __bit U4RXFOIE __attribute__((address(0x1761))); + + +extern volatile __bit U4RXFOIF __attribute__((address(0x1759))); + + +extern volatile __bit U4RXIDL __attribute__((address(0x174B))); + + +extern volatile __bit U4RXIE __attribute__((address(0x2550))); + + +extern volatile __bit U4RXIF __attribute__((address(0x25D0))); + + +extern volatile __bit U4RXIP __attribute__((address(0x1B70))); + + +extern volatile __bit U4RXPOL __attribute__((address(0x1736))); + + +extern volatile __bit U4RXPPS0 __attribute__((address(0x13C0))); + + +extern volatile __bit U4RXPPS1 __attribute__((address(0x13C1))); + + +extern volatile __bit U4RXPPS2 __attribute__((address(0x13C2))); + + +extern volatile __bit U4RXPPS3 __attribute__((address(0x13C3))); + + +extern volatile __bit U4RXPPS4 __attribute__((address(0x13C4))); + + +extern volatile __bit U4SENDB __attribute__((address(0x1728))); + + +extern volatile __bit U4STP0 __attribute__((address(0x1734))); + + +extern volatile __bit U4STP1 __attribute__((address(0x1735))); + + +extern volatile __bit U4STPMD __attribute__((address(0x174E))); + + +extern volatile __bit U4TXBE __attribute__((address(0x174D))); + + +extern volatile __bit U4TXBF __attribute__((address(0x174C))); + + +extern volatile __bit U4TXCIE __attribute__((address(0x1760))); + + +extern volatile __bit U4TXCIF __attribute__((address(0x1758))); + + +extern volatile __bit U4TXEN __attribute__((address(0x1725))); + + +extern volatile __bit U4TXIE __attribute__((address(0x2551))); + + +extern volatile __bit U4TXIF __attribute__((address(0x25D1))); + + +extern volatile __bit U4TXIP __attribute__((address(0x1B71))); + + +extern volatile __bit U4TXMTIE __attribute__((address(0x1767))); + + +extern volatile __bit U4TXMTIF __attribute__((address(0x175F))); + + +extern volatile __bit U4TXPOL __attribute__((address(0x1732))); + + +extern volatile __bit U4TXWRE __attribute__((address(0x174F))); + + +extern volatile __bit U4WUE __attribute__((address(0x172C))); + + +extern volatile __bit U4WUIF __attribute__((address(0x1757))); + + +extern volatile __bit U4XON __attribute__((address(0x174A))); + + +extern volatile __bit U5ABDEN __attribute__((address(0x17BE))); + + +extern volatile __bit U5ABDIE __attribute__((address(0x17EA))); + + +extern volatile __bit U5ABDIF __attribute__((address(0x17EE))); + + +extern volatile __bit U5ABDOVE __attribute__((address(0x17FD))); + + +extern volatile __bit U5ABDOVF __attribute__((address(0x17F5))); + + +extern volatile __bit U5BRGS __attribute__((address(0x17BF))); + + +extern volatile __bit U5BRKOVR __attribute__((address(0x17C1))); + + +extern volatile __bit U5CERIE __attribute__((address(0x17FC))); + + +extern volatile __bit U5CERIF __attribute__((address(0x17F4))); + + +extern volatile __bit U5CTSPPS0 __attribute__((address(0x13D8))); + + +extern volatile __bit U5CTSPPS1 __attribute__((address(0x13D9))); + + +extern volatile __bit U5CTSPPS2 __attribute__((address(0x13DA))); + + +extern volatile __bit U5CTSPPS3 __attribute__((address(0x13DB))); + + +extern volatile __bit U5CTSPPS4 __attribute__((address(0x13DC))); + + +extern volatile __bit U5CTSPPS5 __attribute__((address(0x13DD))); + + +extern volatile __bit U5EIE __attribute__((address(0x255A))); + + +extern volatile __bit U5EIF __attribute__((address(0x25DA))); + + +extern volatile __bit U5EIP __attribute__((address(0x1B7A))); + + +extern volatile __bit U5FERIE __attribute__((address(0x17FB))); + + +extern volatile __bit U5FERIF __attribute__((address(0x17F3))); + + +extern volatile __bit U5FLO0 __attribute__((address(0x17C8))); + + +extern volatile __bit U5FLO1 __attribute__((address(0x17C9))); + + +extern volatile __bit U5IE __attribute__((address(0x255B))); + + +extern volatile __bit U5IF __attribute__((address(0x25DB))); + + +extern volatile __bit U5IP __attribute__((address(0x1B7B))); + + +extern volatile __bit U5MD __attribute__((address(0x337))); + + +extern volatile __bit U5MODE0 __attribute__((address(0x17B8))); + + +extern volatile __bit U5MODE1 __attribute__((address(0x17B9))); + + +extern volatile __bit U5MODE2 __attribute__((address(0x17BA))); + + +extern volatile __bit U5ON __attribute__((address(0x17C7))); + + +extern volatile __bit U5PERIE __attribute__((address(0x17FE))); + + +extern volatile __bit U5PERIF __attribute__((address(0x17F6))); + + +extern volatile __bit U5RCIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RUNOVF __attribute__((address(0x17CF))); + + +extern volatile __bit U5RXBE __attribute__((address(0x17E1))); + + +extern volatile __bit U5RXBF __attribute__((address(0x17E0))); + + +extern volatile __bit U5RXBIMD __attribute__((address(0x17C3))); + + +extern volatile __bit U5RXBKIE __attribute__((address(0x17FA))); + + +extern volatile __bit U5RXBKIF __attribute__((address(0x17F2))); + + +extern volatile __bit U5RXEN __attribute__((address(0x17BC))); + + +extern volatile __bit U5RXFOIE __attribute__((address(0x17F9))); + + +extern volatile __bit U5RXFOIF __attribute__((address(0x17F1))); + + +extern volatile __bit U5RXIDL __attribute__((address(0x17E3))); + + +extern volatile __bit U5RXIE __attribute__((address(0x2558))); + + +extern volatile __bit U5RXIF __attribute__((address(0x25D8))); + + +extern volatile __bit U5RXIP __attribute__((address(0x1B78))); + + +extern volatile __bit U5RXPOL __attribute__((address(0x17CE))); + + +extern volatile __bit U5RXPPS0 __attribute__((address(0x13D0))); + + +extern volatile __bit U5RXPPS1 __attribute__((address(0x13D1))); + + +extern volatile __bit U5RXPPS2 __attribute__((address(0x13D2))); + + +extern volatile __bit U5RXPPS3 __attribute__((address(0x13D3))); + + +extern volatile __bit U5RXPPS4 __attribute__((address(0x13D4))); + + +extern volatile __bit U5RXPPS5 __attribute__((address(0x13D5))); + + +extern volatile __bit U5SENDB __attribute__((address(0x17C0))); + + +extern volatile __bit U5STP0 __attribute__((address(0x17CC))); + + +extern volatile __bit U5STP1 __attribute__((address(0x17CD))); + + +extern volatile __bit U5STPMD __attribute__((address(0x17E6))); + + +extern volatile __bit U5TXBE __attribute__((address(0x17E5))); + + +extern volatile __bit U5TXBF __attribute__((address(0x17E4))); + + +extern volatile __bit U5TXCIE __attribute__((address(0x17F8))); + + +extern volatile __bit U5TXCIF __attribute__((address(0x17F0))); + + +extern volatile __bit U5TXEN __attribute__((address(0x17BD))); + + +extern volatile __bit U5TXIE __attribute__((address(0x2559))); + + +extern volatile __bit U5TXIF __attribute__((address(0x25D9))); + + +extern volatile __bit U5TXIP __attribute__((address(0x1B79))); + + +extern volatile __bit U5TXMTIE __attribute__((address(0x17FF))); + + +extern volatile __bit U5TXMTIF __attribute__((address(0x17F7))); + + +extern volatile __bit U5TXPOL __attribute__((address(0x17CA))); + + +extern volatile __bit U5TXWRE __attribute__((address(0x17E7))); + + +extern volatile __bit U5WUE __attribute__((address(0x17C4))); + + +extern volatile __bit U5WUIF __attribute__((address(0x17EF))); + + +extern volatile __bit U5XON __attribute__((address(0x17E2))); + + +extern volatile __bit UTH0 __attribute__((address(0x1ED8))); + + +extern volatile __bit UTH1 __attribute__((address(0x1ED9))); + + +extern volatile __bit UTH10 __attribute__((address(0x1EE2))); + + +extern volatile __bit UTH11 __attribute__((address(0x1EE3))); + + +extern volatile __bit UTH12 __attribute__((address(0x1EE4))); + + +extern volatile __bit UTH13 __attribute__((address(0x1EE5))); + + +extern volatile __bit UTH14 __attribute__((address(0x1EE6))); + + +extern volatile __bit UTH15 __attribute__((address(0x1EE7))); + + +extern volatile __bit UTH2 __attribute__((address(0x1EDA))); + + +extern volatile __bit UTH3 __attribute__((address(0x1EDB))); + + +extern volatile __bit UTH4 __attribute__((address(0x1EDC))); + + +extern volatile __bit UTH5 __attribute__((address(0x1EDD))); + + +extern volatile __bit UTH6 __attribute__((address(0x1EDE))); + + +extern volatile __bit UTH7 __attribute__((address(0x1EDF))); + + +extern volatile __bit UTH8 __attribute__((address(0x1EE0))); + + +extern volatile __bit UTH9 __attribute__((address(0x1EE1))); + + +extern volatile __bit UTHR __attribute__((address(0x1FBE))); + + +extern volatile __bit VREGPM0 __attribute__((address(0x240))); + + +extern volatile __bit VREGPM1 __attribute__((address(0x241))); + + +extern volatile __bit WAKFIL __attribute__((address(0x808))); + + +extern volatile __bit WAKIE __attribute__((address(0x8FE))); + + +extern volatile __bit WAKIF __attribute__((address(0x8EE))); + + +extern volatile __bit WDTCS0 __attribute__((address(0x3CC))); + + +extern volatile __bit WDTCS1 __attribute__((address(0x3CD))); + + +extern volatile __bit WDTCS2 __attribute__((address(0x3CE))); + + +extern volatile __bit WDTPS0 __attribute__((address(0x3C1))); + + +extern volatile __bit WDTPS1 __attribute__((address(0x3C2))); + + +extern volatile __bit WDTPS2 __attribute__((address(0x3C3))); + + +extern volatile __bit WDTPS3 __attribute__((address(0x3C4))); + + +extern volatile __bit WDTPS4 __attribute__((address(0x3C5))); + + +extern volatile __bit WDTPSCNT0 __attribute__((address(0x3D0))); + + +extern volatile __bit WDTPSCNT1 __attribute__((address(0x3D1))); + + +extern volatile __bit WDTPSCNT10 __attribute__((address(0x3DA))); + + +extern volatile __bit WDTPSCNT11 __attribute__((address(0x3DB))); + + +extern volatile __bit WDTPSCNT12 __attribute__((address(0x3DC))); + + +extern volatile __bit WDTPSCNT13 __attribute__((address(0x3DD))); + + +extern volatile __bit WDTPSCNT14 __attribute__((address(0x3DE))); + + +extern volatile __bit WDTPSCNT15 __attribute__((address(0x3DF))); + + +extern volatile __bit WDTPSCNT16 __attribute__((address(0x3E0))); + + +extern volatile __bit WDTPSCNT17 __attribute__((address(0x3E1))); + + +extern volatile __bit WDTPSCNT2 __attribute__((address(0x3D2))); + + +extern volatile __bit WDTPSCNT3 __attribute__((address(0x3D3))); + + +extern volatile __bit WDTPSCNT4 __attribute__((address(0x3D4))); + + +extern volatile __bit WDTPSCNT5 __attribute__((address(0x3D5))); + + +extern volatile __bit WDTPSCNT6 __attribute__((address(0x3D6))); + + +extern volatile __bit WDTPSCNT7 __attribute__((address(0x3D7))); + + +extern volatile __bit WDTPSCNT8 __attribute__((address(0x3D8))); + + +extern volatile __bit WDTPSCNT9 __attribute__((address(0x3D9))); + + +extern volatile __bit WDTSEN __attribute__((address(0x3C0))); + + +extern volatile __bit WDTSTATE __attribute__((address(0x3E2))); + + +extern volatile __bit WDTTMR0 __attribute__((address(0x3E3))); + + +extern volatile __bit WDTTMR1 __attribute__((address(0x3E4))); + + +extern volatile __bit WDTTMR2 __attribute__((address(0x3E5))); + + +extern volatile __bit WDTTMR3 __attribute__((address(0x3E6))); + + +extern volatile __bit WDTTMR4 __attribute__((address(0x3E7))); + + +extern volatile __bit WDTWINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WDTWINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WDTWINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WDTWV __attribute__((address(0x2785))); + + +extern volatile __bit WFT0 __attribute__((address(0x809))); + + +extern volatile __bit WFT1 __attribute__((address(0x80A))); + + +extern volatile __bit WINDOW0 __attribute__((address(0x3C8))); + + +extern volatile __bit WINDOW1 __attribute__((address(0x3C9))); + + +extern volatile __bit WINDOW2 __attribute__((address(0x3CA))); + + +extern volatile __bit WPOL __attribute__((address(0x1864))); + + +extern volatile __bit WPUA0 __attribute__((address(0x2008))); + + +extern volatile __bit WPUA1 __attribute__((address(0x2009))); + + +extern volatile __bit WPUA2 __attribute__((address(0x200A))); + + +extern volatile __bit WPUA3 __attribute__((address(0x200B))); + + +extern volatile __bit WPUA4 __attribute__((address(0x200C))); + + +extern volatile __bit WPUA5 __attribute__((address(0x200D))); + + +extern volatile __bit WPUA6 __attribute__((address(0x200E))); + + +extern volatile __bit WPUA7 __attribute__((address(0x200F))); + + +extern volatile __bit WPUB0 __attribute__((address(0x2048))); + + +extern volatile __bit WPUB1 __attribute__((address(0x2049))); + + +extern volatile __bit WPUB2 __attribute__((address(0x204A))); + + +extern volatile __bit WPUB3 __attribute__((address(0x204B))); + + +extern volatile __bit WPUB4 __attribute__((address(0x204C))); + + +extern volatile __bit WPUB5 __attribute__((address(0x204D))); + + +extern volatile __bit WPUB6 __attribute__((address(0x204E))); + + +extern volatile __bit WPUB7 __attribute__((address(0x204F))); + + +extern volatile __bit WPUC0 __attribute__((address(0x2088))); + + +extern volatile __bit WPUC1 __attribute__((address(0x2089))); + + +extern volatile __bit WPUC2 __attribute__((address(0x208A))); + + +extern volatile __bit WPUC3 __attribute__((address(0x208B))); + + +extern volatile __bit WPUC4 __attribute__((address(0x208C))); + + +extern volatile __bit WPUC5 __attribute__((address(0x208D))); + + +extern volatile __bit WPUC6 __attribute__((address(0x208E))); + + +extern volatile __bit WPUC7 __attribute__((address(0x208F))); + + +extern volatile __bit WPUE3 __attribute__((address(0x210B))); + + +extern volatile __bit WR1IE __attribute__((address(0x14DC))); + + +extern volatile __bit WR1IF __attribute__((address(0x14D4))); + + +extern volatile __bit WRERR __attribute__((address(0x20F))); + + +extern volatile __bit WRIE __attribute__((address(0x14DC))); + + +extern volatile __bit WRIF __attribute__((address(0x14D4))); + + +extern volatile __bit WS __attribute__((address(0x1871))); + + +extern volatile __bit WSEL0 __attribute__((address(0x1888))); + + +extern volatile __bit WSEL1 __attribute__((address(0x1889))); + + +extern volatile __bit WSEL2 __attribute__((address(0x188A))); + + +extern volatile __bit WSEL3 __attribute__((address(0x188B))); + + +extern volatile __bit WSEL4 __attribute__((address(0x188C))); + + +extern volatile __bit XIP __attribute__((address(0x7E0))); + + +extern volatile __bit XOR0 __attribute__((address(0x1A98))); + + +extern volatile __bit XOR1 __attribute__((address(0x1A99))); + + +extern volatile __bit XOR10 __attribute__((address(0x1AA2))); + + +extern volatile __bit XOR11 __attribute__((address(0x1AA3))); + + +extern volatile __bit XOR12 __attribute__((address(0x1AA4))); + + +extern volatile __bit XOR13 __attribute__((address(0x1AA5))); + + +extern volatile __bit XOR14 __attribute__((address(0x1AA6))); + + +extern volatile __bit XOR15 __attribute__((address(0x1AA7))); + + +extern volatile __bit XOR16 __attribute__((address(0x1AA8))); + + +extern volatile __bit XOR17 __attribute__((address(0x1AA9))); + + +extern volatile __bit XOR18 __attribute__((address(0x1AAA))); + + +extern volatile __bit XOR19 __attribute__((address(0x1AAB))); + + +extern volatile __bit XOR2 __attribute__((address(0x1A9A))); + + +extern volatile __bit XOR20 __attribute__((address(0x1AAC))); + + +extern volatile __bit XOR21 __attribute__((address(0x1AAD))); + + +extern volatile __bit XOR22 __attribute__((address(0x1AAE))); + + +extern volatile __bit XOR23 __attribute__((address(0x1AAF))); + + +extern volatile __bit XOR24 __attribute__((address(0x1AB0))); + + +extern volatile __bit XOR25 __attribute__((address(0x1AB1))); + + +extern volatile __bit XOR26 __attribute__((address(0x1AB2))); + + +extern volatile __bit XOR27 __attribute__((address(0x1AB3))); + + +extern volatile __bit XOR28 __attribute__((address(0x1AB4))); + + +extern volatile __bit XOR29 __attribute__((address(0x1AB5))); + + +extern volatile __bit XOR3 __attribute__((address(0x1A9B))); + + +extern volatile __bit XOR30 __attribute__((address(0x1AB6))); + + +extern volatile __bit XOR31 __attribute__((address(0x1AB7))); + + +extern volatile __bit XOR4 __attribute__((address(0x1A9C))); + + +extern volatile __bit XOR5 __attribute__((address(0x1A9D))); + + +extern volatile __bit XOR6 __attribute__((address(0x1A9E))); + + +extern volatile __bit XOR7 __attribute__((address(0x1A9F))); + + +extern volatile __bit XOR8 __attribute__((address(0x1AA0))); + + +extern volatile __bit XOR9 __attribute__((address(0x1AA1))); + + +extern volatile __bit ZCDIE __attribute__((address(0x24F9))); + + +extern volatile __bit ZCDIF __attribute__((address(0x2579))); + + +extern volatile __bit ZCDINTN __attribute__((address(0x260))); + + +extern volatile __bit ZCDINTP __attribute__((address(0x261))); + + +extern volatile __bit ZCDIP __attribute__((address(0x1B19))); + + +extern volatile __bit ZCDMD __attribute__((address(0x318))); + + +extern volatile __bit ZCDOUT __attribute__((address(0x265))); + + +extern volatile __bit ZCDPOL __attribute__((address(0x264))); + + +extern volatile __bit ZCDSEN __attribute__((address(0x267))); + + +extern volatile __bit nBOR __attribute__((address(0x2780))); + + +extern volatile __bit nDONE __attribute__((address(0x200))); + + +extern volatile __bit nMEMV __attribute__((address(0x2789))); + + +extern volatile __bit nPOR __attribute__((address(0x2781))); + + +extern volatile __bit nRI __attribute__((address(0x2782))); + + +extern volatile __bit nRMCLR __attribute__((address(0x2783))); + + +extern volatile __bit nRWDT __attribute__((address(0x2784))); + + +extern volatile __bit nWDTWV __attribute__((address(0x2785))); +# 131 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18_chip_select.h" 2 3 +# 9 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 19 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "flash_write" " routine is no longer supported. Please use the MPLAB X MCC."))) void flash_write(const unsigned char *, unsigned int, __far unsigned char *); +__attribute__((__unsupported__("The " "EraseFlash" " routine is no longer supported. Please use the MPLAB X MCC."))) void EraseFlash(unsigned long startaddr, unsigned long endaddr); + + + + + + + +# 1 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\errata.h" 1 3 +# 28 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 2 3 +# 156 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The " "Read_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) unsigned char Read_b_eep(unsigned int badd); +__attribute__((__unsupported__("The " "Busy_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Busy_eep(void); +__attribute__((__unsupported__("The " "Write_b_eep" " routine is no longer supported. Please use the MPLAB X MCC."))) void Write_b_eep(unsigned int badd, unsigned char bdat); +# 176 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\pic18.h" 3 +__attribute__((__unsupported__("The READTIMER" "0" "() macro is not available with the current device."))) unsigned short __readtimer0(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "1" "() macro is not available with the current device."))) unsigned short __readtimer1(void); + + + + + +__attribute__((__unsupported__("The READTIMER" "3" "() macro is not available with the current device."))) unsigned short __readtimer3(void); + + + +unsigned char __t1rd16on(void); +unsigned char __t3rd16on(void); +# 34 "C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\\pic\\include\\xc.h" 2 3 +# 51 "mcc_generated_files/tmr1.c" 2 + +# 1 "mcc_generated_files/tmr1.h" 1 +# 54 "mcc_generated_files/tmr1.h" +# 1 "C:\\Program Files\\Microchip\\xc8\\v2.31\\pic\\include\\c99\\stdbool.h" 1 3 +# 54 "mcc_generated_files/tmr1.h" 2 +# 101 "mcc_generated_files/tmr1.h" +void TMR1_Initialize(void); +# 130 "mcc_generated_files/tmr1.h" +void TMR1_StartTimer(void); +# 162 "mcc_generated_files/tmr1.h" +void TMR1_StopTimer(void); +# 197 "mcc_generated_files/tmr1.h" +uint16_t TMR1_ReadTimer(void); +# 236 "mcc_generated_files/tmr1.h" +void TMR1_WriteTimer(uint16_t timerVal); +# 272 "mcc_generated_files/tmr1.h" +void TMR1_Reload(void); +# 311 "mcc_generated_files/tmr1.h" +void TMR1_StartSinglePulseAcquisition(void); +# 350 "mcc_generated_files/tmr1.h" +uint8_t TMR1_CheckGateValueStatus(void); +# 368 "mcc_generated_files/tmr1.h" +void TMR1_ISR(void); +# 385 "mcc_generated_files/tmr1.h" +void TMR1_CallBack(void); +# 403 "mcc_generated_files/tmr1.h" + void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +# 421 "mcc_generated_files/tmr1.h" +extern void (*TMR1_InterruptHandler)(void); +# 439 "mcc_generated_files/tmr1.h" +void TMR1_DefaultInterruptHandler(void); +# 52 "mcc_generated_files/tmr1.c" 2 + +# 1 "mcc_generated_files/../TEMPORIZATIONS.h" 1 +# 23 "mcc_generated_files/../TEMPORIZATIONS.h" +extern unsigned char ucCount500ms; +extern unsigned char ucCount1s; +extern unsigned char ucCount10s; +extern unsigned int uiCount30s; +extern unsigned int uiCount1min; +extern unsigned char ucCount50ms; + + + +void TEMPORIZATION_10ms (void); +void TEMPORIZATION_100ms (void); +void TEMPORIZATION_500ms (void); +void TEMPORIZATION_1s (void); +void TEMPORIZATION_10s (void); +void TEMPORIZATION_30s (void); +void TEMPORIZATION_1mins (void); +# 53 "mcc_generated_files/tmr1.c" 2 + + + + + +volatile uint16_t timer1ReloadVal; +void (*TMR1_InterruptHandler)(void); + + + + + +void TMR1_Initialize(void) +{ + + + + T1GCON = 0x00; + + + T1GATE = 0x00; + + + T1CLK = 0x01; + + + TMR1H = 0x85; + + + TMR1L = 0xEE; + + + PIR3bits.TMR1IF = 0; + + + timer1ReloadVal=(uint16_t)((TMR1H << 8) | TMR1L); + + + PIE3bits.TMR1IE = 1; + + + TMR1_SetInterruptHandler(TMR1_DefaultInterruptHandler); + + + T1CON = 0x31; +} + +void TMR1_StartTimer(void) +{ + + T1CONbits.TMR1ON = 1; +} + +void TMR1_StopTimer(void) +{ + + T1CONbits.TMR1ON = 0; +} + +uint16_t TMR1_ReadTimer(void) +{ + uint16_t readVal; + uint8_t readValHigh; + uint8_t readValLow; + + T1CONbits.T1RD16 = 1; + + readValLow = TMR1L; + readValHigh = TMR1H; + + readVal = ((uint16_t)readValHigh << 8) | readValLow; + + return readVal; +} + +void TMR1_WriteTimer(uint16_t timerVal) +{ + if (T1CONbits.NOT_SYNC == 1) + { + + T1CONbits.TMR1ON = 0; + + + TMR1H = (uint8_t)(timerVal >> 8); + TMR1L = (uint8_t)timerVal; + + + T1CONbits.TMR1ON =1; + } + else + { + + TMR1H = (uint8_t)(timerVal >> 8); + TMR1L = (uint8_t)timerVal; + } +} + +void TMR1_Reload(void) +{ + TMR1_WriteTimer(timer1ReloadVal); +} + +void TMR1_StartSinglePulseAcquisition(void) +{ + T1GCONbits.T1GGO = 1; +} + +uint8_t TMR1_CheckGateValueStatus(void) +{ + return (T1GCONbits.T1GVAL); +} + +void TMR1_ISR(void) +{ + static volatile unsigned int CountCallBack = 0; + + + PIR3bits.TMR1IF = 0; + TMR1_WriteTimer(timer1ReloadVal); + + + if (++CountCallBack >= 5) + { + + + + + CountCallBack = 0; + } + TMR1_CallBack(); +} + +void TMR1_CallBack(void) +{ + + if(TMR1_InterruptHandler) + { + TMR1_InterruptHandler(); + } + + TEMPORIZATION_100ms(); + + if ( ucCount500ms++ == 5 ) + { + ucCount500ms = 0; + TEMPORIZATION_500ms(); + } + if ( ucCount1s++ == 10 ) + { + ucCount1s = 0; + TEMPORIZATION_1s(); + } + if ( ucCount10s++ == 100 ) + { + ucCount10s = 0; + TEMPORIZATION_10s(); + } + if ( uiCount30s++ == 300 ) + { + uiCount30s = 0; + TEMPORIZATION_30s(); + } + if ( uiCount1min++ == 600 ) + { + uiCount1min = 0; + TEMPORIZATION_1mins(); + } + +} + +void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)){ + TMR1_InterruptHandler = InterruptHandler; +} + +void TMR1_DefaultInterruptHandler(void){ + + +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/tmr1.p1 b/ETC.X/build/default/debug/mcc_generated_files/tmr1.p1 new file mode 100644 index 0000000..9173694 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/tmr1.p1 @@ -0,0 +1,4038 @@ +Version 4.0 HI-TECH Software Intermediate Code +[v F22175 `(v ~T0 @X0 0 tf ] +"39512 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39512: extern volatile unsigned char T1GCON __attribute__((address(0x31F))); +[v _T1GCON `Vuc ~T0 @X0 0 e@799 ] +"39726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39726: extern volatile unsigned char T1GATE __attribute__((address(0x320))); +[v _T1GATE `Vuc ~T0 @X0 0 e@800 ] +"39892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39892: extern volatile unsigned char T1CLK __attribute__((address(0x321))); +[v _T1CLK `Vuc ~T0 @X0 0 e@801 ] +"39252 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39252: extern volatile unsigned char TMR1H __attribute__((address(0x31D))); +[v _TMR1H `Vuc ~T0 @X0 0 e@797 ] +"39182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39182: extern volatile unsigned char TMR1L __attribute__((address(0x31C))); +[v _TMR1L `Vuc ~T0 @X0 0 e@796 ] +"689 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 689: }; +[s S3035 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3035 . SPI1RXIF SPI1TXIF SPI1IF TMR2IF TMR1IF TMR1GIF CCP1IF TMR0IF ] +"688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 688: unsigned NVMADRL :8; +[u S3034 `S3035 1 ] +[n S3034 . . ] +"700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 700: } NVMADRLbits_t; +[v _PIR3bits `VS3034 ~T0 @X0 0 e@1201 ] +"65240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65240: struct { +[s S3002 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S3002 . SPI1RXIE SPI1TXIE SPI1IE TMR2IE TMR1IE TMR1GIE CCP1IE TMR0IE ] +"65239 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65239: typedef union { +[u S3001 `S3002 1 ] +[n S3001 . . ] +"65251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65251: extern volatile PIE3bits_t PIE3bits __attribute__((address(0x4A1))); +[v _PIE3bits `VS3001 ~T0 @X0 0 e@1185 ] +[v F22154 `(v ~T0 @X0 0 tf ] +"403 mcc_generated_files/tmr1.h +[; ;mcc_generated_files/tmr1.h: 403: void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)); +[v _TMR1_SetInterruptHandler `(v ~T0 @X0 0 ef1`*F22154 ] +"439 +[; ;mcc_generated_files/tmr1.h: 439: void TMR1_DefaultInterruptHandler(void); +[v _TMR1_DefaultInterruptHandler `(v ~T0 @X0 0 ef ] +"39322 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39322: extern volatile unsigned char T1CON __attribute__((address(0x31E))); +[v _T1CON `Vuc ~T0 @X0 0 e@798 ] +"39333 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39333: struct { +[s S1833 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :2 `uc 1 ] +[n S1833 . ON RD16 NOT_SYNC . CKPS ] +"39340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39340: struct { +[s S1834 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1834 . TMR1ON T1RD16 NOT_T1SYNC . T1CKPS0 T1CKPS1 ] +"39348 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39348: struct { +[s S1835 :4 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1835 . . CKPS0 CKPS1 ] +"39353 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39353: struct { +[s S1836 :1 `uc 1 :1 `uc 1 ] +[n S1836 . . RD161 ] +"39332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39332: typedef union { +[u S1832 `S1833 1 `S1834 1 `S1835 1 `S1836 1 ] +[n S1832 . . . . . ] +"39358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39358: extern volatile T1CONbits_t T1CONbits __attribute__((address(0x31E))); +[v _T1CONbits `VS1832 ~T0 @X0 0 e@798 ] +"39523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39523: struct { +[s S1843 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1843 . . GVAL GGO GSPM GTM GPOL GE ] +"39532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39532: struct { +[s S1844 :2 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 :1 `uc 1 ] +[n S1844 . . T1GVAL T1GGO T1GSPM T1GTM T1GPOL T1GE ] +"39541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39541: struct { +[s S1845 :3 `uc 1 :1 `uc 1 ] +[n S1845 . . NOT_DONE ] +"39545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39545: struct { +[s S1846 :3 `uc 1 :1 `uc 1 ] +[n S1846 . . NOT_T1DONE ] +"39522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39522: typedef union { +[u S1842 `S1843 1 `S1844 1 `S1845 1 `S1846 1 ] +[n S1842 . . . . . ] +"39550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39550: extern volatile T1GCONbits_t T1GCONbits __attribute__((address(0x31F))); +[v _T1GCONbits `VS1842 ~T0 @X0 0 e@799 ] +"385 mcc_generated_files/tmr1.h +[; ;mcc_generated_files/tmr1.h: 385: void TMR1_CallBack(void); +[v _TMR1_CallBack `(v ~T0 @X0 0 ef ] +[v F22192 `(v ~T0 @X0 0 tf ] +"33 mcc_generated_files/../TEMPORIZATIONS.h +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 33: void TEMPORIZATION_100ms (void); +[v _TEMPORIZATION_100ms `(v ~T0 @X0 0 ef ] +"23 +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 23: extern unsigned char ucCount500ms; +[v _ucCount500ms `uc ~T0 @X0 0 e ] +"34 +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 34: void TEMPORIZATION_500ms (void); +[v _TEMPORIZATION_500ms `(v ~T0 @X0 0 ef ] +"24 +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 24: extern unsigned char ucCount1s; +[v _ucCount1s `uc ~T0 @X0 0 e ] +"35 +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 35: void TEMPORIZATION_1s (void); +[v _TEMPORIZATION_1s `(v ~T0 @X0 0 ef ] +"25 +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 25: extern unsigned char ucCount10s; +[v _ucCount10s `uc ~T0 @X0 0 e ] +"36 +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 36: void TEMPORIZATION_10s (void); +[v _TEMPORIZATION_10s `(v ~T0 @X0 0 ef ] +"26 +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 26: extern unsigned int uiCount30s; +[v _uiCount30s `ui ~T0 @X0 0 e ] +"37 +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 37: void TEMPORIZATION_30s (void); +[v _TEMPORIZATION_30s `(v ~T0 @X0 0 ef ] +"27 +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 27: extern unsigned int uiCount1min; +[v _uiCount1min `ui ~T0 @X0 0 e ] +"38 +[; ;mcc_generated_files/../TEMPORIZATIONS.h: 38: void TEMPORIZATION_1mins (void); +[v _TEMPORIZATION_1mins `(v ~T0 @X0 0 ef ] +[v F22194 `(v ~T0 @X0 0 tf ] +[v F22196 `(v ~T0 @X0 0 tf ] +"363 C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 363: __asm("BOOTREG equ 038h"); +[; <" BOOTREG equ 038h ;# "> +"395 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 395: __asm("CLKRCON equ 039h"); +[; <" CLKRCON equ 039h ;# "> +"499 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 499: __asm("CLKRCLK equ 03Ah"); +[; <" CLKRCLK equ 03Ah ;# "> +"583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 583: __asm("NVMCON0 equ 040h"); +[; <" NVMCON0 equ 040h ;# "> +"619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 619: __asm("NVMCON1 equ 041h"); +[; <" NVMCON1 equ 041h ;# "> +"654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 654: __asm("NVMLOCK equ 042h"); +[; <" NVMLOCK equ 042h ;# "> +"676 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 676: __asm("NVMADR equ 043h"); +[; <" NVMADR equ 043h ;# "> +"683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 683: __asm("NVMADRL equ 043h"); +[; <" NVMADRL equ 043h ;# "> +"753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 753: __asm("NVMADRH equ 044h"); +[; <" NVMADRH equ 044h ;# "> +"823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 823: __asm("NVMADRU equ 045h"); +[; <" NVMADRU equ 045h ;# "> +"881 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 881: __asm("NVMDAT equ 046h"); +[; <" NVMDAT equ 046h ;# "> +"888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 888: __asm("NVMDATL equ 046h"); +[; <" NVMDATL equ 046h ;# "> +"958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 958: __asm("NVMDATH equ 047h"); +[; <" NVMDATH equ 047h ;# "> +"1028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1028: __asm("VREGCON equ 048h"); +[; <" VREGCON equ 048h ;# "> +"1082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1082: __asm("BORCON equ 049h"); +[; <" BORCON equ 049h ;# "> +"1109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1109: __asm("HLVDCON0 equ 04Ah"); +[; <" HLVDCON0 equ 04Ah ;# "> +"1189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1189: __asm("HLVDCON1 equ 04Bh"); +[; <" HLVDCON1 equ 04Bh ;# "> +"1261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1261: __asm("ZCDCON equ 04Ch"); +[; <" ZCDCON equ 04Ch ;# "> +"1341 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1341: __asm("PMD0 equ 060h"); +[; <" PMD0 equ 060h ;# "> +"1407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1407: __asm("PMD1 equ 061h"); +[; <" PMD1 equ 061h ;# "> +"1469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1469: __asm("PMD2 equ 062h"); +[; <" PMD2 equ 062h ;# "> +"1516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1516: __asm("PMD3 equ 063h"); +[; <" PMD3 equ 063h ;# "> +"1567 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1567: __asm("PMD4 equ 064h"); +[; <" PMD4 equ 064h ;# "> +"1623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1623: __asm("PMD5 equ 065h"); +[; <" PMD5 equ 065h ;# "> +"1680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1680: __asm("PMD6 equ 066h"); +[; <" PMD6 equ 066h ;# "> +"1742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1742: __asm("PMD7 equ 067h"); +[; <" PMD7 equ 067h ;# "> +"1804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1804: __asm("PMD8 equ 068h"); +[; <" PMD8 equ 068h ;# "> +"1866 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1866: __asm("MD1CON0 equ 06Ah"); +[; <" MD1CON0 equ 06Ah ;# "> +"1934 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 1934: __asm("MD1CON1 equ 06Bh"); +[; <" MD1CON1 equ 06Bh ;# "> +"2000 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2000: __asm("MD1SRC equ 06Ch"); +[; <" MD1SRC equ 06Ch ;# "> +"2104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2104: __asm("MD1CARL equ 06Dh"); +[; <" MD1CARL equ 06Dh ;# "> +"2196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2196: __asm("MD1CARH equ 06Eh"); +[; <" MD1CARH equ 06Eh ;# "> +"2288 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2288: __asm("CMOUT equ 06Fh"); +[; <" CMOUT equ 06Fh ;# "> +"2314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2314: __asm("CM1CON0 equ 070h"); +[; <" CM1CON0 equ 070h ;# "> +"2394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2394: __asm("CM1CON1 equ 071h"); +[; <" CM1CON1 equ 071h ;# "> +"2434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2434: __asm("CM1NCH equ 072h"); +[; <" CM1NCH equ 072h ;# "> +"2494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2494: __asm("CM1PCH equ 073h"); +[; <" CM1PCH equ 073h ;# "> +"2554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2554: __asm("CM2CON0 equ 074h"); +[; <" CM2CON0 equ 074h ;# "> +"2634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2634: __asm("CM2CON1 equ 075h"); +[; <" CM2CON1 equ 075h ;# "> +"2674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2674: __asm("CM2NCH equ 076h"); +[; <" CM2NCH equ 076h ;# "> +"2734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2734: __asm("CM2PCH equ 077h"); +[; <" CM2PCH equ 077h ;# "> +"2794 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2794: __asm("WDTCON0 equ 078h"); +[; <" WDTCON0 equ 078h ;# "> +"2869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2869: __asm("WDTCON1 equ 079h"); +[; <" WDTCON1 equ 079h ;# "> +"2963 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 2963: __asm("WDTPSL equ 07Ah"); +[; <" WDTPSL equ 07Ah ;# "> +"3091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3091: __asm("WDTPSH equ 07Bh"); +[; <" WDTPSH equ 07Bh ;# "> +"3219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3219: __asm("WDTTMR equ 07Ch"); +[; <" WDTTMR equ 07Ch ;# "> +"3307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3307: __asm("DAC1DAT equ 07Dh"); +[; <" DAC1DAT equ 07Dh ;# "> +"3314 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3314: __asm("DAC1DATL equ 07Dh"); +[; <" DAC1DATL equ 07Dh ;# "> +"3392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3392: __asm("DAC1CON equ 07Fh"); +[; <" DAC1CON equ 07Fh ;# "> +"3495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3495: __asm("SPI1RXB equ 080h"); +[; <" SPI1RXB equ 080h ;# "> +"3565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3565: __asm("SPI1TXB equ 081h"); +[; <" SPI1TXB equ 081h ;# "> +"3635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3635: __asm("SPI1TCNT equ 082h"); +[; <" SPI1TCNT equ 082h ;# "> +"3642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3642: __asm("SPI1TCNTL equ 082h"); +[; <" SPI1TCNTL equ 082h ;# "> +"3662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3662: __asm("SPI1TCNTH equ 083h"); +[; <" SPI1TCNTH equ 083h ;# "> +"3682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3682: __asm("SPI1CON0 equ 084h"); +[; <" SPI1CON0 equ 084h ;# "> +"3748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3748: __asm("SPI1CON1 equ 085h"); +[; <" SPI1CON1 equ 085h ;# "> +"3850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3850: __asm("SPI1CON2 equ 086h"); +[; <" SPI1CON2 equ 086h ;# "> +"3928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 3928: __asm("SPI1STATUS equ 087h"); +[; <" SPI1STATUS equ 087h ;# "> +"4010 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4010: __asm("SPI1TWIDTH equ 088h"); +[; <" SPI1TWIDTH equ 088h ;# "> +"4050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4050: __asm("SPI1BAUD equ 089h"); +[; <" SPI1BAUD equ 089h ;# "> +"4120 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4120: __asm("SPI1INTF equ 08Ah"); +[; <" SPI1INTF equ 08Ah ;# "> +"4212 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4212: __asm("SPI1INTE equ 08Bh"); +[; <" SPI1INTE equ 08Bh ;# "> +"4304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4304: __asm("SPI1CLK equ 08Ch"); +[; <" SPI1CLK equ 08Ch ;# "> +"4396 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4396: __asm("SPI2RXB equ 08Dh"); +[; <" SPI2RXB equ 08Dh ;# "> +"4466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4466: __asm("SPI2TXB equ 08Eh"); +[; <" SPI2TXB equ 08Eh ;# "> +"4536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4536: __asm("SPI2TCNT equ 08Fh"); +[; <" SPI2TCNT equ 08Fh ;# "> +"4543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4543: __asm("SPI2TCNTL equ 08Fh"); +[; <" SPI2TCNTL equ 08Fh ;# "> +"4563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4563: __asm("SPI2TCNTH equ 090h"); +[; <" SPI2TCNTH equ 090h ;# "> +"4583 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4583: __asm("SPI2CON0 equ 091h"); +[; <" SPI2CON0 equ 091h ;# "> +"4649 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4649: __asm("SPI2CON1 equ 092h"); +[; <" SPI2CON1 equ 092h ;# "> +"4751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4751: __asm("SPI2CON2 equ 093h"); +[; <" SPI2CON2 equ 093h ;# "> +"4829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4829: __asm("SPI2STATUS equ 094h"); +[; <" SPI2STATUS equ 094h ;# "> +"4911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4911: __asm("SPI2TWIDTH equ 095h"); +[; <" SPI2TWIDTH equ 095h ;# "> +"4951 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 4951: __asm("SPI2BAUD equ 096h"); +[; <" SPI2BAUD equ 096h ;# "> +"5021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5021: __asm("SPI2INTF equ 097h"); +[; <" SPI2INTF equ 097h ;# "> +"5113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5113: __asm("SPI2INTE equ 098h"); +[; <" SPI2INTE equ 098h ;# "> +"5205 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5205: __asm("SPI2CLK equ 099h"); +[; <" SPI2CLK equ 099h ;# "> +"5297 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5297: __asm("ACTCON equ 0ACh"); +[; <" ACTCON equ 0ACh ;# "> +"5338 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5338: __asm("OSCCON1 equ 0ADh"); +[; <" OSCCON1 equ 0ADh ;# "> +"5408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5408: __asm("OSCCON2 equ 0AEh"); +[; <" OSCCON2 equ 0AEh ;# "> +"5478 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5478: __asm("OSCCON3 equ 0AFh"); +[; <" OSCCON3 equ 0AFh ;# "> +"5518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5518: __asm("OSCTUNE equ 0B0h"); +[; <" OSCTUNE equ 0B0h ;# "> +"5576 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5576: __asm("OSCFRQ equ 0B1h"); +[; <" OSCFRQ equ 0B1h ;# "> +"5581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5581: __asm("OSCFREQ equ 0B1h"); +[; <" OSCFREQ equ 0B1h ;# "> +"5666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5666: __asm("OSCSTAT equ 0B2h"); +[; <" OSCSTAT equ 0B2h ;# "> +"5671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5671: __asm("OSCSTAT1 equ 0B2h"); +[; <" OSCSTAT1 equ 0B2h ;# "> +"5778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5778: __asm("OSCEN equ 0B3h"); +[; <" OSCEN equ 0B3h ;# "> +"5835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5835: __asm("PRLOCK equ 0B4h"); +[; <" PRLOCK equ 0B4h ;# "> +"5855 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5855: __asm("SCANPR equ 0B5h"); +[; <" SCANPR equ 0B5h ;# "> +"5923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5923: __asm("DMA1PR equ 0B6h"); +[; <" DMA1PR equ 0B6h ;# "> +"5991 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 5991: __asm("DMA2PR equ 0B7h"); +[; <" DMA2PR equ 0B7h ;# "> +"6059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6059: __asm("DMA3PR equ 0B8h"); +[; <" DMA3PR equ 0B8h ;# "> +"6127 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6127: __asm("DMA4PR equ 0B9h"); +[; <" DMA4PR equ 0B9h ;# "> +"6195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6195: __asm("DMA5PR equ 0BAh"); +[; <" DMA5PR equ 0BAh ;# "> +"6263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6263: __asm("DMA6PR equ 0BBh"); +[; <" DMA6PR equ 0BBh ;# "> +"6331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6331: __asm("DMA7PR equ 0BCh"); +[; <" DMA7PR equ 0BCh ;# "> +"6399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6399: __asm("DMA8PR equ 0BDh"); +[; <" DMA8PR equ 0BDh ;# "> +"6467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6467: __asm("MAINPR equ 0BEh"); +[; <" MAINPR equ 0BEh ;# "> +"6535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6535: __asm("ISRPR equ 0BFh"); +[; <" ISRPR equ 0BFh ;# "> +"6603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6603: __asm("CLCDATA equ 0D4h"); +[; <" CLCDATA equ 0D4h ;# "> +"6723 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6723: __asm("CLCSELECT equ 0D5h"); +[; <" CLCSELECT equ 0D5h ;# "> +"6763 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6763: __asm("CLCnCON equ 0D6h"); +[; <" CLCnCON equ 0D6h ;# "> +"6833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6833: __asm("CLCnPOL equ 0D7h"); +[; <" CLCnPOL equ 0D7h ;# "> +"6878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6878: __asm("CLCnSEL0 equ 0D8h"); +[; <" CLCnSEL0 equ 0D8h ;# "> +"6948 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 6948: __asm("CLCnSEL1 equ 0D9h"); +[; <" CLCnSEL1 equ 0D9h ;# "> +"7018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7018: __asm("CLCnSEL2 equ 0DAh"); +[; <" CLCnSEL2 equ 0DAh ;# "> +"7088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7088: __asm("CLCnSEL3 equ 0DBh"); +[; <" CLCnSEL3 equ 0DBh ;# "> +"7158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7158: __asm("CLCnGLS0 equ 0DCh"); +[; <" CLCnGLS0 equ 0DCh ;# "> +"7220 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7220: __asm("CLCnGLS1 equ 0DDh"); +[; <" CLCnGLS1 equ 0DDh ;# "> +"7282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7282: __asm("CLCnGLS2 equ 0DEh"); +[; <" CLCnGLS2 equ 0DEh ;# "> +"7344 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7344: __asm("CLCnGLS3 equ 0DFh"); +[; <" CLCnGLS3 equ 0DFh ;# "> +"7406 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7406: __asm("DMASELECT equ 0E8h"); +[; <" DMASELECT equ 0E8h ;# "> +"7446 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7446: __asm("DMAnBUF equ 0E9h"); +[; <" DMAnBUF equ 0E9h ;# "> +"7516 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7516: __asm("DMAnDCNT equ 0EAh"); +[; <" DMAnDCNT equ 0EAh ;# "> +"7523 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7523: __asm("DMAnDCNTL equ 0EAh"); +[; <" DMAnDCNTL equ 0EAh ;# "> +"7593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7593: __asm("DMAnDCNTH equ 0EBh"); +[; <" DMAnDCNTH equ 0EBh ;# "> +"7639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7639: __asm("DMAnDPTR equ 0ECh"); +[; <" DMAnDPTR equ 0ECh ;# "> +"7646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7646: __asm("DMAnDPTRL equ 0ECh"); +[; <" DMAnDPTRL equ 0ECh ;# "> +"7716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7716: __asm("DMAnDPTRH equ 0EDh"); +[; <" DMAnDPTRH equ 0EDh ;# "> +"7786 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7786: __asm("DMAnDSZ equ 0EEh"); +[; <" DMAnDSZ equ 0EEh ;# "> +"7793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7793: __asm("DMAnDSZL equ 0EEh"); +[; <" DMAnDSZL equ 0EEh ;# "> +"7863 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7863: __asm("DMAnDSZH equ 0EFh"); +[; <" DMAnDSZH equ 0EFh ;# "> +"7909 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7909: __asm("DMAnDSA equ 0F0h"); +[; <" DMAnDSA equ 0F0h ;# "> +"7916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7916: __asm("DMAnDSAL equ 0F0h"); +[; <" DMAnDSAL equ 0F0h ;# "> +"7986 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 7986: __asm("DMAnDSAH equ 0F1h"); +[; <" DMAnDSAH equ 0F1h ;# "> +"8056 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8056: __asm("DMAnSCNT equ 0F2h"); +[; <" DMAnSCNT equ 0F2h ;# "> +"8063 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8063: __asm("DMAnSCNTL equ 0F2h"); +[; <" DMAnSCNTL equ 0F2h ;# "> +"8133 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8133: __asm("DMAnSCNTH equ 0F3h"); +[; <" DMAnSCNTH equ 0F3h ;# "> +"8181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8181: __asm("DMAnSPTR equ 0F4h"); +[; <" DMAnSPTR equ 0F4h ;# "> +"8188 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8188: __asm("DMAnSPTRL equ 0F4h"); +[; <" DMAnSPTRL equ 0F4h ;# "> +"8258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8258: __asm("DMAnSPTRH equ 0F5h"); +[; <" DMAnSPTRH equ 0F5h ;# "> +"8328 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8328: __asm("DMAnSPTRU equ 0F6h"); +[; <" DMAnSPTRU equ 0F6h ;# "> +"8386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8386: __asm("DMAnSSZ equ 0F7h"); +[; <" DMAnSSZ equ 0F7h ;# "> +"8393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8393: __asm("DMAnSSZL equ 0F7h"); +[; <" DMAnSSZL equ 0F7h ;# "> +"8463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8463: __asm("DMAnSSZH equ 0F8h"); +[; <" DMAnSSZH equ 0F8h ;# "> +"8511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8511: __asm("DMAnSSA equ 0F9h"); +[; <" DMAnSSA equ 0F9h ;# "> +"8518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8518: __asm("DMAnSSAL equ 0F9h"); +[; <" DMAnSSAL equ 0F9h ;# "> +"8588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8588: __asm("DMAnSSAH equ 0FAh"); +[; <" DMAnSSAH equ 0FAh ;# "> +"8658 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8658: __asm("DMAnSSAU equ 0FBh"); +[; <" DMAnSSAU equ 0FBh ;# "> +"8716 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8716: __asm("DMAnCON0 equ 0FCh"); +[; <" DMAnCON0 equ 0FCh ;# "> +"8762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8762: __asm("DMAnCON1 equ 0FDh"); +[; <" DMAnCON1 equ 0FDh ;# "> +"8806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8806: __asm("DMAnAIRQ equ 0FEh"); +[; <" DMAnAIRQ equ 0FEh ;# "> +"8876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8876: __asm("DMAnSIRQ equ 0FFh"); +[; <" DMAnSIRQ equ 0FFh ;# "> +"8946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 8946: __asm("C1CONL equ 0100h"); +[; <" C1CONL equ 0100h ;# "> +"9016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9016: __asm("C1CONH equ 0101h"); +[; <" C1CONH equ 0101h ;# "> +"9087 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9087: __asm("C1CONU equ 0102h"); +[; <" C1CONU equ 0102h ;# "> +"9158 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9158: __asm("C1CONT equ 0103h"); +[; <" C1CONT equ 0103h ;# "> +"9235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9235: __asm("C1NBTCFGL equ 0104h"); +[; <" C1NBTCFGL equ 0104h ;# "> +"9299 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9299: __asm("C1NBTCFGH equ 0105h"); +[; <" C1NBTCFGH equ 0105h ;# "> +"9363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9363: __asm("C1NBTCFGU equ 0106h"); +[; <" C1NBTCFGU equ 0106h ;# "> +"9433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9433: __asm("C1NBTCFGT equ 0107h"); +[; <" C1NBTCFGT equ 0107h ;# "> +"9503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9503: __asm("C1DBTCFGL equ 0108h"); +[; <" C1DBTCFGL equ 0108h ;# "> +"9549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9549: __asm("C1DBTCFGH equ 0109h"); +[; <" C1DBTCFGH equ 0109h ;# "> +"9595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9595: __asm("C1DBTCFGU equ 010Ah"); +[; <" C1DBTCFGU equ 010Ah ;# "> +"9647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9647: __asm("C1DBTCFGT equ 010Bh"); +[; <" C1DBTCFGT equ 010Bh ;# "> +"9717 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9717: __asm("C1TDCL equ 010Ch"); +[; <" C1TDCL equ 010Ch ;# "> +"9775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9775: __asm("C1TDCH equ 010Dh"); +[; <" C1TDCH equ 010Dh ;# "> +"9839 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9839: __asm("C1TDCU equ 010Eh"); +[; <" C1TDCU equ 010Eh ;# "> +"9873 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9873: __asm("C1TDCT equ 010Fh"); +[; <" C1TDCT equ 010Fh ;# "> +"9899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9899: __asm("C1TBC equ 0110h"); +[; <" C1TBC equ 0110h ;# "> +"9906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9906: __asm("C1TBCL equ 0110h"); +[; <" C1TBCL equ 0110h ;# "> +"9976 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 9976: __asm("C1TBCH equ 0111h"); +[; <" C1TBCH equ 0111h ;# "> +"10046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10046: __asm("C1TBCU equ 0112h"); +[; <" C1TBCU equ 0112h ;# "> +"10116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10116: __asm("C1TBCT equ 0113h"); +[; <" C1TBCT equ 0113h ;# "> +"10186 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10186: __asm("C1TSCONL equ 0114h"); +[; <" C1TSCONL equ 0114h ;# "> +"10256 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10256: __asm("C1TSCONH equ 0115h"); +[; <" C1TSCONH equ 0115h ;# "> +"10290 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10290: __asm("C1TSCONU equ 0116h"); +[; <" C1TSCONU equ 0116h ;# "> +"10322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10322: __asm("C1TSCONT equ 0117h"); +[; <" C1TSCONT equ 0117h ;# "> +"10329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10329: __asm("C1VECL equ 0118h"); +[; <" C1VECL equ 0118h ;# "> +"10349 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10349: __asm("C1VECH equ 0119h"); +[; <" C1VECH equ 0119h ;# "> +"10369 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10369: __asm("C1VECU equ 011Ah"); +[; <" C1VECU equ 011Ah ;# "> +"10389 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10389: __asm("C1VECT equ 011Bh"); +[; <" C1VECT equ 011Bh ;# "> +"10409 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10409: __asm("C1INTL equ 011Ch"); +[; <" C1INTL equ 011Ch ;# "> +"10453 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10453: __asm("C1INTH equ 011Dh"); +[; <" C1INTH equ 011Dh ;# "> +"10504 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10504: __asm("C1INTU equ 011Eh"); +[; <" C1INTU equ 011Eh ;# "> +"10548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10548: __asm("C1INTT equ 011Fh"); +[; <" C1INTT equ 011Fh ;# "> +"10599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10599: __asm("C1RXIF equ 0120h"); +[; <" C1RXIF equ 0120h ;# "> +"10606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10606: __asm("C1RXIFL equ 0120h"); +[; <" C1RXIFL equ 0120h ;# "> +"10672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10672: __asm("C1RXIFH equ 0121h"); +[; <" C1RXIFH equ 0121h ;# "> +"10742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10742: __asm("C1RXIFU equ 0122h"); +[; <" C1RXIFU equ 0122h ;# "> +"10812 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10812: __asm("C1RXIFT equ 0123h"); +[; <" C1RXIFT equ 0123h ;# "> +"10882 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10882: __asm("C1TXIF equ 0124h"); +[; <" C1TXIF equ 0124h ;# "> +"10889 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10889: __asm("C1TXIFL equ 0124h"); +[; <" C1TXIFL equ 0124h ;# "> +"10959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 10959: __asm("C1TXIFH equ 0125h"); +[; <" C1TXIFH equ 0125h ;# "> +"11029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11029: __asm("C1TXIFU equ 0126h"); +[; <" C1TXIFU equ 0126h ;# "> +"11099 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11099: __asm("C1TXIFT equ 0127h"); +[; <" C1TXIFT equ 0127h ;# "> +"11169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11169: __asm("C1RXOVIF equ 0128h"); +[; <" C1RXOVIF equ 0128h ;# "> +"11176 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11176: __asm("C1RXOVIFL equ 0128h"); +[; <" C1RXOVIFL equ 0128h ;# "> +"11242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11242: __asm("C1RXOVIFH equ 0129h"); +[; <" C1RXOVIFH equ 0129h ;# "> +"11312 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11312: __asm("C1RXOVIFU equ 012Ah"); +[; <" C1RXOVIFU equ 012Ah ;# "> +"11382 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11382: __asm("C1RXOVIFT equ 012Bh"); +[; <" C1RXOVIFT equ 012Bh ;# "> +"11452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11452: __asm("C1TXATIF equ 012Ch"); +[; <" C1TXATIF equ 012Ch ;# "> +"11459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11459: __asm("C1TXATIFL equ 012Ch"); +[; <" C1TXATIFL equ 012Ch ;# "> +"11529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11529: __asm("C1TXATIFH equ 012Dh"); +[; <" C1TXATIFH equ 012Dh ;# "> +"11599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11599: __asm("C1TXATIFU equ 012Eh"); +[; <" C1TXATIFU equ 012Eh ;# "> +"11669 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11669: __asm("C1TXATIFT equ 012Fh"); +[; <" C1TXATIFT equ 012Fh ;# "> +"11739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11739: __asm("C1TXREQ equ 0130h"); +[; <" C1TXREQ equ 0130h ;# "> +"11746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11746: __asm("C1TXREQL equ 0130h"); +[; <" C1TXREQL equ 0130h ;# "> +"11816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11816: __asm("C1TXREQH equ 0131h"); +[; <" C1TXREQH equ 0131h ;# "> +"11886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11886: __asm("C1TXREQU equ 0132h"); +[; <" C1TXREQU equ 0132h ;# "> +"11956 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 11956: __asm("C1TXREQT equ 0133h"); +[; <" C1TXREQT equ 0133h ;# "> +"12026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12026: __asm("C1TRECL equ 0134h"); +[; <" C1TRECL equ 0134h ;# "> +"12096 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12096: __asm("C1TRECH equ 0135h"); +[; <" C1TRECH equ 0135h ;# "> +"12166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12166: __asm("C1TRECU equ 0136h"); +[; <" C1TRECU equ 0136h ;# "> +"12216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12216: __asm("C1TRECT equ 0137h"); +[; <" C1TRECT equ 0137h ;# "> +"12223 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12223: __asm("C1BDIAG0L equ 0138h"); +[; <" C1BDIAG0L equ 0138h ;# "> +"12293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12293: __asm("C1BDIAG0H equ 0139h"); +[; <" C1BDIAG0H equ 0139h ;# "> +"12363 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12363: __asm("C1BDIAG0U equ 013Ah"); +[; <" C1BDIAG0U equ 013Ah ;# "> +"12433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12433: __asm("C1BDIAG0T equ 013Bh"); +[; <" C1BDIAG0T equ 013Bh ;# "> +"12503 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12503: __asm("C1BDIAG1L equ 013Ch"); +[; <" C1BDIAG1L equ 013Ch ;# "> +"12573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12573: __asm("C1BDIAG1H equ 013Dh"); +[; <" C1BDIAG1H equ 013Dh ;# "> +"12643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12643: __asm("C1BDIAG1U equ 013Eh"); +[; <" C1BDIAG1U equ 013Eh ;# "> +"12700 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12700: __asm("C1BDIAG1T equ 013Fh"); +[; <" C1BDIAG1T equ 013Fh ;# "> +"12757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12757: __asm("C1TEFCONL equ 0140h"); +[; <" C1TEFCONL equ 0140h ;# "> +"12802 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12802: __asm("C1TEFCONH equ 0141h"); +[; <" C1TEFCONH equ 0141h ;# "> +"12829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12829: __asm("C1TEFCONU equ 0142h"); +[; <" C1TEFCONU equ 0142h ;# "> +"12836 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12836: __asm("C1TEFCONT equ 0143h"); +[; <" C1TEFCONT equ 0143h ;# "> +"12888 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12888: __asm("C1TEFSTAL equ 0144h"); +[; <" C1TEFSTAL equ 0144h ;# "> +"12926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12926: __asm("C1TEFSTAH equ 0145h"); +[; <" C1TEFSTAH equ 0145h ;# "> +"12933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12933: __asm("C1TEFSTAU equ 0146h"); +[; <" C1TEFSTAU equ 0146h ;# "> +"12940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12940: __asm("C1TEFSTAT equ 0147h"); +[; <" C1TEFSTAT equ 0147h ;# "> +"12947 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12947: __asm("C1TEFUA equ 0148h"); +[; <" C1TEFUA equ 0148h ;# "> +"12954 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 12954: __asm("C1TEFUAL equ 0148h"); +[; <" C1TEFUAL equ 0148h ;# "> +"13024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13024: __asm("C1TEFUAH equ 0149h"); +[; <" C1TEFUAH equ 0149h ;# "> +"13094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13094: __asm("C1TEFUAU equ 014Ah"); +[; <" C1TEFUAU equ 014Ah ;# "> +"13164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13164: __asm("C1TEFUAT equ 014Bh"); +[; <" C1TEFUAT equ 014Bh ;# "> +"13234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13234: __asm("C1FIFOBA equ 014Ch"); +[; <" C1FIFOBA equ 014Ch ;# "> +"13241 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13241: __asm("C1FIFOBAL equ 014Ch"); +[; <" C1FIFOBAL equ 014Ch ;# "> +"13311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13311: __asm("C1FIFOBAH equ 014Dh"); +[; <" C1FIFOBAH equ 014Dh ;# "> +"13381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13381: __asm("C1FIFOBAU equ 014Eh"); +[; <" C1FIFOBAU equ 014Eh ;# "> +"13451 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13451: __asm("C1FIFOBAT equ 014Fh"); +[; <" C1FIFOBAT equ 014Fh ;# "> +"13521 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13521: __asm("C1TXQCONL equ 0150h"); +[; <" C1TXQCONL equ 0150h ;# "> +"13562 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13562: __asm("C1TXQCONH equ 0151h"); +[; <" C1TXQCONH equ 0151h ;# "> +"13594 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13594: __asm("C1TXQCONU equ 0152h"); +[; <" C1TXQCONU equ 0152h ;# "> +"13664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13664: __asm("C1TXQCONT equ 0153h"); +[; <" C1TXQCONT equ 0153h ;# "> +"13740 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13740: __asm("C1TXQSTAL equ 0154h"); +[; <" C1TXQSTAL equ 0154h ;# "> +"13792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13792: __asm("C1TXQSTAH equ 0155h"); +[; <" C1TXQSTAH equ 0155h ;# "> +"13844 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13844: __asm("C1TXQSTAU equ 0156h"); +[; <" C1TXQSTAU equ 0156h ;# "> +"13851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13851: __asm("C1TXQSTAT equ 0157h"); +[; <" C1TXQSTAT equ 0157h ;# "> +"13858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13858: __asm("C1TXQUA equ 0158h"); +[; <" C1TXQUA equ 0158h ;# "> +"13865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13865: __asm("C1TXQUAL equ 0158h"); +[; <" C1TXQUAL equ 0158h ;# "> +"13935 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 13935: __asm("C1TXQUAH equ 0159h"); +[; <" C1TXQUAH equ 0159h ;# "> +"14005 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14005: __asm("C1TXQUAU equ 015Ah"); +[; <" C1TXQUAU equ 015Ah ;# "> +"14075 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14075: __asm("C1TXQUAT equ 015Bh"); +[; <" C1TXQUAT equ 015Bh ;# "> +"14145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14145: __asm("C1FIFOCON1 equ 015Ch"); +[; <" C1FIFOCON1 equ 015Ch ;# "> +"14152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14152: __asm("C1FIFOCON1L equ 015Ch"); +[; <" C1FIFOCON1L equ 015Ch ;# "> +"14214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14214: __asm("C1FIFOCON1H equ 015Dh"); +[; <" C1FIFOCON1H equ 015Dh ;# "> +"14246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14246: __asm("C1FIFOCON1U equ 015Eh"); +[; <" C1FIFOCON1U equ 015Eh ;# "> +"14316 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14316: __asm("C1FIFOCON1T equ 015Fh"); +[; <" C1FIFOCON1T equ 015Fh ;# "> +"14392 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14392: __asm("C1FIFOSTA1 equ 0160h"); +[; <" C1FIFOSTA1 equ 0160h ;# "> +"14399 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14399: __asm("C1FIFOSTA1L equ 0160h"); +[; <" C1FIFOSTA1L equ 0160h ;# "> +"14461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14461: __asm("C1FIFOSTA1H equ 0161h"); +[; <" C1FIFOSTA1H equ 0161h ;# "> +"14513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14513: __asm("C1FIFOSTA1U equ 0162h"); +[; <" C1FIFOSTA1U equ 0162h ;# "> +"14520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14520: __asm("C1FIFOSTA1T equ 0163h"); +[; <" C1FIFOSTA1T equ 0163h ;# "> +"14527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14527: __asm("C1FIFOUA1 equ 0164h"); +[; <" C1FIFOUA1 equ 0164h ;# "> +"14534 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14534: __asm("C1FIFOUA1L equ 0164h"); +[; <" C1FIFOUA1L equ 0164h ;# "> +"14604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14604: __asm("C1FIFOUA1H equ 0165h"); +[; <" C1FIFOUA1H equ 0165h ;# "> +"14674 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14674: __asm("C1FIFOUA1U equ 0166h"); +[; <" C1FIFOUA1U equ 0166h ;# "> +"14744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14744: __asm("C1FIFOUA1T equ 0167h"); +[; <" C1FIFOUA1T equ 0167h ;# "> +"14814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14814: __asm("C1FIFOCON2 equ 0168h"); +[; <" C1FIFOCON2 equ 0168h ;# "> +"14821 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14821: __asm("C1FIFOCON2L equ 0168h"); +[; <" C1FIFOCON2L equ 0168h ;# "> +"14883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14883: __asm("C1FIFOCON2H equ 0169h"); +[; <" C1FIFOCON2H equ 0169h ;# "> +"14915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14915: __asm("C1FIFOCON2U equ 016Ah"); +[; <" C1FIFOCON2U equ 016Ah ;# "> +"14985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 14985: __asm("C1FIFOCON2T equ 016Bh"); +[; <" C1FIFOCON2T equ 016Bh ;# "> +"15061 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15061: __asm("C1FIFOSTA2 equ 016Ch"); +[; <" C1FIFOSTA2 equ 016Ch ;# "> +"15068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15068: __asm("C1FIFOSTA2L equ 016Ch"); +[; <" C1FIFOSTA2L equ 016Ch ;# "> +"15130 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15130: __asm("C1FIFOSTA2H equ 016Dh"); +[; <" C1FIFOSTA2H equ 016Dh ;# "> +"15182 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15182: __asm("C1FIFOSTA2U equ 016Eh"); +[; <" C1FIFOSTA2U equ 016Eh ;# "> +"15189 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15189: __asm("C1FIFOSTA2T equ 016Fh"); +[; <" C1FIFOSTA2T equ 016Fh ;# "> +"15196 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15196: __asm("C1FIFOUA2 equ 0170h"); +[; <" C1FIFOUA2 equ 0170h ;# "> +"15203 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15203: __asm("C1FIFOUA2L equ 0170h"); +[; <" C1FIFOUA2L equ 0170h ;# "> +"15273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15273: __asm("C1FIFOUA2H equ 0171h"); +[; <" C1FIFOUA2H equ 0171h ;# "> +"15343 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15343: __asm("C1FIFOUA2U equ 0172h"); +[; <" C1FIFOUA2U equ 0172h ;# "> +"15413 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15413: __asm("C1FIFOUA2T equ 0173h"); +[; <" C1FIFOUA2T equ 0173h ;# "> +"15483 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15483: __asm("C1FIFOCON3 equ 0174h"); +[; <" C1FIFOCON3 equ 0174h ;# "> +"15490 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15490: __asm("C1FIFOCON3L equ 0174h"); +[; <" C1FIFOCON3L equ 0174h ;# "> +"15552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15552: __asm("C1FIFOCON3H equ 0175h"); +[; <" C1FIFOCON3H equ 0175h ;# "> +"15584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15584: __asm("C1FIFOCON3U equ 0176h"); +[; <" C1FIFOCON3U equ 0176h ;# "> +"15654 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15654: __asm("C1FIFOCON3T equ 0177h"); +[; <" C1FIFOCON3T equ 0177h ;# "> +"15730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15730: __asm("C1FIFOSTA3 equ 0178h"); +[; <" C1FIFOSTA3 equ 0178h ;# "> +"15737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15737: __asm("C1FIFOSTA3L equ 0178h"); +[; <" C1FIFOSTA3L equ 0178h ;# "> +"15799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15799: __asm("C1FIFOSTA3H equ 0179h"); +[; <" C1FIFOSTA3H equ 0179h ;# "> +"15851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15851: __asm("C1FIFOSTA3U equ 017Ah"); +[; <" C1FIFOSTA3U equ 017Ah ;# "> +"15858 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15858: __asm("C1FIFOSTA3T equ 017Bh"); +[; <" C1FIFOSTA3T equ 017Bh ;# "> +"15865 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15865: __asm("C1FIFOUA3 equ 017Ch"); +[; <" C1FIFOUA3 equ 017Ch ;# "> +"15872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15872: __asm("C1FIFOUA3L equ 017Ch"); +[; <" C1FIFOUA3L equ 017Ch ;# "> +"15942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 15942: __asm("C1FIFOUA3H equ 017Dh"); +[; <" C1FIFOUA3H equ 017Dh ;# "> +"16012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16012: __asm("C1FIFOUA3U equ 017Eh"); +[; <" C1FIFOUA3U equ 017Eh ;# "> +"16082 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16082: __asm("C1FIFOUA3T equ 017Fh"); +[; <" C1FIFOUA3T equ 017Fh ;# "> +"16152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16152: __asm("C1FLTCON0L equ 0180h"); +[; <" C1FLTCON0L equ 0180h ;# "> +"16211 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16211: __asm("C1FLTCON0H equ 0181h"); +[; <" C1FLTCON0H equ 0181h ;# "> +"16270 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16270: __asm("C1FLTCON0U equ 0182h"); +[; <" C1FLTCON0U equ 0182h ;# "> +"16329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16329: __asm("C1FLTCON0T equ 0183h"); +[; <" C1FLTCON0T equ 0183h ;# "> +"16388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16388: __asm("C1FLTCON1L equ 0184h"); +[; <" C1FLTCON1L equ 0184h ;# "> +"16447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16447: __asm("C1FLTCON1H equ 0185h"); +[; <" C1FLTCON1H equ 0185h ;# "> +"16506 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16506: __asm("C1FLTCON1U equ 0186h"); +[; <" C1FLTCON1U equ 0186h ;# "> +"16565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16565: __asm("C1FLTCON1T equ 0187h"); +[; <" C1FLTCON1T equ 0187h ;# "> +"16624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16624: __asm("C1FLTCON2L equ 0188h"); +[; <" C1FLTCON2L equ 0188h ;# "> +"16683 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16683: __asm("C1FLTCON2H equ 0189h"); +[; <" C1FLTCON2H equ 0189h ;# "> +"16742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16742: __asm("C1FLTCON2U equ 018Ah"); +[; <" C1FLTCON2U equ 018Ah ;# "> +"16801 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16801: __asm("C1FLTCON2T equ 018Bh"); +[; <" C1FLTCON2T equ 018Bh ;# "> +"16860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16860: __asm("C1FLTOBJ0 equ 018Ch"); +[; <" C1FLTOBJ0 equ 018Ch ;# "> +"16867 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16867: __asm("C1FLTOBJ0L equ 018Ch"); +[; <" C1FLTOBJ0L equ 018Ch ;# "> +"16937 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 16937: __asm("C1FLTOBJ0H equ 018Dh"); +[; <" C1FLTOBJ0H equ 018Dh ;# "> +"17013 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17013: __asm("C1FLTOBJ0U equ 018Eh"); +[; <" C1FLTOBJ0U equ 018Eh ;# "> +"17083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17083: __asm("C1FLTOBJ0T equ 018Fh"); +[; <" C1FLTOBJ0T equ 018Fh ;# "> +"17147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17147: __asm("C1MASK0 equ 0190h"); +[; <" C1MASK0 equ 0190h ;# "> +"17154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17154: __asm("C1MASK0L equ 0190h"); +[; <" C1MASK0L equ 0190h ;# "> +"17224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17224: __asm("C1MASK0H equ 0191h"); +[; <" C1MASK0H equ 0191h ;# "> +"17300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17300: __asm("C1MASK0U equ 0192h"); +[; <" C1MASK0U equ 0192h ;# "> +"17370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17370: __asm("C1MASK0T equ 0193h"); +[; <" C1MASK0T equ 0193h ;# "> +"17434 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17434: __asm("C1FLTOBJ1 equ 0194h"); +[; <" C1FLTOBJ1 equ 0194h ;# "> +"17441 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17441: __asm("C1FLTOBJ1L equ 0194h"); +[; <" C1FLTOBJ1L equ 0194h ;# "> +"17511 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17511: __asm("C1FLTOBJ1H equ 0195h"); +[; <" C1FLTOBJ1H equ 0195h ;# "> +"17587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17587: __asm("C1FLTOBJ1U equ 0196h"); +[; <" C1FLTOBJ1U equ 0196h ;# "> +"17657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17657: __asm("C1FLTOBJ1T equ 0197h"); +[; <" C1FLTOBJ1T equ 0197h ;# "> +"17721 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17721: __asm("C1MASK1 equ 0198h"); +[; <" C1MASK1 equ 0198h ;# "> +"17728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17728: __asm("C1MASK1L equ 0198h"); +[; <" C1MASK1L equ 0198h ;# "> +"17798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17798: __asm("C1MASK1H equ 0199h"); +[; <" C1MASK1H equ 0199h ;# "> +"17874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17874: __asm("C1MASK1U equ 019Ah"); +[; <" C1MASK1U equ 019Ah ;# "> +"17944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 17944: __asm("C1MASK1T equ 019Bh"); +[; <" C1MASK1T equ 019Bh ;# "> +"18008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18008: __asm("C1FLTOBJ2 equ 019Ch"); +[; <" C1FLTOBJ2 equ 019Ch ;# "> +"18015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18015: __asm("C1FLTOBJ2L equ 019Ch"); +[; <" C1FLTOBJ2L equ 019Ch ;# "> +"18085 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18085: __asm("C1FLTOBJ2H equ 019Dh"); +[; <" C1FLTOBJ2H equ 019Dh ;# "> +"18161 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18161: __asm("C1FLTOBJ2U equ 019Eh"); +[; <" C1FLTOBJ2U equ 019Eh ;# "> +"18231 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18231: __asm("C1FLTOBJ2T equ 019Fh"); +[; <" C1FLTOBJ2T equ 019Fh ;# "> +"18295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18295: __asm("C1MASK2 equ 01A0h"); +[; <" C1MASK2 equ 01A0h ;# "> +"18302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18302: __asm("C1MASK2L equ 01A0h"); +[; <" C1MASK2L equ 01A0h ;# "> +"18372 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18372: __asm("C1MASK2H equ 01A1h"); +[; <" C1MASK2H equ 01A1h ;# "> +"18448 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18448: __asm("C1MASK2U equ 01A2h"); +[; <" C1MASK2U equ 01A2h ;# "> +"18518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18518: __asm("C1MASK2T equ 01A3h"); +[; <" C1MASK2T equ 01A3h ;# "> +"18582 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18582: __asm("C1FLTOBJ3 equ 01A4h"); +[; <" C1FLTOBJ3 equ 01A4h ;# "> +"18589 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18589: __asm("C1FLTOBJ3L equ 01A4h"); +[; <" C1FLTOBJ3L equ 01A4h ;# "> +"18659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18659: __asm("C1FLTOBJ3H equ 01A5h"); +[; <" C1FLTOBJ3H equ 01A5h ;# "> +"18735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18735: __asm("C1FLTOBJ3U equ 01A6h"); +[; <" C1FLTOBJ3U equ 01A6h ;# "> +"18805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18805: __asm("C1FLTOBJ3T equ 01A7h"); +[; <" C1FLTOBJ3T equ 01A7h ;# "> +"18869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18869: __asm("C1MASK3 equ 01A8h"); +[; <" C1MASK3 equ 01A8h ;# "> +"18876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18876: __asm("C1MASK3L equ 01A8h"); +[; <" C1MASK3L equ 01A8h ;# "> +"18946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 18946: __asm("C1MASK3H equ 01A9h"); +[; <" C1MASK3H equ 01A9h ;# "> +"19022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19022: __asm("C1MASK3U equ 01AAh"); +[; <" C1MASK3U equ 01AAh ;# "> +"19092 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19092: __asm("C1MASK3T equ 01ABh"); +[; <" C1MASK3T equ 01ABh ;# "> +"19156 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19156: __asm("C1FLTOBJ4 equ 01ACh"); +[; <" C1FLTOBJ4 equ 01ACh ;# "> +"19163 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19163: __asm("C1FLTOBJ4L equ 01ACh"); +[; <" C1FLTOBJ4L equ 01ACh ;# "> +"19233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19233: __asm("C1FLTOBJ4H equ 01ADh"); +[; <" C1FLTOBJ4H equ 01ADh ;# "> +"19309 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19309: __asm("C1FLTOBJ4U equ 01AEh"); +[; <" C1FLTOBJ4U equ 01AEh ;# "> +"19379 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19379: __asm("C1FLTOBJ4T equ 01AFh"); +[; <" C1FLTOBJ4T equ 01AFh ;# "> +"19443 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19443: __asm("C1MASK4 equ 01B0h"); +[; <" C1MASK4 equ 01B0h ;# "> +"19450 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19450: __asm("C1MASK4L equ 01B0h"); +[; <" C1MASK4L equ 01B0h ;# "> +"19520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19520: __asm("C1MASK4H equ 01B1h"); +[; <" C1MASK4H equ 01B1h ;# "> +"19596 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19596: __asm("C1MASK4U equ 01B2h"); +[; <" C1MASK4U equ 01B2h ;# "> +"19666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19666: __asm("C1MASK4T equ 01B3h"); +[; <" C1MASK4T equ 01B3h ;# "> +"19730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19730: __asm("C1FLTOBJ5 equ 01B4h"); +[; <" C1FLTOBJ5 equ 01B4h ;# "> +"19737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19737: __asm("C1FLTOBJ5L equ 01B4h"); +[; <" C1FLTOBJ5L equ 01B4h ;# "> +"19807 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19807: __asm("C1FLTOBJ5H equ 01B5h"); +[; <" C1FLTOBJ5H equ 01B5h ;# "> +"19883 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19883: __asm("C1FLTOBJ5U equ 01B6h"); +[; <" C1FLTOBJ5U equ 01B6h ;# "> +"19953 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 19953: __asm("C1FLTOBJ5T equ 01B7h"); +[; <" C1FLTOBJ5T equ 01B7h ;# "> +"20017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20017: __asm("C1MASK5 equ 01B8h"); +[; <" C1MASK5 equ 01B8h ;# "> +"20024 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20024: __asm("C1MASK5L equ 01B8h"); +[; <" C1MASK5L equ 01B8h ;# "> +"20094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20094: __asm("C1MASK5H equ 01B9h"); +[; <" C1MASK5H equ 01B9h ;# "> +"20170 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20170: __asm("C1MASK5U equ 01BAh"); +[; <" C1MASK5U equ 01BAh ;# "> +"20240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20240: __asm("C1MASK5T equ 01BBh"); +[; <" C1MASK5T equ 01BBh ;# "> +"20304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20304: __asm("C1FLTOBJ6 equ 01BCh"); +[; <" C1FLTOBJ6 equ 01BCh ;# "> +"20311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20311: __asm("C1FLTOBJ6L equ 01BCh"); +[; <" C1FLTOBJ6L equ 01BCh ;# "> +"20381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20381: __asm("C1FLTOBJ6H equ 01BDh"); +[; <" C1FLTOBJ6H equ 01BDh ;# "> +"20457 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20457: __asm("C1FLTOBJ6U equ 01BEh"); +[; <" C1FLTOBJ6U equ 01BEh ;# "> +"20527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20527: __asm("C1FLTOBJ6T equ 01BFh"); +[; <" C1FLTOBJ6T equ 01BFh ;# "> +"20591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20591: __asm("C1MASK6 equ 01C0h"); +[; <" C1MASK6 equ 01C0h ;# "> +"20598 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20598: __asm("C1MASK6L equ 01C0h"); +[; <" C1MASK6L equ 01C0h ;# "> +"20668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20668: __asm("C1MASK6H equ 01C1h"); +[; <" C1MASK6H equ 01C1h ;# "> +"20744 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20744: __asm("C1MASK6U equ 01C2h"); +[; <" C1MASK6U equ 01C2h ;# "> +"20814 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20814: __asm("C1MASK6T equ 01C3h"); +[; <" C1MASK6T equ 01C3h ;# "> +"20878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20878: __asm("C1FLTOBJ7 equ 01C4h"); +[; <" C1FLTOBJ7 equ 01C4h ;# "> +"20885 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20885: __asm("C1FLTOBJ7L equ 01C4h"); +[; <" C1FLTOBJ7L equ 01C4h ;# "> +"20955 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 20955: __asm("C1FLTOBJ7H equ 01C5h"); +[; <" C1FLTOBJ7H equ 01C5h ;# "> +"21031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21031: __asm("C1FLTOBJ7U equ 01C6h"); +[; <" C1FLTOBJ7U equ 01C6h ;# "> +"21101 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21101: __asm("C1FLTOBJ7T equ 01C7h"); +[; <" C1FLTOBJ7T equ 01C7h ;# "> +"21165 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21165: __asm("C1MASK7 equ 01C8h"); +[; <" C1MASK7 equ 01C8h ;# "> +"21172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21172: __asm("C1MASK7L equ 01C8h"); +[; <" C1MASK7L equ 01C8h ;# "> +"21242 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21242: __asm("C1MASK7H equ 01C9h"); +[; <" C1MASK7H equ 01C9h ;# "> +"21318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21318: __asm("C1MASK7U equ 01CAh"); +[; <" C1MASK7U equ 01CAh ;# "> +"21388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21388: __asm("C1MASK7T equ 01CBh"); +[; <" C1MASK7T equ 01CBh ;# "> +"21452 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21452: __asm("C1FLTOBJ8 equ 01CCh"); +[; <" C1FLTOBJ8 equ 01CCh ;# "> +"21459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21459: __asm("C1FLTOBJ8L equ 01CCh"); +[; <" C1FLTOBJ8L equ 01CCh ;# "> +"21529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21529: __asm("C1FLTOBJ8H equ 01CDh"); +[; <" C1FLTOBJ8H equ 01CDh ;# "> +"21605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21605: __asm("C1FLTOBJ8U equ 01CEh"); +[; <" C1FLTOBJ8U equ 01CEh ;# "> +"21675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21675: __asm("C1FLTOBJ8T equ 01CFh"); +[; <" C1FLTOBJ8T equ 01CFh ;# "> +"21739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21739: __asm("C1MASK8 equ 01D0h"); +[; <" C1MASK8 equ 01D0h ;# "> +"21746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21746: __asm("C1MASK8L equ 01D0h"); +[; <" C1MASK8L equ 01D0h ;# "> +"21816 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21816: __asm("C1MASK8H equ 01D1h"); +[; <" C1MASK8H equ 01D1h ;# "> +"21892 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21892: __asm("C1MASK8U equ 01D2h"); +[; <" C1MASK8U equ 01D2h ;# "> +"21962 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 21962: __asm("C1MASK8T equ 01D3h"); +[; <" C1MASK8T equ 01D3h ;# "> +"22026 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22026: __asm("C1FLTOBJ9 equ 01D4h"); +[; <" C1FLTOBJ9 equ 01D4h ;# "> +"22033 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22033: __asm("C1FLTOBJ9L equ 01D4h"); +[; <" C1FLTOBJ9L equ 01D4h ;# "> +"22103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22103: __asm("C1FLTOBJ9H equ 01D5h"); +[; <" C1FLTOBJ9H equ 01D5h ;# "> +"22179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22179: __asm("C1FLTOBJ9U equ 01D6h"); +[; <" C1FLTOBJ9U equ 01D6h ;# "> +"22249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22249: __asm("C1FLTOBJ9T equ 01D7h"); +[; <" C1FLTOBJ9T equ 01D7h ;# "> +"22313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22313: __asm("C1MASK9 equ 01D8h"); +[; <" C1MASK9 equ 01D8h ;# "> +"22320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22320: __asm("C1MASK9L equ 01D8h"); +[; <" C1MASK9L equ 01D8h ;# "> +"22390 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22390: __asm("C1MASK9H equ 01D9h"); +[; <" C1MASK9H equ 01D9h ;# "> +"22466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22466: __asm("C1MASK9U equ 01DAh"); +[; <" C1MASK9U equ 01DAh ;# "> +"22536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22536: __asm("C1MASK9T equ 01DBh"); +[; <" C1MASK9T equ 01DBh ;# "> +"22600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22600: __asm("C1FLTOBJ10 equ 01DCh"); +[; <" C1FLTOBJ10 equ 01DCh ;# "> +"22607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22607: __asm("C1FLTOBJ10L equ 01DCh"); +[; <" C1FLTOBJ10L equ 01DCh ;# "> +"22677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22677: __asm("C1FLTOBJ10H equ 01DDh"); +[; <" C1FLTOBJ10H equ 01DDh ;# "> +"22753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22753: __asm("C1FLTOBJ10U equ 01DEh"); +[; <" C1FLTOBJ10U equ 01DEh ;# "> +"22823 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22823: __asm("C1FLTOBJ10T equ 01DFh"); +[; <" C1FLTOBJ10T equ 01DFh ;# "> +"22887 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22887: __asm("C1MASK10 equ 01E0h"); +[; <" C1MASK10 equ 01E0h ;# "> +"22894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22894: __asm("C1MASK10L equ 01E0h"); +[; <" C1MASK10L equ 01E0h ;# "> +"22964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 22964: __asm("C1MASK10H equ 01E1h"); +[; <" C1MASK10H equ 01E1h ;# "> +"23040 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23040: __asm("C1MASK10U equ 01E2h"); +[; <" C1MASK10U equ 01E2h ;# "> +"23110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23110: __asm("C1MASK10T equ 01E3h"); +[; <" C1MASK10T equ 01E3h ;# "> +"23174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23174: __asm("C1FLTOBJ11 equ 01E4h"); +[; <" C1FLTOBJ11 equ 01E4h ;# "> +"23181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23181: __asm("C1FLTOBJ11L equ 01E4h"); +[; <" C1FLTOBJ11L equ 01E4h ;# "> +"23251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23251: __asm("C1FLTOBJ11H equ 01E5h"); +[; <" C1FLTOBJ11H equ 01E5h ;# "> +"23327 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23327: __asm("C1FLTOBJ11U equ 01E6h"); +[; <" C1FLTOBJ11U equ 01E6h ;# "> +"23397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23397: __asm("C1FLTOBJ11T equ 01E7h"); +[; <" C1FLTOBJ11T equ 01E7h ;# "> +"23461 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23461: __asm("C1MASK11 equ 01E8h"); +[; <" C1MASK11 equ 01E8h ;# "> +"23468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23468: __asm("C1MASK11L equ 01E8h"); +[; <" C1MASK11L equ 01E8h ;# "> +"23538 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23538: __asm("C1MASK11H equ 01E9h"); +[; <" C1MASK11H equ 01E9h ;# "> +"23614 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23614: __asm("C1MASK11U equ 01EAh"); +[; <" C1MASK11U equ 01EAh ;# "> +"23684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23684: __asm("C1MASK11T equ 01EBh"); +[; <" C1MASK11T equ 01EBh ;# "> +"23748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23748: __asm("PPSLOCK equ 0200h"); +[; <" PPSLOCK equ 0200h ;# "> +"23768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23768: __asm("RA0PPS equ 0201h"); +[; <" RA0PPS equ 0201h ;# "> +"23818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23818: __asm("RA1PPS equ 0202h"); +[; <" RA1PPS equ 0202h ;# "> +"23868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23868: __asm("RA2PPS equ 0203h"); +[; <" RA2PPS equ 0203h ;# "> +"23918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23918: __asm("RA3PPS equ 0204h"); +[; <" RA3PPS equ 0204h ;# "> +"23968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 23968: __asm("RA4PPS equ 0205h"); +[; <" RA4PPS equ 0205h ;# "> +"24018 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24018: __asm("RA5PPS equ 0206h"); +[; <" RA5PPS equ 0206h ;# "> +"24068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24068: __asm("RA6PPS equ 0207h"); +[; <" RA6PPS equ 0207h ;# "> +"24118 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24118: __asm("RA7PPS equ 0208h"); +[; <" RA7PPS equ 0208h ;# "> +"24168 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24168: __asm("RB0PPS equ 0209h"); +[; <" RB0PPS equ 0209h ;# "> +"24218 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24218: __asm("RB1PPS equ 020Ah"); +[; <" RB1PPS equ 020Ah ;# "> +"24268 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24268: __asm("RB2PPS equ 020Bh"); +[; <" RB2PPS equ 020Bh ;# "> +"24318 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24318: __asm("RB3PPS equ 020Ch"); +[; <" RB3PPS equ 020Ch ;# "> +"24368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24368: __asm("RB4PPS equ 020Dh"); +[; <" RB4PPS equ 020Dh ;# "> +"24418 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24418: __asm("RB5PPS equ 020Eh"); +[; <" RB5PPS equ 020Eh ;# "> +"24468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24468: __asm("RB6PPS equ 020Fh"); +[; <" RB6PPS equ 020Fh ;# "> +"24518 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24518: __asm("RB7PPS equ 0210h"); +[; <" RB7PPS equ 0210h ;# "> +"24568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24568: __asm("RC0PPS equ 0211h"); +[; <" RC0PPS equ 0211h ;# "> +"24618 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24618: __asm("RC1PPS equ 0212h"); +[; <" RC1PPS equ 0212h ;# "> +"24668 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24668: __asm("RC2PPS equ 0213h"); +[; <" RC2PPS equ 0213h ;# "> +"24718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24718: __asm("RC3PPS equ 0214h"); +[; <" RC3PPS equ 0214h ;# "> +"24768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24768: __asm("RC4PPS equ 0215h"); +[; <" RC4PPS equ 0215h ;# "> +"24818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24818: __asm("RC5PPS equ 0216h"); +[; <" RC5PPS equ 0216h ;# "> +"24868 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24868: __asm("RC6PPS equ 0217h"); +[; <" RC6PPS equ 0217h ;# "> +"24918 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24918: __asm("RC7PPS equ 0218h"); +[; <" RC7PPS equ 0218h ;# "> +"24968 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 24968: __asm("CANRXPPS equ 023Dh"); +[; <" CANRXPPS equ 023Dh ;# "> +"25034 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25034: __asm("INT0PPS equ 023Eh"); +[; <" INT0PPS equ 023Eh ;# "> +"25094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25094: __asm("INT1PPS equ 023Fh"); +[; <" INT1PPS equ 023Fh ;# "> +"25160 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25160: __asm("INT2PPS equ 0240h"); +[; <" INT2PPS equ 0240h ;# "> +"25232 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25232: __asm("T0CKIPPS equ 0241h"); +[; <" T0CKIPPS equ 0241h ;# "> +"25304 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25304: __asm("T1CKIPPS equ 0242h"); +[; <" T1CKIPPS equ 0242h ;# "> +"25376 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25376: __asm("T1GPPS equ 0243h"); +[; <" T1GPPS equ 0243h ;# "> +"25442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25442: __asm("T3CKIPPS equ 0244h"); +[; <" T3CKIPPS equ 0244h ;# "> +"25514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25514: __asm("T3GPPS equ 0245h"); +[; <" T3GPPS equ 0245h ;# "> +"25580 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25580: __asm("T5CKIPPS equ 0246h"); +[; <" T5CKIPPS equ 0246h ;# "> +"25652 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25652: __asm("T5GPPS equ 0247h"); +[; <" T5GPPS equ 0247h ;# "> +"25718 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25718: __asm("T2INPPS equ 0248h"); +[; <" T2INPPS equ 0248h ;# "> +"25784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25784: __asm("T4INPPS equ 0249h"); +[; <" T4INPPS equ 0249h ;# "> +"25850 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25850: __asm("T6INPPS equ 024Ah"); +[; <" T6INPPS equ 024Ah ;# "> +"25916 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25916: __asm("TUIN0PPS equ 024Bh"); +[; <" TUIN0PPS equ 024Bh ;# "> +"25988 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 25988: __asm("TUIN1PPS equ 024Ch"); +[; <" TUIN1PPS equ 024Ch ;# "> +"26060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26060: __asm("TUIN2PPS equ 024Dh"); +[; <" TUIN2PPS equ 024Dh ;# "> +"26126 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26126: __asm("TUIN3PPS equ 024Eh"); +[; <" TUIN3PPS equ 024Eh ;# "> +"26192 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26192: __asm("CCP1PPS equ 024Fh"); +[; <" CCP1PPS equ 024Fh ;# "> +"26264 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26264: __asm("CCP2PPS equ 0250h"); +[; <" CCP2PPS equ 0250h ;# "> +"26336 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26336: __asm("CCP3PPS equ 0251h"); +[; <" CCP3PPS equ 0251h ;# "> +"26402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26402: __asm("PWM1ERSPPS equ 0253h"); +[; <" PWM1ERSPPS equ 0253h ;# "> +"26468 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26468: __asm("PWM2ERSPPS equ 0254h"); +[; <" PWM2ERSPPS equ 0254h ;# "> +"26540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26540: __asm("PWM3ERSPPS equ 0255h"); +[; <" PWM3ERSPPS equ 0255h ;# "> +"26606 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26606: __asm("PWM4ERSPPS equ 0256h"); +[; <" PWM4ERSPPS equ 0256h ;# "> +"26613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26613: __asm("PWMIN0PPS equ 0257h"); +[; <" PWMIN0PPS equ 0257h ;# "> +"26685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26685: __asm("PWMIN1PPS equ 0258h"); +[; <" PWMIN1PPS equ 0258h ;# "> +"26757 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26757: __asm("SMT1WINPPS equ 0259h"); +[; <" SMT1WINPPS equ 0259h ;# "> +"26829 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26829: __asm("SMT1SIGPPS equ 025Ah"); +[; <" SMT1SIGPPS equ 025Ah ;# "> +"26901 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26901: __asm("CWG1PPS equ 025Bh"); +[; <" CWG1PPS equ 025Bh ;# "> +"26906 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 26906: __asm("CWG1INPPS equ 025Bh"); +[; <" CWG1INPPS equ 025Bh ;# "> +"27111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27111: __asm("CWG2PPS equ 025Ch"); +[; <" CWG2PPS equ 025Ch ;# "> +"27116 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27116: __asm("CWG2INPPS equ 025Ch"); +[; <" CWG2INPPS equ 025Ch ;# "> +"27321 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27321: __asm("CWG3PPS equ 025Dh"); +[; <" CWG3PPS equ 025Dh ;# "> +"27326 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27326: __asm("CWG3INPPS equ 025Dh"); +[; <" CWG3INPPS equ 025Dh ;# "> +"27531 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27531: __asm("MD1CARLPPS equ 025Eh"); +[; <" MD1CARLPPS equ 025Eh ;# "> +"27536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27536: __asm("MDCARLPPS equ 025Eh"); +[; <" MDCARLPPS equ 025Eh ;# "> +"27661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27661: __asm("MD1CARHPPS equ 025Fh"); +[; <" MD1CARHPPS equ 025Fh ;# "> +"27666 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27666: __asm("MDCARHPPS equ 025Fh"); +[; <" MDCARHPPS equ 025Fh ;# "> +"27791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27791: __asm("MD1SRCPPS equ 0260h"); +[; <" MD1SRCPPS equ 0260h ;# "> +"27796 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27796: __asm("MDSRCPPS equ 0260h"); +[; <" MDSRCPPS equ 0260h ;# "> +"27921 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27921: __asm("CLCIN0PPS equ 0261h"); +[; <" CLCIN0PPS equ 0261h ;# "> +"27987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 27987: __asm("CLCIN1PPS equ 0262h"); +[; <" CLCIN1PPS equ 0262h ;# "> +"28053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28053: __asm("CLCIN2PPS equ 0263h"); +[; <" CLCIN2PPS equ 0263h ;# "> +"28119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28119: __asm("CLCIN3PPS equ 0264h"); +[; <" CLCIN3PPS equ 0264h ;# "> +"28185 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28185: __asm("CLCIN4PPS equ 0265h"); +[; <" CLCIN4PPS equ 0265h ;# "> +"28251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28251: __asm("CLCIN5PPS equ 0266h"); +[; <" CLCIN5PPS equ 0266h ;# "> +"28317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28317: __asm("CLCIN6PPS equ 0267h"); +[; <" CLCIN6PPS equ 0267h ;# "> +"28383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28383: __asm("CLCIN7PPS equ 0268h"); +[; <" CLCIN7PPS equ 0268h ;# "> +"28449 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28449: __asm("ADACTPPS equ 0269h"); +[; <" ADACTPPS equ 0269h ;# "> +"28515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28515: __asm("SPI1SCKPPS equ 026Ah"); +[; <" SPI1SCKPPS equ 026Ah ;# "> +"28581 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28581: __asm("SPI1SDIPPS equ 026Bh"); +[; <" SPI1SDIPPS equ 026Bh ;# "> +"28647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28647: __asm("SPI1SSPPS equ 026Ch"); +[; <" SPI1SSPPS equ 026Ch ;# "> +"28713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28713: __asm("SPI2SCKPPS equ 026Dh"); +[; <" SPI2SCKPPS equ 026Dh ;# "> +"28779 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28779: __asm("SPI2SDIPPS equ 026Eh"); +[; <" SPI2SDIPPS equ 026Eh ;# "> +"28845 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28845: __asm("SPI2SSPPS equ 026Fh"); +[; <" SPI2SSPPS equ 026Fh ;# "> +"28911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28911: __asm("I2C1SDAPPS equ 0270h"); +[; <" I2C1SDAPPS equ 0270h ;# "> +"28977 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 28977: __asm("I2C1SCLPPS equ 0271h"); +[; <" I2C1SCLPPS equ 0271h ;# "> +"29043 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29043: __asm("U1RXPPS equ 0272h"); +[; <" U1RXPPS equ 0272h ;# "> +"29115 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29115: __asm("U1CTSPPS equ 0273h"); +[; <" U1CTSPPS equ 0273h ;# "> +"29187 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29187: __asm("U2RXPPS equ 0274h"); +[; <" U2RXPPS equ 0274h ;# "> +"29253 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29253: __asm("U2CTSPPS equ 0275h"); +[; <" U2CTSPPS equ 0275h ;# "> +"29319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29319: __asm("U3RXPPS equ 0276h"); +[; <" U3RXPPS equ 0276h ;# "> +"29391 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29391: __asm("U3CTSPPS equ 0277h"); +[; <" U3CTSPPS equ 0277h ;# "> +"29463 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29463: __asm("U4RXPPS equ 0278h"); +[; <" U4RXPPS equ 0278h ;# "> +"29529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29529: __asm("U4CTSPPS equ 0279h"); +[; <" U4CTSPPS equ 0279h ;# "> +"29595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29595: __asm("U5RXPPS equ 027Ah"); +[; <" U5RXPPS equ 027Ah ;# "> +"29667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29667: __asm("U5CTSPPS equ 027Bh"); +[; <" U5CTSPPS equ 027Bh ;# "> +"29739 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29739: __asm("RC4I2C equ 0286h"); +[; <" RC4I2C equ 0286h ;# "> +"29871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 29871: __asm("RC3I2C equ 0287h"); +[; <" RC3I2C equ 0287h ;# "> +"30003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30003: __asm("RB2I2C equ 0288h"); +[; <" RB2I2C equ 0288h ;# "> +"30135 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30135: __asm("RB1I2C equ 0289h"); +[; <" RB1I2C equ 0289h ;# "> +"30267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30267: __asm("I2C1RXB equ 028Ah"); +[; <" I2C1RXB equ 028Ah ;# "> +"30287 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30287: __asm("I2C1TXB equ 028Bh"); +[; <" I2C1TXB equ 028Bh ;# "> +"30307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30307: __asm("I2C1CNTL equ 028Ch"); +[; <" I2C1CNTL equ 028Ch ;# "> +"30377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30377: __asm("I2C1CNTH equ 028Dh"); +[; <" I2C1CNTH equ 028Dh ;# "> +"30447 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30447: __asm("I2C1ADB0 equ 028Eh"); +[; <" I2C1ADB0 equ 028Eh ;# "> +"30467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30467: __asm("I2C1ADB1 equ 028Fh"); +[; <" I2C1ADB1 equ 028Fh ;# "> +"30487 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30487: __asm("I2C1ADR0 equ 0290h"); +[; <" I2C1ADR0 equ 0290h ;# "> +"30507 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30507: __asm("I2C1ADR1 equ 0291h"); +[; <" I2C1ADR1 equ 0291h ;# "> +"30528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30528: __asm("I2C1ADR2 equ 0292h"); +[; <" I2C1ADR2 equ 0292h ;# "> +"30548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30548: __asm("I2C1ADR3 equ 0293h"); +[; <" I2C1ADR3 equ 0293h ;# "> +"30569 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30569: __asm("I2C1CON0 equ 0294h"); +[; <" I2C1CON0 equ 0294h ;# "> +"30646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30646: __asm("I2C1CON1 equ 0295h"); +[; <" I2C1CON1 equ 0295h ;# "> +"30708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30708: __asm("I2C1CON2 equ 0296h"); +[; <" I2C1CON2 equ 0296h ;# "> +"30784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30784: __asm("I2C1ERR equ 0297h"); +[; <" I2C1ERR equ 0297h ;# "> +"30874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30874: __asm("I2C1STAT0 equ 0298h"); +[; <" I2C1STAT0 equ 0298h ;# "> +"30964 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 30964: __asm("I2C1STAT1 equ 0299h"); +[; <" I2C1STAT1 equ 0299h ;# "> +"31011 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31011: __asm("I2C1PIR equ 029Ah"); +[; <" I2C1PIR equ 029Ah ;# "> +"31113 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31113: __asm("I2C1PIE equ 029Bh"); +[; <" I2C1PIE equ 029Bh ;# "> +"31215 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31215: __asm("I2C1BTO equ 029Ch"); +[; <" I2C1BTO equ 029Ch ;# "> +"31285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31285: __asm("I2C1BAUD equ 029Dh"); +[; <" I2C1BAUD equ 029Dh ;# "> +"31305 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31305: __asm("I2C1CLK equ 029Eh"); +[; <" I2C1CLK equ 029Eh ;# "> +"31397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31397: __asm("I2C1BTOC equ 029Fh"); +[; <" I2C1BTOC equ 029Fh ;# "> +"31477 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31477: __asm("U1RXB equ 02A1h"); +[; <" U1RXB equ 02A1h ;# "> +"31482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31482: __asm("U1RXBL equ 02A1h"); +[; <" U1RXBL equ 02A1h ;# "> +"31515 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31515: __asm("U1RXCHK equ 02A2h"); +[; <" U1RXCHK equ 02A2h ;# "> +"31535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31535: __asm("U1TXB equ 02A3h"); +[; <" U1TXB equ 02A3h ;# "> +"31540 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31540: __asm("U1TXBL equ 02A3h"); +[; <" U1TXBL equ 02A3h ;# "> +"31573 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31573: __asm("U1TXCHK equ 02A4h"); +[; <" U1TXCHK equ 02A4h ;# "> +"31593 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31593: __asm("U1P1 equ 02A5h"); +[; <" U1P1 equ 02A5h ;# "> +"31600 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31600: __asm("U1P1L equ 02A5h"); +[; <" U1P1L equ 02A5h ;# "> +"31620 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31620: __asm("U1P1H equ 02A6h"); +[; <" U1P1H equ 02A6h ;# "> +"31640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31640: __asm("U1P2 equ 02A7h"); +[; <" U1P2 equ 02A7h ;# "> +"31647 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31647: __asm("U1P2L equ 02A7h"); +[; <" U1P2L equ 02A7h ;# "> +"31667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31667: __asm("U1P2H equ 02A8h"); +[; <" U1P2H equ 02A8h ;# "> +"31687 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31687: __asm("U1P3 equ 02A9h"); +[; <" U1P3 equ 02A9h ;# "> +"31694 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31694: __asm("U1P3L equ 02A9h"); +[; <" U1P3L equ 02A9h ;# "> +"31714 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31714: __asm("U1P3H equ 02AAh"); +[; <" U1P3H equ 02AAh ;# "> +"31734 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31734: __asm("U1CON0 equ 02ABh"); +[; <" U1CON0 equ 02ABh ;# "> +"31862 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31862: __asm("U1CON1 equ 02ACh"); +[; <" U1CON1 equ 02ACh ;# "> +"31942 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 31942: __asm("U1CON2 equ 02ADh"); +[; <" U1CON2 equ 02ADh ;# "> +"32084 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32084: __asm("U1BRG equ 02AEh"); +[; <" U1BRG equ 02AEh ;# "> +"32091 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32091: __asm("U1BRGL equ 02AEh"); +[; <" U1BRGL equ 02AEh ;# "> +"32111 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32111: __asm("U1BRGH equ 02AFh"); +[; <" U1BRGH equ 02AFh ;# "> +"32131 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32131: __asm("U1FIFO equ 02B0h"); +[; <" U1FIFO equ 02B0h ;# "> +"32261 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32261: __asm("U1UIR equ 02B1h"); +[; <" U1UIR equ 02B1h ;# "> +"32317 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32317: __asm("U1ERRIR equ 02B2h"); +[; <" U1ERRIR equ 02B2h ;# "> +"32429 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32429: __asm("U1ERRIE equ 02B3h"); +[; <" U1ERRIE equ 02B3h ;# "> +"32541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32541: __asm("U2RXB equ 02B4h"); +[; <" U2RXB equ 02B4h ;# "> +"32546 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32546: __asm("U2RXBL equ 02B4h"); +[; <" U2RXBL equ 02B4h ;# "> +"32579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32579: __asm("U2RXCHK equ 02B5h"); +[; <" U2RXCHK equ 02B5h ;# "> +"32599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32599: __asm("U2TXB equ 02B6h"); +[; <" U2TXB equ 02B6h ;# "> +"32604 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32604: __asm("U2TXBL equ 02B6h"); +[; <" U2TXBL equ 02B6h ;# "> +"32637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32637: __asm("U2TXCHK equ 02B7h"); +[; <" U2TXCHK equ 02B7h ;# "> +"32657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32657: __asm("U2P1 equ 02B8h"); +[; <" U2P1 equ 02B8h ;# "> +"32664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32664: __asm("U2P1L equ 02B8h"); +[; <" U2P1L equ 02B8h ;# "> +"32684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32684: __asm("U2P1H equ 02B9h"); +[; <" U2P1H equ 02B9h ;# "> +"32704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32704: __asm("U2P2 equ 02BAh"); +[; <" U2P2 equ 02BAh ;# "> +"32711 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32711: __asm("U2P2L equ 02BAh"); +[; <" U2P2L equ 02BAh ;# "> +"32731 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32731: __asm("U2P2H equ 02BBh"); +[; <" U2P2H equ 02BBh ;# "> +"32751 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32751: __asm("U2P3 equ 02BCh"); +[; <" U2P3 equ 02BCh ;# "> +"32758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32758: __asm("U2P3L equ 02BCh"); +[; <" U2P3L equ 02BCh ;# "> +"32778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32778: __asm("U2P3H equ 02BDh"); +[; <" U2P3H equ 02BDh ;# "> +"32798 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32798: __asm("U2CON0 equ 02BEh"); +[; <" U2CON0 equ 02BEh ;# "> +"32926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 32926: __asm("U2CON1 equ 02BFh"); +[; <" U2CON1 equ 02BFh ;# "> +"33006 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33006: __asm("U2CON2 equ 02C0h"); +[; <" U2CON2 equ 02C0h ;# "> +"33148 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33148: __asm("U2BRG equ 02C1h"); +[; <" U2BRG equ 02C1h ;# "> +"33155 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33155: __asm("U2BRGL equ 02C1h"); +[; <" U2BRGL equ 02C1h ;# "> +"33175 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33175: __asm("U2BRGH equ 02C2h"); +[; <" U2BRGH equ 02C2h ;# "> +"33195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33195: __asm("U2FIFO equ 02C3h"); +[; <" U2FIFO equ 02C3h ;# "> +"33325 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33325: __asm("U2UIR equ 02C4h"); +[; <" U2UIR equ 02C4h ;# "> +"33381 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33381: __asm("U2ERRIR equ 02C5h"); +[; <" U2ERRIR equ 02C5h ;# "> +"33493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33493: __asm("U2ERRIE equ 02C6h"); +[; <" U2ERRIE equ 02C6h ;# "> +"33605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33605: __asm("U3RXB equ 02C7h"); +[; <" U3RXB equ 02C7h ;# "> +"33610 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33610: __asm("U3RXBL equ 02C7h"); +[; <" U3RXBL equ 02C7h ;# "> +"33643 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33643: __asm("U3TXB equ 02C9h"); +[; <" U3TXB equ 02C9h ;# "> +"33648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33648: __asm("U3TXBL equ 02C9h"); +[; <" U3TXBL equ 02C9h ;# "> +"33681 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33681: __asm("U3P1 equ 02CBh"); +[; <" U3P1 equ 02CBh ;# "> +"33688 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33688: __asm("U3P1L equ 02CBh"); +[; <" U3P1L equ 02CBh ;# "> +"33708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33708: __asm("U3P2 equ 02CDh"); +[; <" U3P2 equ 02CDh ;# "> +"33715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33715: __asm("U3P2L equ 02CDh"); +[; <" U3P2L equ 02CDh ;# "> +"33735 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33735: __asm("U3P3 equ 02CFh"); +[; <" U3P3 equ 02CFh ;# "> +"33742 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33742: __asm("U3P3L equ 02CFh"); +[; <" U3P3L equ 02CFh ;# "> +"33762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33762: __asm("U3CON0 equ 02D1h"); +[; <" U3CON0 equ 02D1h ;# "> +"33878 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33878: __asm("U3CON1 equ 02D2h"); +[; <" U3CON1 equ 02D2h ;# "> +"33958 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 33958: __asm("U3CON2 equ 02D3h"); +[; <" U3CON2 equ 02D3h ;# "> +"34090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34090: __asm("U3BRG equ 02D4h"); +[; <" U3BRG equ 02D4h ;# "> +"34097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34097: __asm("U3BRGL equ 02D4h"); +[; <" U3BRGL equ 02D4h ;# "> +"34117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34117: __asm("U3BRGH equ 02D5h"); +[; <" U3BRGH equ 02D5h ;# "> +"34137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34137: __asm("U3FIFO equ 02D6h"); +[; <" U3FIFO equ 02D6h ;# "> +"34267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34267: __asm("U3UIR equ 02D7h"); +[; <" U3UIR equ 02D7h ;# "> +"34323 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34323: __asm("U3ERRIR equ 02D8h"); +[; <" U3ERRIR equ 02D8h ;# "> +"34435 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34435: __asm("U3ERRIE equ 02D9h"); +[; <" U3ERRIE equ 02D9h ;# "> +"34547 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34547: __asm("U4RXB equ 02DAh"); +[; <" U4RXB equ 02DAh ;# "> +"34552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34552: __asm("U4RXBL equ 02DAh"); +[; <" U4RXBL equ 02DAh ;# "> +"34585 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34585: __asm("U4TXB equ 02DCh"); +[; <" U4TXB equ 02DCh ;# "> +"34590 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34590: __asm("U4TXBL equ 02DCh"); +[; <" U4TXBL equ 02DCh ;# "> +"34623 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34623: __asm("U4P1 equ 02DEh"); +[; <" U4P1 equ 02DEh ;# "> +"34630 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34630: __asm("U4P1L equ 02DEh"); +[; <" U4P1L equ 02DEh ;# "> +"34650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34650: __asm("U4P2 equ 02E0h"); +[; <" U4P2 equ 02E0h ;# "> +"34657 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34657: __asm("U4P2L equ 02E0h"); +[; <" U4P2L equ 02E0h ;# "> +"34677 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34677: __asm("U4P3 equ 02E2h"); +[; <" U4P3 equ 02E2h ;# "> +"34684 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34684: __asm("U4P3L equ 02E2h"); +[; <" U4P3L equ 02E2h ;# "> +"34704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34704: __asm("U4CON0 equ 02E4h"); +[; <" U4CON0 equ 02E4h ;# "> +"34820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34820: __asm("U4CON1 equ 02E5h"); +[; <" U4CON1 equ 02E5h ;# "> +"34900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 34900: __asm("U4CON2 equ 02E6h"); +[; <" U4CON2 equ 02E6h ;# "> +"35032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35032: __asm("U4BRG equ 02E7h"); +[; <" U4BRG equ 02E7h ;# "> +"35039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35039: __asm("U4BRGL equ 02E7h"); +[; <" U4BRGL equ 02E7h ;# "> +"35059 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35059: __asm("U4BRGH equ 02E8h"); +[; <" U4BRGH equ 02E8h ;# "> +"35079 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35079: __asm("U4FIFO equ 02E9h"); +[; <" U4FIFO equ 02E9h ;# "> +"35209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35209: __asm("U4UIR equ 02EAh"); +[; <" U4UIR equ 02EAh ;# "> +"35265 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35265: __asm("U4ERRIR equ 02EBh"); +[; <" U4ERRIR equ 02EBh ;# "> +"35377 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35377: __asm("U4ERRIE equ 02ECh"); +[; <" U4ERRIE equ 02ECh ;# "> +"35489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35489: __asm("U5RXB equ 02EDh"); +[; <" U5RXB equ 02EDh ;# "> +"35494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35494: __asm("U5RXBL equ 02EDh"); +[; <" U5RXBL equ 02EDh ;# "> +"35527 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35527: __asm("U5TXB equ 02EFh"); +[; <" U5TXB equ 02EFh ;# "> +"35532 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35532: __asm("U5TXBL equ 02EFh"); +[; <" U5TXBL equ 02EFh ;# "> +"35565 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35565: __asm("U5P1 equ 02F1h"); +[; <" U5P1 equ 02F1h ;# "> +"35572 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35572: __asm("U5P1L equ 02F1h"); +[; <" U5P1L equ 02F1h ;# "> +"35592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35592: __asm("U5P2 equ 02F3h"); +[; <" U5P2 equ 02F3h ;# "> +"35599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35599: __asm("U5P2L equ 02F3h"); +[; <" U5P2L equ 02F3h ;# "> +"35619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35619: __asm("U5P3 equ 02F5h"); +[; <" U5P3 equ 02F5h ;# "> +"35626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35626: __asm("U5P3L equ 02F5h"); +[; <" U5P3L equ 02F5h ;# "> +"35646 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35646: __asm("U5CON0 equ 02F7h"); +[; <" U5CON0 equ 02F7h ;# "> +"35762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35762: __asm("U5CON1 equ 02F8h"); +[; <" U5CON1 equ 02F8h ;# "> +"35842 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35842: __asm("U5CON2 equ 02F9h"); +[; <" U5CON2 equ 02F9h ;# "> +"35974 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35974: __asm("U5BRG equ 02FAh"); +[; <" U5BRG equ 02FAh ;# "> +"35981 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 35981: __asm("U5BRGL equ 02FAh"); +[; <" U5BRGL equ 02FAh ;# "> +"36001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36001: __asm("U5BRGH equ 02FBh"); +[; <" U5BRGH equ 02FBh ;# "> +"36021 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36021: __asm("U5FIFO equ 02FCh"); +[; <" U5FIFO equ 02FCh ;# "> +"36151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36151: __asm("U5UIR equ 02FDh"); +[; <" U5UIR equ 02FDh ;# "> +"36207 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36207: __asm("U5ERRIR equ 02FEh"); +[; <" U5ERRIR equ 02FEh ;# "> +"36319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36319: __asm("U5ERRIE equ 02FFh"); +[; <" U5ERRIE equ 02FFh ;# "> +"36433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36433: __asm("SMT1TMR equ 0300h"); +[; <" SMT1TMR equ 0300h ;# "> +"36440 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36440: __asm("SMT1TMRL equ 0300h"); +[; <" SMT1TMRL equ 0300h ;# "> +"36568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36568: __asm("SMT1TMRH equ 0301h"); +[; <" SMT1TMRH equ 0301h ;# "> +"36696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36696: __asm("SMT1TMRU equ 0302h"); +[; <" SMT1TMRU equ 0302h ;# "> +"36826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36826: __asm("SMT1CPR equ 0303h"); +[; <" SMT1CPR equ 0303h ;# "> +"36833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36833: __asm("SMT1CPRL equ 0303h"); +[; <" SMT1CPRL equ 0303h ;# "> +"36961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 36961: __asm("SMT1CPRH equ 0304h"); +[; <" SMT1CPRH equ 0304h ;# "> +"37089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37089: __asm("SMT1CPRU equ 0305h"); +[; <" SMT1CPRU equ 0305h ;# "> +"37219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37219: __asm("SMT1CPW equ 0306h"); +[; <" SMT1CPW equ 0306h ;# "> +"37226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37226: __asm("SMT1CPWL equ 0306h"); +[; <" SMT1CPWL equ 0306h ;# "> +"37354 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37354: __asm("SMT1CPWH equ 0307h"); +[; <" SMT1CPWH equ 0307h ;# "> +"37482 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37482: __asm("SMT1CPWU equ 0308h"); +[; <" SMT1CPWU equ 0308h ;# "> +"37612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37612: __asm("SMT1PR equ 0309h"); +[; <" SMT1PR equ 0309h ;# "> +"37619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37619: __asm("SMT1PRL equ 0309h"); +[; <" SMT1PRL equ 0309h ;# "> +"37747 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37747: __asm("SMT1PRH equ 030Ah"); +[; <" SMT1PRH equ 030Ah ;# "> +"37875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 37875: __asm("SMT1PRU equ 030Bh"); +[; <" SMT1PRU equ 030Bh ;# "> +"38003 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38003: __asm("SMT1CON0 equ 030Ch"); +[; <" SMT1CON0 equ 030Ch ;# "> +"38121 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38121: __asm("SMT1CON1 equ 030Dh"); +[; <" SMT1CON1 equ 030Dh ;# "> +"38201 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38201: __asm("SMT1STAT equ 030Eh"); +[; <" SMT1STAT equ 030Eh ;# "> +"38300 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38300: __asm("SMT1CLK equ 030Fh"); +[; <" SMT1CLK equ 030Fh ;# "> +"38368 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38368: __asm("SMT1SIG equ 0310h"); +[; <" SMT1SIG equ 0310h ;# "> +"38460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38460: __asm("SMT1WIN equ 0311h"); +[; <" SMT1WIN equ 0311h ;# "> +"38552 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38552: __asm("TMR0L equ 0318h"); +[; <" TMR0L equ 0318h ;# "> +"38557 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38557: __asm("TMR0 equ 0318h"); +[; <" TMR0 equ 0318h ;# "> +"38690 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38690: __asm("TMR0H equ 0319h"); +[; <" TMR0H equ 0319h ;# "> +"38695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38695: __asm("PR0 equ 0319h"); +[; <" PR0 equ 0319h ;# "> +"38944 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 38944: __asm("T0CON0 equ 031Ah"); +[; <" T0CON0 equ 031Ah ;# "> +"39042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39042: __asm("T0CON1 equ 031Bh"); +[; <" T0CON1 equ 031Bh ;# "> +"39184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39184: __asm("TMR1L equ 031Ch"); +[; <" TMR1L equ 031Ch ;# "> +"39254 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39254: __asm("TMR1H equ 031Dh"); +[; <" TMR1H equ 031Dh ;# "> +"39324 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39324: __asm("T1CON equ 031Eh"); +[; <" T1CON equ 031Eh ;# "> +"39329 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39329: __asm("TMR1CON equ 031Eh"); +[; <" TMR1CON equ 031Eh ;# "> +"39514 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39514: __asm("T1GCON equ 031Fh"); +[; <" T1GCON equ 031Fh ;# "> +"39519 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39519: __asm("TMR1GCON equ 031Fh"); +[; <" TMR1GCON equ 031Fh ;# "> +"39728 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39728: __asm("T1GATE equ 0320h"); +[; <" T1GATE equ 0320h ;# "> +"39733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39733: __asm("TMR1GATE equ 0320h"); +[; <" TMR1GATE equ 0320h ;# "> +"39894 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39894: __asm("T1CLK equ 0321h"); +[; <" T1CLK equ 0321h ;# "> +"39899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 39899: __asm("TMR1CLK equ 0321h"); +[; <" TMR1CLK equ 0321h ;# "> +"40060 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40060: __asm("T2TMR equ 0322h"); +[; <" T2TMR equ 0322h ;# "> +"40065 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40065: __asm("TMR2 equ 0322h"); +[; <" TMR2 equ 0322h ;# "> +"40098 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40098: __asm("T2PR equ 0323h"); +[; <" T2PR equ 0323h ;# "> +"40103 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40103: __asm("PR2 equ 0323h"); +[; <" PR2 equ 0323h ;# "> +"40136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40136: __asm("T2CON equ 0324h"); +[; <" T2CON equ 0324h ;# "> +"40282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40282: __asm("T2HLT equ 0325h"); +[; <" T2HLT equ 0325h ;# "> +"40410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40410: __asm("T2CLKCON equ 0326h"); +[; <" T2CLKCON equ 0326h ;# "> +"40415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40415: __asm("T2CLK equ 0326h"); +[; <" T2CLK equ 0326h ;# "> +"40568 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40568: __asm("T2RST equ 0327h"); +[; <" T2RST equ 0327h ;# "> +"40660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40660: __asm("TMR3L equ 0328h"); +[; <" TMR3L equ 0328h ;# "> +"40730 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40730: __asm("TMR3H equ 0329h"); +[; <" TMR3H equ 0329h ;# "> +"40800 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40800: __asm("T3CON equ 032Ah"); +[; <" T3CON equ 032Ah ;# "> +"40805 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40805: __asm("TMR3CON equ 032Ah"); +[; <" TMR3CON equ 032Ah ;# "> +"40990 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40990: __asm("T3GCON equ 032Bh"); +[; <" T3GCON equ 032Bh ;# "> +"40995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 40995: __asm("TMR3GCON equ 032Bh"); +[; <" TMR3GCON equ 032Bh ;# "> +"41204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41204: __asm("T3GATE equ 032Ch"); +[; <" T3GATE equ 032Ch ;# "> +"41209 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41209: __asm("TMR3GATE equ 032Ch"); +[; <" TMR3GATE equ 032Ch ;# "> +"41370 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41370: __asm("T3CLK equ 032Dh"); +[; <" T3CLK equ 032Dh ;# "> +"41375 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41375: __asm("TMR3CLK equ 032Dh"); +[; <" TMR3CLK equ 032Dh ;# "> +"41536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41536: __asm("T4TMR equ 032Eh"); +[; <" T4TMR equ 032Eh ;# "> +"41541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41541: __asm("TMR4 equ 032Eh"); +[; <" TMR4 equ 032Eh ;# "> +"41574 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41574: __asm("T4PR equ 032Fh"); +[; <" T4PR equ 032Fh ;# "> +"41579 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41579: __asm("PR4 equ 032Fh"); +[; <" PR4 equ 032Fh ;# "> +"41612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41612: __asm("T4CON equ 0330h"); +[; <" T4CON equ 0330h ;# "> +"41758 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41758: __asm("T4HLT equ 0331h"); +[; <" T4HLT equ 0331h ;# "> +"41886 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41886: __asm("T4CLKCON equ 0332h"); +[; <" T4CLKCON equ 0332h ;# "> +"41891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 41891: __asm("T4CLK equ 0332h"); +[; <" T4CLK equ 0332h ;# "> +"42044 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42044: __asm("T4RST equ 0333h"); +[; <" T4RST equ 0333h ;# "> +"42136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42136: __asm("TMR5L equ 0334h"); +[; <" TMR5L equ 0334h ;# "> +"42206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42206: __asm("TMR5H equ 0335h"); +[; <" TMR5H equ 0335h ;# "> +"42276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42276: __asm("T5CON equ 0336h"); +[; <" T5CON equ 0336h ;# "> +"42281 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42281: __asm("TMR5CON equ 0336h"); +[; <" TMR5CON equ 0336h ;# "> +"42466 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42466: __asm("T5GCON equ 0337h"); +[; <" T5GCON equ 0337h ;# "> +"42471 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42471: __asm("TMR5GCON equ 0337h"); +[; <" TMR5GCON equ 0337h ;# "> +"42680 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42680: __asm("T5GATE equ 0338h"); +[; <" T5GATE equ 0338h ;# "> +"42685 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42685: __asm("TMR5GATE equ 0338h"); +[; <" TMR5GATE equ 0338h ;# "> +"42846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42846: __asm("T5CLK equ 0339h"); +[; <" T5CLK equ 0339h ;# "> +"42851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 42851: __asm("TMR5CLK equ 0339h"); +[; <" TMR5CLK equ 0339h ;# "> +"43012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43012: __asm("T6TMR equ 033Ah"); +[; <" T6TMR equ 033Ah ;# "> +"43017 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43017: __asm("TMR6 equ 033Ah"); +[; <" TMR6 equ 033Ah ;# "> +"43050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43050: __asm("T6PR equ 033Bh"); +[; <" T6PR equ 033Bh ;# "> +"43055 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43055: __asm("PR6 equ 033Bh"); +[; <" PR6 equ 033Bh ;# "> +"43088 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43088: __asm("T6CON equ 033Ch"); +[; <" T6CON equ 033Ch ;# "> +"43234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43234: __asm("T6HLT equ 033Dh"); +[; <" T6HLT equ 033Dh ;# "> +"43362 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43362: __asm("T6CLKCON equ 033Eh"); +[; <" T6CLKCON equ 033Eh ;# "> +"43367 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43367: __asm("T6CLK equ 033Eh"); +[; <" T6CLK equ 033Eh ;# "> +"43520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43520: __asm("T6RST equ 033Fh"); +[; <" T6RST equ 033Fh ;# "> +"43612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43612: __asm("CCPR1 equ 0340h"); +[; <" CCPR1 equ 0340h ;# "> +"43619 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43619: __asm("CCPR1L equ 0340h"); +[; <" CCPR1L equ 0340h ;# "> +"43639 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43639: __asm("CCPR1H equ 0341h"); +[; <" CCPR1H equ 0341h ;# "> +"43659 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43659: __asm("CCP1CON equ 0342h"); +[; <" CCP1CON equ 0342h ;# "> +"43777 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43777: __asm("CCP1CAP equ 0343h"); +[; <" CCP1CAP equ 0343h ;# "> +"43857 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43857: __asm("CCPR2 equ 0344h"); +[; <" CCPR2 equ 0344h ;# "> +"43864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43864: __asm("CCPR2L equ 0344h"); +[; <" CCPR2L equ 0344h ;# "> +"43884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43884: __asm("CCPR2H equ 0345h"); +[; <" CCPR2H equ 0345h ;# "> +"43904 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 43904: __asm("CCP2CON equ 0346h"); +[; <" CCP2CON equ 0346h ;# "> +"44022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44022: __asm("CCP2CAP equ 0347h"); +[; <" CCP2CAP equ 0347h ;# "> +"44102 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44102: __asm("CCPR3 equ 0348h"); +[; <" CCPR3 equ 0348h ;# "> +"44109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44109: __asm("CCPR3L equ 0348h"); +[; <" CCPR3L equ 0348h ;# "> +"44129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44129: __asm("CCPR3H equ 0349h"); +[; <" CCPR3H equ 0349h ;# "> +"44149 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44149: __asm("CCP3CON equ 034Ah"); +[; <" CCP3CON equ 034Ah ;# "> +"44267 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44267: __asm("CCP3CAP equ 034Bh"); +[; <" CCP3CAP equ 034Bh ;# "> +"44347 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44347: __asm("CCPTMRS0 equ 034Ch"); +[; <" CCPTMRS0 equ 034Ch ;# "> +"44417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44417: __asm("CRCDATA equ 034Fh"); +[; <" CRCDATA equ 034Fh ;# "> +"44424 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44424: __asm("CRCDATAL equ 034Fh"); +[; <" CRCDATAL equ 034Fh ;# "> +"44494 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44494: __asm("CRCDATAH equ 0350h"); +[; <" CRCDATAH equ 0350h ;# "> +"44564 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44564: __asm("CRCDATAU equ 0351h"); +[; <" CRCDATAU equ 0351h ;# "> +"44634 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44634: __asm("CRCDATAT equ 0352h"); +[; <" CRCDATAT equ 0352h ;# "> +"44704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44704: __asm("CRCOUT equ 0353h"); +[; <" CRCOUT equ 0353h ;# "> +"44709 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44709: __asm("CRCSHFT equ 0353h"); +[; <" CRCSHFT equ 0353h ;# "> +"44713 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44713: __asm("CRCXOR equ 0353h"); +[; <" CRCXOR equ 0353h ;# "> +"44720 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44720: __asm("CRCOUTL equ 0353h"); +[; <" CRCOUTL equ 0353h ;# "> +"44790 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44790: __asm("CRCSHFTL equ 0353h"); +[; <" CRCSHFTL equ 0353h ;# "> +"44795 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44795: __asm("CRCSHIFTL equ 0353h"); +[; <" CRCSHIFTL equ 0353h ;# "> +"44928 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44928: __asm("CRCXORL equ 0353h"); +[; <" CRCXORL equ 0353h ;# "> +"44998 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 44998: __asm("CRCOUTH equ 0354h"); +[; <" CRCOUTH equ 0354h ;# "> +"45068 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45068: __asm("CRCSHFTH equ 0354h"); +[; <" CRCSHFTH equ 0354h ;# "> +"45073 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45073: __asm("CRCSHIFTH equ 0354h"); +[; <" CRCSHIFTH equ 0354h ;# "> +"45206 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45206: __asm("CRCXORH equ 0354h"); +[; <" CRCXORH equ 0354h ;# "> +"45276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45276: __asm("CRCOUTU equ 0355h"); +[; <" CRCOUTU equ 0355h ;# "> +"45346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45346: __asm("CRCSHFTU equ 0355h"); +[; <" CRCSHFTU equ 0355h ;# "> +"45351 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45351: __asm("CRCSHIFTU equ 0355h"); +[; <" CRCSHIFTU equ 0355h ;# "> +"45484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45484: __asm("CRCXORU equ 0355h"); +[; <" CRCXORU equ 0355h ;# "> +"45554 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45554: __asm("CRCOUTT equ 0356h"); +[; <" CRCOUTT equ 0356h ;# "> +"45624 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45624: __asm("CRCSHFTT equ 0356h"); +[; <" CRCSHFTT equ 0356h ;# "> +"45629 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45629: __asm("CRCSHIFTT equ 0356h"); +[; <" CRCSHIFTT equ 0356h ;# "> +"45762 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45762: __asm("CRCXORT equ 0356h"); +[; <" CRCXORT equ 0356h ;# "> +"45832 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45832: __asm("CRCCON0 equ 0357h"); +[; <" CRCCON0 equ 0357h ;# "> +"45933 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45933: __asm("CRCCON1 equ 0358h"); +[; <" CRCCON1 equ 0358h ;# "> +"45985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 45985: __asm("CRCCON2 equ 0359h"); +[; <" CRCCON2 equ 0359h ;# "> +"46039 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46039: __asm("SCANLADR equ 035Ah"); +[; <" SCANLADR equ 035Ah ;# "> +"46046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46046: __asm("SCANLADRL equ 035Ah"); +[; <" SCANLADRL equ 035Ah ;# "> +"46174 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46174: __asm("SCANLADRH equ 035Bh"); +[; <" SCANLADRH equ 035Bh ;# "> +"46302 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46302: __asm("SCANLADRU equ 035Ch"); +[; <" SCANLADRU equ 035Ch ;# "> +"46408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46408: __asm("SCANHADR equ 035Dh"); +[; <" SCANHADR equ 035Dh ;# "> +"46415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46415: __asm("SCANHADRL equ 035Dh"); +[; <" SCANHADRL equ 035Dh ;# "> +"46543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46543: __asm("SCANHADRH equ 035Eh"); +[; <" SCANHADRH equ 035Eh ;# "> +"46671 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46671: __asm("SCANHADRU equ 035Fh"); +[; <" SCANHADRU equ 035Fh ;# "> +"46775 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46775: __asm("SCANCON0 equ 0360h"); +[; <" SCANCON0 equ 0360h ;# "> +"46835 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46835: __asm("SCANTRIG equ 0361h"); +[; <" SCANTRIG equ 0361h ;# "> +"46895 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46895: __asm("IPR0 equ 0362h"); +[; <" IPR0 equ 0362h ;# "> +"46957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 46957: __asm("IPR1 equ 0363h"); +[; <" IPR1 equ 0363h ;# "> +"47019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47019: __asm("IPR2 equ 0364h"); +[; <" IPR2 equ 0364h ;# "> +"47089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47089: __asm("IPR3 equ 0365h"); +[; <" IPR3 equ 0365h ;# "> +"47151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47151: __asm("IPR4 equ 0366h"); +[; <" IPR4 equ 0366h ;# "> +"47213 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47213: __asm("IPR5 equ 0367h"); +[; <" IPR5 equ 0367h ;# "> +"47275 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47275: __asm("IPR6 equ 0368h"); +[; <" IPR6 equ 0368h ;# "> +"47337 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47337: __asm("IPR7 equ 0369h"); +[; <" IPR7 equ 0369h ;# "> +"47394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47394: __asm("IPR8 equ 036Ah"); +[; <" IPR8 equ 036Ah ;# "> +"47456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47456: __asm("IPR9 equ 036Bh"); +[; <" IPR9 equ 036Bh ;# "> +"47513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47513: __asm("IPR10 equ 036Ch"); +[; <" IPR10 equ 036Ch ;# "> +"47575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47575: __asm("IPR11 equ 036Dh"); +[; <" IPR11 equ 036Dh ;# "> +"47637 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47637: __asm("IPR12 equ 036Eh"); +[; <" IPR12 equ 036Eh ;# "> +"47699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47699: __asm("IPR13 equ 036Fh"); +[; <" IPR13 equ 036Fh ;# "> +"47761 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47761: __asm("IPR14 equ 0370h"); +[; <" IPR14 equ 0370h ;# "> +"47818 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47818: __asm("IPR15 equ 0371h"); +[; <" IPR15 equ 0371h ;# "> +"47880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47880: __asm("STATUS_CSHAD equ 0373h"); +[; <" STATUS_CSHAD equ 0373h ;# "> +"47969 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47969: __asm("WREG_CSHAD equ 0374h"); +[; <" WREG_CSHAD equ 0374h ;# "> +"47989 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47989: __asm("BSR_CSHAD equ 0375h"); +[; <" BSR_CSHAD equ 0375h ;# "> +"47996 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 47996: __asm("SHADCON equ 0376h"); +[; <" SHADCON equ 0376h ;# "> +"48016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48016: __asm("STATUS_SHAD equ 0377h"); +[; <" STATUS_SHAD equ 0377h ;# "> +"48105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48105: __asm("WREG_SHAD equ 0378h"); +[; <" WREG_SHAD equ 0378h ;# "> +"48125 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48125: __asm("BSR_SHAD equ 0379h"); +[; <" BSR_SHAD equ 0379h ;# "> +"48132 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48132: __asm("PCLATH_SHAD equ 037Ah"); +[; <" PCLATH_SHAD equ 037Ah ;# "> +"48152 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48152: __asm("PCLATU_SHAD equ 037Bh"); +[; <" PCLATU_SHAD equ 037Bh ;# "> +"48172 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48172: __asm("FSR0SH equ 037Ch"); +[; <" FSR0SH equ 037Ch ;# "> +"48179 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48179: __asm("FSR0L_SHAD equ 037Ch"); +[; <" FSR0L_SHAD equ 037Ch ;# "> +"48199 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48199: __asm("FSR0H_SHAD equ 037Dh"); +[; <" FSR0H_SHAD equ 037Dh ;# "> +"48219 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48219: __asm("FSR1SH equ 037Eh"); +[; <" FSR1SH equ 037Eh ;# "> +"48226 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48226: __asm("FSR1L_SHAD equ 037Eh"); +[; <" FSR1L_SHAD equ 037Eh ;# "> +"48246 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48246: __asm("FSR1H_SHAD equ 037Fh"); +[; <" FSR1H_SHAD equ 037Fh ;# "> +"48266 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48266: __asm("FSR2SH equ 0380h"); +[; <" FSR2SH equ 0380h ;# "> +"48273 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48273: __asm("FSR2L_SHAD equ 0380h"); +[; <" FSR2L_SHAD equ 0380h ;# "> +"48293 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48293: __asm("FSR2H_SHAD equ 0381h"); +[; <" FSR2H_SHAD equ 0381h ;# "> +"48313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48313: __asm("PRODSH equ 0382h"); +[; <" PRODSH equ 0382h ;# "> +"48320 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48320: __asm("PRODL_SHAD equ 0382h"); +[; <" PRODL_SHAD equ 0382h ;# "> +"48340 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48340: __asm("PRODH_SHAD equ 0383h"); +[; <" PRODH_SHAD equ 0383h ;# "> +"48360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48360: __asm("TU16ACON0 equ 0387h"); +[; <" TU16ACON0 equ 0387h ;# "> +"48472 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48472: __asm("TU16ACON1 equ 0388h"); +[; <" TU16ACON1 equ 0388h ;# "> +"48584 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48584: __asm("TU16AHLT equ 0389h"); +[; <" TU16AHLT equ 0389h ;# "> +"48736 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48736: __asm("TU16APS equ 038Ah"); +[; <" TU16APS equ 038Ah ;# "> +"48864 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48864: __asm("TU16ATMR equ 038Bh"); +[; <" TU16ATMR equ 038Bh ;# "> +"48869 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48869: __asm("TU16ACR equ 038Bh"); +[; <" TU16ACR equ 038Bh ;# "> +"48876 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 48876: __asm("TU16ATMRL equ 038Bh"); +[; <" TU16ATMRL equ 038Bh ;# "> +"49046 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49046: __asm("TU16ACRL equ 038Bh"); +[; <" TU16ACRL equ 038Bh ;# "> +"49216 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49216: __asm("TU16ATMRH equ 038Ch"); +[; <" TU16ATMRH equ 038Ch ;# "> +"49386 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49386: __asm("TU16ACRH equ 038Ch"); +[; <" TU16ACRH equ 038Ch ;# "> +"49556 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49556: __asm("TU16APR equ 038Dh"); +[; <" TU16APR equ 038Dh ;# "> +"49563 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49563: __asm("TU16APRL equ 038Dh"); +[; <" TU16APRL equ 038Dh ;# "> +"49733 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49733: __asm("TU16APRH equ 038Eh"); +[; <" TU16APRH equ 038Eh ;# "> +"49903 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49903: __asm("TU16ACLK equ 038Fh"); +[; <" TU16ACLK equ 038Fh ;# "> +"49987 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 49987: __asm("TU16AERS equ 0390h"); +[; <" TU16AERS equ 0390h ;# "> +"50083 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50083: __asm("TU16BCON0 equ 0393h"); +[; <" TU16BCON0 equ 0393h ;# "> +"50195 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50195: __asm("TU16BCON1 equ 0394h"); +[; <" TU16BCON1 equ 0394h ;# "> +"50307 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50307: __asm("TU16BHLT equ 0395h"); +[; <" TU16BHLT equ 0395h ;# "> +"50459 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50459: __asm("TU16BPS equ 0396h"); +[; <" TU16BPS equ 0396h ;# "> +"50587 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50587: __asm("TU16BTMR equ 0397h"); +[; <" TU16BTMR equ 0397h ;# "> +"50592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50592: __asm("TU16BCR equ 0397h"); +[; <" TU16BCR equ 0397h ;# "> +"50599 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50599: __asm("TU16BTMRL equ 0397h"); +[; <" TU16BTMRL equ 0397h ;# "> +"50769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50769: __asm("TU16BCRL equ 0397h"); +[; <" TU16BCRL equ 0397h ;# "> +"50939 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 50939: __asm("TU16BTMRH equ 0398h"); +[; <" TU16BTMRH equ 0398h ;# "> +"51109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51109: __asm("TU16BCRH equ 0398h"); +[; <" TU16BCRH equ 0398h ;# "> +"51279 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51279: __asm("TU16BPR equ 0399h"); +[; <" TU16BPR equ 0399h ;# "> +"51286 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51286: __asm("TU16BPRL equ 0399h"); +[; <" TU16BPRL equ 0399h ;# "> +"51456 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51456: __asm("TU16BPRH equ 039Ah"); +[; <" TU16BPRH equ 039Ah ;# "> +"51626 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51626: __asm("TU16BCLK equ 039Bh"); +[; <" TU16BCLK equ 039Bh ;# "> +"51710 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51710: __asm("TU16BERS equ 039Ch"); +[; <" TU16BERS equ 039Ch ;# "> +"51806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51806: __asm("TUCHAIN equ 03BBh"); +[; <" TUCHAIN equ 03BBh ;# "> +"51826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51826: __asm("CWG1CLK equ 03BCh"); +[; <" CWG1CLK equ 03BCh ;# "> +"51831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51831: __asm("CWG1CLKCON equ 03BCh"); +[; <" CWG1CLKCON equ 03BCh ;# "> +"51880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51880: __asm("CWG1ISM equ 03BDh"); +[; <" CWG1ISM equ 03BDh ;# "> +"51926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 51926: __asm("CWG1DBR equ 03BEh"); +[; <" CWG1DBR equ 03BEh ;# "> +"52030 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52030: __asm("CWG1DBF equ 03BFh"); +[; <" CWG1DBF equ 03BFh ;# "> +"52134 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52134: __asm("CWG1CON0 equ 03C0h"); +[; <" CWG1CON0 equ 03C0h ;# "> +"52235 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52235: __asm("CWG1CON1 equ 03C1h"); +[; <" CWG1CON1 equ 03C1h ;# "> +"52313 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52313: __asm("CWG1AS0 equ 03C2h"); +[; <" CWG1AS0 equ 03C2h ;# "> +"52433 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52433: __asm("CWG1AS1 equ 03C3h"); +[; <" CWG1AS1 equ 03C3h ;# "> +"52495 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52495: __asm("CWG1STR equ 03C4h"); +[; <" CWG1STR equ 03C4h ;# "> +"52607 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52607: __asm("CWG2CLK equ 03C5h"); +[; <" CWG2CLK equ 03C5h ;# "> +"52612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52612: __asm("CWG2CLKCON equ 03C5h"); +[; <" CWG2CLKCON equ 03C5h ;# "> +"52661 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52661: __asm("CWG2ISM equ 03C6h"); +[; <" CWG2ISM equ 03C6h ;# "> +"52707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52707: __asm("CWG2DBR equ 03C7h"); +[; <" CWG2DBR equ 03C7h ;# "> +"52811 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52811: __asm("CWG2DBF equ 03C8h"); +[; <" CWG2DBF equ 03C8h ;# "> +"52915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 52915: __asm("CWG2CON0 equ 03C9h"); +[; <" CWG2CON0 equ 03C9h ;# "> +"53016 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53016: __asm("CWG2CON1 equ 03CAh"); +[; <" CWG2CON1 equ 03CAh ;# "> +"53094 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53094: __asm("CWG2AS0 equ 03CBh"); +[; <" CWG2AS0 equ 03CBh ;# "> +"53214 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53214: __asm("CWG2AS1 equ 03CCh"); +[; <" CWG2AS1 equ 03CCh ;# "> +"53276 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53276: __asm("CWG2STR equ 03CDh"); +[; <" CWG2STR equ 03CDh ;# "> +"53388 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53388: __asm("CWG3CLK equ 03CEh"); +[; <" CWG3CLK equ 03CEh ;# "> +"53393 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53393: __asm("CWG3CLKCON equ 03CEh"); +[; <" CWG3CLKCON equ 03CEh ;# "> +"53442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53442: __asm("CWG3ISM equ 03CFh"); +[; <" CWG3ISM equ 03CFh ;# "> +"53488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53488: __asm("CWG3DBR equ 03D0h"); +[; <" CWG3DBR equ 03D0h ;# "> +"53592 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53592: __asm("CWG3DBF equ 03D1h"); +[; <" CWG3DBF equ 03D1h ;# "> +"53696 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53696: __asm("CWG3CON0 equ 03D2h"); +[; <" CWG3CON0 equ 03D2h ;# "> +"53797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53797: __asm("CWG3CON1 equ 03D3h"); +[; <" CWG3CON1 equ 03D3h ;# "> +"53875 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53875: __asm("CWG3AS0 equ 03D4h"); +[; <" CWG3AS0 equ 03D4h ;# "> +"53995 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 53995: __asm("CWG3AS1 equ 03D5h"); +[; <" CWG3AS1 equ 03D5h ;# "> +"54057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54057: __asm("CWG3STR equ 03D6h"); +[; <" CWG3STR equ 03D6h ;# "> +"54169 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54169: __asm("FVRCON equ 03D7h"); +[; <" FVRCON equ 03D7h ;# "> +"54258 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54258: __asm("ADCPCON equ 03D8h"); +[; <" ADCPCON equ 03D8h ;# "> +"54263 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54263: __asm("ADCP equ 03D8h"); +[; <" ADCP equ 03D8h ;# "> +"54358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54358: __asm("ADLTH equ 03D9h"); +[; <" ADLTH equ 03D9h ;# "> +"54365 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54365: __asm("ADLTHL equ 03D9h"); +[; <" ADLTHL equ 03D9h ;# "> +"54493 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54493: __asm("ADLTHH equ 03DAh"); +[; <" ADLTHH equ 03DAh ;# "> +"54621 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54621: __asm("ADUTH equ 03DBh"); +[; <" ADUTH equ 03DBh ;# "> +"54628 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54628: __asm("ADUTHL equ 03DBh"); +[; <" ADUTHL equ 03DBh ;# "> +"54756 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54756: __asm("ADUTHH equ 03DCh"); +[; <" ADUTHH equ 03DCh ;# "> +"54884 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54884: __asm("ADERR equ 03DDh"); +[; <" ADERR equ 03DDh ;# "> +"54891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 54891: __asm("ADERRL equ 03DDh"); +[; <" ADERRL equ 03DDh ;# "> +"55019 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55019: __asm("ADERRH equ 03DEh"); +[; <" ADERRH equ 03DEh ;# "> +"55147 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55147: __asm("ADSTPT equ 03DFh"); +[; <" ADSTPT equ 03DFh ;# "> +"55154 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55154: __asm("ADSTPTL equ 03DFh"); +[; <" ADSTPTL equ 03DFh ;# "> +"55282 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55282: __asm("ADSTPTH equ 03E0h"); +[; <" ADSTPTH equ 03E0h ;# "> +"55410 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55410: __asm("ADFLTR equ 03E1h"); +[; <" ADFLTR equ 03E1h ;# "> +"55417 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55417: __asm("ADFLTRL equ 03E1h"); +[; <" ADFLTRL equ 03E1h ;# "> +"55545 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55545: __asm("ADFLTRH equ 03E2h"); +[; <" ADFLTRH equ 03E2h ;# "> +"55675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55675: __asm("ADACC equ 03E3h"); +[; <" ADACC equ 03E3h ;# "> +"55682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55682: __asm("ADACCL equ 03E3h"); +[; <" ADACCL equ 03E3h ;# "> +"55810 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55810: __asm("ADACCH equ 03E4h"); +[; <" ADACCH equ 03E4h ;# "> +"55938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55938: __asm("ADACCU equ 03E5h"); +[; <" ADACCU equ 03E5h ;# "> +"55994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 55994: __asm("ADCNT equ 03E6h"); +[; <" ADCNT equ 03E6h ;# "> +"56122 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56122: __asm("ADRPT equ 03E7h"); +[; <" ADRPT equ 03E7h ;# "> +"56250 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56250: __asm("ADPREV equ 03E8h"); +[; <" ADPREV equ 03E8h ;# "> +"56257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56257: __asm("ADPREVL equ 03E8h"); +[; <" ADPREVL equ 03E8h ;# "> +"56385 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56385: __asm("ADPREVH equ 03E9h"); +[; <" ADPREVH equ 03E9h ;# "> +"56513 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56513: __asm("ADRES equ 03EAh"); +[; <" ADRES equ 03EAh ;# "> +"56520 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56520: __asm("ADRESL equ 03EAh"); +[; <" ADRESL equ 03EAh ;# "> +"56648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56648: __asm("ADRESH equ 03EBh"); +[; <" ADRESH equ 03EBh ;# "> +"56768 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56768: __asm("ADPCH equ 03ECh"); +[; <" ADPCH equ 03ECh ;# "> +"56826 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56826: __asm("ADACQ equ 03EEh"); +[; <" ADACQ equ 03EEh ;# "> +"56833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56833: __asm("ADACQL equ 03EEh"); +[; <" ADACQL equ 03EEh ;# "> +"56961 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 56961: __asm("ADACQH equ 03EFh"); +[; <" ADACQH equ 03EFh ;# "> +"57053 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57053: __asm("ADCAP equ 03F0h"); +[; <" ADCAP equ 03F0h ;# "> +"57105 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57105: __asm("ADPRE equ 03F1h"); +[; <" ADPRE equ 03F1h ;# "> +"57112 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57112: __asm("ADPREL equ 03F1h"); +[; <" ADPREL equ 03F1h ;# "> +"57240 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57240: __asm("ADPREH equ 03F2h"); +[; <" ADPREH equ 03F2h ;# "> +"57332 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57332: __asm("ADCON0 equ 03F3h"); +[; <" ADCON0 equ 03F3h ;# "> +"57460 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57460: __asm("ADCON1 equ 03F4h"); +[; <" ADCON1 equ 03F4h ;# "> +"57526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57526: __asm("ADCON2 equ 03F5h"); +[; <" ADCON2 equ 03F5h ;# "> +"57704 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57704: __asm("ADCON3 equ 03F6h"); +[; <" ADCON3 equ 03F6h ;# "> +"57834 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57834: __asm("ADSTAT equ 03F7h"); +[; <" ADSTAT equ 03F7h ;# "> +"57959 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 57959: __asm("ADREF equ 03F8h"); +[; <" ADREF equ 03F8h ;# "> +"58041 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58041: __asm("ADACT equ 03F9h"); +[; <" ADACT equ 03F9h ;# "> +"58145 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58145: __asm("ADCLK equ 03FAh"); +[; <" ADCLK equ 03FAh ;# "> +"58249 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58249: __asm("ADCTX equ 03FBh"); +[; <" ADCTX equ 03FBh ;# "> +"58319 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58319: __asm("ADCSEL1 equ 03FCh"); +[; <" ADCSEL1 equ 03FCh ;# "> +"58346 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58346: __asm("ADCSEL2 equ 03FDh"); +[; <" ADCSEL2 equ 03FDh ;# "> +"58373 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58373: __asm("ADCSEL3 equ 03FEh"); +[; <" ADCSEL3 equ 03FEh ;# "> +"58400 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58400: __asm("ADCSEL4 equ 03FFh"); +[; <" ADCSEL4 equ 03FFh ;# "> +"58427 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58427: __asm("ANSELA equ 0400h"); +[; <" ANSELA equ 0400h ;# "> +"58489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58489: __asm("WPUA equ 0401h"); +[; <" WPUA equ 0401h ;# "> +"58551 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58551: __asm("ODCONA equ 0402h"); +[; <" ODCONA equ 0402h ;# "> +"58613 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58613: __asm("SLRCONA equ 0403h"); +[; <" SLRCONA equ 0403h ;# "> +"58675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58675: __asm("INLVLA equ 0404h"); +[; <" INLVLA equ 0404h ;# "> +"58737 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58737: __asm("IOCAP equ 0405h"); +[; <" IOCAP equ 0405h ;# "> +"58799 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58799: __asm("IOCAN equ 0406h"); +[; <" IOCAN equ 0406h ;# "> +"58861 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58861: __asm("IOCAF equ 0407h"); +[; <" IOCAF equ 0407h ;# "> +"58923 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58923: __asm("ANSELB equ 0408h"); +[; <" ANSELB equ 0408h ;# "> +"58985 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 58985: __asm("WPUB equ 0409h"); +[; <" WPUB equ 0409h ;# "> +"59047 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59047: __asm("ODCONB equ 040Ah"); +[; <" ODCONB equ 040Ah ;# "> +"59109 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59109: __asm("SLRCONB equ 040Bh"); +[; <" SLRCONB equ 040Bh ;# "> +"59171 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59171: __asm("INLVLB equ 040Ch"); +[; <" INLVLB equ 040Ch ;# "> +"59233 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59233: __asm("IOCBP equ 040Dh"); +[; <" IOCBP equ 040Dh ;# "> +"59295 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59295: __asm("IOCBN equ 040Eh"); +[; <" IOCBN equ 040Eh ;# "> +"59357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59357: __asm("IOCBF equ 040Fh"); +[; <" IOCBF equ 040Fh ;# "> +"59419 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59419: __asm("ANSELC equ 0410h"); +[; <" ANSELC equ 0410h ;# "> +"59481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59481: __asm("WPUC equ 0411h"); +[; <" WPUC equ 0411h ;# "> +"59543 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59543: __asm("ODCONC equ 0412h"); +[; <" ODCONC equ 0412h ;# "> +"59605 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59605: __asm("SLRCONC equ 0413h"); +[; <" SLRCONC equ 0413h ;# "> +"59667 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59667: __asm("INLVLC equ 0414h"); +[; <" INLVLC equ 0414h ;# "> +"59729 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59729: __asm("IOCCP equ 0415h"); +[; <" IOCCP equ 0415h ;# "> +"59791 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59791: __asm("IOCCN equ 0416h"); +[; <" IOCCN equ 0416h ;# "> +"59853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59853: __asm("IOCCF equ 0417h"); +[; <" IOCCF equ 0417h ;# "> +"59915 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59915: __asm("WPUE equ 0421h"); +[; <" WPUE equ 0421h ;# "> +"59936 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59936: __asm("INLVLE equ 0424h"); +[; <" INLVLE equ 0424h ;# "> +"59957 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59957: __asm("IOCEP equ 0425h"); +[; <" IOCEP equ 0425h ;# "> +"59978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59978: __asm("IOCEN equ 0426h"); +[; <" IOCEN equ 0426h ;# "> +"59999 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 59999: __asm("IOCEF equ 0427h"); +[; <" IOCEF equ 0427h ;# "> +"60022 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60022: __asm("NCO1ACC equ 0440h"); +[; <" NCO1ACC equ 0440h ;# "> +"60029 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60029: __asm("NCO1ACCL equ 0440h"); +[; <" NCO1ACCL equ 0440h ;# "> +"60157 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60157: __asm("NCO1ACCH equ 0441h"); +[; <" NCO1ACCH equ 0441h ;# "> +"60285 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60285: __asm("NCO1ACCU equ 0442h"); +[; <" NCO1ACCU equ 0442h ;# "> +"60415 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60415: __asm("NCO1INC equ 0443h"); +[; <" NCO1INC equ 0443h ;# "> +"60422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60422: __asm("NCO1INCL equ 0443h"); +[; <" NCO1INCL equ 0443h ;# "> +"60550 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60550: __asm("NCO1INCH equ 0444h"); +[; <" NCO1INCH equ 0444h ;# "> +"60678 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60678: __asm("NCO1INCU equ 0445h"); +[; <" NCO1INCU equ 0445h ;# "> +"60806 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60806: __asm("NCO1CON equ 0446h"); +[; <" NCO1CON equ 0446h ;# "> +"60874 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 60874: __asm("NCO1CLK equ 0447h"); +[; <" NCO1CLK equ 0447h ;# "> +"61008 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61008: __asm("NCO2ACC equ 0448h"); +[; <" NCO2ACC equ 0448h ;# "> +"61015 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61015: __asm("NCO2ACCL equ 0448h"); +[; <" NCO2ACCL equ 0448h ;# "> +"61143 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61143: __asm("NCO2ACCH equ 0449h"); +[; <" NCO2ACCH equ 0449h ;# "> +"61271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61271: __asm("NCO2ACCU equ 044Ah"); +[; <" NCO2ACCU equ 044Ah ;# "> +"61401 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61401: __asm("NCO2INC equ 044Bh"); +[; <" NCO2INC equ 044Bh ;# "> +"61408 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61408: __asm("NCO2INCL equ 044Bh"); +[; <" NCO2INCL equ 044Bh ;# "> +"61536 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61536: __asm("NCO2INCH equ 044Ch"); +[; <" NCO2INCH equ 044Ch ;# "> +"61664 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61664: __asm("NCO2INCU equ 044Dh"); +[; <" NCO2INCU equ 044Dh ;# "> +"61792 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61792: __asm("NCO2CON equ 044Eh"); +[; <" NCO2CON equ 044Eh ;# "> +"61860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61860: __asm("NCO2CLK equ 044Fh"); +[; <" NCO2CLK equ 044Fh ;# "> +"61994 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 61994: __asm("NCO3ACC equ 0450h"); +[; <" NCO3ACC equ 0450h ;# "> +"62001 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62001: __asm("NCO3ACCL equ 0450h"); +[; <" NCO3ACCL equ 0450h ;# "> +"62129 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62129: __asm("NCO3ACCH equ 0451h"); +[; <" NCO3ACCH equ 0451h ;# "> +"62257 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62257: __asm("NCO3ACCU equ 0452h"); +[; <" NCO3ACCU equ 0452h ;# "> +"62387 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62387: __asm("NCO3INC equ 0453h"); +[; <" NCO3INC equ 0453h ;# "> +"62394 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62394: __asm("NCO3INCL equ 0453h"); +[; <" NCO3INCL equ 0453h ;# "> +"62522 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62522: __asm("NCO3INCH equ 0454h"); +[; <" NCO3INCH equ 0454h ;# "> +"62650 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62650: __asm("NCO3INCU equ 0455h"); +[; <" NCO3INCU equ 0455h ;# "> +"62778 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62778: __asm("NCO3CON equ 0456h"); +[; <" NCO3CON equ 0456h ;# "> +"62846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62846: __asm("NCO3CLK equ 0457h"); +[; <" NCO3CLK equ 0457h ;# "> +"62978 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 62978: __asm("FSCMCON equ 0458h"); +[; <" FSCMCON equ 0458h ;# "> +"63028 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63028: __asm("IVTLOCK equ 0459h"); +[; <" IVTLOCK equ 0459h ;# "> +"63050 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63050: __asm("IVTAD equ 045Ah"); +[; <" IVTAD equ 045Ah ;# "> +"63057 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63057: __asm("IVTADL equ 045Ah"); +[; <" IVTADL equ 045Ah ;# "> +"63119 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63119: __asm("IVTADH equ 045Bh"); +[; <" IVTADH equ 045Bh ;# "> +"63181 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63181: __asm("IVTADU equ 045Ch"); +[; <" IVTADU equ 045Ch ;# "> +"63227 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63227: __asm("IVTBASE equ 045Dh"); +[; <" IVTBASE equ 045Dh ;# "> +"63234 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63234: __asm("IVTBASEL equ 045Dh"); +[; <" IVTBASEL equ 045Dh ;# "> +"63296 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63296: __asm("IVTBASEH equ 045Eh"); +[; <" IVTBASEH equ 045Eh ;# "> +"63358 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63358: __asm("IVTBASEU equ 045Fh"); +[; <" IVTBASEU equ 045Fh ;# "> +"63402 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63402: __asm("PWM1ERS equ 0460h"); +[; <" PWM1ERS equ 0460h ;# "> +"63422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63422: __asm("PWM1CLK equ 0461h"); +[; <" PWM1CLK equ 0461h ;# "> +"63442 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63442: __asm("PWM1LDS equ 0462h"); +[; <" PWM1LDS equ 0462h ;# "> +"63462 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63462: __asm("PWM1PR equ 0463h"); +[; <" PWM1PR equ 0463h ;# "> +"63469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63469: __asm("PWM1PRL equ 0463h"); +[; <" PWM1PRL equ 0463h ;# "> +"63489 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63489: __asm("PWM1PRH equ 0464h"); +[; <" PWM1PRH equ 0464h ;# "> +"63509 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63509: __asm("PWM1CPRE equ 0465h"); +[; <" PWM1CPRE equ 0465h ;# "> +"63529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63529: __asm("PWM1PIPOS equ 0466h"); +[; <" PWM1PIPOS equ 0466h ;# "> +"63549 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63549: __asm("PWM1GIR equ 0467h"); +[; <" PWM1GIR equ 0467h ;# "> +"63575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63575: __asm("PWM1GIE equ 0468h"); +[; <" PWM1GIE equ 0468h ;# "> +"63601 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63601: __asm("PWM1CON equ 0469h"); +[; <" PWM1CON equ 0469h ;# "> +"63640 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63640: __asm("PWM1S1CFG equ 046Ah"); +[; <" PWM1S1CFG equ 046Ah ;# "> +"63699 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63699: __asm("PWM1S1P1 equ 046Bh"); +[; <" PWM1S1P1 equ 046Bh ;# "> +"63706 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63706: __asm("PWM1S1P1L equ 046Bh"); +[; <" PWM1S1P1L equ 046Bh ;# "> +"63726 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63726: __asm("PWM1S1P1H equ 046Ch"); +[; <" PWM1S1P1H equ 046Ch ;# "> +"63746 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63746: __asm("PWM1S1P2 equ 046Dh"); +[; <" PWM1S1P2 equ 046Dh ;# "> +"63753 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63753: __asm("PWM1S1P2L equ 046Dh"); +[; <" PWM1S1P2L equ 046Dh ;# "> +"63773 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63773: __asm("PWM1S1P2H equ 046Eh"); +[; <" PWM1S1P2H equ 046Eh ;# "> +"63793 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63793: __asm("PWM2ERS equ 046Fh"); +[; <" PWM2ERS equ 046Fh ;# "> +"63813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63813: __asm("PWM2CLK equ 0470h"); +[; <" PWM2CLK equ 0470h ;# "> +"63833 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63833: __asm("PWM2LDS equ 0471h"); +[; <" PWM2LDS equ 0471h ;# "> +"63853 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63853: __asm("PWM2PR equ 0472h"); +[; <" PWM2PR equ 0472h ;# "> +"63860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63860: __asm("PWM2PRL equ 0472h"); +[; <" PWM2PRL equ 0472h ;# "> +"63880 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63880: __asm("PWM2PRH equ 0473h"); +[; <" PWM2PRH equ 0473h ;# "> +"63900 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63900: __asm("PWM2CPRE equ 0474h"); +[; <" PWM2CPRE equ 0474h ;# "> +"63920 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63920: __asm("PWM2PIPOS equ 0475h"); +[; <" PWM2PIPOS equ 0475h ;# "> +"63940 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63940: __asm("PWM2GIR equ 0476h"); +[; <" PWM2GIR equ 0476h ;# "> +"63966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63966: __asm("PWM2GIE equ 0477h"); +[; <" PWM2GIE equ 0477h ;# "> +"63992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 63992: __asm("PWM2CON equ 0478h"); +[; <" PWM2CON equ 0478h ;# "> +"64031 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64031: __asm("PWM2S1CFG equ 0479h"); +[; <" PWM2S1CFG equ 0479h ;# "> +"64090 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64090: __asm("PWM2S1P1 equ 047Ah"); +[; <" PWM2S1P1 equ 047Ah ;# "> +"64097 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64097: __asm("PWM2S1P1L equ 047Ah"); +[; <" PWM2S1P1L equ 047Ah ;# "> +"64117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64117: __asm("PWM2S1P1H equ 047Bh"); +[; <" PWM2S1P1H equ 047Bh ;# "> +"64137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64137: __asm("PWM2S1P2 equ 047Ch"); +[; <" PWM2S1P2 equ 047Ch ;# "> +"64144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64144: __asm("PWM2S1P2L equ 047Ch"); +[; <" PWM2S1P2L equ 047Ch ;# "> +"64164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64164: __asm("PWM2S1P2H equ 047Dh"); +[; <" PWM2S1P2H equ 047Dh ;# "> +"64184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64184: __asm("PWM3ERS equ 047Eh"); +[; <" PWM3ERS equ 047Eh ;# "> +"64204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64204: __asm("PWM3CLK equ 047Fh"); +[; <" PWM3CLK equ 047Fh ;# "> +"64224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64224: __asm("PWM3LDS equ 0480h"); +[; <" PWM3LDS equ 0480h ;# "> +"64244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64244: __asm("PWM3PR equ 0481h"); +[; <" PWM3PR equ 0481h ;# "> +"64251 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64251: __asm("PWM3PRL equ 0481h"); +[; <" PWM3PRL equ 0481h ;# "> +"64271 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64271: __asm("PWM3PRH equ 0482h"); +[; <" PWM3PRH equ 0482h ;# "> +"64291 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64291: __asm("PWM3CPRE equ 0483h"); +[; <" PWM3CPRE equ 0483h ;# "> +"64311 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64311: __asm("PWM3PIPOS equ 0484h"); +[; <" PWM3PIPOS equ 0484h ;# "> +"64331 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64331: __asm("PWM3GIR equ 0485h"); +[; <" PWM3GIR equ 0485h ;# "> +"64357 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64357: __asm("PWM3GIE equ 0486h"); +[; <" PWM3GIE equ 0486h ;# "> +"64383 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64383: __asm("PWM3CON equ 0487h"); +[; <" PWM3CON equ 0487h ;# "> +"64422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64422: __asm("PWM3S1CFG equ 0488h"); +[; <" PWM3S1CFG equ 0488h ;# "> +"64481 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64481: __asm("PWM3S1P1 equ 0489h"); +[; <" PWM3S1P1 equ 0489h ;# "> +"64488 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64488: __asm("PWM3S1P1L equ 0489h"); +[; <" PWM3S1P1L equ 0489h ;# "> +"64508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64508: __asm("PWM3S1P1H equ 048Ah"); +[; <" PWM3S1P1H equ 048Ah ;# "> +"64528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64528: __asm("PWM3S1P2 equ 048Bh"); +[; <" PWM3S1P2 equ 048Bh ;# "> +"64535 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64535: __asm("PWM3S1P2L equ 048Bh"); +[; <" PWM3S1P2L equ 048Bh ;# "> +"64555 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64555: __asm("PWM3S1P2H equ 048Ch"); +[; <" PWM3S1P2H equ 048Ch ;# "> +"64575 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64575: __asm("PWM4ERS equ 048Dh"); +[; <" PWM4ERS equ 048Dh ;# "> +"64595 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64595: __asm("PWM4CLK equ 048Eh"); +[; <" PWM4CLK equ 048Eh ;# "> +"64615 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64615: __asm("PWM4LDS equ 048Fh"); +[; <" PWM4LDS equ 048Fh ;# "> +"64635 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64635: __asm("PWM4PR equ 0490h"); +[; <" PWM4PR equ 0490h ;# "> +"64642 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64642: __asm("PWM4PRL equ 0490h"); +[; <" PWM4PRL equ 0490h ;# "> +"64662 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64662: __asm("PWM4PRH equ 0491h"); +[; <" PWM4PRH equ 0491h ;# "> +"64682 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64682: __asm("PWM4CPRE equ 0492h"); +[; <" PWM4CPRE equ 0492h ;# "> +"64702 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64702: __asm("PWM4PIPOS equ 0493h"); +[; <" PWM4PIPOS equ 0493h ;# "> +"64722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64722: __asm("PWM4GIR equ 0494h"); +[; <" PWM4GIR equ 0494h ;# "> +"64748 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64748: __asm("PWM4GIE equ 0495h"); +[; <" PWM4GIE equ 0495h ;# "> +"64774 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64774: __asm("PWM4CON equ 0496h"); +[; <" PWM4CON equ 0496h ;# "> +"64813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64813: __asm("PWM4S1CFG equ 0497h"); +[; <" PWM4S1CFG equ 0497h ;# "> +"64872 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64872: __asm("PWM4S1P1 equ 0498h"); +[; <" PWM4S1P1 equ 0498h ;# "> +"64879 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64879: __asm("PWM4S1P1L equ 0498h"); +[; <" PWM4S1P1L equ 0498h ;# "> +"64899 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64899: __asm("PWM4S1P1H equ 0499h"); +[; <" PWM4S1P1H equ 0499h ;# "> +"64919 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64919: __asm("PWM4S1P2 equ 049Ah"); +[; <" PWM4S1P2 equ 049Ah ;# "> +"64926 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64926: __asm("PWM4S1P2L equ 049Ah"); +[; <" PWM4S1P2L equ 049Ah ;# "> +"64946 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64946: __asm("PWM4S1P2H equ 049Bh"); +[; <" PWM4S1P2H equ 049Bh ;# "> +"64966 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 64966: __asm("PWMLOAD equ 049Ch"); +[; <" PWMLOAD equ 049Ch ;# "> +"65004 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65004: __asm("PWMEN equ 049Dh"); +[; <" PWMEN equ 049Dh ;# "> +"65042 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65042: __asm("PIE0 equ 049Eh"); +[; <" PIE0 equ 049Eh ;# "> +"65104 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65104: __asm("PIE1 equ 049Fh"); +[; <" PIE1 equ 049Fh ;# "> +"65166 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65166: __asm("PIE2 equ 04A0h"); +[; <" PIE2 equ 04A0h ;# "> +"65236 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65236: __asm("PIE3 equ 04A1h"); +[; <" PIE3 equ 04A1h ;# "> +"65298 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65298: __asm("PIE4 equ 04A2h"); +[; <" PIE4 equ 04A2h ;# "> +"65360 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65360: __asm("PIE5 equ 04A3h"); +[; <" PIE5 equ 04A3h ;# "> +"65422 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65422: __asm("PIE6 equ 04A4h"); +[; <" PIE6 equ 04A4h ;# "> +"65484 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65484: __asm("PIE7 equ 04A5h"); +[; <" PIE7 equ 04A5h ;# "> +"65541 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65541: __asm("PIE8 equ 04A6h"); +[; <" PIE8 equ 04A6h ;# "> +"65603 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65603: __asm("PIE9 equ 04A7h"); +[; <" PIE9 equ 04A7h ;# "> +"65660 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65660: __asm("PIE10 equ 04A8h"); +[; <" PIE10 equ 04A8h ;# "> +"65722 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65722: __asm("PIE11 equ 04A9h"); +[; <" PIE11 equ 04A9h ;# "> +"65784 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65784: __asm("PIE12 equ 04AAh"); +[; <" PIE12 equ 04AAh ;# "> +"65846 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65846: __asm("PIE13 equ 04ABh"); +[; <" PIE13 equ 04ABh ;# "> +"65908 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65908: __asm("PIE14 equ 04ACh"); +[; <" PIE14 equ 04ACh ;# "> +"65965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 65965: __asm("PIE15 equ 04ADh"); +[; <" PIE15 equ 04ADh ;# "> +"66027 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66027: __asm("PIR0 equ 04AEh"); +[; <" PIR0 equ 04AEh ;# "> +"66089 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66089: __asm("PIR1 equ 04AFh"); +[; <" PIR1 equ 04AFh ;# "> +"66151 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66151: __asm("PIR2 equ 04B0h"); +[; <" PIR2 equ 04B0h ;# "> +"66221 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66221: __asm("PIR3 equ 04B1h"); +[; <" PIR3 equ 04B1h ;# "> +"66283 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66283: __asm("PIR4 equ 04B2h"); +[; <" PIR4 equ 04B2h ;# "> +"66345 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66345: __asm("PIR5 equ 04B3h"); +[; <" PIR5 equ 04B3h ;# "> +"66407 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66407: __asm("PIR6 equ 04B4h"); +[; <" PIR6 equ 04B4h ;# "> +"66469 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66469: __asm("PIR7 equ 04B5h"); +[; <" PIR7 equ 04B5h ;# "> +"66526 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66526: __asm("PIR8 equ 04B6h"); +[; <" PIR8 equ 04B6h ;# "> +"66588 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66588: __asm("PIR9 equ 04B7h"); +[; <" PIR9 equ 04B7h ;# "> +"66645 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66645: __asm("PIR10 equ 04B8h"); +[; <" PIR10 equ 04B8h ;# "> +"66707 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66707: __asm("PIR11 equ 04B9h"); +[; <" PIR11 equ 04B9h ;# "> +"66769 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66769: __asm("PIR12 equ 04BAh"); +[; <" PIR12 equ 04BAh ;# "> +"66831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66831: __asm("PIR13 equ 04BBh"); +[; <" PIR13 equ 04BBh ;# "> +"66893 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66893: __asm("PIR14 equ 04BCh"); +[; <" PIR14 equ 04BCh ;# "> +"66950 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 66950: __asm("PIR15 equ 04BDh"); +[; <" PIR15 equ 04BDh ;# "> +"67012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67012: __asm("LATA equ 04BEh"); +[; <" LATA equ 04BEh ;# "> +"67074 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67074: __asm("LATB equ 04BFh"); +[; <" LATB equ 04BFh ;# "> +"67136 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67136: __asm("LATC equ 04C0h"); +[; <" LATC equ 04C0h ;# "> +"67198 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67198: __asm("TRISA equ 04C6h"); +[; <" TRISA equ 04C6h ;# "> +"67260 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67260: __asm("TRISB equ 04C7h"); +[; <" TRISB equ 04C7h ;# "> +"67322 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67322: __asm("TRISC equ 04C8h"); +[; <" TRISC equ 04C8h ;# "> +"67384 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67384: __asm("TRISE equ 04CAh"); +[; <" TRISE equ 04CAh ;# "> +"67405 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67405: __asm("PORTA equ 04CEh"); +[; <" PORTA equ 04CEh ;# "> +"67467 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67467: __asm("PORTB equ 04CFh"); +[; <" PORTB equ 04CFh ;# "> +"67529 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67529: __asm("PORTC equ 04D0h"); +[; <" PORTC equ 04D0h ;# "> +"67591 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67591: __asm("PORTE equ 04D2h"); +[; <" PORTE equ 04D2h ;# "> +"67612 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67612: __asm("INTCON0 equ 04D6h"); +[; <" INTCON0 equ 04D6h ;# "> +"67672 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67672: __asm("INTCON1 equ 04D7h"); +[; <" INTCON1 equ 04D7h ;# "> +"67708 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67708: __asm("STATUS equ 04D8h"); +[; <" STATUS equ 04D8h ;# "> +"67797 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67797: __asm("FSR2 equ 04D9h"); +[; <" FSR2 equ 04D9h ;# "> +"67804 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67804: __asm("FSR2L equ 04D9h"); +[; <" FSR2L equ 04D9h ;# "> +"67824 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67824: __asm("FSR2H equ 04DAh"); +[; <" FSR2H equ 04DAh ;# "> +"67831 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67831: __asm("PLUSW2 equ 04DBh"); +[; <" PLUSW2 equ 04DBh ;# "> +"67851 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67851: __asm("PREINC2 equ 04DCh"); +[; <" PREINC2 equ 04DCh ;# "> +"67871 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67871: __asm("POSTDEC2 equ 04DDh"); +[; <" POSTDEC2 equ 04DDh ;# "> +"67891 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67891: __asm("POSTINC2 equ 04DEh"); +[; <" POSTINC2 equ 04DEh ;# "> +"67911 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67911: __asm("INDF2 equ 04DFh"); +[; <" INDF2 equ 04DFh ;# "> +"67931 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67931: __asm("BSR equ 04E0h"); +[; <" BSR equ 04E0h ;# "> +"67938 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67938: __asm("FSR1 equ 04E1h"); +[; <" FSR1 equ 04E1h ;# "> +"67945 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67945: __asm("FSR1L equ 04E1h"); +[; <" FSR1L equ 04E1h ;# "> +"67965 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67965: __asm("FSR1H equ 04E2h"); +[; <" FSR1H equ 04E2h ;# "> +"67972 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67972: __asm("PLUSW1 equ 04E3h"); +[; <" PLUSW1 equ 04E3h ;# "> +"67992 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 67992: __asm("PREINC1 equ 04E4h"); +[; <" PREINC1 equ 04E4h ;# "> +"68012 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68012: __asm("POSTDEC1 equ 04E5h"); +[; <" POSTDEC1 equ 04E5h ;# "> +"68032 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68032: __asm("POSTINC1 equ 04E6h"); +[; <" POSTINC1 equ 04E6h ;# "> +"68052 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68052: __asm("INDF1 equ 04E7h"); +[; <" INDF1 equ 04E7h ;# "> +"68072 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68072: __asm("WREG equ 04E8h"); +[; <" WREG equ 04E8h ;# "> +"68110 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68110: __asm("FSR0 equ 04E9h"); +[; <" FSR0 equ 04E9h ;# "> +"68117 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68117: __asm("FSR0L equ 04E9h"); +[; <" FSR0L equ 04E9h ;# "> +"68137 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68137: __asm("FSR0H equ 04EAh"); +[; <" FSR0H equ 04EAh ;# "> +"68144 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68144: __asm("PLUSW0 equ 04EBh"); +[; <" PLUSW0 equ 04EBh ;# "> +"68164 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68164: __asm("PREINC0 equ 04ECh"); +[; <" PREINC0 equ 04ECh ;# "> +"68184 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68184: __asm("POSTDEC0 equ 04EDh"); +[; <" POSTDEC0 equ 04EDh ;# "> +"68204 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68204: __asm("POSTINC0 equ 04EEh"); +[; <" POSTINC0 equ 04EEh ;# "> +"68224 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68224: __asm("INDF0 equ 04EFh"); +[; <" INDF0 equ 04EFh ;# "> +"68244 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68244: __asm("PCON0 equ 04F0h"); +[; <" PCON0 equ 04F0h ;# "> +"68397 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68397: __asm("PCON1 equ 04F1h"); +[; <" PCON1 equ 04F1h ;# "> +"68436 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68436: __asm("CPUDOZE equ 04F2h"); +[; <" CPUDOZE equ 04F2h ;# "> +"68501 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68501: __asm("PROD equ 04F3h"); +[; <" PROD equ 04F3h ;# "> +"68508 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68508: __asm("PRODL equ 04F3h"); +[; <" PRODL equ 04F3h ;# "> +"68528 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68528: __asm("PRODH equ 04F4h"); +[; <" PRODH equ 04F4h ;# "> +"68548 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68548: __asm("TABLAT equ 04F5h"); +[; <" TABLAT equ 04F5h ;# "> +"68570 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68570: __asm("TBLPTR equ 04F6h"); +[; <" TBLPTR equ 04F6h ;# "> +"68577 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68577: __asm("TBLPTRL equ 04F6h"); +[; <" TBLPTRL equ 04F6h ;# "> +"68597 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68597: __asm("TBLPTRH equ 04F7h"); +[; <" TBLPTRH equ 04F7h ;# "> +"68617 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68617: __asm("TBLPTRU equ 04F8h"); +[; <" TBLPTRU equ 04F8h ;# "> +"68648 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68648: __asm("PCLAT equ 04F9h"); +[; <" PCLAT equ 04F9h ;# "> +"68655 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68655: __asm("PCL equ 04F9h"); +[; <" PCL equ 04F9h ;# "> +"68675 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68675: __asm("PCLATH equ 04FAh"); +[; <" PCLATH equ 04FAh ;# "> +"68695 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68695: __asm("PCLATU equ 04FBh"); +[; <" PCLATU equ 04FBh ;# "> +"68715 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68715: __asm("STKPTR equ 04FCh"); +[; <" STKPTR equ 04FCh ;# "> +"68813 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68813: __asm("TOS equ 04FDh"); +[; <" TOS equ 04FDh ;# "> +"68820 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68820: __asm("TOSL equ 04FDh"); +[; <" TOSL equ 04FDh ;# "> +"68840 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68840: __asm("TOSH equ 04FEh"); +[; <" TOSH equ 04FEh ;# "> +"68860 +[; ;C:/Users/panze/.mchp_packs/Microchip/PIC18F-Q_DFP/1.13.211/xc8\pic\include\proc\pic18f26q84.h: 68860: __asm("TOSU equ 04FFh"); +[; <" TOSU equ 04FFh ;# "> +"58 mcc_generated_files/tmr1.c +[; ;mcc_generated_files/tmr1.c: 58: volatile uint16_t timer1ReloadVal; +[v _timer1ReloadVal `Vus ~T0 @X0 1 e ] +"59 +[; ;mcc_generated_files/tmr1.c: 59: void (*TMR1_InterruptHandler)(void); +[v _TMR1_InterruptHandler `*F22175 ~T0 @X0 1 e ] +"65 +[; ;mcc_generated_files/tmr1.c: 65: void TMR1_Initialize(void) +[v _TMR1_Initialize `(v ~T0 @X0 1 ef ] +"66 +[; ;mcc_generated_files/tmr1.c: 66: { +{ +[e :U _TMR1_Initialize ] +[f ] +"70 +[; ;mcc_generated_files/tmr1.c: 70: T1GCON = 0x00; +[e = _T1GCON -> -> 0 `i `uc ] +"73 +[; ;mcc_generated_files/tmr1.c: 73: T1GATE = 0x00; +[e = _T1GATE -> -> 0 `i `uc ] +"76 +[; ;mcc_generated_files/tmr1.c: 76: T1CLK = 0x01; +[e = _T1CLK -> -> 1 `i `uc ] +"79 +[; ;mcc_generated_files/tmr1.c: 79: TMR1H = 0x85; +[e = _TMR1H -> -> 133 `i `uc ] +"82 +[; ;mcc_generated_files/tmr1.c: 82: TMR1L = 0xEE; +[e = _TMR1L -> -> 238 `i `uc ] +"85 +[; ;mcc_generated_files/tmr1.c: 85: PIR3bits.TMR1IF = 0; +[e = . . _PIR3bits 0 4 -> -> 0 `i `uc ] +"88 +[; ;mcc_generated_files/tmr1.c: 88: timer1ReloadVal=(uint16_t)((TMR1H << 8) | TMR1L); +[e = _timer1ReloadVal -> | << -> _TMR1H `i -> 8 `i -> _TMR1L `i `us ] +"91 +[; ;mcc_generated_files/tmr1.c: 91: PIE3bits.TMR1IE = 1; +[e = . . _PIE3bits 0 4 -> -> 1 `i `uc ] +"94 +[; ;mcc_generated_files/tmr1.c: 94: TMR1_SetInterruptHandler(TMR1_DefaultInterruptHandler); +[e ( _TMR1_SetInterruptHandler (1 &U _TMR1_DefaultInterruptHandler ] +"97 +[; ;mcc_generated_files/tmr1.c: 97: T1CON = 0x31; +[e = _T1CON -> -> 49 `i `uc ] +"98 +[; ;mcc_generated_files/tmr1.c: 98: } +[e :UE 3176 ] +} +"100 +[; ;mcc_generated_files/tmr1.c: 100: void TMR1_StartTimer(void) +[v _TMR1_StartTimer `(v ~T0 @X0 1 ef ] +"101 +[; ;mcc_generated_files/tmr1.c: 101: { +{ +[e :U _TMR1_StartTimer ] +[f ] +"103 +[; ;mcc_generated_files/tmr1.c: 103: T1CONbits.TMR1ON = 1; +[e = . . _T1CONbits 1 0 -> -> 1 `i `uc ] +"104 +[; ;mcc_generated_files/tmr1.c: 104: } +[e :UE 3177 ] +} +"106 +[; ;mcc_generated_files/tmr1.c: 106: void TMR1_StopTimer(void) +[v _TMR1_StopTimer `(v ~T0 @X0 1 ef ] +"107 +[; ;mcc_generated_files/tmr1.c: 107: { +{ +[e :U _TMR1_StopTimer ] +[f ] +"109 +[; ;mcc_generated_files/tmr1.c: 109: T1CONbits.TMR1ON = 0; +[e = . . _T1CONbits 1 0 -> -> 0 `i `uc ] +"110 +[; ;mcc_generated_files/tmr1.c: 110: } +[e :UE 3178 ] +} +"112 +[; ;mcc_generated_files/tmr1.c: 112: uint16_t TMR1_ReadTimer(void) +[v _TMR1_ReadTimer `(us ~T0 @X0 1 ef ] +"113 +[; ;mcc_generated_files/tmr1.c: 113: { +{ +[e :U _TMR1_ReadTimer ] +[f ] +"114 +[; ;mcc_generated_files/tmr1.c: 114: uint16_t readVal; +[v _readVal `us ~T0 @X0 1 a ] +"115 +[; ;mcc_generated_files/tmr1.c: 115: uint8_t readValHigh; +[v _readValHigh `uc ~T0 @X0 1 a ] +"116 +[; ;mcc_generated_files/tmr1.c: 116: uint8_t readValLow; +[v _readValLow `uc ~T0 @X0 1 a ] +"118 +[; ;mcc_generated_files/tmr1.c: 118: T1CONbits.T1RD16 = 1; +[e = . . _T1CONbits 1 1 -> -> 1 `i `uc ] +"120 +[; ;mcc_generated_files/tmr1.c: 120: readValLow = TMR1L; +[e = _readValLow _TMR1L ] +"121 +[; ;mcc_generated_files/tmr1.c: 121: readValHigh = TMR1H; +[e = _readValHigh _TMR1H ] +"123 +[; ;mcc_generated_files/tmr1.c: 123: readVal = ((uint16_t)readValHigh << 8) | readValLow; +[e = _readVal -> | << -> -> _readValHigh `us `ui -> 8 `i -> _readValLow `ui `us ] +"125 +[; ;mcc_generated_files/tmr1.c: 125: return readVal; +[e ) _readVal ] +[e $UE 3179 ] +"126 +[; ;mcc_generated_files/tmr1.c: 126: } +[e :UE 3179 ] +} +"128 +[; ;mcc_generated_files/tmr1.c: 128: void TMR1_WriteTimer(uint16_t timerVal) +[v _TMR1_WriteTimer `(v ~T0 @X0 1 ef1`us ] +"129 +[; ;mcc_generated_files/tmr1.c: 129: { +{ +[e :U _TMR1_WriteTimer ] +"128 +[; ;mcc_generated_files/tmr1.c: 128: void TMR1_WriteTimer(uint16_t timerVal) +[v _timerVal `us ~T0 @X0 1 r1 ] +"129 +[; ;mcc_generated_files/tmr1.c: 129: { +[f ] +"130 +[; ;mcc_generated_files/tmr1.c: 130: if (T1CONbits.NOT_SYNC == 1) +[e $ ! == -> . . _T1CONbits 0 2 `i -> 1 `i 3181 ] +"131 +[; ;mcc_generated_files/tmr1.c: 131: { +{ +"133 +[; ;mcc_generated_files/tmr1.c: 133: T1CONbits.TMR1ON = 0; +[e = . . _T1CONbits 1 0 -> -> 0 `i `uc ] +"136 +[; ;mcc_generated_files/tmr1.c: 136: TMR1H = (uint8_t)(timerVal >> 8); +[e = _TMR1H -> >> -> _timerVal `ui -> 8 `i `uc ] +"137 +[; ;mcc_generated_files/tmr1.c: 137: TMR1L = (uint8_t)timerVal; +[e = _TMR1L -> _timerVal `uc ] +"140 +[; ;mcc_generated_files/tmr1.c: 140: T1CONbits.TMR1ON =1; +[e = . . _T1CONbits 1 0 -> -> 1 `i `uc ] +"141 +[; ;mcc_generated_files/tmr1.c: 141: } +} +[e $U 3182 ] +"142 +[; ;mcc_generated_files/tmr1.c: 142: else +[e :U 3181 ] +"143 +[; ;mcc_generated_files/tmr1.c: 143: { +{ +"145 +[; ;mcc_generated_files/tmr1.c: 145: TMR1H = (uint8_t)(timerVal >> 8); +[e = _TMR1H -> >> -> _timerVal `ui -> 8 `i `uc ] +"146 +[; ;mcc_generated_files/tmr1.c: 146: TMR1L = (uint8_t)timerVal; +[e = _TMR1L -> _timerVal `uc ] +"147 +[; ;mcc_generated_files/tmr1.c: 147: } +} +[e :U 3182 ] +"148 +[; ;mcc_generated_files/tmr1.c: 148: } +[e :UE 3180 ] +} +"150 +[; ;mcc_generated_files/tmr1.c: 150: void TMR1_Reload(void) +[v _TMR1_Reload `(v ~T0 @X0 1 ef ] +"151 +[; ;mcc_generated_files/tmr1.c: 151: { +{ +[e :U _TMR1_Reload ] +[f ] +"152 +[; ;mcc_generated_files/tmr1.c: 152: TMR1_WriteTimer(timer1ReloadVal); +[e ( _TMR1_WriteTimer (1 _timer1ReloadVal ] +"153 +[; ;mcc_generated_files/tmr1.c: 153: } +[e :UE 3183 ] +} +"155 +[; ;mcc_generated_files/tmr1.c: 155: void TMR1_StartSinglePulseAcquisition(void) +[v _TMR1_StartSinglePulseAcquisition `(v ~T0 @X0 1 ef ] +"156 +[; ;mcc_generated_files/tmr1.c: 156: { +{ +[e :U _TMR1_StartSinglePulseAcquisition ] +[f ] +"157 +[; ;mcc_generated_files/tmr1.c: 157: T1GCONbits.T1GGO = 1; +[e = . . _T1GCONbits 1 2 -> -> 1 `i `uc ] +"158 +[; ;mcc_generated_files/tmr1.c: 158: } +[e :UE 3184 ] +} +"160 +[; ;mcc_generated_files/tmr1.c: 160: uint8_t TMR1_CheckGateValueStatus(void) +[v _TMR1_CheckGateValueStatus `(uc ~T0 @X0 1 ef ] +"161 +[; ;mcc_generated_files/tmr1.c: 161: { +{ +[e :U _TMR1_CheckGateValueStatus ] +[f ] +"162 +[; ;mcc_generated_files/tmr1.c: 162: return (T1GCONbits.T1GVAL); +[e ) . . _T1GCONbits 1 1 ] +[e $UE 3185 ] +"163 +[; ;mcc_generated_files/tmr1.c: 163: } +[e :UE 3185 ] +} +"165 +[; ;mcc_generated_files/tmr1.c: 165: void TMR1_ISR(void) +[v _TMR1_ISR `(v ~T0 @X0 1 ef ] +"166 +[; ;mcc_generated_files/tmr1.c: 166: { +{ +[e :U _TMR1_ISR ] +[f ] +"167 +[; ;mcc_generated_files/tmr1.c: 167: static volatile unsigned int CountCallBack = 0; +[v F22190 `Vui ~T0 @X0 1 s CountCallBack ] +[i F22190 +-> -> 0 `i `ui +] +"170 +[; ;mcc_generated_files/tmr1.c: 170: PIR3bits.TMR1IF = 0; +[e = . . _PIR3bits 0 4 -> -> 0 `i `uc ] +"171 +[; ;mcc_generated_files/tmr1.c: 171: TMR1_WriteTimer(timer1ReloadVal); +[e ( _TMR1_WriteTimer (1 _timer1ReloadVal ] +"174 +[; ;mcc_generated_files/tmr1.c: 174: if (++CountCallBack >= 5) +[e $ ! >= =+ F22190 -> -> 1 `i `Vui -> -> 5 `i `ui 3187 ] +"175 +[; ;mcc_generated_files/tmr1.c: 175: { +{ +"180 +[; ;mcc_generated_files/tmr1.c: 180: CountCallBack = 0; +[e = F22190 -> -> 0 `i `ui ] +"181 +[; ;mcc_generated_files/tmr1.c: 181: } +} +[e :U 3187 ] +"182 +[; ;mcc_generated_files/tmr1.c: 182: TMR1_CallBack(); +[e ( _TMR1_CallBack .. ] +"183 +[; ;mcc_generated_files/tmr1.c: 183: } +[e :UE 3186 ] +} +"185 +[; ;mcc_generated_files/tmr1.c: 185: void TMR1_CallBack(void) +[v _TMR1_CallBack `(v ~T0 @X0 1 ef ] +"186 +[; ;mcc_generated_files/tmr1.c: 186: { +{ +[e :U _TMR1_CallBack ] +[f ] +"188 +[; ;mcc_generated_files/tmr1.c: 188: if(TMR1_InterruptHandler) +[e $ ! != _TMR1_InterruptHandler -> -> 0 `i `*F22192 3189 ] +"189 +[; ;mcc_generated_files/tmr1.c: 189: { +{ +"190 +[; ;mcc_generated_files/tmr1.c: 190: TMR1_InterruptHandler(); +[e ( *U _TMR1_InterruptHandler .. ] +"191 +[; ;mcc_generated_files/tmr1.c: 191: } +} +[e :U 3189 ] +"193 +[; ;mcc_generated_files/tmr1.c: 193: TEMPORIZATION_100ms(); +[e ( _TEMPORIZATION_100ms .. ] +"195 +[; ;mcc_generated_files/tmr1.c: 195: if ( ucCount500ms++ == 5 ) +[e $ ! == -> ++ _ucCount500ms -> -> 1 `i `uc `i -> 5 `i 3190 ] +"196 +[; ;mcc_generated_files/tmr1.c: 196: { +{ +"197 +[; ;mcc_generated_files/tmr1.c: 197: ucCount500ms = 0; +[e = _ucCount500ms -> -> 0 `i `uc ] +"198 +[; ;mcc_generated_files/tmr1.c: 198: TEMPORIZATION_500ms(); +[e ( _TEMPORIZATION_500ms .. ] +"199 +[; ;mcc_generated_files/tmr1.c: 199: } +} +[e :U 3190 ] +"200 +[; ;mcc_generated_files/tmr1.c: 200: if ( ucCount1s++ == 10 ) +[e $ ! == -> ++ _ucCount1s -> -> 1 `i `uc `i -> 10 `i 3191 ] +"201 +[; ;mcc_generated_files/tmr1.c: 201: { +{ +"202 +[; ;mcc_generated_files/tmr1.c: 202: ucCount1s = 0; +[e = _ucCount1s -> -> 0 `i `uc ] +"203 +[; ;mcc_generated_files/tmr1.c: 203: TEMPORIZATION_1s(); +[e ( _TEMPORIZATION_1s .. ] +"204 +[; ;mcc_generated_files/tmr1.c: 204: } +} +[e :U 3191 ] +"205 +[; ;mcc_generated_files/tmr1.c: 205: if ( ucCount10s++ == 100 ) +[e $ ! == -> ++ _ucCount10s -> -> 1 `i `uc `i -> 100 `i 3192 ] +"206 +[; ;mcc_generated_files/tmr1.c: 206: { +{ +"207 +[; ;mcc_generated_files/tmr1.c: 207: ucCount10s = 0; +[e = _ucCount10s -> -> 0 `i `uc ] +"208 +[; ;mcc_generated_files/tmr1.c: 208: TEMPORIZATION_10s(); +[e ( _TEMPORIZATION_10s .. ] +"209 +[; ;mcc_generated_files/tmr1.c: 209: } +} +[e :U 3192 ] +"210 +[; ;mcc_generated_files/tmr1.c: 210: if ( uiCount30s++ == 300 ) +[e $ ! == ++ _uiCount30s -> -> 1 `i `ui -> -> 300 `i `ui 3193 ] +"211 +[; ;mcc_generated_files/tmr1.c: 211: { +{ +"212 +[; ;mcc_generated_files/tmr1.c: 212: uiCount30s = 0; +[e = _uiCount30s -> -> 0 `i `ui ] +"213 +[; ;mcc_generated_files/tmr1.c: 213: TEMPORIZATION_30s(); +[e ( _TEMPORIZATION_30s .. ] +"214 +[; ;mcc_generated_files/tmr1.c: 214: } +} +[e :U 3193 ] +"215 +[; ;mcc_generated_files/tmr1.c: 215: if ( uiCount1min++ == 600 ) +[e $ ! == ++ _uiCount1min -> -> 1 `i `ui -> -> 600 `i `ui 3194 ] +"216 +[; ;mcc_generated_files/tmr1.c: 216: { +{ +"217 +[; ;mcc_generated_files/tmr1.c: 217: uiCount1min = 0; +[e = _uiCount1min -> -> 0 `i `ui ] +"218 +[; ;mcc_generated_files/tmr1.c: 218: TEMPORIZATION_1mins(); +[e ( _TEMPORIZATION_1mins .. ] +"219 +[; ;mcc_generated_files/tmr1.c: 219: } +} +[e :U 3194 ] +"221 +[; ;mcc_generated_files/tmr1.c: 221: } +[e :UE 3188 ] +} +"223 +[; ;mcc_generated_files/tmr1.c: 223: void TMR1_SetInterruptHandler(void (* InterruptHandler)(void)){ +[v _TMR1_SetInterruptHandler `(v ~T0 @X0 1 ef1`*F22194 ] +{ +[e :U _TMR1_SetInterruptHandler ] +[v _InterruptHandler `*F22196 ~T0 @X0 1 r1 ] +[f ] +"224 +[; ;mcc_generated_files/tmr1.c: 224: TMR1_InterruptHandler = InterruptHandler; +[e = _TMR1_InterruptHandler _InterruptHandler ] +"225 +[; ;mcc_generated_files/tmr1.c: 225: } +[e :UE 3195 ] +} +"227 +[; ;mcc_generated_files/tmr1.c: 227: void TMR1_DefaultInterruptHandler(void){ +[v _TMR1_DefaultInterruptHandler `(v ~T0 @X0 1 ef ] +{ +[e :U _TMR1_DefaultInterruptHandler ] +[f ] +"230 +[; ;mcc_generated_files/tmr1.c: 230: } +[e :UE 3196 ] +} diff --git a/ETC.X/build/default/debug/mcc_generated_files/tmr1.p1.d b/ETC.X/build/default/debug/mcc_generated_files/tmr1.p1.d new file mode 100644 index 0000000..249de33 --- /dev/null +++ b/ETC.X/build/default/debug/mcc_generated_files/tmr1.p1.d @@ -0,0 +1,4 @@ +build/default/debug/mcc_generated_files/tmr1.p1: \ +mcc_generated_files/tmr1.c \ +mcc_generated_files/tmr1.h \ +mcc_generated_files/../TEMPORIZATIONS.h diff --git a/ETC.X/build/default/production/ETC.i b/ETC.X/build/default/production/ETC.i index 964f962..fbbd545 100644 --- a/ETC.X/build/default/production/ETC.i +++ b/ETC.X/build/default/production/ETC.i @@ -38563,8 +38563,8 @@ void APPSReadmin (void) void APPSReadmax (void) { - uiAPPS1max = 1990 - 100; - uiAPPS2max = 160 + 100; + uiAPPS1max = 2670 - 100; + uiAPPS2max = 4600 + 100; } @@ -38589,7 +38589,7 @@ void ETCModeSelect (unsigned char ucModeSelect) void ETCRulesSensorsSupervision(void) { - if ( 1 == 1 ) + if ( 0 == 1 ) { if (ucTPS1Perc>ucTPS2Perc+30) @@ -38625,7 +38625,7 @@ void ETCRulesSensorsSupervision(void) void ETC100msSupervisor (void) { - if ( 1 == 1 ) + if ( 0 == 1 ) { if ( ucETCTimerRuleTPS == 0x00 ) { @@ -38657,7 +38657,7 @@ void ETC100msSupervisor (void) void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactual) { CANWriteMessage(0x500, 6, ucTPStarget, ucTPSactual, ucTPS, ucAPPS, ucTPS_STATE, 0, 0, 0); - if ( 1 == 1 ) + if ( 0 == 1 ) { if (ucTPStarget>ucTPSactual+30) { @@ -38685,7 +38685,7 @@ void ETCRulesMotorSupervisor (unsigned char ucTPStarget, unsigned char ucTPSactu } void ETC500msSupervisor (void) { - if ( 1 == 1 ) + if ( 0 == 1 ) { if ( ucETCTargetTPSDiff == 0x00 ) { @@ -38829,7 +38829,8 @@ void APPSAnalysis (void) # 412 "ETC.c" ucAPPS1Perc = ETCPercentCalc(uiAPPS1, uiAPPS1min, uiAPPS1max); ucAPPS2Perc = ETCPercentCalc(uiAPPS2, uiAPPS2min, uiAPPS2max); - ucAPPS = ( ( ucAPPS1Perc + ucAPPS2Perc ) / 2 ); + + ucAPPS = ucAPPS1Perc; __nop(); } @@ -39020,7 +39021,7 @@ float PIDController_Update(PIDController *pid, float setpoint, float measurement pid->integrator = pid->integrator + 0.5f * pid->Ki * pid->T * (error + pid->prevError); -# 624 "ETC.c" +# 625 "ETC.c" pid->differentiator = -(2.0f * pid->Kd * (measurement - pid->prevMeasurement) + (2.0f * pid->tau - pid->T) * pid->differentiator) / (2.0f * pid->tau + pid->T); diff --git a/ETC.X/build/default/production/ETC.p1 b/ETC.X/build/default/production/ETC.p1 index 764773b..24b6092 100644 --- a/ETC.X/build/default/production/ETC.p1 +++ b/ETC.X/build/default/production/ETC.p1 @@ -4003,11 +4003,11 @@ Version 4.0 HI-TECH Software Intermediate Code [e :U _APPSReadmax ] [f ] "107 -[; ;ETC.c: 107: uiAPPS1max = 1990 - 100; -[e = _uiAPPS1max -> - -> 1990 `i -> 100 `i `ui ] +[; ;ETC.c: 107: uiAPPS1max = 2670 - 100; +[e = _uiAPPS1max -> - -> 2670 `i -> 100 `i `ui ] "108 -[; ;ETC.c: 108: uiAPPS2max = 160 + 100; -[e = _uiAPPS2max -> + -> 160 `i -> 100 `i `ui ] +[; ;ETC.c: 108: uiAPPS2max = 4600 + 100; +[e = _uiAPPS2max -> + -> 4600 `i -> 100 `i `ui ] "109 [; ;ETC.c: 109: } [e :UE 3191 ] @@ -4092,8 +4092,8 @@ Version 4.0 HI-TECH Software Intermediate Code [e :U _ETCRulesSensorsSupervision ] [f ] "133 -[; ;ETC.c: 133: if ( 1 == 1 ) -[e $ ! == -> 1 `i -> 1 `i 3208 ] +[; ;ETC.c: 133: if ( 0 == 1 ) +[e $ ! == -> 0 `i -> 1 `i 3208 ] "134 [; ;ETC.c: 134: { { @@ -4202,8 +4202,8 @@ Version 4.0 HI-TECH Software Intermediate Code [e :U _ETC100msSupervisor ] [f ] "169 -[; ;ETC.c: 169: if ( 1 == 1 ) -[e $ ! == -> 1 `i -> 1 `i 3218 ] +[; ;ETC.c: 169: if ( 0 == 1 ) +[e $ ! == -> 0 `i -> 1 `i 3218 ] "170 [; ;ETC.c: 170: { { @@ -4311,8 +4311,8 @@ Version 4.0 HI-TECH Software Intermediate Code [; ;ETC.c: 200: CANWriteMessage(0x500, 6, ucTPStarget, ucTPSactual, ucTPS, ucAPPS, ucTPS_STATE, 0, 0, 0); [e ( _CANWriteMessage (4 , , , , , , , , , -> -> -> 1280 `i `l `ul -> -> 6 `i `uc _ucTPStarget _ucTPSactual -> _ucTPS `uc -> _ucAPPS `uc _ucTPS_STATE -> -> 0 `i `uc -> -> 0 `i `uc -> -> 0 `i `uc ] "201 -[; ;ETC.c: 201: if ( 1 == 1 ) -[e $ ! == -> 1 `i -> 1 `i 3226 ] +[; ;ETC.c: 201: if ( 0 == 1 ) +[e $ ! == -> 0 `i -> 1 `i 3226 ] "202 [; ;ETC.c: 202: { { @@ -4406,8 +4406,8 @@ Version 4.0 HI-TECH Software Intermediate Code [e :U _ETC500msSupervisor ] [f ] "229 -[; ;ETC.c: 229: if ( 1 == 1 ) -[e $ ! == -> 1 `i -> 1 `i 3234 ] +[; ;ETC.c: 229: if ( 0 == 1 ) +[e $ ! == -> 0 `i -> 1 `i 3234 ] "230 [; ;ETC.c: 230: { { @@ -4753,489 +4753,489 @@ Version 4.0 HI-TECH Software Intermediate Code "413 [; ;ETC.c: 413: ucAPPS2Perc = ETCPercentCalc(uiAPPS2, uiAPPS2min, uiAPPS2max); [e = _ucAPPS2Perc ( _ETCPercentCalc (3 , , -> _uiAPPS2 `l -> _uiAPPS2min `l -> _uiAPPS2max `l ] -"414 -[; ;ETC.c: 414: ucAPPS = ( ( ucAPPS1Perc + ucAPPS2Perc ) / 2 ); -[e = _ucAPPS / + _ucAPPS1Perc _ucAPPS2Perc -> -> 2 `i `ui ] "415 -[; ;ETC.c: 415: __nop(); -[e ( ___nop .. ] +[; ;ETC.c: 415: ucAPPS = ucAPPS1Perc; +[e = _ucAPPS _ucAPPS1Perc ] "416 -[; ;ETC.c: 416: } +[; ;ETC.c: 416: __nop(); +[e ( ___nop .. ] +"417 +[; ;ETC.c: 417: } [e :UE 3260 ] } -"419 -[; ;ETC.c: 419: void ETCMove(unsigned char ucTargetMove, unsigned char ucMode) -[v _ETCMove `(v ~T0 @X0 1 ef2`uc`uc ] "420 -[; ;ETC.c: 420: { +[; ;ETC.c: 420: void ETCMove(unsigned char ucTargetMove, unsigned char ucMode) +[v _ETCMove `(v ~T0 @X0 1 ef2`uc`uc ] +"421 +[; ;ETC.c: 421: { { [e :U _ETCMove ] -"419 -[; ;ETC.c: 419: void ETCMove(unsigned char ucTargetMove, unsigned char ucMode) +"420 +[; ;ETC.c: 420: void ETCMove(unsigned char ucTargetMove, unsigned char ucMode) [v _ucTargetMove `uc ~T0 @X0 1 r1 ] [v _ucMode `uc ~T0 @X0 1 r2 ] -"420 -[; ;ETC.c: 420: { -[f ] "421 -[; ;ETC.c: 421: ETCRulesMotorSupervisor (ucTargetMove, ucTPS); +[; ;ETC.c: 421: { +[f ] +"422 +[; ;ETC.c: 422: ETCRulesMotorSupervisor (ucTargetMove, ucTPS); [e ( _ETCRulesMotorSupervisor (2 , _ucTargetMove -> _ucTPS `uc ] -"423 -[; ;ETC.c: 423: if ( ( ucETCFlagSupervisor == 0x01 ) && ( ucETCRuleSupervisor == 0x01 ) ) -[e $ ! && == -> _ucETCFlagSupervisor `i -> 1 `i == -> _ucETCRuleSupervisor `i -> 1 `i 3262 ] "424 -[; ;ETC.c: 424: { +[; ;ETC.c: 424: if ( ( ucETCFlagSupervisor == 0x01 ) && ( ucETCRuleSupervisor == 0x01 ) ) +[e $ ! && == -> _ucETCFlagSupervisor `i -> 1 `i == -> _ucETCRuleSupervisor `i -> 1 `i 3262 ] +"425 +[; ;ETC.c: 425: { { -"426 -[; ;ETC.c: 426: uiETCDuty = ucTargetMove; +"427 +[; ;ETC.c: 427: uiETCDuty = ucTargetMove; [e = _uiETCDuty -> _ucTargetMove `ui ] -"428 -[; ;ETC.c: 428: if ( ucMode == ucASMode ) -[e $ ! == -> _ucMode `i -> _ucASMode `i 3263 ] "429 -[; ;ETC.c: 429: { -{ +[; ;ETC.c: 429: if ( ucMode == ucASMode ) +[e $ ! == -> _ucMode `i -> _ucASMode `i 3263 ] "430 -[; ;ETC.c: 430: if ( ucASMode == 1 ) -[e $ ! == -> _ucASMode `i -> 1 `i 3264 ] +[; ;ETC.c: 430: { +{ "431 -[; ;ETC.c: 431: { +[; ;ETC.c: 431: if ( ucASMode == 1 ) +[e $ ! == -> _ucASMode `i -> 1 `i 3264 ] +"432 +[; ;ETC.c: 432: { { -"434 -[; ;ETC.c: 434: GPIO_PWM2_Control(PIDController_Update(&pid, (float)(ucTargetMove), (float)(ucTPS)), 600); -[e ( _GPIO_PWM2_Control (2 , -> ( _PIDController_Update (3 , , &U _pid -> _ucTargetMove `f -> _ucTPS `f `ui -> -> 600 `i `ui ] "435 -[; ;ETC.c: 435: } +[; ;ETC.c: 435: GPIO_PWM2_Control(PIDController_Update(&pid, (float)(ucTargetMove), (float)(ucTPS)), 600); +[e ( _GPIO_PWM2_Control (2 , -> ( _PIDController_Update (3 , , &U _pid -> _ucTargetMove `f -> _ucTPS `f `ui -> -> 600 `i `ui ] +"436 +[; ;ETC.c: 436: } } [e $U 3265 ] -"436 -[; ;ETC.c: 436: else if ( ucASMode == 0 ) +"437 +[; ;ETC.c: 437: else if ( ucASMode == 0 ) [e :U 3264 ] [e $ ! == -> _ucASMode `i -> 0 `i 3266 ] -"437 -[; ;ETC.c: 437: { +"438 +[; ;ETC.c: 438: { { -"440 -[; ;ETC.c: 440: GPIO_PWM2_Control(PIDController_Update(&pid, (float)(ucTargetMove), (float)(ucTPS)), 600); -[e ( _GPIO_PWM2_Control (2 , -> ( _PIDController_Update (3 , , &U _pid -> _ucTargetMove `f -> _ucTPS `f `ui -> -> 600 `i `ui ] "441 -[; ;ETC.c: 441: } +[; ;ETC.c: 441: GPIO_PWM2_Control(PIDController_Update(&pid, (float)(ucTargetMove), (float)(ucTPS)), 600); +[e ( _GPIO_PWM2_Control (2 , -> ( _PIDController_Update (3 , , &U _pid -> _ucTargetMove `f -> _ucTPS `f `ui -> -> 600 `i `ui ] +"442 +[; ;ETC.c: 442: } } [e $U 3267 ] -"442 -[; ;ETC.c: 442: else -[e :U 3266 ] "443 -[; ;ETC.c: 443: { +[; ;ETC.c: 443: else +[e :U 3266 ] +"444 +[; ;ETC.c: 444: { { -"445 -[; ;ETC.c: 445: } +"446 +[; ;ETC.c: 446: } } [e :U 3267 ] [e :U 3265 ] -"446 -[; ;ETC.c: 446: } +"447 +[; ;ETC.c: 447: } } [e $U 3268 ] -"447 -[; ;ETC.c: 447: else -[e :U 3263 ] "448 -[; ;ETC.c: 448: { +[; ;ETC.c: 448: else +[e :U 3263 ] +"449 +[; ;ETC.c: 449: { { -"450 -[; ;ETC.c: 450: } +"451 +[; ;ETC.c: 451: } } [e :U 3268 ] -"451 -[; ;ETC.c: 451: do { LATAbits.LATA0 = 0; } while(0); +"452 +[; ;ETC.c: 452: do { LATAbits.LATA0 = 0; } while(0); [e :U 3271 ] { [e = . . _LATAbits 0 0 -> -> 0 `i `uc ] } [e :U 3270 ] -"452 -[; ;ETC.c: 452: } +"453 +[; ;ETC.c: 453: } } [e $U 3272 ] -"453 -[; ;ETC.c: 453: else -[e :U 3262 ] "454 -[; ;ETC.c: 454: { -{ +[; ;ETC.c: 454: else +[e :U 3262 ] "455 -[; ;ETC.c: 455: do { LATAbits.LATA0 = 1; } while(0); +[; ;ETC.c: 455: { +{ +"456 +[; ;ETC.c: 456: do { LATAbits.LATA0 = 1; } while(0); [e :U 3275 ] { [e = . . _LATAbits 0 0 -> -> 1 `i `uc ] } [e :U 3274 ] -"456 -[; ;ETC.c: 456: GPIO_PWM2_Control(0, 600); -[e ( _GPIO_PWM2_Control (2 , -> -> 0 `i `ui -> -> 600 `i `ui ] "457 -[; ;ETC.c: 457: } +[; ;ETC.c: 457: GPIO_PWM2_Control(0, 600); +[e ( _GPIO_PWM2_Control (2 , -> -> 0 `i `ui -> -> 600 `i `ui ] +"458 +[; ;ETC.c: 458: } } [e :U 3272 ] -"458 -[; ;ETC.c: 458: } +"459 +[; ;ETC.c: 459: } [e :UE 3261 ] } -"460 -[; ;ETC.c: 460: void ETCXavierSupervisor (void) -[v _ETCXavierSupervisor `(v ~T0 @X0 1 ef ] "461 -[; ;ETC.c: 461: { +[; ;ETC.c: 461: void ETCXavierSupervisor (void) +[v _ETCXavierSupervisor `(v ~T0 @X0 1 ef ] +"462 +[; ;ETC.c: 462: { { [e :U _ETCXavierSupervisor ] [f ] -"462 -[; ;ETC.c: 462: __nop(); -[e ( ___nop .. ] "463 -[; ;ETC.c: 463: if ( ucASMode == 1 ) -[e $ ! == -> _ucASMode `i -> 1 `i 3277 ] +[; ;ETC.c: 463: __nop(); +[e ( ___nop .. ] "464 -[; ;ETC.c: 464: { -{ +[; ;ETC.c: 464: if ( ucASMode == 1 ) +[e $ ! == -> _ucASMode `i -> 1 `i 3277 ] "465 -[; ;ETC.c: 465: if ( ucETCBeatSupervisor == 0x01 ) -[e $ ! == -> _ucETCBeatSupervisor `i -> 1 `i 3278 ] -"466 -[; ;ETC.c: 466: { +[; ;ETC.c: 465: { { +"466 +[; ;ETC.c: 466: if ( ucETCBeatSupervisor == 0x01 ) +[e $ ! == -> _ucETCBeatSupervisor `i -> 1 `i 3278 ] "467 -[; ;ETC.c: 467: ucETCFlagSupervisor = 0x01; -[e = _ucETCFlagSupervisor -> -> 1 `i `uc ] +[; ;ETC.c: 467: { +{ "468 -[; ;ETC.c: 468: } +[; ;ETC.c: 468: ucETCFlagSupervisor = 0x01; +[e = _ucETCFlagSupervisor -> -> 1 `i `uc ] +"469 +[; ;ETC.c: 469: } } [e $U 3279 ] -"469 -[; ;ETC.c: 469: else -[e :U 3278 ] "470 -[; ;ETC.c: 470: { -{ +[; ;ETC.c: 470: else +[e :U 3278 ] "471 -[; ;ETC.c: 471: ucETCFlagSupervisor = 0x00; +[; ;ETC.c: 471: { +{ +"472 +[; ;ETC.c: 472: ucETCFlagSupervisor = 0x00; [e = _ucETCFlagSupervisor -> -> 0 `i `uc ] -"473 -[; ;ETC.c: 473: GPIO_PWM1_Control(0, 300); -[e ( _GPIO_PWM1_Control (2 , -> -> 0 `i `ui -> -> 300 `i `ui ] "474 -[; ;ETC.c: 474: GPIO_PWM2_Control(0, 600); -[e ( _GPIO_PWM2_Control (2 , -> -> 0 `i `ui -> -> 600 `i `ui ] +[; ;ETC.c: 474: GPIO_PWM1_Control(0, 300); +[e ( _GPIO_PWM1_Control (2 , -> -> 0 `i `ui -> -> 300 `i `ui ] "475 -[; ;ETC.c: 475: } +[; ;ETC.c: 475: GPIO_PWM2_Control(0, 600); +[e ( _GPIO_PWM2_Control (2 , -> -> 0 `i `ui -> -> 600 `i `ui ] +"476 +[; ;ETC.c: 476: } } [e :U 3279 ] -"476 -[; ;ETC.c: 476: } +"477 +[; ;ETC.c: 477: } } [e $U 3280 ] -"477 -[; ;ETC.c: 477: else if ( ucASMode == 0 ) +"478 +[; ;ETC.c: 478: else if ( ucASMode == 0 ) [e :U 3277 ] [e $ ! == -> _ucASMode `i -> 0 `i 3281 ] -"478 -[; ;ETC.c: 478: { -{ "479 -[; ;ETC.c: 479: ucETCFlagSupervisor = 0x01; -[e = _ucETCFlagSupervisor -> -> 1 `i `uc ] +[; ;ETC.c: 479: { +{ "480 -[; ;ETC.c: 480: } +[; ;ETC.c: 480: ucETCFlagSupervisor = 0x01; +[e = _ucETCFlagSupervisor -> -> 1 `i `uc ] +"481 +[; ;ETC.c: 481: } } [e :U 3281 ] [e :U 3280 ] -"482 -[; ;ETC.c: 482: } +"483 +[; ;ETC.c: 483: } [e :UE 3276 ] } -"485 -[; ;ETC.c: 485: void ETCManual (unsigned char ucTargetManual) -[v _ETCManual `(v ~T0 @X0 1 ef1`uc ] "486 -[; ;ETC.c: 486: { +[; ;ETC.c: 486: void ETCManual (unsigned char ucTargetManual) +[v _ETCManual `(v ~T0 @X0 1 ef1`uc ] +"487 +[; ;ETC.c: 487: { { [e :U _ETCManual ] -"485 -[; ;ETC.c: 485: void ETCManual (unsigned char ucTargetManual) -[v _ucTargetManual `uc ~T0 @X0 1 r1 ] "486 -[; ;ETC.c: 486: { -[f ] +[; ;ETC.c: 486: void ETCManual (unsigned char ucTargetManual) +[v _ucTargetManual `uc ~T0 @X0 1 r1 ] "487 -[; ;ETC.c: 487: if ( ucASMode == 0 ) -[e $ ! == -> _ucASMode `i -> 0 `i 3283 ] +[; ;ETC.c: 487: { +[f ] "488 -[; ;ETC.c: 488: { -{ +[; ;ETC.c: 488: if ( ucASMode == 0 ) +[e $ ! == -> _ucASMode `i -> 0 `i 3283 ] "489 -[; ;ETC.c: 489: ETCMove(ucTargetManual, 0); +[; ;ETC.c: 489: { +{ +"490 +[; ;ETC.c: 490: ETCMove(ucTargetManual, 0); [e ( _ETCMove (2 , _ucTargetManual -> -> 0 `i `uc ] -"491 -[; ;ETC.c: 491: } +"492 +[; ;ETC.c: 492: } } [e :U 3283 ] -"492 -[; ;ETC.c: 492: } +"493 +[; ;ETC.c: 493: } [e :UE 3282 ] } -"495 -[; ;ETC.c: 495: unsigned int ETCPercentCalc(signed long val, signed long min, signed long max) -[v _ETCPercentCalc `(ui ~T0 @X0 1 ef3`l`l`l ] "496 -[; ;ETC.c: 496: { +[; ;ETC.c: 496: unsigned int ETCPercentCalc(signed long val, signed long min, signed long max) +[v _ETCPercentCalc `(ui ~T0 @X0 1 ef3`l`l`l ] +"497 +[; ;ETC.c: 497: { { [e :U _ETCPercentCalc ] -"495 -[; ;ETC.c: 495: unsigned int ETCPercentCalc(signed long val, signed long min, signed long max) +"496 +[; ;ETC.c: 496: unsigned int ETCPercentCalc(signed long val, signed long min, signed long max) [v _val `l ~T0 @X0 1 r1 ] [v _min `l ~T0 @X0 1 r2 ] [v _max `l ~T0 @X0 1 r3 ] -"496 -[; ;ETC.c: 496: { +"497 +[; ;ETC.c: 497: { [f ] -"503 -[; ;ETC.c: 503: val = (100*(val - min))/(max - min); -[e = _val / * -> -> 100 `i `l - _val _min - _max _min ] "504 -[; ;ETC.c: 504: if (val < 0) -[e $ ! < _val -> -> 0 `i `l 3285 ] +[; ;ETC.c: 504: val = (100*(val - min))/(max - min); +[e = _val / * -> -> 100 `i `l - _val _min - _max _min ] "505 -[; ;ETC.c: 505: { -{ +[; ;ETC.c: 505: if (val < 0) +[e $ ! < _val -> -> 0 `i `l 3285 ] "506 -[; ;ETC.c: 506: val = 0; -[e = _val -> -> 0 `i `l ] +[; ;ETC.c: 506: { +{ "507 -[; ;ETC.c: 507: } +[; ;ETC.c: 507: val = 0; +[e = _val -> -> 0 `i `l ] +"508 +[; ;ETC.c: 508: } } [e $U 3286 ] -"508 -[; ;ETC.c: 508: else if (val > 100 ) +"509 +[; ;ETC.c: 509: else if (val > 100 ) [e :U 3285 ] [e $ ! > _val -> -> 100 `i `l 3287 ] -"509 -[; ;ETC.c: 509: { -{ "510 -[; ;ETC.c: 510: val = 100; -[e = _val -> -> 100 `i `l ] +[; ;ETC.c: 510: { +{ "511 -[; ;ETC.c: 511: } +[; ;ETC.c: 511: val = 100; +[e = _val -> -> 100 `i `l ] +"512 +[; ;ETC.c: 512: } } [e :U 3287 ] [e :U 3286 ] -"513 -[; ;ETC.c: 513: return val; +"514 +[; ;ETC.c: 514: return val; [e ) -> _val `ui ] [e $UE 3284 ] -"514 -[; ;ETC.c: 514: } +"515 +[; ;ETC.c: 515: } [e :UE 3284 ] } -"516 -[; ;ETC.c: 516: unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) -[v _ETCPercentMultiCalcTPS1 `(ui ~T0 @X0 1 ef4`l`*ui`*uc`uc ] "517 -[; ;ETC.c: 517: { +[; ;ETC.c: 517: unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) +[v _ETCPercentMultiCalcTPS1 `(ui ~T0 @X0 1 ef4`l`*ui`*uc`uc ] +"518 +[; ;ETC.c: 518: { { [e :U _ETCPercentMultiCalcTPS1 ] -"516 -[; ;ETC.c: 516: unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) +"517 +[; ;ETC.c: 517: unsigned int ETCPercentMultiCalcTPS1(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) [v _value `l ~T0 @X0 1 r1 ] [v _uiTab_in `*ui ~T0 @X0 1 r2 ] [v _ucTab_out `*uc ~T0 @X0 1 r3 ] [v _ucSize `uc ~T0 @X0 1 r4 ] -"517 -[; ;ETC.c: 517: { -[f ] "518 -[; ;ETC.c: 518: unsigned char ucPos = 1; +[; ;ETC.c: 518: { +[f ] +"519 +[; ;ETC.c: 519: unsigned char ucPos = 1; [v _ucPos `uc ~T0 @X0 1 a ] [e = _ucPos -> -> 1 `i `uc ] -"519 -[; ;ETC.c: 519: signed long slResult; -[v _slResult `l ~T0 @X0 1 a ] "520 -[; ;ETC.c: 520: unsigned int ucValCero= uiTab_in[0]; +[; ;ETC.c: 520: signed long slResult; +[v _slResult `l ~T0 @X0 1 a ] +"521 +[; ;ETC.c: 521: unsigned int ucValCero= uiTab_in[0]; [v _ucValCero `ui ~T0 @X0 1 a ] [e = _ucValCero *U + _uiTab_in * -> -> 0 `i `x -> -> # *U _uiTab_in `i `x ] -"521 -[; ;ETC.c: 521: unsigned int ucValMax= uiTab_in[ucSize-1]; +"522 +[; ;ETC.c: 522: unsigned int ucValMax= uiTab_in[ucSize-1]; [v _ucValMax `ui ~T0 @X0 1 a ] [e = _ucValMax *U + _uiTab_in * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _uiTab_in `i `x ] -"522 -[; ;ETC.c: 522: unsigned char ucValout=0; +"523 +[; ;ETC.c: 523: unsigned char ucValout=0; [v _ucValout `uc ~T0 @X0 1 a ] [e = _ucValout -> -> 0 `i `uc ] -"525 -[; ;ETC.c: 525: if (value <= ucValCero) return ucTab_out[0]; +"526 +[; ;ETC.c: 526: if (value <= ucValCero) return ucTab_out[0]; [e $ ! <= _value -> _ucValCero `l 3289 ] [e ) -> *U + _ucTab_out * -> -> 0 `i `x -> -> # *U _ucTab_out `i `x `ui ] [e $UE 3288 ] [e :U 3289 ] -"526 -[; ;ETC.c: 526: if (value >= ucValMax) return ucTab_out[ucSize-1]; +"527 +[; ;ETC.c: 527: if (value >= ucValMax) return ucTab_out[ucSize-1]; [e $ ! >= _value -> _ucValMax `l 3290 ] [e ) -> *U + _ucTab_out * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `ui ] [e $UE 3288 ] [e :U 3290 ] -"530 -[; ;ETC.c: 530: while(value > uiTab_in[ucPos]) ucPos++; +"531 +[; ;ETC.c: 531: while(value > uiTab_in[ucPos]) ucPos++; [e $U 3291 ] [e :U 3292 ] [e ++ _ucPos -> -> 1 `i `uc ] [e :U 3291 ] [e $ > _value -> *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux `l 3292 ] [e :U 3293 ] -"531 -[; ;ETC.c: 531: ucValout = ucTab_out[ucPos]; +"532 +[; ;ETC.c: 532: ucValout = ucTab_out[ucPos]; [e = _ucValout *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux ] -"533 -[; ;ETC.c: 533: if (value == uiTab_in[ucPos]) return ucTab_out[ucPos]; +"534 +[; ;ETC.c: 534: if (value == uiTab_in[ucPos]) return ucTab_out[ucPos]; [e $ ! == _value -> *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux `l 3294 ] [e ) -> *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux `ui ] [e $UE 3288 ] [e :U 3294 ] -"536 -[; ;ETC.c: 536: slResult = ( (value - uiTab_in[ucPos-1]) * (ucTab_out[ucPos] - ucTab_out[ucPos-1]) / (uiTab_in[ucPos] - uiTab_in[ucPos-1]) + ucTab_out[ucPos-1] ); +"537 +[; ;ETC.c: 537: slResult = ( (value - uiTab_in[ucPos-1]) * (ucTab_out[ucPos] - ucTab_out[ucPos-1]) / (uiTab_in[ucPos] - uiTab_in[ucPos-1]) + ucTab_out[ucPos-1] ); [e = _slResult + / * - _value -> *U + _uiTab_in * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _uiTab_in `i `x `l -> - -> *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux `i -> *U + _ucTab_out * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `i `l -> - *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux *U + _uiTab_in * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _uiTab_in `i `x `l -> *U + _ucTab_out * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `l ] -"538 -[; ;ETC.c: 538: if ( slResult < 0 ) slResult = ucTab_out[0]; +"539 +[; ;ETC.c: 539: if ( slResult < 0 ) slResult = ucTab_out[0]; [e $ ! < _slResult -> -> 0 `i `l 3295 ] [e = _slResult -> *U + _ucTab_out * -> -> 0 `i `x -> -> # *U _ucTab_out `i `x `l ] [e :U 3295 ] -"539 -[; ;ETC.c: 539: if ( slResult > 100 ) slResult = ucTab_out[ucSize-1]; +"540 +[; ;ETC.c: 540: if ( slResult > 100 ) slResult = ucTab_out[ucSize-1]; [e $ ! > _slResult -> -> 100 `i `l 3296 ] [e = _slResult -> *U + _ucTab_out * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `l ] [e :U 3296 ] -"541 -[; ;ETC.c: 541: return slResult ; +"542 +[; ;ETC.c: 542: return slResult ; [e ) -> _slResult `ui ] [e $UE 3288 ] -"542 -[; ;ETC.c: 542: } +"543 +[; ;ETC.c: 543: } [e :UE 3288 ] } -"544 -[; ;ETC.c: 544: unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) -[v _ETCPercentMultiCalcTPS2 `(ui ~T0 @X0 1 ef4`l`*ui`*uc`uc ] "545 -[; ;ETC.c: 545: { +[; ;ETC.c: 545: unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) +[v _ETCPercentMultiCalcTPS2 `(ui ~T0 @X0 1 ef4`l`*ui`*uc`uc ] +"546 +[; ;ETC.c: 546: { { [e :U _ETCPercentMultiCalcTPS2 ] -"544 -[; ;ETC.c: 544: unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) +"545 +[; ;ETC.c: 545: unsigned int ETCPercentMultiCalcTPS2(signed long value, unsigned int *uiTab_in, unsigned char *ucTab_out, unsigned char ucSize) [v _value `l ~T0 @X0 1 r1 ] [v _uiTab_in `*ui ~T0 @X0 1 r2 ] [v _ucTab_out `*uc ~T0 @X0 1 r3 ] [v _ucSize `uc ~T0 @X0 1 r4 ] -"545 -[; ;ETC.c: 545: { -[f ] "546 -[; ;ETC.c: 546: unsigned char ucPos = 1; +[; ;ETC.c: 546: { +[f ] +"547 +[; ;ETC.c: 547: unsigned char ucPos = 1; [v _ucPos `uc ~T0 @X0 1 a ] [e = _ucPos -> -> 1 `i `uc ] -"547 -[; ;ETC.c: 547: signed long slResult; -[v _slResult `l ~T0 @X0 1 a ] "548 -[; ;ETC.c: 548: unsigned int ucValCero= uiTab_in[0]; +[; ;ETC.c: 548: signed long slResult; +[v _slResult `l ~T0 @X0 1 a ] +"549 +[; ;ETC.c: 549: unsigned int ucValCero= uiTab_in[0]; [v _ucValCero `ui ~T0 @X0 1 a ] [e = _ucValCero *U + _uiTab_in * -> -> 0 `i `x -> -> # *U _uiTab_in `i `x ] -"549 -[; ;ETC.c: 549: unsigned int ucValMax= uiTab_in[ucSize-1]; +"550 +[; ;ETC.c: 550: unsigned int ucValMax= uiTab_in[ucSize-1]; [v _ucValMax `ui ~T0 @X0 1 a ] [e = _ucValMax *U + _uiTab_in * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _uiTab_in `i `x ] -"550 -[; ;ETC.c: 550: unsigned char ucValout=0; +"551 +[; ;ETC.c: 551: unsigned char ucValout=0; [v _ucValout `uc ~T0 @X0 1 a ] [e = _ucValout -> -> 0 `i `uc ] -"553 -[; ;ETC.c: 553: if (value >= ucValCero) return ucTab_out[0]; +"554 +[; ;ETC.c: 554: if (value >= ucValCero) return ucTab_out[0]; [e $ ! >= _value -> _ucValCero `l 3298 ] [e ) -> *U + _ucTab_out * -> -> 0 `i `x -> -> # *U _ucTab_out `i `x `ui ] [e $UE 3297 ] [e :U 3298 ] -"554 -[; ;ETC.c: 554: if (value <= ucValMax) return ucTab_out[ucSize-1]; +"555 +[; ;ETC.c: 555: if (value <= ucValMax) return ucTab_out[ucSize-1]; [e $ ! <= _value -> _ucValMax `l 3299 ] [e ) -> *U + _ucTab_out * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `ui ] [e $UE 3297 ] [e :U 3299 ] -"558 -[; ;ETC.c: 558: while(value < uiTab_in[ucPos]) ucPos++; +"559 +[; ;ETC.c: 559: while(value < uiTab_in[ucPos]) ucPos++; [e $U 3300 ] [e :U 3301 ] [e ++ _ucPos -> -> 1 `i `uc ] [e :U 3300 ] [e $ < _value -> *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux `l 3301 ] [e :U 3302 ] -"559 -[; ;ETC.c: 559: ucValout = ucTab_out[ucPos]; +"560 +[; ;ETC.c: 560: ucValout = ucTab_out[ucPos]; [e = _ucValout *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux ] -"561 -[; ;ETC.c: 561: if (value == uiTab_in[ucPos]) return ucTab_out[ucPos]; +"562 +[; ;ETC.c: 562: if (value == uiTab_in[ucPos]) return ucTab_out[ucPos]; [e $ ! == _value -> *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux `l 3303 ] [e ) -> *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux `ui ] [e $UE 3297 ] [e :U 3303 ] -"564 -[; ;ETC.c: 564: slResult = ( ( (value - uiTab_in[ucPos-1]) * (ucTab_out[ucPos] - ucTab_out[ucPos-1]) / (uiTab_in[ucPos] - uiTab_in[ucPos-1]) ) + ucTab_out[ucPos-1] ); +"565 +[; ;ETC.c: 565: slResult = ( ( (value - uiTab_in[ucPos-1]) * (ucTab_out[ucPos] - ucTab_out[ucPos-1]) / (uiTab_in[ucPos] - uiTab_in[ucPos-1]) ) + ucTab_out[ucPos-1] ); [e = _slResult + / * - _value -> *U + _uiTab_in * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _uiTab_in `i `x `l -> - -> *U + _ucTab_out * -> _ucPos `ux -> -> # *U _ucTab_out `ui `ux `i -> *U + _ucTab_out * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `i `l -> - *U + _uiTab_in * -> _ucPos `ux -> -> # *U _uiTab_in `ui `ux *U + _uiTab_in * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _uiTab_in `i `x `l -> *U + _ucTab_out * -> - -> _ucPos `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `l ] -"566 -[; ;ETC.c: 566: if ( slResult < 0 ) slResult = ucTab_out[0]; +"567 +[; ;ETC.c: 567: if ( slResult < 0 ) slResult = ucTab_out[0]; [e $ ! < _slResult -> -> 0 `i `l 3304 ] [e = _slResult -> *U + _ucTab_out * -> -> 0 `i `x -> -> # *U _ucTab_out `i `x `l ] [e :U 3304 ] -"567 -[; ;ETC.c: 567: if ( slResult > 100 ) slResult = ucTab_out[ucSize-1]; +"568 +[; ;ETC.c: 568: if ( slResult > 100 ) slResult = ucTab_out[ucSize-1]; [e $ ! > _slResult -> -> 100 `i `l 3305 ] [e = _slResult -> *U + _ucTab_out * -> - -> _ucSize `i -> 1 `i `x -> -> # *U _ucTab_out `i `x `l ] [e :U 3305 ] -"569 -[; ;ETC.c: 569: return slResult ; +"570 +[; ;ETC.c: 570: return slResult ; [e ) -> _slResult `ui ] [e $UE 3297 ] -"570 -[; ;ETC.c: 570: } +"571 +[; ;ETC.c: 571: } [e :UE 3297 ] } -"574 -[; ;ETC.c: 574: void PIDController_Init(PIDController *pid) { +"575 +[; ;ETC.c: 575: void PIDController_Init(PIDController *pid) { [v _PIDController_Init `(v ~T0 @X0 1 ef1`*S3181 ] { [e :U _PIDController_Init ] [v _pid `*S3181 ~T0 @X0 1 r1 ] [f ] -"577 -[; ;ETC.c: 577: pid->integrator = 0.0f; -[e = . *U _pid 9 -> .0.0 `f ] "578 -[; ;ETC.c: 578: pid->prevError = 0.0f; +[; ;ETC.c: 578: pid->integrator = 0.0f; +[e = . *U _pid 9 -> .0.0 `f ] +"579 +[; ;ETC.c: 579: pid->prevError = 0.0f; [e = . *U _pid 10 -> .0.0 `f ] -"580 -[; ;ETC.c: 580: pid->differentiator = 0.0f; -[e = . *U _pid 11 -> .0.0 `f ] "581 -[; ;ETC.c: 581: pid->prevMeasurement = 0.0f; +[; ;ETC.c: 581: pid->differentiator = 0.0f; +[e = . *U _pid 11 -> .0.0 `f ] +"582 +[; ;ETC.c: 582: pid->prevMeasurement = 0.0f; [e = . *U _pid 12 -> .0.0 `f ] -"583 -[; ;ETC.c: 583: pid->out = 0.0f; +"584 +[; ;ETC.c: 584: pid->out = 0.0f; [e = . *U _pid 13 -> .0.0 `f ] -"585 -[; ;ETC.c: 585: } +"586 +[; ;ETC.c: 586: } [e :UE 3306 ] } -"587 -[; ;ETC.c: 587: float PIDController_Update(PIDController *pid, float setpoint, float measurement) { +"588 +[; ;ETC.c: 588: float PIDController_Update(PIDController *pid, float setpoint, float measurement) { [v _PIDController_Update `(f ~T0 @X0 1 ef3`*S3181`f`f ] { [e :U _PIDController_Update ] @@ -5243,67 +5243,67 @@ Version 4.0 HI-TECH Software Intermediate Code [v _setpoint `f ~T0 @X0 1 r2 ] [v _measurement `f ~T0 @X0 1 r3 ] [f ] -"592 -[; ;ETC.c: 592: float error = setpoint - measurement; +"593 +[; ;ETC.c: 593: float error = setpoint - measurement; [v _error `f ~T0 @X0 1 a ] [e = _error - _setpoint _measurement ] -"598 -[; ;ETC.c: 598: float proportional = pid->Kp * error; +"599 +[; ;ETC.c: 599: float proportional = pid->Kp * error; [v _proportional `f ~T0 @X0 1 a ] [e = _proportional * . *U _pid 0 _error ] -"604 -[; ;ETC.c: 604: pid->integrator = pid->integrator + 0.5f * pid->Ki * pid->T * (error + pid->prevError); +"605 +[; ;ETC.c: 605: pid->integrator = pid->integrator + 0.5f * pid->Ki * pid->T * (error + pid->prevError); [e = . *U _pid 9 + . *U _pid 9 * * * -> .0.5 `f . *U _pid 1 . *U _pid 8 + _error . *U _pid 10 ] -"624 -[; ;ETC.c: 624: pid->differentiator = -(2.0f * pid->Kd * (measurement - pid->prevMeasurement) +"625 +[; ;ETC.c: 625: pid->differentiator = -(2.0f * pid->Kd * (measurement - pid->prevMeasurement) [e = . *U _pid 11 / -U + * * -> .2.0 `f . *U _pid 2 - _measurement . *U _pid 12 * - * -> .2.0 `f . *U _pid 3 . *U _pid 8 . *U _pid 11 + * -> .2.0 `f . *U _pid 3 . *U _pid 8 ] -"630 -[; ;ETC.c: 630: if ((pid->differentiator > 2.0f) || (pid->differentiator < -2.0f)){ +"631 +[; ;ETC.c: 631: if ((pid->differentiator > 2.0f) || (pid->differentiator < -2.0f)){ [e $ ! || > . *U _pid 11 -> .2.0 `f < . *U _pid 11 -U -> .2.0 `f 3308 ] { -"631 -[; ;ETC.c: 631: pid->integrator = 0; -[e = . *U _pid 9 -> -> 0 `i `f ] "632 -[; ;ETC.c: 632: } +[; ;ETC.c: 632: pid->integrator = 0; +[e = . *U _pid 9 -> -> 0 `i `f ] +"633 +[; ;ETC.c: 633: } } [e :U 3308 ] -"636 -[; ;ETC.c: 636: pid->out = proportional + pid->integrator + pid->differentiator; +"637 +[; ;ETC.c: 637: pid->out = proportional + pid->integrator + pid->differentiator; [e = . *U _pid 13 + + _proportional . *U _pid 9 . *U _pid 11 ] -"638 -[; ;ETC.c: 638: if (pid->out > pid->limMax) { +"639 +[; ;ETC.c: 639: if (pid->out > pid->limMax) { [e $ ! > . *U _pid 13 . *U _pid 5 3309 ] { -"640 -[; ;ETC.c: 640: pid->out = pid->limMax; +"641 +[; ;ETC.c: 641: pid->out = pid->limMax; [e = . *U _pid 13 . *U _pid 5 ] -"642 -[; ;ETC.c: 642: } else if (pid->out < pid->limMin) { +"643 +[; ;ETC.c: 643: } else if (pid->out < pid->limMin) { } [e $U 3310 ] [e :U 3309 ] [e $ ! < . *U _pid 13 . *U _pid 4 3311 ] { -"644 -[; ;ETC.c: 644: pid->out = pid->limMin; +"645 +[; ;ETC.c: 645: pid->out = pid->limMin; [e = . *U _pid 13 . *U _pid 4 ] -"646 -[; ;ETC.c: 646: } +"647 +[; ;ETC.c: 647: } } [e :U 3311 ] [e :U 3310 ] -"649 -[; ;ETC.c: 649: pid->prevError = error; -[e = . *U _pid 10 _error ] "650 -[; ;ETC.c: 650: pid->prevMeasurement = measurement; +[; ;ETC.c: 650: pid->prevError = error; +[e = . *U _pid 10 _error ] +"651 +[; ;ETC.c: 651: pid->prevMeasurement = measurement; [e = . *U _pid 12 _measurement ] -"653 -[; ;ETC.c: 653: return pid->out; +"654 +[; ;ETC.c: 654: return pid->out; [e ) . *U _pid 13 ] [e $UE 3307 ] -"655 -[; ;ETC.c: 655: } +"656 +[; ;ETC.c: 656: } [e :UE 3307 ] } diff --git a/ETC.X/dist/default/debug/ETC.X.debug.cmf b/ETC.X/dist/default/debug/ETC.X.debug.cmf new file mode 100644 index 0000000..3c82b45 --- /dev/null +++ b/ETC.X/dist/default/debug/ETC.X.debug.cmf @@ -0,0 +1,4308 @@ +%CMF +# %PSECTS Section +# For each object file, details of its psects are enumerated here. +# The begining of the section is indicated by %PSECTS. The first +# line indicates the name of the first object file, e.g. +# $foo.obj +# Each line that follows describes a psect in that object file, until +# the next object file. The lines that describe a psect have the +# format: +# +# All addresses and the length are given in unqualified hexadecimal +# in delta units. Any other numeric values are decimal. +%PSECTS +$dist/default/debug\ETC.X.debug.o +ivt0x8 CODE 0 8 8 12 1 +cinit CODE 0 6D64 6D64 90 1 +idloc IDLOC 5 200000 200000 40 1 +text0 CODE 0 6B08 6B08 9A 1 +text1 CODE 0 4738 4738 1F4 1 +text2 CODE 0 7998 7998 2E 1 +text3 CODE 0 7602 7602 50 1 +text4 CODE 0 7E5E 7E5E A 1 +text5 CODE 0 7B54 7B54 28 1 +text6 CODE 0 7E68 7E68 A 1 +text7 CODE 0 71FA 71FA 74 1 +text8 CODE 0 7E72 7E72 A 1 +text9 CODE 0 7E7C 7E7C A 1 +text10 CODE 0 7E86 7E86 A 1 +text11 CODE 0 726E 726E 74 1 +text12 CODE 0 7E90 7E90 A 1 +text13 CODE 0 7E9A 7E9A A 1 +text14 CODE 0 7EA4 7EA4 A 1 +text15 CODE 0 7B7C 7B7C 28 1 +text16 CODE 0 7016 7016 7E 1 +text17 CODE 0 7CB8 7CB8 18 1 +text18 CODE 0 7F5A 7F5A 4 1 +text19 CODE 0 7A7C 7A7C 2C 1 +text20 CODE 0 749E 749E 5C 1 +text21 CODE 0 7D9C 7D9C 14 1 +text22 CODE 0 79C6 79C6 2E 1 +text23 CODE 0 7BCC 7BCC 22 1 +text24 CODE 0 7B00 7B00 2A 1 +text25 CODE 0 7EAE 7EAE A 1 +text26 CODE 0 6BA2 6BA2 98 1 +text27 CODE 0 7094 7094 7A 1 +text28 CODE 0 7EB8 7EB8 A 1 +text29 CODE 0 7EC2 7EC2 A 1 +text30 CODE 0 7ECC 7ECC A 1 +text31 CODE 0 7ED6 7ED6 A 1 +text32 CODE 0 7EE0 7EE0 A 1 +text33 CODE 0 7EEA 7EEA A 1 +text34 CODE 0 7EF4 7EF4 A 1 +text35 CODE 0 7DB0 7DB0 14 1 +text36 CODE 0 4512 4512 226 1 +text37 CODE 0 7EFE 7EFE A 1 +text38 CODE 0 7F08 7F08 A 1 +text39 CODE 0 7F12 7F12 A 1 +text40 CODE 0 7F1C 7F1C A 1 +text41 CODE 0 7F26 7F26 A 1 +text42 CODE 0 7F30 7F30 A 1 +text43 CODE 0 7724 7724 3E 1 +text44 CODE 0 6868 6868 B4 1 +text45 CODE 0 503E 503E 186 1 +text46 CODE 0 25BC 25BC 712 1 +text47 CODE 0 7652 7652 48 1 +text48 CODE 0 7858 7858 3A 1 +text49 CODE 0 3650 3650 450 1 +text50 CODE 0 588C 588C 106 1 +text51 CODE 0 3AA0 3AA0 39C 1 +text52 CODE 0 5A98 5A98 F2 1 +text53 CODE 0 611A 611A E2 1 +text54 CODE 0 7904 7904 32 1 +text55 CODE 0 69CC 69CC 9E 1 +text56 CODE 0 769A 769A 46 1 +text57 CODE 0 3E3C 3E3C 250 1 +text58 CODE 0 74FA 74FA 5C 1 +text59 CODE 0 6032 6032 E8 1 +text60 CODE 0 7C4C 7C4C 1C 1 +text61 CODE 0 7F3A 7F3A A 1 +text62 CODE 0 7D18 7D18 16 1 +text63 CODE 0 7C84 7C84 1A 1 +text64 CODE 0 7D2E 7D2E 16 1 +text65 CODE 0 7D44 7D44 16 1 +text66 CODE 0 7CD0 7CD0 18 1 +text67 CODE 0 6DF4 6DF4 90 1 +text68 CODE 0 544A 544A 120 1 +text69 CODE 0 5B8A 5B8A F2 1 +text70 CODE 0 7DEA 7DEA E 1 +text71 CODE 0 7DF8 7DF8 E 1 +text72 CODE 0 7F5E 7F5E 4 1 +text73 CODE 0 781C 781C 3C 1 +text74 CODE 0 531A 531A 130 1 +text75 CODE 0 7E22 7E22 C 1 +text76 CODE 0 7762 7762 3E 1 +text77 CODE 0 7F4E 7F4E 6 1 +text78 CODE 0 7C10 7C10 1E 1 +text79 CODE 0 691C 691C B0 1 +text80 CODE 0 6A6A 6A6A 9E 1 +text81 CODE 0 5C7C 5C7C F2 1 +text82 CODE 0 4B1A 4B1A 1B8 1 +text83 CODE 0 7AA8 7AA8 2C 1 +text84 CODE 0 710E 710E 76 1 +text85 CODE 0 5784 5784 108 1 +text86 CODE 0 2CCE 2CCE 4C2 1 +text87 CODE 0 7E06 7E06 E 1 +text88 CODE 0 7E14 7E14 E 1 +text89 CODE 0 7F62 7F62 4 1 +text90 CODE 0 7968 7968 30 1 +text91 CODE 0 7C68 7C68 1C 1 +text92 CODE 0 7DC4 7DC4 14 1 +text93 CODE 0 6F10 6F10 86 1 +text94 CODE 0 6484 6484 CA 1 +text95 CODE 0 73C8 73C8 6C 1 +text96 CODE 0 556A 556A 10E 1 +text97 CODE 0 67A6 67A6 C2 1 +text98 CODE 0 78CC 78CC 38 1 +text99 CODE 0 79F4 79F4 2E 1 +nvBANK6 BANK6 1 6DB 6DB 18 1 +idataCOMRAM CODE 0 7F6E 7F6E 2 1 +cstackCOMRAM COMRAM 1 501 501 3B 1 +cstackBANK5 BANK5 1 560 560 9C 1 +bssBANK5 BANK5 1 5FC 5FC 3 1 +bssBANK6 BANK6 1 600 600 AF 1 +smallconst SMALLCONST 0 2500 2500 BC 1 +idataBANK6 CODE 0 7A50 7A50 2C 1 +idataBANK7 CODE 0 6E84 6E84 8C 1 +dataBANK6 BANK6 1 6AF 6AF 2C 1 +dataBANK7 BANK7 1 700 700 8C 1 +dataCOMRAM COMRAM 1 55E 55E 2 1 +text100 CODE 0 61FC 61FC D8 1 +text101 CODE 0 7F70 7F70 2 1 +text102 CODE 0 7DD8 7DD8 12 1 +text103 CODE 0 7356 7356 72 1 +text104 CODE 0 5D6E 5D6E EC 1 +text105 CODE 0 7E2E 7E2E C 1 +text106 CODE 0 7E3A 7E3A C 1 +text107 CODE 0 7F66 7F66 4 1 +text108 CODE 0 5E5A 5E5A EC 1 +text109 CODE 0 4E8A 4E8A 1B4 1 +text110 CODE 0 7B2A 7B2A 2A 1 +text111 CODE 0 72E2 72E2 74 1 +text112 CODE 0 5992 5992 106 1 +text113 CODE 0 3190 3190 4C0 1 +text114 CODE 0 7E46 7E46 C 1 +text115 CODE 0 7E52 7E52 C 1 +text116 CODE 0 7F6A 7F6A 4 1 +text117 CODE 0 6C3A 6C3A 96 1 +text118 CODE 0 654E 654E CA 1 +text119 CODE 0 7F72 7F72 2 1 +text120 CODE 0 7892 7892 3A 1 +text121 CODE 0 7F74 7F74 2 1 +text122 CODE 0 7F76 7F76 2 1 +text123 CODE 0 77A0 77A0 3E 1 +text124 CODE 0 62D4 62D4 D8 1 +text125 CODE 0 7BA4 7BA4 28 1 +text126 CODE 0 6CD0 6CD0 94 1 +text127 CODE 0 77DE 77DE 3E 1 +text128 CODE 0 408C 408C 246 1 +text129 CODE 0 63AC 63AC D8 1 +text130 CODE 0 7CE8 7CE8 18 1 +text131 CODE 0 7F44 7F44 A 1 +text132 CODE 0 7D5A 7D5A 16 1 +text133 CODE 0 7C9E 7C9E 1A 1 +text134 CODE 0 7D70 7D70 16 1 +text135 CODE 0 7D86 7D86 16 1 +text136 CODE 0 7184 7184 76 1 +text137 CODE 0 7936 7936 32 1 +text138 CODE 0 7A22 7A22 2E 1 +text139 CODE 0 7F78 7F78 2 1 +text140 CODE 0 7BEE 7BEE 22 1 +text141 CODE 0 4CD2 4CD2 1B8 1 +text142 CODE 0 6F96 6F96 80 1 +text143 CODE 0 66E2 66E2 C4 1 +text144 CODE 0 7434 7434 6A 1 +text145 CODE 0 5678 5678 10C 1 +text146 CODE 0 7AD4 7AD4 2C 1 +text147 CODE 0 7F54 7F54 6 1 +text148 CODE 0 492C 492C 1EE 1 +text149 CODE 0 76E0 76E0 44 1 +text150 CODE 0 6618 6618 CA 1 +text151 CODE 0 75B0 75B0 52 1 +text152 CODE 0 5F46 5F46 EC 1 +text153 CODE 0 42D2 42D2 240 1 +text154 CODE 0 7556 7556 5A 1 +text155 CODE 0 7D00 7D00 18 1 +text156 CODE 0 7C2E 7C2E 1E 1 +text157 CODE 0 51C4 51C4 156 1 +text158 CODE 0 7F7A 7F7A 2 1 +text159 CODE 0 7F7C 7F7C 2 1 +text160 CODE 0 7F7E 7F7E 2 1 +text161 CODE 0 7F80 7F80 2 1 +text162 CODE 0 7F82 7F82 2 1 +text163 CODE 0 7F84 7F84 2 1 +text164 CODE 0 7F86 7F86 2 1 +bssCOMRAM COMRAM 1 53C 53C 22 1 +config CONFIG 4 300000 300000 24 1 +$C:\Users\panze\AppData\Local\Temp\s598.o +idloc IDLOC 5 200000 200000 40 1 +init CODE 0 1A 1A 4 1 +reset_vec CODE 0 0 0 4 1 +config CONFIG 4 300000 300000 24 1 +# %UNUSED Section +# This section enumerates the unused ranges of each CLASS. Each entry +# is described on a single line as follows: +# +# Addresses given in the range are in hexadecimal and units of delta. +%UNUSED +RAM 5FF-5FF 1 +RAM 6F3-6FF 1 +RAM 78C-24FF 1 +SFR 0-4FF 1 +SFR 2500-2DFF 1 +BANK5 5FF-5FF 1 +BANK6 6F3-6FF 1 +BANK7 78C-7FF 1 +BANK8 800-8FF 1 +BANK9 900-9FF 1 +CONST 4-7 1 +CONST 1E-24FF 1 +CONST 7F88-FFFF 1 +STACK 78C-24FF 1 +SMALLCONST 7F88-FFFF 1 +CODE 4-7 1 +CODE 1E-24FF 1 +CODE 7F88-FFFF 1 +BANK10 A00-AFF 1 +BANK11 B00-BFF 1 +BANK12 C00-CFF 1 +BANK13 D00-DFF 1 +BANK14 E00-EFF 1 +BANK15 F00-FFF 1 +BANK16 1000-10FF 1 +BANK17 1100-11FF 1 +BANK18 1200-12FF 1 +BANK19 1300-13FF 1 +BANK20 1400-14FF 1 +BANK21 1500-15FF 1 +BANK22 1600-16FF 1 +BANK23 1700-17FF 1 +BANK24 1800-18FF 1 +BANK25 1900-19FF 1 +BANK26 1A00-1AFF 1 +BANK27 1B00-1BFF 1 +BANK28 1C00-1CFF 1 +BANK29 1D00-1DFF 1 +BANK30 1E00-1EFF 1 +BANK31 1F00-1FFF 1 +BANK32 2000-20FF 1 +BANK33 2100-21FF 1 +BANK34 2200-22FF 1 +BANK35 2300-23FF 1 +BANK36 2400-24FF 1 +BIGRAM 5FF-5FF 1 +BIGRAM 6F3-6FF 1 +BIGRAM 78C-24FF 1 +EEDATA 380000-3803FF 1 +MEDIUMCONST 7F88-FFFF 1 +# %LINETAB Section +# This section enumerates the file/line to address mappings. +# The beginning of the section is indicated by %LINETAB. +# The first line indicates the name of the first object file, e.g. +# $foo.obj +# Each line that follows describes a single mapping until the next +# object file. Mappings have the following format: +#
>: +# The address is absolute and given given in unqualified hex +# in delta units of the psect. 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>44059:C:\Users\panze\AppData\Local\Temp\s598.s +6D68 cinit CODE >44060:C:\Users\panze\AppData\Local\Temp\s598.s +6D6A cinit CODE >44061:C:\Users\panze\AppData\Local\Temp\s598.s +6D6C cinit CODE >44062:C:\Users\panze\AppData\Local\Temp\s598.s +6D6E cinit CODE >44063:C:\Users\panze\AppData\Local\Temp\s598.s +6D70 cinit CODE >44064:C:\Users\panze\AppData\Local\Temp\s598.s +6D74 cinit CODE >44065:C:\Users\panze\AppData\Local\Temp\s598.s +6D78 cinit CODE >44066:C:\Users\panze\AppData\Local\Temp\s598.s +6D78 cinit CODE >44067:C:\Users\panze\AppData\Local\Temp\s598.s +6D7A cinit CODE >44068:C:\Users\panze\AppData\Local\Temp\s598.s +6D7E cinit CODE >44069:C:\Users\panze\AppData\Local\Temp\s598.s +6D80 cinit CODE >44070:C:\Users\panze\AppData\Local\Temp\s598.s +6D82 cinit CODE >44071:C:\Users\panze\AppData\Local\Temp\s598.s +6D84 cinit CODE >44075:C:\Users\panze\AppData\Local\Temp\s598.s +6D86 cinit CODE >44076:C:\Users\panze\AppData\Local\Temp\s598.s +6D88 cinit CODE >44077:C:\Users\panze\AppData\Local\Temp\s598.s +6D8A cinit CODE >44078:C:\Users\panze\AppData\Local\Temp\s598.s +6D8C cinit CODE >44079:C:\Users\panze\AppData\Local\Temp\s598.s +6D8E cinit CODE >44080:C:\Users\panze\AppData\Local\Temp\s598.s +6D90 cinit CODE >44081:C:\Users\panze\AppData\Local\Temp\s598.s +6D94 cinit CODE >44082:C:\Users\panze\AppData\Local\Temp\s598.s +6D98 cinit CODE >44083:C:\Users\panze\AppData\Local\Temp\s598.s +6D98 cinit CODE >44084:C:\Users\panze\AppData\Local\Temp\s598.s +6D9A cinit CODE >44085:C:\Users\panze\AppData\Local\Temp\s598.s +6D9E cinit CODE >44086:C:\Users\panze\AppData\Local\Temp\s598.s +6DA0 cinit CODE >44087:C:\Users\panze\AppData\Local\Temp\s598.s +6DA2 cinit CODE >44088:C:\Users\panze\AppData\Local\Temp\s598.s +6DA4 cinit CODE >44092:C:\Users\panze\AppData\Local\Temp\s598.s +6DA6 cinit CODE >44093:C:\Users\panze\AppData\Local\Temp\s598.s +6DA8 cinit CODE >44094:C:\Users\panze\AppData\Local\Temp\s598.s +6DAA cinit CODE >44095:C:\Users\panze\AppData\Local\Temp\s598.s +6DAC cinit CODE >44096:C:\Users\panze\AppData\Local\Temp\s598.s +6DAE cinit CODE >44097:C:\Users\panze\AppData\Local\Temp\s598.s +6DB0 cinit CODE >44098:C:\Users\panze\AppData\Local\Temp\s598.s +6DB2 cinit CODE >44099:C:\Users\panze\AppData\Local\Temp\s598.s +6DB8 cinit CODE >44100:C:\Users\panze\AppData\Local\Temp\s598.s +6DBA cinit CODE >44101:C:\Users\panze\AppData\Local\Temp\s598.s +6DC0 cinit CODE >44105:C:\Users\panze\AppData\Local\Temp\s598.s +6DC4 cinit CODE >44106:C:\Users\panze\AppData\Local\Temp\s598.s +6DC6 cinit CODE >44107:C:\Users\panze\AppData\Local\Temp\s598.s +6DC6 cinit CODE >44108:C:\Users\panze\AppData\Local\Temp\s598.s +6DC8 cinit CODE >44109:C:\Users\panze\AppData\Local\Temp\s598.s +6DCA cinit CODE >44110:C:\Users\panze\AppData\Local\Temp\s598.s +6DCC cinit CODE >44113:C:\Users\panze\AppData\Local\Temp\s598.s +6DCE cinit CODE >44114:C:\Users\panze\AppData\Local\Temp\s598.s +6DD0 cinit CODE >44115:C:\Users\panze\AppData\Local\Temp\s598.s +6DD2 cinit CODE >44116:C:\Users\panze\AppData\Local\Temp\s598.s +6DD4 cinit CODE >44119:C:\Users\panze\AppData\Local\Temp\s598.s +6DD8 cinit CODE >44120:C:\Users\panze\AppData\Local\Temp\s598.s +6DDA cinit CODE >44121:C:\Users\panze\AppData\Local\Temp\s598.s +6DDA cinit CODE >44122:C:\Users\panze\AppData\Local\Temp\s598.s +6DDC cinit CODE >44123:C:\Users\panze\AppData\Local\Temp\s598.s +6DDE cinit CODE >44124:C:\Users\panze\AppData\Local\Temp\s598.s +6DE0 cinit CODE >44132:C:\Users\panze\AppData\Local\Temp\s598.s +6DE2 cinit CODE >44133:C:\Users\panze\AppData\Local\Temp\s598.s +6DE4 cinit CODE >44134:C:\Users\panze\AppData\Local\Temp\s598.s +6DE6 cinit CODE >44135:C:\Users\panze\AppData\Local\Temp\s598.s +6DE8 cinit CODE >44136:C:\Users\panze\AppData\Local\Temp\s598.s +6DEA cinit CODE >44137:C:\Users\panze\AppData\Local\Temp\s598.s +6DEC cinit CODE >44138:C:\Users\panze\AppData\Local\Temp\s598.s +6DEE cinit CODE >44144:C:\Users\panze\AppData\Local\Temp\s598.s +6DEE cinit CODE >44146:C:\Users\panze\AppData\Local\Temp\s598.s +6DF0 cinit CODE >44147:C:\Users\panze\AppData\Local\Temp\s598.s +# %SYMTAB Section +# An enumeration of all symbols in the program. +# The beginning of the section is indicated by %SYMTAB. +# Each line describes a single symbol as follows: +#